1 // Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
\r
3 // This file is part of SCSI2SD.
\r
5 // SCSI2SD is free software: you can redistribute it and/or modify
\r
6 // it under the terms of the GNU General Public License as published by
\r
7 // the Free Software Foundation, either version 3 of the License, or
\r
8 // (at your option) any later version.
\r
10 // SCSI2SD is distributed in the hope that it will be useful,
\r
11 // but WITHOUT ANY WARRANTY; without even the implied warranty of
\r
12 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
\r
13 // GNU General Public License for more details.
\r
15 // You should have received a copy of the GNU General Public License
\r
16 // along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
\r
17 #pragma GCC push_options
\r
18 #pragma GCC optimize("-flto")
\r
29 #include "scsiPhy.h"
\r
36 enum SD_IO_STATE { SD_DMA, SD_ACCEPTED, SD_BUSY, SD_IDLE };
\r
37 static int sdIOState = SD_IDLE;
\r
39 // Private DMA variables.
\r
40 static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL;
\r
41 static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL;
\r
43 // Dummy location for DMA to send unchecked CRC bytes to
\r
44 static uint8 discardBuffer;
\r
46 // 2 bytes CRC, response, 8bits to close the clock..
\r
47 // "NCR" time is up to 8 bytes.
\r
48 static uint8_t writeResponseBuffer[8];
\r
50 static uint8_t writeStartToken = 0xFC;
\r
52 // Source of dummy SPI bytes for DMA
\r
53 static uint8 dummyBuffer = 0xFF;
\r
55 volatile uint8_t sdRxDMAComplete;
\r
56 volatile uint8_t sdTxDMAComplete;
\r
58 CY_ISR_PROTO(sdRxISR);
\r
61 sdRxDMAComplete = 1;
\r
63 CY_ISR_PROTO(sdTxISR);
\r
66 sdTxDMAComplete = 1;
\r
69 static uint8 sdCrc7(uint8* chr, uint8 cnt, uint8 crc)
\r
72 for(a = 0; a < cnt; a++)
\r
74 uint8 Data = chr[a];
\r
76 for(i = 0; i < 8; i++)
\r
79 if( (Data & 0x80) ^ (crc & 0x80) ) {crc ^= 0x09;}
\r
86 // Read and write 1 byte.
\r
87 static uint8_t sdSpiByte(uint8_t value)
\r
89 SDCard_WriteTxData(value);
\r
90 trace(trace_spinSpiByte);
\r
91 while (!(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)) {}
\r
92 trace(trace_sdSpiByte);
\r
93 return SDCard_ReadRxData();
\r
96 static uint16_t sdDoCommand(
\r
100 int use2byteResponse)
\r
102 int waitWhileBusy = (cmd != SD_GO_IDLE_STATE) && (cmd != SD_STOP_TRANSMISSION);
\r
104 // "busy" probe. We'll examine the results later.
\r
107 SDCard_WriteTxData(0xFF);
\r
110 // send is static as the address must remain consistent for the static
\r
111 // DMA descriptors to work.
\r
112 static uint8_t send[7];
\r
113 send[0] = cmd | 0x40;
\r
114 send[1] = param >> 24;
\r
115 send[2] = param >> 16;
\r
116 send[3] = param >> 8;
\r
118 if (unlikely(useCRC))
\r
120 send[5] = (sdCrc7(send, 5, 0) << 1) | 1;
\r
124 send[5] = 1; // stop bit
\r
126 send[6] = 0xFF; // Result code or stuff byte.
\r
128 static uint8_t dmaRxTd = CY_DMA_INVALID_TD;
\r
129 static uint8_t dmaTxTd = CY_DMA_INVALID_TD;
\r
130 if (unlikely(dmaRxTd == CY_DMA_INVALID_TD))
\r
132 dmaRxTd = CyDmaTdAllocate();
\r
133 dmaTxTd = CyDmaTdAllocate();
\r
134 CyDmaTdSetConfiguration(dmaTxTd, sizeof(send), CY_DMA_DISABLE_TD, TD_INC_SRC_ADR|SD_TX_DMA__TD_TERMOUT_EN);
\r
135 CyDmaTdSetAddress(dmaTxTd, LO16((uint32)&send), LO16((uint32)SDCard_TXDATA_PTR));
\r
136 CyDmaTdSetConfiguration(dmaRxTd, sizeof(send), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
\r
137 CyDmaTdSetAddress(dmaRxTd, LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
\r
140 sdTxDMAComplete = 0;
\r
141 sdRxDMAComplete = 0;
\r
143 CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd);
\r
144 CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd);
\r
146 // Some Samsung cards enter a busy-state after single-sector reads.
\r
147 // But we also need to wait for R1B to complete from the multi-sector
\r
151 trace(trace_spinSDRxFIFO);
\r
152 while (!(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)) {}
\r
153 int busy = SDCard_ReadRxData() != 0xFF;
\r
154 if (unlikely(busy))
\r
156 trace(trace_spinSDBusy);
\r
157 while (sdSpiByte(0xFF) != 0xFF) {}
\r
161 // The DMA controller is a bit trigger-happy. It will retain
\r
162 // a drq request that was triggered while the channel was
\r
164 CyDmaClearPendingDrq(sdDMATxChan);
\r
165 CyDmaClearPendingDrq(sdDMARxChan);
\r
167 // There is no flow control, so we must ensure we can read the bytes
\r
168 // before we start transmitting
\r
169 CyDmaChEnable(sdDMARxChan, 1);
\r
170 CyDmaChEnable(sdDMATxChan, 1);
\r
172 trace(trace_spinSDDMA);
\r
173 while (!(sdTxDMAComplete && sdRxDMAComplete)) { __WFI(); }
\r
175 uint16_t response = discardBuffer;
\r
176 if (unlikely(cmd == SD_STOP_TRANSMISSION))
\r
178 // Stuff byte is required for this command only.
\r
179 // Part 1 Simplified standard 3.01
\r
180 // "The stop command has an execution delay due to the serial command
\r
182 response = sdSpiByte(0xFF);
\r
185 uint32_t start = getTime_ms();
\r
187 trace(trace_spinSDBusy);
\r
188 while ((response & 0x80) && likely(elapsedTime_ms(start) <= 200))
\r
190 response = sdSpiByte(0xFF);
\r
192 if (unlikely(use2byteResponse))
\r
194 response = (response << 8) | sdSpiByte(0xFF);
\r
200 static inline uint16_t sdCommandAndResponse(uint8_t cmd, uint32_t param)
\r
202 return sdDoCommand(cmd, param, 0, 0);
\r
205 static inline uint16_t sdCRCCommandAndResponse(uint8_t cmd, uint32_t param)
\r
207 return sdDoCommand(cmd, param, 1, 0);
\r
210 // Clear the sticky status bits on error.
\r
211 static void sdClearStatus()
\r
214 uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 1, 1);
\r
219 sdReadMultiSectorPrep()
\r
222 uint32 scsiLBA = (transfer.lba + transfer.currentBlock);
\r
225 scsiDev.target->cfg->sdSectorStart,
\r
226 scsiDev.target->liveCfg.bytesPerSector,
\r
231 sdLBA = sdLBA * SD_SECTOR_SIZE;
\r
233 v = sdCommandAndResponse(SD_READ_MULTIPLE_BLOCK, sdLBA);
\r
239 scsiDev.status = CHECK_CONDITION;
\r
240 scsiDev.target->sense.code = HARDWARE_ERROR;
\r
241 scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
\r
242 scsiDev.phase = STATUS;
\r
246 transfer.inProgress = 1;
\r
251 dmaReadSector(uint8_t* outputBuffer)
\r
253 // Wait for a start-block token.
\r
254 // Don't wait more than 200ms. The standard recommends 100ms.
\r
255 uint32_t start = getTime_ms();
\r
256 uint8_t token = sdSpiByte(0xFF);
\r
257 trace(trace_spinSDBusy);
\r
258 while (token != 0xFE && likely(elapsedTime_ms(start) <= 200))
\r
260 if (unlikely(token && ((token & 0xE0) == 0)))
\r
265 token = sdSpiByte(0xFF);
\r
267 if (unlikely(token != 0xFE))
\r
269 if (transfer.multiBlock)
\r
273 if (scsiDev.status != CHECK_CONDITION)
\r
275 scsiDev.status = CHECK_CONDITION;
\r
276 scsiDev.target->sense.code = HARDWARE_ERROR;
\r
277 scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;
\r
278 scsiDev.phase = STATUS;
\r
284 static uint8_t dmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD};
\r
285 static uint8_t dmaTxTd = CY_DMA_INVALID_TD;
\r
286 if (unlikely(dmaRxTd[0] == CY_DMA_INVALID_TD))
\r
288 dmaRxTd[0] = CyDmaTdAllocate();
\r
289 dmaRxTd[1] = CyDmaTdAllocate();
\r
290 dmaTxTd = CyDmaTdAllocate();
\r
292 // Receive 512 bytes of data and then 2 bytes CRC.
\r
293 CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE, dmaRxTd[1], TD_INC_DST_ADR);
\r
294 CyDmaTdSetConfiguration(dmaRxTd[1], 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
\r
295 CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
\r
297 CyDmaTdSetConfiguration(dmaTxTd, SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
\r
298 CyDmaTdSetAddress(dmaTxTd, LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
\r
301 CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)outputBuffer));
\r
303 sdIOState = SD_DMA;
\r
304 sdTxDMAComplete = 0;
\r
305 sdRxDMAComplete = 0;
\r
307 // Re-loading the initial TD's here is very important, or else
\r
308 // we'll be re-using the last-used TD, which would be the last
\r
309 // in the chain (ie. CRC TD)
\r
310 CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd[0]);
\r
311 CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd);
\r
313 // The DMA controller is a bit trigger-happy. It will retain
\r
314 // a drq request that was triggered while the channel was
\r
316 CyDmaClearPendingDrq(sdDMATxChan);
\r
317 CyDmaClearPendingDrq(sdDMARxChan);
\r
319 // There is no flow control, so we must ensure we can read the bytes
\r
320 // before we start transmitting
\r
321 CyDmaChEnable(sdDMARxChan, 1);
\r
322 CyDmaChEnable(sdDMATxChan, 1);
\r
326 sdReadSectorDMAPoll()
\r
328 if (sdRxDMAComplete && sdTxDMAComplete)
\r
330 // DMA transfer is complete
\r
331 sdIOState = SD_IDLE;
\r
340 void sdReadSingleSectorDMA(uint32_t lba, uint8_t* outputBuffer)
\r
345 lba = lba * SD_SECTOR_SIZE;
\r
347 v = sdCommandAndResponse(SD_READ_SINGLE_BLOCK, lba);
\r
353 scsiDev.status = CHECK_CONDITION;
\r
354 scsiDev.target->sense.code = HARDWARE_ERROR;
\r
355 scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
\r
356 scsiDev.phase = STATUS;
\r
360 dmaReadSector(outputBuffer);
\r
365 sdReadMultiSectorDMA(uint8_t* outputBuffer)
\r
367 // Pre: sdReadMultiSectorPrep called.
\r
368 dmaReadSector(outputBuffer);
\r
372 void sdCompleteRead()
\r
374 if (unlikely(sdIOState != SD_IDLE))
\r
376 // Not much choice but to wait until we've completed the transfer.
\r
377 // Cancelling the transfer can't be done as we have no way to reset
\r
379 trace(trace_spinSDCompleteRead);
\r
380 while (!sdReadSectorDMAPoll()) { /* spin */ }
\r
383 if (transfer.inProgress)
\r
385 transfer.inProgress = 0;
\r
386 uint8 r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0);
\r
390 scsiDev.status = CHECK_CONDITION;
\r
391 scsiDev.target->sense.code = HARDWARE_ERROR;
\r
392 scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;
\r
393 scsiDev.phase = STATUS;
\r
397 // R1b has an optional trailing "busy" signal, but we defer waiting on this.
\r
398 // The next call so sdCommandAndResponse will wait for the busy state to
\r
402 static void sdWaitWriteBusy()
\r
407 val = sdSpiByte(0xFF);
\r
408 } while (val != 0xFF);
\r
412 sdWriteMultiSectorDMA(uint8_t* outputBuffer)
\r
414 static uint8_t dmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD};
\r
415 static uint8_t dmaTxTd[3] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD, CY_DMA_INVALID_TD};
\r
416 if (unlikely(dmaRxTd[0] == CY_DMA_INVALID_TD))
\r
418 dmaRxTd[0] = CyDmaTdAllocate();
\r
419 dmaRxTd[1] = CyDmaTdAllocate();
\r
420 dmaTxTd[0] = CyDmaTdAllocate();
\r
421 dmaTxTd[1] = CyDmaTdAllocate();
\r
422 dmaTxTd[2] = CyDmaTdAllocate();
\r
424 // Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte
\r
425 // We need to do this without stopping the clock
\r
426 CyDmaTdSetConfiguration(dmaTxTd[0], 1, dmaTxTd[1], TD_INC_SRC_ADR);
\r
427 CyDmaTdSetAddress(dmaTxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR));
\r
429 CyDmaTdSetConfiguration(dmaTxTd[1], SD_SECTOR_SIZE, dmaTxTd[2], TD_INC_SRC_ADR);
\r
431 CyDmaTdSetConfiguration(dmaTxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
\r
432 CyDmaTdSetAddress(dmaTxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
\r
434 CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 3, dmaRxTd[1], 0);
\r
435 CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
\r
436 CyDmaTdSetConfiguration(dmaRxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR);
\r
437 CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer));
\r
439 CyDmaTdSetAddress(dmaTxTd[1], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));
\r
442 sdIOState = SD_DMA;
\r
443 // The DMA controller is a bit trigger-happy. It will retain
\r
444 // a drq request that was triggered while the channel was
\r
446 CyDmaClearPendingDrq(sdDMATxChan);
\r
447 CyDmaClearPendingDrq(sdDMARxChan);
\r
449 sdTxDMAComplete = 0;
\r
450 sdRxDMAComplete = 0;
\r
452 // Re-loading the initial TD's here is very important, or else
\r
453 // we'll be re-using the last-used TD, which would be the last
\r
454 // in the chain (ie. CRC TD)
\r
455 CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd[0]);
\r
456 CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd[0]);
\r
458 // There is no flow control, so we must ensure we can read the bytes
\r
459 // before we start transmitting
\r
460 CyDmaChEnable(sdDMARxChan, 1);
\r
461 CyDmaChEnable(sdDMATxChan, 1);
\r
465 sdWriteSectorDMAPoll(int sendStopToken)
\r
467 if (sdRxDMAComplete && sdTxDMAComplete)
\r
469 if (sdIOState == SD_DMA)
\r
471 // Retry a few times. The data token format is:
\r
477 dataToken = writeResponseBuffer[i]; // Response
\r
479 } while (((dataToken & 0x0101) != 1) && (i < sizeof(writeResponseBuffer)));
\r
481 // At this point we should either have an accepted token, or we'll
\r
482 // timeout and proceed into the error case below.
\r
483 if (unlikely(((dataToken & 0x1F) >> 1) != 0x2)) // Accepted.
\r
485 sdIOState = SD_IDLE;
\r
488 sdSpiByte(0xFD); // STOP TOKEN
\r
491 transfer.inProgress = 0;
\r
495 scsiDev.status = CHECK_CONDITION;
\r
496 scsiDev.target->sense.code = HARDWARE_ERROR;
\r
497 scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
\r
498 scsiDev.phase = STATUS;
\r
502 sdIOState = SD_ACCEPTED;
\r
506 if (sdIOState == SD_ACCEPTED)
\r
508 // Wait while the SD card is busy
\r
509 if (sdSpiByte(0xFF) == 0xFF)
\r
513 sdIOState = SD_BUSY;
\r
514 transfer.inProgress = 0;
\r
516 sdSpiByte(0xFD); // STOP TOKEN
\r
520 sdIOState = SD_IDLE;
\r
525 if (sdIOState == SD_BUSY)
\r
527 // Wait while the SD card is busy
\r
528 if (sdSpiByte(0xFF) == 0xFF)
\r
530 sdIOState = SD_IDLE;
\r
534 return sdIOState == SD_IDLE;
\r
542 void sdCompleteWrite()
\r
544 if (unlikely(sdIOState != SD_IDLE))
\r
546 // Not much choice but to wait until we've completed the transfer.
\r
547 // Cancelling the transfer can't be done as we have no way to reset
\r
549 trace(trace_spinSDCompleteWrite);
\r
550 while (!sdWriteSectorDMAPoll(1)) { /* spin */ }
\r
553 if (transfer.inProgress && likely(scsiDev.phase == DATA_OUT))
\r
555 uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 0, 1);
\r
559 scsiDev.status = CHECK_CONDITION;
\r
560 scsiDev.target->sense.code = HARDWARE_ERROR;
\r
561 scsiDev.target->sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED;
\r
562 scsiDev.phase = STATUS;
\r
565 transfer.inProgress = 0;
\r
569 // SD Version 2 (SDHC) support
\r
570 static int sendIfCond()
\r
576 // 11:8 Host voltage. 1 = 2.7-3.6V
\r
577 // 7:0 Echo bits. Ignore.
\r
578 uint8 status = sdCRCCommandAndResponse(SD_SEND_IF_COND, 0x000001AA);
\r
580 if (status == SD_R1_IDLE)
\r
584 // Read 32bit response. Should contain the same bytes that
\r
585 // we sent in the command parameter.
\r
592 else if (status & SD_R1_ILLEGAL)
\r
601 } while (--retries > 0);
\r
603 return retries > 0;
\r
606 static int sdOpCond()
\r
608 uint32_t start = getTime_ms();
\r
613 sdCRCCommandAndResponse(SD_APP_CMD, 0);
\r
614 // Host Capacity Support = 1 (SDHC/SDXC supported)
\r
615 status = sdCRCCommandAndResponse(SD_APP_SEND_OP_COND, 0x40000000);
\r
619 // Spec says to poll for 1 second.
\r
620 } while ((status != 0) && (elapsedTime_ms(start) < 1000));
\r
622 return status == 0;
\r
625 static int sdReadOCR()
\r
627 uint32_t start = getTime_ms();
\r
636 status = sdCRCCommandAndResponse(SD_READ_OCR, 0);
\r
637 if(status) { break; }
\r
639 for (i = 0; i < 4; ++i)
\r
641 buf[i] = sdSpiByte(0xFF);
\r
644 sdDev.ccs = (buf[0] & 0x40) ? 1 : 0;
\r
645 complete = (buf[0] & 0x80);
\r
647 } while (!status &&
\r
649 (elapsedTime_ms(start) < 1000));
\r
651 return (status == 0) && complete;
\r
654 static void sdReadCID()
\r
659 uint8 status = sdCRCCommandAndResponse(SD_SEND_CID, 0);
\r
660 if(status){return;}
\r
665 startToken = sdSpiByte(0xFF);
\r
666 } while(maxWait-- && (startToken != 0xFE));
\r
667 if (startToken != 0xFE) { return; }
\r
669 for (i = 0; i < 16; ++i)
\r
671 sdDev.cid[i] = sdSpiByte(0xFF);
\r
673 sdSpiByte(0xFF); // CRC
\r
674 sdSpiByte(0xFF); // CRC
\r
677 static int sdReadCSD()
\r
682 uint8 status = sdCRCCommandAndResponse(SD_SEND_CSD, 0);
\r
683 if(status){goto bad;}
\r
688 startToken = sdSpiByte(0xFF);
\r
689 } while(maxWait-- && (startToken != 0xFE));
\r
690 if (startToken != 0xFE) { goto bad; }
\r
692 for (i = 0; i < 16; ++i)
\r
694 sdDev.csd[i] = sdSpiByte(0xFF);
\r
696 sdSpiByte(0xFF); // CRC
\r
697 sdSpiByte(0xFF); // CRC
\r
699 if ((sdDev.csd[0] >> 6) == 0x00)
\r
702 // C_SIZE in bits [73:62]
\r
703 uint32 c_size = (((((uint32)sdDev.csd[6]) & 0x3) << 16) | (((uint32)sdDev.csd[7]) << 8) | sdDev.csd[8]) >> 6;
\r
704 uint32 c_mult = (((((uint32)sdDev.csd[9]) & 0x3) << 8) | ((uint32)sdDev.csd[0xa])) >> 7;
\r
705 uint32 sectorSize = sdDev.csd[5] & 0x0F;
\r
706 sdDev.capacity = ((c_size+1) * ((uint64)1 << (c_mult+2)) * ((uint64)1 << sectorSize)) / SD_SECTOR_SIZE;
\r
708 else if ((sdDev.csd[0] >> 6) == 0x01)
\r
711 // C_SIZE in bits [69:48]
\r
714 ((((uint32)sdDev.csd[7]) & 0x3F) << 16) |
\r
715 (((uint32)sdDev.csd[8]) << 8) |
\r
716 ((uint32)sdDev.csd[7]);
\r
717 sdDev.capacity = (c_size + 1) * 1024;
\r
729 static void sdInitDMA()
\r
731 // One-time init only.
\r
732 if (sdDMATxChan == CY_DMA_INVALID_CHANNEL)
\r
735 SD_TX_DMA_DmaInitialize(
\r
736 1, // Bytes per burst
\r
737 1, // request per burst
\r
738 HI16(CYDEV_SRAM_BASE),
\r
739 HI16(CYDEV_PERIPH_BASE)
\r
743 SD_RX_DMA_DmaInitialize(
\r
744 1, // Bytes per burst
\r
745 1, // request per burst
\r
746 HI16(CYDEV_PERIPH_BASE),
\r
747 HI16(CYDEV_SRAM_BASE)
\r
750 CyDmaChDisable(sdDMATxChan);
\r
751 CyDmaChDisable(sdDMARxChan);
\r
753 SD_RX_DMA_COMPLETE_StartEx(sdRxISR);
\r
754 SD_TX_DMA_COMPLETE_StartEx(sdTxISR);
\r
766 sdDev.capacity = 0;
\r
767 memset(sdDev.csd, 0, sizeof(sdDev.csd));
\r
768 memset(sdDev.cid, 0, sizeof(sdDev.cid));
\r
772 SD_CS_SetDriveMode(SD_CS_DM_STRONG);
\r
773 SD_CS_Write(1); // Set CS inactive (active low)
\r
775 // Set the SPI clock for 400kHz transfers
\r
776 // 25MHz / 400kHz approx factor of 63.
\r
777 // The register contains (divider - 1)
\r
778 uint16_t clkDiv25MHz = SD_Data_Clk_GetDividerRegister();
\r
779 SD_Data_Clk_SetDivider(((clkDiv25MHz + 1) * 63) - 1);
\r
780 // Wait for the clock to settle.
\r
783 SDCard_Start(); // Enable SPI hardware
\r
785 // Power on sequence. 74 clock cycles of a "1" while CS unasserted.
\r
786 for (i = 0; i < 10; ++i)
\r
791 SD_CS_Write(0); // Set CS active (active low)
\r
795 v = sdDoCommand(SD_GO_IDLE_STATE, 0, 1, 0);
\r
796 if(v != 1){goto bad;}
\r
799 if (!sendIfCond()) goto bad; // Sets V1 or V2 flag CMD8
\r
800 if (!sdOpCond()) goto bad; // ACMD41. Wait for init completes.
\r
801 if (!sdReadOCR()) goto bad; // CMD58. Get CCS flag. Only valid after init.
\r
803 // This command will be ignored if sdDev.ccs is set.
\r
804 // SDHC and SDXC are always 512bytes.
\r
805 v = sdCRCCommandAndResponse(SD_SET_BLOCKLEN, SD_SECTOR_SIZE); //Force sector size
\r
807 v = sdCRCCommandAndResponse(SD_CRC_ON_OFF, 0); //crc off
\r
810 // now set the sd card back to full speed.
\r
811 // The SD Card spec says we can run SPI @ 25MHz
\r
814 // We can't run at full-speed with the pullup resistors enabled.
\r
815 SD_MISO_SetDriveMode(SD_MISO_DM_DIG_HIZ);
\r
816 SD_MOSI_SetDriveMode(SD_MOSI_DM_STRONG);
\r
817 SD_SCK_SetDriveMode(SD_SCK_DM_STRONG);
\r
819 SD_Data_Clk_SetDivider(clkDiv25MHz);
\r
823 // Clear out rubbish data through clock change
\r
825 SDCard_ReadRxStatus();
\r
826 SDCard_ReadTxStatus();
\r
827 SDCard_ClearFIFO();
\r
829 if (!sdReadCSD()) goto bad;
\r
836 SD_Data_Clk_SetDivider(clkDiv25MHz); // Restore the clock for our next retry
\r
837 sdDev.capacity = 0;
\r
846 void sdWriteMultiSectorPrep()
\r
850 // Set the number of blocks to pre-erase by the multiple block write command
\r
851 // We don't care about the response - if the command is not accepted, writes
\r
852 // will just be a bit slower.
\r
853 // Max 22bit parameter.
\r
854 uint32_t sdBlocks =
\r
856 SDSectorsPerSCSISector(scsiDev.target->liveCfg.bytesPerSector);
\r
857 uint32 blocks = sdBlocks > 0x7FFFFF ? 0x7FFFFF : sdBlocks;
\r
858 sdCommandAndResponse(SD_APP_CMD, 0);
\r
859 sdCommandAndResponse(SD_APP_SET_WR_BLK_ERASE_COUNT, blocks);
\r
861 uint32 scsiLBA = (transfer.lba + transfer.currentBlock);
\r
864 scsiDev.target->cfg->sdSectorStart,
\r
865 scsiDev.target->liveCfg.bytesPerSector,
\r
869 sdLBA = sdLBA * SD_SECTOR_SIZE;
\r
871 v = sdCommandAndResponse(SD_WRITE_MULTIPLE_BLOCK, sdLBA);
\r
876 scsiDev.status = CHECK_CONDITION;
\r
877 scsiDev.target->sense.code = HARDWARE_ERROR;
\r
878 scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
\r
879 scsiDev.phase = STATUS;
\r
883 transfer.inProgress = 1;
\r
889 // Check if there's an SD card present.
\r
890 if ((scsiDev.phase == BUS_FREE) &&
\r
891 (sdIOState == SD_IDLE))
\r
893 // The CS line is pulled high by the SD card.
\r
894 // De-assert the line, and check if it's high.
\r
895 // This isn't foolproof as it'll be left floating without
\r
896 // an SD card. We can't use the built-in pull-down resistor as it will
\r
897 // overpower the SD pullup resistor.
\r
899 SD_CS_SetDriveMode(SD_CS_DM_DIG_HIZ);
\r
902 uint8_t cs = SD_CS_Read();
\r
903 SD_CS_SetDriveMode(SD_CS_DM_STRONG) ;
\r
905 if (cs && !(blockDev.state & DISK_PRESENT))
\r
907 static int firstInit = 1;
\r
914 blockDev.state |= DISK_PRESENT | DISK_INITIALISED;
\r
919 for (i = 0; i < MAX_SCSI_TARGETS; ++i)
\r
921 scsiDev.targets[i].unitAttention = PARAMETERS_CHANGED;
\r
927 else if (!cs && (blockDev.state & DISK_PRESENT))
\r
929 sdDev.capacity = 0;
\r
930 blockDev.state &= ~DISK_PRESENT;
\r
931 blockDev.state &= ~DISK_INITIALISED;
\r
933 for (i = 0; i < MAX_SCSI_TARGETS; ++i)
\r
935 scsiDev.targets[i].unitAttention = PARAMETERS_CHANGED;
\r
941 #pragma GCC pop_options
\r