Final tweaks for v4.5
[SCSI2SD-V6.git] / software / SCSI2SD / v3 / SCSI2SD.cydsn / Generated_Source / PSoC5 / cyfitter_cfg.c
1 /*******************************************************************************\r
2 * File Name: cyfitter_cfg.c\r
3\r
4 * PSoC Creator  3.3\r
5 *\r
6 * Description:\r
7 * This file contains device initialization code.\r
8 * Except for the user defined sections in CyClockStartupError(), this file should not be modified.\r
9 * This file is automatically generated by PSoC Creator.\r
10 *\r
11 ********************************************************************************\r
12 * Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.\r
13 * You may use this file only in accordance with the license, terms, conditions, \r
14 * disclaimers, and limitations in the end user license agreement accompanying \r
15 * the software package with which this file was provided.\r
16 ********************************************************************************/\r
17 \r
18 #include <string.h>\r
19 #include "cytypes.h"\r
20 #include "cydevice_trm.h"\r
21 #include "cyfitter.h"\r
22 #include "CyLib.h"\r
23 #include "cyfitter_cfg.h"\r
24 \r
25 #define CY_NEED_CYCLOCKSTARTUPERROR 1\r
26 \r
27 \r
28 #if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
29     #define CYPACKED \r
30     #define CYPACKED_ATTR __attribute__ ((packed))\r
31     #define CYALIGNED __attribute__ ((aligned))\r
32     #define CY_CFG_UNUSED __attribute__ ((unused))\r
33     #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))\r
34     \r
35     #if defined(__ARMCC_VERSION)\r
36         #define CY_CFG_MEMORY_BARRIER() __memory_changed()\r
37     #else\r
38         #define CY_CFG_MEMORY_BARRIER() __sync_synchronize()\r
39     #endif\r
40     \r
41 #elif defined(__ICCARM__)\r
42     #include <intrinsics.h>\r
43 \r
44     #define CYPACKED __packed\r
45     #define CYPACKED_ATTR \r
46     #define CYALIGNED _Pragma("data_alignment=4")\r
47     #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")\r
48     #define CY_CFG_SECTION _Pragma("location=\".psocinit\"")\r
49     \r
50     #define CY_CFG_MEMORY_BARRIER() __DMB()\r
51     \r
52 #else\r
53     #error Unsupported toolchain\r
54 #endif\r
55 \r
56 \r
57 CY_CFG_UNUSED\r
58 static void CYMEMZERO(void *s, size_t n);\r
59 CY_CFG_UNUSED\r
60 static void CYMEMZERO(void *s, size_t n)\r
61 {\r
62         (void)memset(s, 0, n);\r
63 }\r
64 CY_CFG_UNUSED\r
65 static void CYCONFIGCPY(void *dest, const void *src, size_t n);\r
66 CY_CFG_UNUSED\r
67 static void CYCONFIGCPY(void *dest, const void *src, size_t n)\r
68 {\r
69         (void)memcpy(dest, src, n);\r
70 }\r
71 CY_CFG_UNUSED\r
72 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);\r
73 CY_CFG_UNUSED\r
74 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)\r
75 {\r
76         (void)memcpy(dest, src, n);\r
77 }\r
78 \r
79 \r
80 \r
81 /* Clock startup error codes                                                   */\r
82 #define CYCLOCKSTART_NO_ERROR    0u\r
83 #define CYCLOCKSTART_XTAL_ERROR  1u\r
84 #define CYCLOCKSTART_32KHZ_ERROR 2u\r
85 #define CYCLOCKSTART_PLL_ERROR   3u\r
86 \r
87 #ifdef CY_NEED_CYCLOCKSTARTUPERROR\r
88 /*******************************************************************************\r
89 * Function Name: CyClockStartupError\r
90 ********************************************************************************\r
91 * Summary:\r
92 *  If an error is encountered during clock configuration (crystal startup error,\r
93 *  PLL lock error, etc.), the system will end up here.  Unless reimplemented by\r
94 *  the customer, this function will stop in an infinite loop.\r
95 *\r
96 * Parameters:\r
97 *   void\r
98 *\r
99 * Return:\r
100 *   void\r
101 *\r
102 *******************************************************************************/\r
103 CY_CFG_UNUSED\r
104 static void CyClockStartupError(uint8 errorCode);\r
105 CY_CFG_UNUSED\r
106 static void CyClockStartupError(uint8 errorCode)\r
107 {\r
108     /* To remove the compiler warning if errorCode not used.                */\r
109     errorCode = errorCode;\r
110 \r
111     /* `#START CyClockStartupError` */\r
112 \r
113     /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */\r
114     /* we will end up here to allow the customer to implement something to  */\r
115     /* deal with the clock condition.                                       */\r
116 \r
117     /* `#END` */\r
118 \r
119     /* If nothing else, stop here since the clocks have not started         */\r
120     /* correctly.                                                           */\r
121     while(1) {}\r
122 }\r
123 #endif\r
124 \r
125 #define CY_CFG_BASE_ADDR_COUNT 42u\r
126 CYPACKED typedef struct\r
127 {\r
128         uint8 offset;\r
129         uint8 value;\r
130 } CYPACKED_ATTR cy_cfg_addrvalue_t;\r
131 \r
132 \r
133 \r
134 /*******************************************************************************\r
135 * Function Name: cfg_write_bytes32\r
136 ********************************************************************************\r
137 * Summary:\r
138 *  This function is used for setting up the chip configuration areas that\r
139 *  contain relatively sparse data.\r
140 *\r
141 * Parameters:\r
142 *   void\r
143 *\r
144 * Return:\r
145 *   void\r
146 *\r
147 *******************************************************************************/\r
148 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]);\r
149 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[])\r
150 {\r
151         /* For 32-bit little-endian architectures */\r
152         uint32 i, j = 0u;\r
153         for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++)\r
154         {\r
155                 uint32 baseAddr = addr_table[i];\r
156                 uint8 count = (uint8)baseAddr;\r
157                 baseAddr &= 0xFFFFFF00u;\r
158                 while (count != 0u)\r
159                 {\r
160                         CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value);\r
161                         j++;\r
162                         count--;\r
163                 }\r
164         }\r
165 }\r
166 \r
167 /*******************************************************************************\r
168 * Function Name: ClockSetup\r
169 ********************************************************************************\r
170 *\r
171 * Summary:\r
172 *  Performs the initialization of all of the clocks in the device based on the\r
173 *  settings in the Clock tab of the DWR.  This includes enabling the requested\r
174 *  clocks and setting the necessary dividers to produce the desired frequency. \r
175 *\r
176 * Parameters:\r
177 *  void\r
178 *\r
179 * Return:\r
180 *  void\r
181 *\r
182 *******************************************************************************/\r
183 static void ClockSetup(void);\r
184 static void ClockSetup(void)\r
185 {\r
186         uint32 timeout;\r
187         uint8 pllLock;\r
188 \r
189 \r
190         /* Configure Digital Clocks based on settings from Clock DWR */\r
191         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u);\r
192         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u);\r
193         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u);\r
194         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u);\r
195         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);\r
196         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);\r
197 \r
198         /* Configure ILO based on settings from Clock DWR */\r
199         CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);\r
200 \r
201         /* Configure IMO based on settings from Clock DWR */\r
202         CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u);\r
203         CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));\r
204 \r
205         /* Configure PLL based on settings from Clock DWR */\r
206         CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0B19u);\r
207         CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);\r
208         /* Wait up to 250us for the PLL to lock */\r
209         pllLock = 0u;\r
210         for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--)\r
211         { \r
212                 pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));\r
213                 CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */\r
214         }\r
215         /* If we ran out of time the PLL didn't lock so go to the error function */\r
216         if (timeout == 0u)\r
217         {\r
218                 CyClockStartupError(CYCLOCKSTART_PLL_ERROR);\r
219         }\r
220 \r
221         /* Configure Bus/Master Clock based on settings from Clock DWR */\r
222         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);\r
223         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u);\r
224         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u);\r
225         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u);\r
226         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u);\r
227 \r
228         /* Configure USB Clock based on settings from Clock DWR */\r
229         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);\r
230         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);\r
231 \r
232         CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x07u)));\r
233 }\r
234 \r
235 \r
236 /* Analog API Functions */\r
237 \r
238 \r
239 /*******************************************************************************\r
240 * Function Name: AnalogSetDefault\r
241 ********************************************************************************\r
242 *\r
243 * Summary:\r
244 *  Sets up the analog portions of the chip to default values based on chip\r
245 *  configuration options from the project.\r
246 *\r
247 * Parameters:\r
248 *  void\r
249 *\r
250 * Return:\r
251 *  void\r
252 *\r
253 *******************************************************************************/\r
254 static void AnalogSetDefault(void);\r
255 static void AnalogSetDefault(void)\r
256 {\r
257         uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));\r
258         CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));\r
259         CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));\r
260         CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);\r
261 }\r
262 \r
263 \r
264 /*******************************************************************************\r
265 * Function Name: SetAnalogRoutingPumps\r
266 ********************************************************************************\r
267 *\r
268 * Summary:\r
269 * Enables or disables the analog pumps feeding analog routing switches.\r
270 * Intended to be called at startup, based on the Vdda system configuration;\r
271 * may be called during operation when the user informs us that the Vdda voltage\r
272 * crossed the pump threshold.\r
273 *\r
274 * Parameters:\r
275 *  enabled - 1 to enable the pumps, 0 to disable the pumps\r
276 *\r
277 * Return:\r
278 *  void\r
279 *\r
280 *******************************************************************************/\r
281 void SetAnalogRoutingPumps(uint8 enabled)\r
282 {\r
283         uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0);\r
284         if (enabled != 0u)\r
285         {\r
286                 regValue |= 0x00u;\r
287         }\r
288         else\r
289         {\r
290                 regValue &= (uint8)~0x00u;\r
291         }\r
292         CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);\r
293 }\r
294 \r
295 #define CY_AMUX_UNUSED CYREG_BOOST_SR\r
296 \r
297 \r
298 /*******************************************************************************\r
299 * Function Name: cyfitter_cfg\r
300 ********************************************************************************\r
301 * Summary:\r
302 *  This function is called by the start-up code for the selected device. It\r
303 *  performs all of the necessary device configuration based on the design\r
304 *  settings.  This includes settings from the Design Wide Resources (DWR) such\r
305 *  as Clocks and Pins as well as any component configuration that is necessary.\r
306 *\r
307 * Parameters:  \r
308 *   void\r
309 *\r
310 * Return:\r
311 *   void\r
312 *\r
313 *******************************************************************************/\r
314 \r
315 void cyfitter_cfg(void)\r
316 {\r
317         /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */\r
318         static const uint8 CYCODE BS_IOPINS0_0_VAL[] = {\r
319                 0x00u, 0xFFu, 0xFFu, 0x00u, 0x17u, 0x00u, 0x00u, 0x00u};\r
320 \r
321         /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */\r
322         static const uint8 CYCODE BS_IOPINS0_7_VAL[] = {\r
323                 0x08u, 0x00u, 0x30u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
324 \r
325         /* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */\r
326         static const uint8 CYCODE BS_IOPINS1_7_VAL[] = {\r
327                 0x00u, 0x00u, 0x00u, 0x00u, 0x10u};\r
328 \r
329         /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */\r
330         static const uint8 CYCODE BS_IOPINS0_8_VAL[] = {\r
331                 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u};\r
332 \r
333         /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */\r
334         static const uint8 CYCODE BS_IOPINS0_2_VAL[] = {\r
335                 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u};\r
336 \r
337         /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */\r
338         static const uint8 CYCODE BS_IOPINS0_3_VAL[] = {\r
339                 0x10u, 0x00u, 0x63u, 0x1Cu, 0x1Cu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x01u};\r
340 \r
341         /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */\r
342         static const uint8 CYCODE BS_IOPINS0_4_VAL[] = {\r
343                 0x00u, 0xFCu, 0xFCu, 0x00u, 0xF8u, 0x00u, 0x00u, 0x00u};\r
344 \r
345         /* IOPINS0_5 Address: CYREG_PRT5_DM0 Size (bytes): 8 */\r
346         static const uint8 CYCODE BS_IOPINS0_5_VAL[] = {\r
347                 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u};\r
348 \r
349         /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */\r
350         static const uint8 CYCODE BS_IOPINS0_6_VAL[] = {\r
351                 0xF0u, 0x0Fu, 0x0Fu, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x01u};\r
352 \r
353         /* PHUB_CFGMEM1 Address: CYREG_PHUB_CFGMEM1_CFG0 Size (bytes): 4 */\r
354         static const uint8 CYCODE BS_PHUB_CFGMEM1_VAL[] = {\r
355                 0x00u, 0x01u, 0x00u, 0x00u};\r
356 \r
357         /* PHUB_CFGMEM2 Address: CYREG_PHUB_CFGMEM2_CFG0 Size (bytes): 4 */\r
358         static const uint8 CYCODE BS_PHUB_CFGMEM2_VAL[] = {\r
359                 0x00u, 0x02u, 0x00u, 0x00u};\r
360 \r
361         /* PHUB_CFGMEM3 Address: CYREG_PHUB_CFGMEM3_CFG0 Size (bytes): 4 */\r
362         static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = {\r
363                 0x00u, 0x03u, 0x00u, 0x00u};\r
364 \r
365 #ifdef CYGlobalIntDisable\r
366         /* Disable interrupts by default. Let user enable if/when they want. */\r
367         CYGlobalIntDisable\r
368 #endif\r
369 \r
370 \r
371         /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */\r
372         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));\r
373         /* Setup clocks based on selections from Clock DWR */\r
374         ClockSetup();\r
375         /* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */\r
376         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0xC1u : 0xC0u));\r
377         /* Enable/Disable Debug functionality based on settings from System DWR */\r
378         CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u));\r
379 \r
380         {\r
381                 static const uint32 CYCODE cy_cfg_addr_table[] = {\r
382                         0x40004501u, /* Base address: 0x40004500 Count: 1 */\r
383                         0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
384                         0x4000520Bu, /* Base address: 0x40005200 Count: 11 */\r
385                         0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
386                         0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
387                         0x4001003Du, /* Base address: 0x40010000 Count: 61 */\r
388                         0x40010138u, /* Base address: 0x40010100 Count: 56 */\r
389                         0x40010248u, /* Base address: 0x40010200 Count: 72 */\r
390                         0x40010356u, /* Base address: 0x40010300 Count: 86 */\r
391                         0x40010445u, /* Base address: 0x40010400 Count: 69 */\r
392                         0x4001054Au, /* Base address: 0x40010500 Count: 74 */\r
393                         0x4001064Eu, /* Base address: 0x40010600 Count: 78 */\r
394                         0x4001074Fu, /* Base address: 0x40010700 Count: 79 */\r
395                         0x40010856u, /* Base address: 0x40010800 Count: 86 */\r
396                         0x40010954u, /* Base address: 0x40010900 Count: 84 */\r
397                         0x40010A4Cu, /* Base address: 0x40010A00 Count: 76 */\r
398                         0x40010B4Bu, /* Base address: 0x40010B00 Count: 75 */\r
399                         0x40010C51u, /* Base address: 0x40010C00 Count: 81 */\r
400                         0x40010D56u, /* Base address: 0x40010D00 Count: 86 */\r
401                         0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */\r
402                         0x40010F42u, /* Base address: 0x40010F00 Count: 66 */\r
403                         0x4001145Eu, /* Base address: 0x40011400 Count: 94 */\r
404                         0x4001154Au, /* Base address: 0x40011500 Count: 74 */\r
405                         0x40011650u, /* Base address: 0x40011600 Count: 80 */\r
406                         0x4001174Au, /* Base address: 0x40011700 Count: 74 */\r
407                         0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
408                         0x40011913u, /* Base address: 0x40011900 Count: 19 */\r
409                         0x40011B0Cu, /* Base address: 0x40011B00 Count: 12 */\r
410                         0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
411                         0x4001411Au, /* Base address: 0x40014100 Count: 26 */\r
412                         0x40014213u, /* Base address: 0x40014200 Count: 19 */\r
413                         0x4001430Au, /* Base address: 0x40014300 Count: 10 */\r
414                         0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
415                         0x4001451Bu, /* Base address: 0x40014500 Count: 27 */\r
416                         0x4001460Cu, /* Base address: 0x40014600 Count: 12 */\r
417                         0x4001470Fu, /* Base address: 0x40014700 Count: 15 */\r
418                         0x40014807u, /* Base address: 0x40014800 Count: 7 */\r
419                         0x40014909u, /* Base address: 0x40014900 Count: 9 */\r
420                         0x40014C03u, /* Base address: 0x40014C00 Count: 3 */\r
421                         0x40014D03u, /* Base address: 0x40014D00 Count: 3 */\r
422                         0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
423                         0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
424                 };\r
425 \r
426                 static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
427                         {0x7Eu, 0x02u},\r
428                         {0x01u, 0x20u},\r
429                         {0x0Au, 0x36u},\r
430                         {0x00u, 0x05u},\r
431                         {0x01u, 0x13u},\r
432                         {0x18u, 0x08u},\r
433                         {0x1Cu, 0x71u},\r
434                         {0x20u, 0x50u},\r
435                         {0x21u, 0x90u},\r
436                         {0x2Cu, 0x0Eu},\r
437                         {0x30u, 0x0Cu},\r
438                         {0x31u, 0x09u},\r
439                         {0x34u, 0x80u},\r
440                         {0x7Cu, 0x40u},\r
441                         {0x20u, 0x01u},\r
442                         {0x87u, 0x0Fu},\r
443                         {0x00u, 0x20u},\r
444                         {0x02u, 0x40u},\r
445                         {0x03u, 0x04u},\r
446                         {0x04u, 0x01u},\r
447                         {0x05u, 0x08u},\r
448                         {0x08u, 0x0Au},\r
449                         {0x09u, 0x09u},\r
450                         {0x0Au, 0x35u},\r
451                         {0x0Bu, 0x72u},\r
452                         {0x0Cu, 0x48u},\r
453                         {0x0Eu, 0x36u},\r
454                         {0x10u, 0x07u},\r
455                         {0x11u, 0x01u},\r
456                         {0x12u, 0x18u},\r
457                         {0x13u, 0x66u},\r
458                         {0x14u, 0x4Fu},\r
459                         {0x16u, 0x30u},\r
460                         {0x17u, 0x7Fu},\r
461                         {0x1Bu, 0x01u},\r
462                         {0x1Du, 0x62u},\r
463                         {0x1Eu, 0x02u},\r
464                         {0x21u, 0x20u},\r
465                         {0x22u, 0x20u},\r
466                         {0x23u, 0x40u},\r
467                         {0x24u, 0x05u},\r
468                         {0x25u, 0x74u},\r
469                         {0x27u, 0x09u},\r
470                         {0x29u, 0x20u},\r
471                         {0x2Au, 0x27u},\r
472                         {0x2Bu, 0x40u},\r
473                         {0x30u, 0x1Fu},\r
474                         {0x31u, 0x60u},\r
475                         {0x33u, 0x1Fu},\r
476                         {0x36u, 0x60u},\r
477                         {0x3Au, 0x82u},\r
478                         {0x3Bu, 0x02u},\r
479                         {0x40u, 0x32u},\r
480                         {0x41u, 0x04u},\r
481                         {0x42u, 0x10u},\r
482                         {0x45u, 0x2Du},\r
483                         {0x46u, 0xFCu},\r
484                         {0x47u, 0x0Eu},\r
485                         {0x48u, 0x1Fu},\r
486                         {0x49u, 0xFFu},\r
487                         {0x4Au, 0xFFu},\r
488                         {0x4Bu, 0xFFu},\r
489                         {0x4Fu, 0x2Cu},\r
490                         {0x56u, 0x01u},\r
491                         {0x58u, 0x04u},\r
492                         {0x59u, 0x04u},\r
493                         {0x5Au, 0x04u},\r
494                         {0x5Bu, 0x04u},\r
495                         {0x5Cu, 0x11u},\r
496                         {0x5Du, 0x01u},\r
497                         {0x5Fu, 0x01u},\r
498                         {0x60u, 0x08u},\r
499                         {0x62u, 0xC8u},\r
500                         {0x66u, 0x80u},\r
501                         {0x68u, 0x40u},\r
502                         {0x69u, 0x40u},\r
503                         {0x6Eu, 0x08u},\r
504                         {0x02u, 0x04u},\r
505                         {0x03u, 0x91u},\r
506                         {0x04u, 0x30u},\r
507                         {0x0Au, 0x80u},\r
508                         {0x0Bu, 0x11u},\r
509                         {0x11u, 0x10u},\r
510                         {0x12u, 0xA8u},\r
511                         {0x1Au, 0x80u},\r
512                         {0x1Bu, 0x80u},\r
513                         {0x20u, 0x30u},\r
514                         {0x23u, 0x90u},\r
515                         {0x28u, 0x48u},\r
516                         {0x2Au, 0x04u},\r
517                         {0x2Bu, 0x10u},\r
518                         {0x32u, 0x88u},\r
519                         {0x33u, 0x11u},\r
520                         {0x38u, 0x10u},\r
521                         {0x3Bu, 0x05u},\r
522                         {0x40u, 0x10u},\r
523                         {0x42u, 0x04u},\r
524                         {0x43u, 0x81u},\r
525                         {0x4Au, 0x20u},\r
526                         {0x4Bu, 0x05u},\r
527                         {0x50u, 0x80u},\r
528                         {0x53u, 0x28u},\r
529                         {0x58u, 0x40u},\r
530                         {0x59u, 0x20u},\r
531                         {0x5Au, 0x02u},\r
532                         {0x5Bu, 0x84u},\r
533                         {0x60u, 0x04u},\r
534                         {0x61u, 0x49u},\r
535                         {0x69u, 0x84u},\r
536                         {0x6Au, 0x20u},\r
537                         {0x6Bu, 0x40u},\r
538                         {0x71u, 0x80u},\r
539                         {0x72u, 0x88u},\r
540                         {0x73u, 0x20u},\r
541                         {0x80u, 0x80u},\r
542                         {0x81u, 0xC0u},\r
543                         {0x85u, 0x04u},\r
544                         {0x8Au, 0x08u},\r
545                         {0x8Eu, 0x10u},\r
546                         {0x8Fu, 0x22u},\r
547                         {0xC0u, 0x0Fu},\r
548                         {0xC2u, 0x0Du},\r
549                         {0xC4u, 0x0Eu},\r
550                         {0xCAu, 0x07u},\r
551                         {0xCCu, 0x0Fu},\r
552                         {0xCEu, 0x07u},\r
553                         {0xD0u, 0x0Fu},\r
554                         {0xD6u, 0x0Fu},\r
555                         {0xD8u, 0x0Fu},\r
556                         {0xE0u, 0x05u},\r
557                         {0xE2u, 0x02u},\r
558                         {0xE4u, 0x03u},\r
559                         {0xE6u, 0x08u},\r
560                         {0x00u, 0x96u},\r
561                         {0x02u, 0x69u},\r
562                         {0x04u, 0x55u},\r
563                         {0x05u, 0x33u},\r
564                         {0x06u, 0xAAu},\r
565                         {0x07u, 0xCCu},\r
566                         {0x0Au, 0xFFu},\r
567                         {0x0Bu, 0xFFu},\r
568                         {0x0Cu, 0x33u},\r
569                         {0x0Du, 0x0Fu},\r
570                         {0x0Eu, 0xCCu},\r
571                         {0x0Fu, 0xF0u},\r
572                         {0x13u, 0xFFu},\r
573                         {0x14u, 0x0Fu},\r
574                         {0x16u, 0xF0u},\r
575                         {0x17u, 0xFFu},\r
576                         {0x18u, 0xFFu},\r
577                         {0x1Du, 0xFFu},\r
578                         {0x1Eu, 0xFFu},\r
579                         {0x25u, 0xFFu},\r
580                         {0x29u, 0x55u},\r
581                         {0x2Au, 0xFFu},\r
582                         {0x2Bu, 0xAAu},\r
583                         {0x2Cu, 0xFFu},\r
584                         {0x2Du, 0x69u},\r
585                         {0x2Fu, 0x96u},\r
586                         {0x32u, 0xFFu},\r
587                         {0x37u, 0xFFu},\r
588                         {0x3Au, 0x08u},\r
589                         {0x3Bu, 0x80u},\r
590                         {0x58u, 0x04u},\r
591                         {0x59u, 0x04u},\r
592                         {0x5Bu, 0x04u},\r
593                         {0x5Cu, 0x11u},\r
594                         {0x5Fu, 0x01u},\r
595                         {0x80u, 0xE0u},\r
596                         {0x84u, 0x40u},\r
597                         {0x86u, 0x80u},\r
598                         {0x89u, 0x44u},\r
599                         {0x8Au, 0xFFu},\r
600                         {0x8Bu, 0x88u},\r
601                         {0x8Cu, 0x06u},\r
602                         {0x8Eu, 0xF8u},\r
603                         {0x8Fu, 0x80u},\r
604                         {0x91u, 0x99u},\r
605                         {0x93u, 0x22u},\r
606                         {0x94u, 0x01u},\r
607                         {0x97u, 0x07u},\r
608                         {0x98u, 0xC6u},\r
609                         {0x9Au, 0x19u},\r
610                         {0x9Bu, 0x70u},\r
611                         {0x9Cu, 0x40u},\r
612                         {0x9Eu, 0x80u},\r
613                         {0x9Fu, 0x08u},\r
614                         {0xA0u, 0x14u},\r
615                         {0xA5u, 0xAAu},\r
616                         {0xA6u, 0x09u},\r
617                         {0xA7u, 0x55u},\r
618                         {0xA8u, 0x09u},\r
619                         {0xAAu, 0xF2u},\r
620                         {0xB3u, 0x0Fu},\r
621                         {0xB4u, 0x3Fu},\r
622                         {0xB5u, 0xF0u},\r
623                         {0xB6u, 0xC0u},\r
624                         {0xBAu, 0x80u},\r
625                         {0xD6u, 0x08u},\r
626                         {0xD8u, 0x04u},\r
627                         {0xD9u, 0x04u},\r
628                         {0xDBu, 0x04u},\r
629                         {0xDCu, 0x11u},\r
630                         {0xDDu, 0x90u},\r
631                         {0xDFu, 0x01u},\r
632                         {0x01u, 0x10u},\r
633                         {0x02u, 0x90u},\r
634                         {0x03u, 0x01u},\r
635                         {0x04u, 0x20u},\r
636                         {0x05u, 0x04u},\r
637                         {0x06u, 0x40u},\r
638                         {0x07u, 0x02u},\r
639                         {0x09u, 0x04u},\r
640                         {0x0Au, 0x06u},\r
641                         {0x0Eu, 0x26u},\r
642                         {0x10u, 0x80u},\r
643                         {0x12u, 0x20u},\r
644                         {0x13u, 0x18u},\r
645                         {0x15u, 0x90u},\r
646                         {0x1Au, 0x06u},\r
647                         {0x1Bu, 0x30u},\r
648                         {0x1Eu, 0x20u},\r
649                         {0x21u, 0x20u},\r
650                         {0x22u, 0x04u},\r
651                         {0x24u, 0x02u},\r
652                         {0x25u, 0x40u},\r
653                         {0x2Bu, 0x10u},\r
654                         {0x2Eu, 0x20u},\r
655                         {0x2Fu, 0x21u},\r
656                         {0x31u, 0x20u},\r
657                         {0x32u, 0x04u},\r
658                         {0x33u, 0x41u},\r
659                         {0x36u, 0x89u},\r
660                         {0x37u, 0x01u},\r
661                         {0x38u, 0x20u},\r
662                         {0x3Au, 0x80u},\r
663                         {0x3Du, 0x80u},\r
664                         {0x3Fu, 0x18u},\r
665                         {0x58u, 0x10u},\r
666                         {0x5Bu, 0x80u},\r
667                         {0x5Cu, 0x50u},\r
668                         {0x5Du, 0x09u},\r
669                         {0x60u, 0x08u},\r
670                         {0x62u, 0x40u},\r
671                         {0x63u, 0x08u},\r
672                         {0x65u, 0x80u},\r
673                         {0x81u, 0x08u},\r
674                         {0x82u, 0x40u},\r
675                         {0x83u, 0x80u},\r
676                         {0x85u, 0x20u},\r
677                         {0x87u, 0x08u},\r
678                         {0x89u, 0x20u},\r
679                         {0x8Bu, 0x80u},\r
680                         {0x8Cu, 0x40u},\r
681                         {0x8Eu, 0x04u},\r
682                         {0x90u, 0x20u},\r
683                         {0x91u, 0x10u},\r
684                         {0x93u, 0x10u},\r
685                         {0x94u, 0x04u},\r
686                         {0x96u, 0x06u},\r
687                         {0x98u, 0x04u},\r
688                         {0x9Au, 0x80u},\r
689                         {0x9Bu, 0x42u},\r
690                         {0x9Cu, 0x08u},\r
691                         {0x9Du, 0x61u},\r
692                         {0x9Fu, 0x15u},\r
693                         {0xA0u, 0x80u},\r
694                         {0xA2u, 0x28u},\r
695                         {0xA3u, 0x08u},\r
696                         {0xA5u, 0x08u},\r
697                         {0xA6u, 0x80u},\r
698                         {0xA7u, 0x10u},\r
699                         {0xAAu, 0x40u},\r
700                         {0xACu, 0x10u},\r
701                         {0xAEu, 0x04u},\r
702                         {0xB0u, 0x04u},\r
703                         {0xB3u, 0x20u},\r
704                         {0xB6u, 0x28u},\r
705                         {0xC0u, 0xFFu},\r
706                         {0xC2u, 0xE7u},\r
707                         {0xC4u, 0xCEu},\r
708                         {0xCAu, 0x72u},\r
709                         {0xCCu, 0xDFu},\r
710                         {0xCEu, 0x7Cu},\r
711                         {0xD6u, 0xFCu},\r
712                         {0xD8u, 0x1Cu},\r
713                         {0xE0u, 0x08u},\r
714                         {0xE6u, 0x03u},\r
715                         {0xE8u, 0x0Au},\r
716                         {0xEAu, 0x10u},\r
717                         {0xEEu, 0x06u},\r
718                         {0x01u, 0x02u},\r
719                         {0x02u, 0x02u},\r
720                         {0x03u, 0x01u},\r
721                         {0x05u, 0x01u},\r
722                         {0x07u, 0x06u},\r
723                         {0x11u, 0x04u},\r
724                         {0x13u, 0x08u},\r
725                         {0x17u, 0x10u},\r
726                         {0x1Eu, 0x01u},\r
727                         {0x21u, 0x02u},\r
728                         {0x23u, 0x01u},\r
729                         {0x29u, 0x02u},\r
730                         {0x2Bu, 0x01u},\r
731                         {0x2Du, 0x02u},\r
732                         {0x2Fu, 0x29u},\r
733                         {0x30u, 0x01u},\r
734                         {0x31u, 0x20u},\r
735                         {0x33u, 0x03u},\r
736                         {0x34u, 0x02u},\r
737                         {0x35u, 0x10u},\r
738                         {0x37u, 0x0Cu},\r
739                         {0x3Bu, 0x08u},\r
740                         {0x3Fu, 0x40u},\r
741                         {0x56u, 0x08u},\r
742                         {0x58u, 0x04u},\r
743                         {0x59u, 0x04u},\r
744                         {0x5Bu, 0x04u},\r
745                         {0x5Cu, 0x11u},\r
746                         {0x5Du, 0x90u},\r
747                         {0x5Fu, 0x01u},\r
748                         {0x81u, 0x0Du},\r
749                         {0x85u, 0x02u},\r
750                         {0x87u, 0x54u},\r
751                         {0x8Bu, 0x10u},\r
752                         {0x8Cu, 0x02u},\r
753                         {0x8Du, 0x02u},\r
754                         {0x8Eu, 0x01u},\r
755                         {0x8Fu, 0x0Du},\r
756                         {0x94u, 0x02u},\r
757                         {0x95u, 0x62u},\r
758                         {0x96u, 0x09u},\r
759                         {0x97u, 0x08u},\r
760                         {0x98u, 0x01u},\r
761                         {0x99u, 0x01u},\r
762                         {0x9Au, 0x02u},\r
763                         {0x9Bu, 0x32u},\r
764                         {0x9Cu, 0x02u},\r
765                         {0x9Eu, 0x05u},\r
766                         {0xA1u, 0x0Du},\r
767                         {0xA5u, 0x0Du},\r
768                         {0xA8u, 0x02u},\r
769                         {0xA9u, 0x0Du},\r
770                         {0xAAu, 0x11u},\r
771                         {0xADu, 0x0Du},\r
772                         {0xB0u, 0x04u},\r
773                         {0xB2u, 0x10u},\r
774                         {0xB4u, 0x03u},\r
775                         {0xB5u, 0x70u},\r
776                         {0xB6u, 0x08u},\r
777                         {0xB7u, 0x0Fu},\r
778                         {0xBAu, 0x20u},\r
779                         {0xBBu, 0x80u},\r
780                         {0xD6u, 0x08u},\r
781                         {0xD8u, 0x04u},\r
782                         {0xD9u, 0x04u},\r
783                         {0xDBu, 0x04u},\r
784                         {0xDCu, 0x01u},\r
785                         {0xDDu, 0x90u},\r
786                         {0xDFu, 0x01u},\r
787                         {0x01u, 0x06u},\r
788                         {0x03u, 0x20u},\r
789                         {0x04u, 0x40u},\r
790                         {0x0Au, 0x02u},\r
791                         {0x0Eu, 0x1Au},\r
792                         {0x14u, 0x08u},\r
793                         {0x19u, 0x22u},\r
794                         {0x1Cu, 0x40u},\r
795                         {0x1Eu, 0x1Au},\r
796                         {0x20u, 0x01u},\r
797                         {0x21u, 0x45u},\r
798                         {0x22u, 0x91u},\r
799                         {0x25u, 0x50u},\r
800                         {0x28u, 0x02u},\r
801                         {0x29u, 0x22u},\r
802                         {0x2Cu, 0xA8u},\r
803                         {0x2Du, 0x40u},\r
804                         {0x30u, 0x02u},\r
805                         {0x32u, 0x08u},\r
806                         {0x36u, 0x20u},\r
807                         {0x37u, 0x08u},\r
808                         {0x39u, 0x0Au},\r
809                         {0x3Cu, 0x08u},\r
810                         {0x3Du, 0xA0u},\r
811                         {0x3Eu, 0x02u},\r
812                         {0x58u, 0x10u},\r
813                         {0x5Au, 0x84u},\r
814                         {0x5Eu, 0x40u},\r
815                         {0x5Fu, 0x20u},\r
816                         {0x60u, 0x02u},\r
817                         {0x61u, 0x24u},\r
818                         {0x62u, 0x04u},\r
819                         {0x64u, 0x08u},\r
820                         {0x67u, 0x02u},\r
821                         {0x68u, 0x02u},\r
822                         {0x6Du, 0x08u},\r
823                         {0x6Fu, 0x1Au},\r
824                         {0x83u, 0x0Au},\r
825                         {0x84u, 0x10u},\r
826                         {0x85u, 0x08u},\r
827                         {0x86u, 0x04u},\r
828                         {0x8Bu, 0x20u},\r
829                         {0x8Du, 0x10u},\r
830                         {0x90u, 0x22u},\r
831                         {0x92u, 0x80u},\r
832                         {0x94u, 0x14u},\r
833                         {0x95u, 0x89u},\r
834                         {0x97u, 0x02u},\r
835                         {0x98u, 0x04u},\r
836                         {0x9Du, 0x45u},\r
837                         {0x9Eu, 0x30u},\r
838                         {0x9Fu, 0x15u},\r
839                         {0xA2u, 0x10u},\r
840                         {0xA3u, 0x20u},\r
841                         {0xA5u, 0x0Cu},\r
842                         {0xA6u, 0x84u},\r
843                         {0xA7u, 0x80u},\r
844                         {0xABu, 0x18u},\r
845                         {0xACu, 0x10u},\r
846                         {0xAEu, 0x04u},\r
847                         {0xB1u, 0x84u},\r
848                         {0xB3u, 0x01u},\r
849                         {0xC0u, 0x88u},\r
850                         {0xC2u, 0xE1u},\r
851                         {0xC4u, 0x40u},\r
852                         {0xCAu, 0xFDu},\r
853                         {0xCCu, 0x63u},\r
854                         {0xCEu, 0xF3u},\r
855                         {0xD6u, 0x3Eu},\r
856                         {0xD8u, 0x3Eu},\r
857                         {0xE2u, 0x22u},\r
858                         {0xE6u, 0x16u},\r
859                         {0xECu, 0x09u},\r
860                         {0xEEu, 0x06u},\r
861                         {0x00u, 0x02u},\r
862                         {0x02u, 0x01u},\r
863                         {0x05u, 0x34u},\r
864                         {0x07u, 0x08u},\r
865                         {0x09u, 0x01u},\r
866                         {0x0Bu, 0x38u},\r
867                         {0x11u, 0x05u},\r
868                         {0x13u, 0x38u},\r
869                         {0x14u, 0x02u},\r
870                         {0x15u, 0x10u},\r
871                         {0x16u, 0x01u},\r
872                         {0x17u, 0x20u},\r
873                         {0x1Bu, 0x01u},\r
874                         {0x1Cu, 0x01u},\r
875                         {0x1Du, 0x30u},\r
876                         {0x1Eu, 0x02u},\r
877                         {0x1Fu, 0x08u},\r
878                         {0x21u, 0x02u},\r
879                         {0x23u, 0x30u},\r
880                         {0x28u, 0x02u},\r
881                         {0x2Au, 0x01u},\r
882                         {0x2Bu, 0x40u},\r
883                         {0x2Cu, 0x02u},\r
884                         {0x2Du, 0x10u},\r
885                         {0x2Eu, 0x05u},\r
886                         {0x2Fu, 0x20u},\r
887                         {0x32u, 0x04u},\r
888                         {0x33u, 0x40u},\r
889                         {0x35u, 0x30u},\r
890                         {0x36u, 0x03u},\r
891                         {0x37u, 0x0Fu},\r
892                         {0x39u, 0x80u},\r
893                         {0x3Au, 0x80u},\r
894                         {0x3Bu, 0x20u},\r
895                         {0x56u, 0x08u},\r
896                         {0x58u, 0x04u},\r
897                         {0x59u, 0x04u},\r
898                         {0x5Bu, 0x04u},\r
899                         {0x5Cu, 0x11u},\r
900                         {0x5Du, 0x90u},\r
901                         {0x5Fu, 0x01u},\r
902                         {0x81u, 0x01u},\r
903                         {0x82u, 0x3Fu},\r
904                         {0x84u, 0x04u},\r
905                         {0x86u, 0x08u},\r
906                         {0x88u, 0x10u},\r
907                         {0x8Au, 0x20u},\r
908                         {0x8Cu, 0x10u},\r
909                         {0x8Eu, 0x20u},\r
910                         {0x8Fu, 0x01u},\r
911                         {0x90u, 0x04u},\r
912                         {0x92u, 0x08u},\r
913                         {0x95u, 0x01u},\r
914                         {0x98u, 0x01u},\r
915                         {0x99u, 0x01u},\r
916                         {0x9Au, 0x02u},\r
917                         {0x9Cu, 0x01u},\r
918                         {0x9Du, 0x01u},\r
919                         {0x9Eu, 0x02u},\r
920                         {0xA0u, 0x3Fu},\r
921                         {0xA1u, 0x02u},\r
922                         {0xA4u, 0x3Fu},\r
923                         {0xAAu, 0x3Fu},\r
924                         {0xAEu, 0x3Fu},\r
925                         {0xB0u, 0x30u},\r
926                         {0xB1u, 0x01u},\r
927                         {0xB3u, 0x02u},\r
928                         {0xB4u, 0x0Cu},\r
929                         {0xB6u, 0x03u},\r
930                         {0xBAu, 0xA2u},\r
931                         {0xBFu, 0x01u},\r
932                         {0xD6u, 0x08u},\r
933                         {0xD8u, 0x04u},\r
934                         {0xD9u, 0x04u},\r
935                         {0xDBu, 0x04u},\r
936                         {0xDCu, 0x91u},\r
937                         {0xDDu, 0x90u},\r
938                         {0xDFu, 0x01u},\r
939                         {0x00u, 0x04u},\r
940                         {0x01u, 0x01u},\r
941                         {0x02u, 0x04u},\r
942                         {0x03u, 0x02u},\r
943                         {0x07u, 0x40u},\r
944                         {0x08u, 0x02u},\r
945                         {0x09u, 0x20u},\r
946                         {0x0Au, 0x01u},\r
947                         {0x0Eu, 0x12u},\r
948                         {0x11u, 0x94u},\r
949                         {0x12u, 0x80u},\r
950                         {0x14u, 0x01u},\r
951                         {0x17u, 0x20u},\r
952                         {0x18u, 0x04u},\r
953                         {0x19u, 0x41u},\r
954                         {0x1Au, 0x01u},\r
955                         {0x1Bu, 0x02u},\r
956                         {0x1Eu, 0x12u},\r
957                         {0x1Fu, 0x84u},\r
958                         {0x21u, 0x01u},\r
959                         {0x22u, 0x04u},\r
960                         {0x25u, 0x40u},\r
961                         {0x27u, 0x25u},\r
962                         {0x2Bu, 0x80u},\r
963                         {0x2Du, 0x01u},\r
964                         {0x2Fu, 0x09u},\r
965                         {0x30u, 0xA8u},\r
966                         {0x36u, 0x80u},\r
967                         {0x37u, 0x15u},\r
968                         {0x38u, 0x20u},\r
969                         {0x39u, 0x50u},\r
970                         {0x3Au, 0x02u},\r
971                         {0x3Du, 0x14u},\r
972                         {0x58u, 0x84u},\r
973                         {0x59u, 0x20u},\r
974                         {0x5Eu, 0x40u},\r
975                         {0x60u, 0x02u},\r
976                         {0x61u, 0x04u},\r
977                         {0x62u, 0x18u},\r
978                         {0x64u, 0x01u},\r
979                         {0x85u, 0x20u},\r
980                         {0x8Bu, 0x01u},\r
981                         {0x8Du, 0x04u},\r
982                         {0x8Eu, 0x40u},\r
983                         {0x90u, 0x23u},\r
984                         {0x91u, 0x05u},\r
985                         {0x92u, 0x20u},\r
986                         {0x93u, 0x02u},\r
987                         {0x94u, 0x04u},\r
988                         {0x95u, 0x40u},\r
989                         {0x96u, 0x08u},\r
990                         {0x98u, 0x04u},\r
991                         {0x9Au, 0x04u},\r
992                         {0x9Bu, 0x10u},\r
993                         {0x9Du, 0x41u},\r
994                         {0x9Eu, 0x12u},\r
995                         {0x9Fu, 0x0Du},\r
996                         {0xA1u, 0x20u},\r
997                         {0xA2u, 0x90u},\r
998                         {0xA4u, 0xACu},\r
999                         {0xA6u, 0x28u},\r
1000                         {0xA7u, 0x80u},\r
1001                         {0xAEu, 0x24u},\r
1002                         {0xB1u, 0x01u},\r
1003                         {0xB4u, 0x11u},\r
1004                         {0xB6u, 0x40u},\r
1005                         {0xB7u, 0x20u},\r
1006                         {0xC0u, 0x1Fu},\r
1007                         {0xC2u, 0xABu},\r
1008                         {0xC4u, 0xCFu},\r
1009                         {0xCAu, 0xB1u},\r
1010                         {0xCCu, 0xFEu},\r
1011                         {0xCEu, 0x69u},\r
1012                         {0xD6u, 0x1Eu},\r
1013                         {0xD8u, 0x1Eu},\r
1014                         {0xE2u, 0x01u},\r
1015                         {0xE6u, 0x03u},\r
1016                         {0xEAu, 0x0Bu},\r
1017                         {0xEEu, 0x08u},\r
1018                         {0x01u, 0x02u},\r
1019                         {0x03u, 0x01u},\r
1020                         {0x04u, 0x06u},\r
1021                         {0x09u, 0x02u},\r
1022                         {0x0Bu, 0x01u},\r
1023                         {0x0Cu, 0x2Au},\r
1024                         {0x0Eu, 0x11u},\r
1025                         {0x10u, 0x19u},\r
1026                         {0x11u, 0x01u},\r
1027                         {0x12u, 0x24u},\r
1028                         {0x13u, 0x02u},\r
1029                         {0x14u, 0x20u},\r
1030                         {0x15u, 0x02u},\r
1031                         {0x16u, 0x18u},\r
1032                         {0x17u, 0x09u},\r
1033                         {0x18u, 0x09u},\r
1034                         {0x19u, 0x02u},\r
1035                         {0x1Au, 0x32u},\r
1036                         {0x1Bu, 0x05u},\r
1037                         {0x23u, 0x10u},\r
1038                         {0x26u, 0x40u},\r
1039                         {0x2Au, 0x80u},\r
1040                         {0x2Cu, 0x40u},\r
1041                         {0x2Eu, 0x80u},\r
1042                         {0x31u, 0x08u},\r
1043                         {0x32u, 0x38u},\r
1044                         {0x33u, 0x04u},\r
1045                         {0x34u, 0x07u},\r
1046                         {0x35u, 0x10u},\r
1047                         {0x36u, 0xC0u},\r
1048                         {0x37u, 0x03u},\r
1049                         {0x38u, 0x20u},\r
1050                         {0x3Au, 0x08u},\r
1051                         {0x3Bu, 0x80u},\r
1052                         {0x3Eu, 0x40u},\r
1053                         {0x54u, 0x09u},\r
1054                         {0x56u, 0x04u},\r
1055                         {0x58u, 0x04u},\r
1056                         {0x59u, 0x04u},\r
1057                         {0x5Bu, 0x04u},\r
1058                         {0x5Cu, 0x10u},\r
1059                         {0x5Fu, 0x01u},\r
1060                         {0x84u, 0x06u},\r
1061                         {0x86u, 0x09u},\r
1062                         {0x87u, 0xFFu},\r
1063                         {0x88u, 0x05u},\r
1064                         {0x89u, 0x50u},\r
1065                         {0x8Au, 0x0Au},\r
1066                         {0x8Bu, 0xA0u},\r
1067                         {0x8Cu, 0x60u},\r
1068                         {0x8Eu, 0x90u},\r
1069                         {0x90u, 0x0Fu},\r
1070                         {0x91u, 0x90u},\r
1071                         {0x92u, 0xF0u},\r
1072                         {0x93u, 0x60u},\r
1073                         {0x94u, 0x50u},\r
1074                         {0x95u, 0x30u},\r
1075                         {0x96u, 0xA0u},\r
1076                         {0x97u, 0xC0u},\r
1077                         {0x98u, 0x03u},\r
1078                         {0x99u, 0x09u},\r
1079                         {0x9Au, 0x0Cu},\r
1080                         {0x9Bu, 0x06u},\r
1081                         {0x9Du, 0x0Fu},\r
1082                         {0x9Fu, 0xF0u},\r
1083                         {0xA2u, 0xFFu},\r
1084                         {0xA3u, 0xFFu},\r
1085                         {0xA4u, 0x30u},\r
1086                         {0xA5u, 0x03u},\r
1087                         {0xA6u, 0xC0u},\r
1088                         {0xA7u, 0x0Cu},\r
1089                         {0xA8u, 0xFFu},\r
1090                         {0xA9u, 0x05u},\r
1091                         {0xABu, 0x0Au},\r
1092                         {0xAEu, 0xFFu},\r
1093                         {0xAFu, 0xFFu},\r
1094                         {0xB3u, 0xFFu},\r
1095                         {0xB4u, 0xFFu},\r
1096                         {0xBEu, 0x10u},\r
1097                         {0xBFu, 0x04u},\r
1098                         {0xD4u, 0x01u},\r
1099                         {0xD8u, 0x04u},\r
1100                         {0xD9u, 0x04u},\r
1101                         {0xDBu, 0x04u},\r
1102                         {0xDDu, 0x10u},\r
1103                         {0xDFu, 0x01u},\r
1104                         {0x01u, 0x10u},\r
1105                         {0x03u, 0x21u},\r
1106                         {0x04u, 0x04u},\r
1107                         {0x05u, 0x80u},\r
1108                         {0x08u, 0x20u},\r
1109                         {0x0Au, 0x80u},\r
1110                         {0x0Bu, 0x20u},\r
1111                         {0x0Cu, 0x10u},\r
1112                         {0x0Eu, 0x20u},\r
1113                         {0x0Fu, 0x80u},\r
1114                         {0x11u, 0x04u},\r
1115                         {0x12u, 0x45u},\r
1116                         {0x14u, 0x24u},\r
1117                         {0x17u, 0x40u},\r
1118                         {0x19u, 0x20u},\r
1119                         {0x1Cu, 0x04u},\r
1120                         {0x1Eu, 0x22u},\r
1121                         {0x1Fu, 0x04u},\r
1122                         {0x20u, 0x10u},\r
1123                         {0x24u, 0x08u},\r
1124                         {0x25u, 0x01u},\r
1125                         {0x26u, 0x08u},\r
1126                         {0x27u, 0x02u},\r
1127                         {0x28u, 0x20u},\r
1128                         {0x29u, 0x04u},\r
1129                         {0x2Au, 0x41u},\r
1130                         {0x2Bu, 0x05u},\r
1131                         {0x2Du, 0x02u},\r
1132                         {0x30u, 0x04u},\r
1133                         {0x32u, 0x44u},\r
1134                         {0x33u, 0x61u},\r
1135                         {0x35u, 0x10u},\r
1136                         {0x36u, 0x08u},\r
1137                         {0x37u, 0x02u},\r
1138                         {0x39u, 0x28u},\r
1139                         {0x3Au, 0x04u},\r
1140                         {0x3Bu, 0x20u},\r
1141                         {0x3Du, 0x02u},\r
1142                         {0x3Fu, 0x20u},\r
1143                         {0x59u, 0x40u},\r
1144                         {0x5Cu, 0x0Au},\r
1145                         {0x5Eu, 0x90u},\r
1146                         {0x64u, 0x40u},\r
1147                         {0x67u, 0x02u},\r
1148                         {0x8Bu, 0x04u},\r
1149                         {0x8Fu, 0x10u},\r
1150                         {0x91u, 0x3Cu},\r
1151                         {0x92u, 0x88u},\r
1152                         {0x93u, 0x02u},\r
1153                         {0x94u, 0x10u},\r
1154                         {0x97u, 0x80u},\r
1155                         {0x99u, 0x04u},\r
1156                         {0x9Bu, 0x01u},\r
1157                         {0x9Cu, 0x40u},\r
1158                         {0x9Du, 0x20u},\r
1159                         {0x9Eu, 0x01u},\r
1160                         {0x9Fu, 0x42u},\r
1161                         {0xA2u, 0x40u},\r
1162                         {0xA3u, 0x25u},\r
1163                         {0xA5u, 0x04u},\r
1164                         {0xA6u, 0x21u},\r
1165                         {0xA7u, 0x40u},\r
1166                         {0xAAu, 0x04u},\r
1167                         {0xABu, 0x05u},\r
1168                         {0xACu, 0x40u},\r
1169                         {0xAEu, 0x40u},\r
1170                         {0xB2u, 0x01u},\r
1171                         {0xB6u, 0x82u},\r
1172                         {0xB7u, 0x02u},\r
1173                         {0xC0u, 0xA7u},\r
1174                         {0xC2u, 0x7Eu},\r
1175                         {0xC4u, 0xEFu},\r
1176                         {0xCAu, 0x8Fu},\r
1177                         {0xCCu, 0xEFu},\r
1178                         {0xCEu, 0xA6u},\r
1179                         {0xD6u, 0xF8u},\r
1180                         {0xD8u, 0x90u},\r
1181                         {0xE0u, 0x10u},\r
1182                         {0xE2u, 0x81u},\r
1183                         {0xE6u, 0x43u},\r
1184                         {0xE8u, 0x40u},\r
1185                         {0xEAu, 0x12u},\r
1186                         {0xECu, 0x10u},\r
1187                         {0xEEu, 0xC0u},\r
1188                         {0x00u, 0x0Fu},\r
1189                         {0x02u, 0xF0u},\r
1190                         {0x04u, 0x09u},\r
1191                         {0x06u, 0x06u},\r
1192                         {0x07u, 0xFFu},\r
1193                         {0x08u, 0x05u},\r
1194                         {0x09u, 0x50u},\r
1195                         {0x0Au, 0x0Au},\r
1196                         {0x0Bu, 0xA0u},\r
1197                         {0x0Cu, 0x90u},\r
1198                         {0x0Eu, 0x60u},\r
1199                         {0x10u, 0x03u},\r
1200                         {0x11u, 0x60u},\r
1201                         {0x12u, 0x0Cu},\r
1202                         {0x13u, 0x90u},\r
1203                         {0x15u, 0x30u},\r
1204                         {0x16u, 0xFFu},\r
1205                         {0x17u, 0xC0u},\r
1206                         {0x18u, 0xFFu},\r
1207                         {0x19u, 0x06u},\r
1208                         {0x1Bu, 0x09u},\r
1209                         {0x1Du, 0x0Fu},\r
1210                         {0x1Fu, 0xF0u},\r
1211                         {0x23u, 0xFFu},\r
1212                         {0x24u, 0x30u},\r
1213                         {0x25u, 0x03u},\r
1214                         {0x26u, 0xC0u},\r
1215                         {0x27u, 0x0Cu},\r
1216                         {0x28u, 0x50u},\r
1217                         {0x29u, 0x05u},\r
1218                         {0x2Au, 0xA0u},\r
1219                         {0x2Bu, 0x0Au},\r
1220                         {0x2Cu, 0xFFu},\r
1221                         {0x2Du, 0xFFu},\r
1222                         {0x31u, 0xFFu},\r
1223                         {0x32u, 0xFFu},\r
1224                         {0x3Eu, 0x04u},\r
1225                         {0x3Fu, 0x01u},\r
1226                         {0x58u, 0x04u},\r
1227                         {0x59u, 0x04u},\r
1228                         {0x5Bu, 0x04u},\r
1229                         {0x5Fu, 0x01u},\r
1230                         {0x81u, 0x02u},\r
1231                         {0x84u, 0x04u},\r
1232                         {0x86u, 0x38u},\r
1233                         {0x88u, 0x10u},\r
1234                         {0x8Au, 0x20u},\r
1235                         {0x8Cu, 0x10u},\r
1236                         {0x8Du, 0x05u},\r
1237                         {0x8Eu, 0x20u},\r
1238                         {0x96u, 0x07u},\r
1239                         {0x98u, 0x09u},\r
1240                         {0x99u, 0x01u},\r
1241                         {0x9Au, 0x32u},\r
1242                         {0x9Bu, 0x04u},\r
1243                         {0x9Eu, 0x30u},\r
1244                         {0xA0u, 0x30u},\r
1245                         {0xA1u, 0x01u},\r
1246                         {0xA3u, 0x04u},\r
1247                         {0xAAu, 0x08u},\r
1248                         {0xACu, 0x3Au},\r
1249                         {0xAEu, 0x05u},\r
1250                         {0xB2u, 0x0Fu},\r
1251                         {0xB3u, 0x01u},\r
1252                         {0xB4u, 0x30u},\r
1253                         {0xB5u, 0x02u},\r
1254                         {0xB7u, 0x04u},\r
1255                         {0xBAu, 0x20u},\r
1256                         {0xBFu, 0x44u},\r
1257                         {0xD6u, 0x08u},\r
1258                         {0xD8u, 0x04u},\r
1259                         {0xD9u, 0x04u},\r
1260                         {0xDBu, 0x04u},\r
1261                         {0xDCu, 0x91u},\r
1262                         {0xDDu, 0x90u},\r
1263                         {0xDFu, 0x01u},\r
1264                         {0x01u, 0x10u},\r
1265                         {0x03u, 0x61u},\r
1266                         {0x05u, 0x90u},\r
1267                         {0x06u, 0x20u},\r
1268                         {0x08u, 0x12u},\r
1269                         {0x09u, 0x04u},\r
1270                         {0x0Cu, 0x20u},\r
1271                         {0x0Eu, 0x21u},\r
1272                         {0x10u, 0x09u},\r
1273                         {0x11u, 0x04u},\r
1274                         {0x14u, 0x10u},\r
1275                         {0x15u, 0x08u},\r
1276                         {0x16u, 0x8Au},\r
1277                         {0x19u, 0x08u},\r
1278                         {0x1Du, 0x14u},\r
1279                         {0x1Eu, 0x24u},\r
1280                         {0x21u, 0x01u},\r
1281                         {0x26u, 0x44u},\r
1282                         {0x27u, 0x04u},\r
1283                         {0x28u, 0x01u},\r
1284                         {0x29u, 0x04u},\r
1285                         {0x2Au, 0x01u},\r
1286                         {0x2Bu, 0x05u},\r
1287                         {0x2Fu, 0x40u},\r
1288                         {0x32u, 0x44u},\r
1289                         {0x33u, 0x21u},\r
1290                         {0x36u, 0x20u},\r
1291                         {0x39u, 0x28u},\r
1292                         {0x3Eu, 0x01u},\r
1293                         {0x3Fu, 0x80u},\r
1294                         {0x5Cu, 0x80u},\r
1295                         {0x66u, 0x40u},\r
1296                         {0x68u, 0x88u},\r
1297                         {0x69u, 0x24u},\r
1298                         {0x6Au, 0x08u},\r
1299                         {0x6Bu, 0x01u},\r
1300                         {0x71u, 0x60u},\r
1301                         {0x72u, 0x50u},\r
1302                         {0x79u, 0x10u},\r
1303                         {0x7Bu, 0x04u},\r
1304                         {0x80u, 0x80u},\r
1305                         {0x86u, 0x04u},\r
1306                         {0x8Cu, 0x02u},\r
1307                         {0x8Du, 0x04u},\r
1308                         {0x91u, 0x08u},\r
1309                         {0x92u, 0x81u},\r
1310                         {0x94u, 0x10u},\r
1311                         {0x95u, 0x22u},\r
1312                         {0x96u, 0x50u},\r
1313                         {0x99u, 0x80u},\r
1314                         {0x9Au, 0x28u},\r
1315                         {0x9Du, 0x68u},\r
1316                         {0x9Eu, 0xC2u},\r
1317                         {0x9Fu, 0x01u},\r
1318                         {0xA0u, 0x20u},\r
1319                         {0xA3u, 0x25u},\r
1320                         {0xA4u, 0x80u},\r
1321                         {0xA5u, 0x20u},\r
1322                         {0xA6u, 0x01u},\r
1323                         {0xA8u, 0x81u},\r
1324                         {0xAFu, 0x80u},\r
1325                         {0xB0u, 0x20u},\r
1326                         {0xB1u, 0x08u},\r
1327                         {0xC0u, 0xEFu},\r
1328                         {0xC2u, 0xEEu},\r
1329                         {0xC4u, 0xD7u},\r
1330                         {0xCAu, 0x8Fu},\r
1331                         {0xCCu, 0x2Fu},\r
1332                         {0xCEu, 0x96u},\r
1333                         {0xD6u, 0x10u},\r
1334                         {0xD8u, 0x10u},\r
1335                         {0xE2u, 0x20u},\r
1336                         {0xE6u, 0x27u},\r
1337                         {0xECu, 0x20u},\r
1338                         {0xEEu, 0x02u},\r
1339                         {0x00u, 0x03u},\r
1340                         {0x04u, 0x10u},\r
1341                         {0x06u, 0x23u},\r
1342                         {0x0Au, 0x20u},\r
1343                         {0x0Bu, 0x08u},\r
1344                         {0x0Cu, 0x2Bu},\r
1345                         {0x0Du, 0x0Au},\r
1346                         {0x0Eu, 0x14u},\r
1347                         {0x0Fu, 0x05u},\r
1348                         {0x13u, 0x20u},\r
1349                         {0x14u, 0x24u},\r
1350                         {0x16u, 0x0Bu},\r
1351                         {0x1Au, 0x5Cu},\r
1352                         {0x1Bu, 0x17u},\r
1353                         {0x1Eu, 0x03u},\r
1354                         {0x20u, 0x01u},\r
1355                         {0x22u, 0x02u},\r
1356                         {0x24u, 0x01u},\r
1357                         {0x25u, 0x09u},\r
1358                         {0x26u, 0x02u},\r
1359                         {0x27u, 0x02u},\r
1360                         {0x29u, 0x04u},\r
1361                         {0x2Au, 0x80u},\r
1362                         {0x2Bu, 0x08u},\r
1363                         {0x2Cu, 0x40u},\r
1364                         {0x2Du, 0x10u},\r
1365                         {0x2Eu, 0x80u},\r
1366                         {0x2Fu, 0x20u},\r
1367                         {0x32u, 0x03u},\r
1368                         {0x34u, 0x3Cu},\r
1369                         {0x35u, 0x0Fu},\r
1370                         {0x36u, 0xC0u},\r
1371                         {0x37u, 0x30u},\r
1372                         {0x3Au, 0x08u},\r
1373                         {0x3Eu, 0x40u},\r
1374                         {0x3Fu, 0x40u},\r
1375                         {0x58u, 0x04u},\r
1376                         {0x59u, 0x04u},\r
1377                         {0x5Bu, 0x04u},\r
1378                         {0x5Cu, 0x11u},\r
1379                         {0x5Fu, 0x01u},\r
1380                         {0x81u, 0x10u},\r
1381                         {0x84u, 0x06u},\r
1382                         {0x85u, 0x01u},\r
1383                         {0x86u, 0x09u},\r
1384                         {0x87u, 0x02u},\r
1385                         {0x89u, 0x10u},\r
1386                         {0x8Cu, 0x0Fu},\r
1387                         {0x8Du, 0x23u},\r
1388                         {0x8Eu, 0xF0u},\r
1389                         {0x8Fu, 0x4Cu},\r
1390                         {0x90u, 0x30u},\r
1391                         {0x92u, 0xC0u},\r
1392                         {0x93u, 0x40u},\r
1393                         {0x94u, 0x50u},\r
1394                         {0x96u, 0xA0u},\r
1395                         {0x98u, 0x60u},\r
1396                         {0x9Au, 0x90u},\r
1397                         {0x9Bu, 0x20u},\r
1398                         {0x9Du, 0x08u},\r
1399                         {0x9Fu, 0x04u},\r
1400                         {0xA1u, 0x02u},\r
1401                         {0xA3u, 0x01u},\r
1402                         {0xA4u, 0x03u},\r
1403                         {0xA5u, 0x10u},\r
1404                         {0xA6u, 0x0Cu},\r
1405                         {0xA8u, 0x05u},\r
1406                         {0xA9u, 0x10u},\r
1407                         {0xAAu, 0x0Au},\r
1408                         {0xADu, 0x04u},\r
1409                         {0xAFu, 0x08u},\r
1410                         {0xB0u, 0xFFu},\r
1411                         {0xB1u, 0x10u},\r
1412                         {0xB3u, 0x0Fu},\r
1413                         {0xB5u, 0x60u},\r
1414                         {0xB9u, 0x02u},\r
1415                         {0xBEu, 0x01u},\r
1416                         {0xBFu, 0x15u},\r
1417                         {0xD8u, 0x04u},\r
1418                         {0xD9u, 0x04u},\r
1419                         {0xDFu, 0x01u},\r
1420                         {0x00u, 0x04u},\r
1421                         {0x01u, 0x40u},\r
1422                         {0x05u, 0x10u},\r
1423                         {0x06u, 0xA2u},\r
1424                         {0x08u, 0x08u},\r
1425                         {0x09u, 0x20u},\r
1426                         {0x0Au, 0x50u},\r
1427                         {0x0Du, 0x08u},\r
1428                         {0x0Eu, 0x09u},\r
1429                         {0x0Fu, 0x08u},\r
1430                         {0x12u, 0x18u},\r
1431                         {0x13u, 0x08u},\r
1432                         {0x14u, 0x10u},\r
1433                         {0x15u, 0xA0u},\r
1434                         {0x16u, 0x40u},\r
1435                         {0x1Bu, 0x01u},\r
1436                         {0x1Cu, 0x02u},\r
1437                         {0x1Eu, 0x08u},\r
1438                         {0x1Fu, 0x08u},\r
1439                         {0x20u, 0x08u},\r
1440                         {0x21u, 0x04u},\r
1441                         {0x22u, 0x01u},\r
1442                         {0x24u, 0x0Au},\r
1443                         {0x26u, 0x20u},\r
1444                         {0x28u, 0x01u},\r
1445                         {0x29u, 0x68u},\r
1446                         {0x2Bu, 0x80u},\r
1447                         {0x2Cu, 0x24u},\r
1448                         {0x2Du, 0x40u},\r
1449                         {0x2Eu, 0x20u},\r
1450                         {0x30u, 0x80u},\r
1451                         {0x33u, 0x21u},\r
1452                         {0x34u, 0x01u},\r
1453                         {0x36u, 0x20u},\r
1454                         {0x38u, 0x18u},\r
1455                         {0x39u, 0xC2u},\r
1456                         {0x3Du, 0x80u},\r
1457                         {0x3Fu, 0x20u},\r
1458                         {0x5Cu, 0x80u},\r
1459                         {0x5Du, 0x05u},\r
1460                         {0x5Eu, 0x20u},\r
1461                         {0x64u, 0x02u},\r
1462                         {0x78u, 0x02u},\r
1463                         {0x7Au, 0x80u},\r
1464                         {0x84u, 0x10u},\r
1465                         {0x85u, 0x01u},\r
1466                         {0x87u, 0x08u},\r
1467                         {0x88u, 0x05u},\r
1468                         {0x8Bu, 0x08u},\r
1469                         {0x90u, 0x04u},\r
1470                         {0x91u, 0x84u},\r
1471                         {0x92u, 0x81u},\r
1472                         {0x96u, 0x42u},\r
1473                         {0x98u, 0x04u},\r
1474                         {0x99u, 0x90u},\r
1475                         {0x9Au, 0x08u},\r
1476                         {0x9Cu, 0x08u},\r
1477                         {0x9Eu, 0x10u},\r
1478                         {0xA1u, 0x40u},\r
1479                         {0xA2u, 0x98u},\r
1480                         {0xA3u, 0x30u},\r
1481                         {0xA4u, 0xA0u},\r
1482                         {0xA5u, 0x28u},\r
1483                         {0xA6u, 0x01u},\r
1484                         {0xA7u, 0x80u},\r
1485                         {0xAAu, 0x01u},\r
1486                         {0xABu, 0x01u},\r
1487                         {0xACu, 0x04u},\r
1488                         {0xADu, 0x41u},\r
1489                         {0xAEu, 0x05u},\r
1490                         {0xB2u, 0x10u},\r
1491                         {0xB4u, 0x80u},\r
1492                         {0xB7u, 0x40u},\r
1493                         {0xC0u, 0xF5u},\r
1494                         {0xC2u, 0xEEu},\r
1495                         {0xC4u, 0xF6u},\r
1496                         {0xCAu, 0x7Fu},\r
1497                         {0xCCu, 0xADu},\r
1498                         {0xCEu, 0x3Fu},\r
1499                         {0xD6u, 0xF0u},\r
1500                         {0xD8u, 0x10u},\r
1501                         {0xE4u, 0x80u},\r
1502                         {0xE6u, 0x21u},\r
1503                         {0xE8u, 0x80u},\r
1504                         {0xECu, 0x09u},\r
1505                         {0xEEu, 0xC0u},\r
1506                         {0x00u, 0x80u},\r
1507                         {0x02u, 0x40u},\r
1508                         {0x06u, 0x1Cu},\r
1509                         {0x0Cu, 0x80u},\r
1510                         {0x0Du, 0x0Au},\r
1511                         {0x0Eu, 0x41u},\r
1512                         {0x0Fu, 0x14u},\r
1513                         {0x14u, 0x24u},\r
1514                         {0x16u, 0x08u},\r
1515                         {0x18u, 0x80u},\r
1516                         {0x1Au, 0x40u},\r
1517                         {0x1Bu, 0x04u},\r
1518                         {0x1Cu, 0x40u},\r
1519                         {0x1Eu, 0x80u},\r
1520                         {0x1Fu, 0x10u},\r
1521                         {0x20u, 0x80u},\r
1522                         {0x22u, 0x42u},\r
1523                         {0x23u, 0x08u},\r
1524                         {0x26u, 0x20u},\r
1525                         {0x27u, 0x02u},\r
1526                         {0x28u, 0x10u},\r
1527                         {0x2Au, 0x20u},\r
1528                         {0x2Cu, 0x28u},\r
1529                         {0x2Eu, 0x14u},\r
1530                         {0x2Fu, 0x01u},\r
1531                         {0x30u, 0x01u},\r
1532                         {0x31u, 0x01u},\r
1533                         {0x32u, 0x3Cu},\r
1534                         {0x33u, 0x18u},\r
1535                         {0x34u, 0x02u},\r
1536                         {0x36u, 0xC0u},\r
1537                         {0x37u, 0x06u},\r
1538                         {0x3Au, 0x80u},\r
1539                         {0x3Fu, 0x44u},\r
1540                         {0x56u, 0x08u},\r
1541                         {0x58u, 0x04u},\r
1542                         {0x59u, 0x04u},\r
1543                         {0x5Bu, 0x04u},\r
1544                         {0x5Cu, 0x11u},\r
1545                         {0x5Du, 0x90u},\r
1546                         {0x5Fu, 0x01u},\r
1547                         {0x81u, 0x44u},\r
1548                         {0x83u, 0x08u},\r
1549                         {0x86u, 0x10u},\r
1550                         {0x87u, 0x17u},\r
1551                         {0x8Bu, 0x40u},\r
1552                         {0x8Cu, 0x0Au},\r
1553                         {0x8Du, 0x4Au},\r
1554                         {0x8Eu, 0x05u},\r
1555                         {0x8Fu, 0x05u},\r
1556                         {0x91u, 0x10u},\r
1557                         {0x92u, 0x20u},\r
1558                         {0x93u, 0x20u},\r
1559                         {0x94u, 0x09u},\r
1560                         {0x96u, 0x02u},\r
1561                         {0x97u, 0x20u},\r
1562                         {0x9Au, 0x07u},\r
1563                         {0xA0u, 0x04u},\r
1564                         {0xA2u, 0x08u},\r
1565                         {0xA5u, 0x49u},\r
1566                         {0xA7u, 0x02u},\r
1567                         {0xAAu, 0x08u},\r
1568                         {0xABu, 0x08u},\r
1569                         {0xACu, 0x10u},\r
1570                         {0xAEu, 0x20u},\r
1571                         {0xB0u, 0x30u},\r
1572                         {0xB1u, 0x30u},\r
1573                         {0xB3u, 0x0Fu},\r
1574                         {0xB4u, 0x0Fu},\r
1575                         {0xB7u, 0x40u},\r
1576                         {0xBEu, 0x01u},\r
1577                         {0xBFu, 0x41u},\r
1578                         {0xD6u, 0x08u},\r
1579                         {0xD8u, 0x04u},\r
1580                         {0xD9u, 0x04u},\r
1581                         {0xDBu, 0x04u},\r
1582                         {0xDCu, 0x11u},\r
1583                         {0xDDu, 0x90u},\r
1584                         {0xDFu, 0x01u},\r
1585                         {0x00u, 0x84u},\r
1586                         {0x01u, 0x08u},\r
1587                         {0x02u, 0x40u},\r
1588                         {0x04u, 0x40u},\r
1589                         {0x06u, 0x10u},\r
1590                         {0x09u, 0x08u},\r
1591                         {0x0Au, 0x05u},\r
1592                         {0x0Du, 0x08u},\r
1593                         {0x0Eu, 0x48u},\r
1594                         {0x10u, 0x54u},\r
1595                         {0x11u, 0x80u},\r
1596                         {0x15u, 0x85u},\r
1597                         {0x16u, 0x24u},\r
1598                         {0x19u, 0x0Au},\r
1599                         {0x1Au, 0x05u},\r
1600                         {0x1Bu, 0x40u},\r
1601                         {0x1Eu, 0x08u},\r
1602                         {0x1Fu, 0x21u},\r
1603                         {0x20u, 0x82u},\r
1604                         {0x22u, 0x04u},\r
1605                         {0x25u, 0x06u},\r
1606                         {0x26u, 0x88u},\r
1607                         {0x29u, 0x08u},\r
1608                         {0x2Au, 0x40u},\r
1609                         {0x2Bu, 0x80u},\r
1610                         {0x2Cu, 0x60u},\r
1611                         {0x2Du, 0x02u},\r
1612                         {0x2Eu, 0x10u},\r
1613                         {0x30u, 0x80u},\r
1614                         {0x31u, 0x20u},\r
1615                         {0x34u, 0x08u},\r
1616                         {0x37u, 0x01u},\r
1617                         {0x39u, 0x80u},\r
1618                         {0x3Cu, 0x40u},\r
1619                         {0x3Du, 0x89u},\r
1620                         {0x3Eu, 0x20u},\r
1621                         {0x58u, 0x80u},\r
1622                         {0x5Du, 0x40u},\r
1623                         {0x62u, 0x40u},\r
1624                         {0x64u, 0x02u},\r
1625                         {0x65u, 0x80u},\r
1626                         {0x69u, 0x80u},\r
1627                         {0x6Au, 0x80u},\r
1628                         {0x6Bu, 0x01u},\r
1629                         {0x81u, 0x40u},\r
1630                         {0x82u, 0x24u},\r
1631                         {0x83u, 0x10u},\r
1632                         {0x84u, 0x01u},\r
1633                         {0x85u, 0x02u},\r
1634                         {0x86u, 0x08u},\r
1635                         {0x88u, 0x10u},\r
1636                         {0x8Cu, 0x02u},\r
1637                         {0x8Du, 0x10u},\r
1638                         {0x8Eu, 0x10u},\r
1639                         {0xC0u, 0xADu},\r
1640                         {0xC2u, 0x77u},\r
1641                         {0xC4u, 0xDFu},\r
1642                         {0xCAu, 0x6Bu},\r
1643                         {0xCCu, 0xCCu},\r
1644                         {0xCEu, 0xF8u},\r
1645                         {0xD6u, 0x18u},\r
1646                         {0xD8u, 0x18u},\r
1647                         {0xE0u, 0x60u},\r
1648                         {0xE2u, 0x10u},\r
1649                         {0xE4u, 0x10u},\r
1650                         {0xE6u, 0x04u},\r
1651                         {0x01u, 0x5Cu},\r
1652                         {0x05u, 0x11u},\r
1653                         {0x07u, 0x22u},\r
1654                         {0x09u, 0x50u},\r
1655                         {0x0Bu, 0x0Cu},\r
1656                         {0x0Du, 0x0Cu},\r
1657                         {0x0Fu, 0x50u},\r
1658                         {0x15u, 0x30u},\r
1659                         {0x17u, 0x0Fu},\r
1660                         {0x19u, 0x54u},\r
1661                         {0x1Bu, 0x08u},\r
1662                         {0x1Du, 0x5Cu},\r
1663                         {0x21u, 0x08u},\r
1664                         {0x27u, 0x40u},\r
1665                         {0x29u, 0x21u},\r
1666                         {0x2Bu, 0x1Eu},\r
1667                         {0x2Du, 0x24u},\r
1668                         {0x2Fu, 0x10u},\r
1669                         {0x31u, 0x30u},\r
1670                         {0x33u, 0x40u},\r
1671                         {0x35u, 0x0Fu},\r
1672                         {0x3Bu, 0x02u},\r
1673                         {0x3Fu, 0x04u},\r
1674                         {0x40u, 0x23u},\r
1675                         {0x41u, 0x06u},\r
1676                         {0x42u, 0x40u},\r
1677                         {0x44u, 0x01u},\r
1678                         {0x45u, 0xBDu},\r
1679                         {0x46u, 0xF0u},\r
1680                         {0x47u, 0xCEu},\r
1681                         {0x48u, 0x3Bu},\r
1682                         {0x49u, 0xFFu},\r
1683                         {0x4Au, 0xFFu},\r
1684                         {0x4Bu, 0xFFu},\r
1685                         {0x4Cu, 0x22u},\r
1686                         {0x4Eu, 0xF0u},\r
1687                         {0x4Fu, 0x08u},\r
1688                         {0x50u, 0x04u},\r
1689                         {0x54u, 0x40u},\r
1690                         {0x56u, 0x04u},\r
1691                         {0x59u, 0x04u},\r
1692                         {0x5Au, 0x04u},\r
1693                         {0x5Bu, 0x04u},\r
1694                         {0x5Fu, 0x01u},\r
1695                         {0x62u, 0xC0u},\r
1696                         {0x64u, 0x40u},\r
1697                         {0x65u, 0x01u},\r
1698                         {0x66u, 0x10u},\r
1699                         {0x67u, 0x11u},\r
1700                         {0x68u, 0xC0u},\r
1701                         {0x69u, 0x01u},\r
1702                         {0x6Bu, 0x11u},\r
1703                         {0x6Cu, 0x40u},\r
1704                         {0x6Du, 0x01u},\r
1705                         {0x6Eu, 0x40u},\r
1706                         {0x6Fu, 0x01u},\r
1707                         {0x80u, 0x20u},\r
1708                         {0x82u, 0x01u},\r
1709                         {0x84u, 0x10u},\r
1710                         {0x85u, 0x04u},\r
1711                         {0x86u, 0x42u},\r
1712                         {0x87u, 0x23u},\r
1713                         {0x89u, 0x48u},\r
1714                         {0x8Bu, 0x03u},\r
1715                         {0x8Cu, 0x02u},\r
1716                         {0x90u, 0x02u},\r
1717                         {0x91u, 0x80u},\r
1718                         {0x94u, 0x44u},\r
1719                         {0x96u, 0x10u},\r
1720                         {0x97u, 0x7Cu},\r
1721                         {0x98u, 0x02u},\r
1722                         {0x99u, 0x11u},\r
1723                         {0x9Bu, 0x02u},\r
1724                         {0x9Cu, 0x02u},\r
1725                         {0xA0u, 0x08u},\r
1726                         {0xA3u, 0x02u},\r
1727                         {0xA5u, 0x80u},\r
1728                         {0xA8u, 0x0Eu},\r
1729                         {0xA9u, 0x70u},\r
1730                         {0xAAu, 0x30u},\r
1731                         {0xACu, 0x02u},\r
1732                         {0xAFu, 0x01u},\r
1733                         {0xB0u, 0x01u},\r
1734                         {0xB3u, 0x70u},\r
1735                         {0xB4u, 0x7Eu},\r
1736                         {0xB5u, 0x0Fu},\r
1737                         {0xB7u, 0x80u},\r
1738                         {0xB8u, 0x20u},\r
1739                         {0xB9u, 0x80u},\r
1740                         {0xBEu, 0x10u},\r
1741                         {0xBFu, 0x04u},\r
1742                         {0xD8u, 0x04u},\r
1743                         {0xD9u, 0x04u},\r
1744                         {0xDFu, 0x01u},\r
1745                         {0x04u, 0x04u},\r
1746                         {0x05u, 0x02u},\r
1747                         {0x06u, 0x02u},\r
1748                         {0x0Cu, 0xA1u},\r
1749                         {0x0Du, 0x08u},\r
1750                         {0x0Fu, 0x40u},\r
1751                         {0x15u, 0x60u},\r
1752                         {0x17u, 0x02u},\r
1753                         {0x1Fu, 0x22u},\r
1754                         {0x20u, 0x18u},\r
1755                         {0x21u, 0x10u},\r
1756                         {0x22u, 0x20u},\r
1757                         {0x23u, 0x44u},\r
1758                         {0x26u, 0x84u},\r
1759                         {0x27u, 0x0Au},\r
1760                         {0x28u, 0x01u},\r
1761                         {0x29u, 0x04u},\r
1762                         {0x2Au, 0x01u},\r
1763                         {0x2Bu, 0x04u},\r
1764                         {0x2Du, 0x02u},\r
1765                         {0x2Eu, 0x20u},\r
1766                         {0x2Fu, 0x22u},\r
1767                         {0x30u, 0xA0u},\r
1768                         {0x31u, 0x08u},\r
1769                         {0x36u, 0x21u},\r
1770                         {0x37u, 0x08u},\r
1771                         {0x39u, 0x50u},\r
1772                         {0x3Au, 0x02u},\r
1773                         {0x3Bu, 0x04u},\r
1774                         {0x3Cu, 0x24u},\r
1775                         {0x40u, 0x04u},\r
1776                         {0x41u, 0x09u},\r
1777                         {0x42u, 0x01u},\r
1778                         {0x48u, 0x04u},\r
1779                         {0x49u, 0x06u},\r
1780                         {0x51u, 0x20u},\r
1781                         {0x52u, 0x01u},\r
1782                         {0x53u, 0x04u},\r
1783                         {0x60u, 0x92u},\r
1784                         {0x61u, 0x20u},\r
1785                         {0x82u, 0x20u},\r
1786                         {0x84u, 0x04u},\r
1787                         {0x86u, 0x01u},\r
1788                         {0x8Cu, 0x02u},\r
1789                         {0x8Du, 0x04u},\r
1790                         {0x8Eu, 0x04u},\r
1791                         {0x90u, 0x04u},\r
1792                         {0x91u, 0x52u},\r
1793                         {0x97u, 0x48u},\r
1794                         {0x9Au, 0x02u},\r
1795                         {0x9Cu, 0x80u},\r
1796                         {0x9Du, 0x02u},\r
1797                         {0x9Eu, 0x01u},\r
1798                         {0xA0u, 0xB0u},\r
1799                         {0xA1u, 0x08u},\r
1800                         {0xA2u, 0x01u},\r
1801                         {0xA3u, 0x04u},\r
1802                         {0xA6u, 0xA0u},\r
1803                         {0xABu, 0x01u},\r
1804                         {0xB2u, 0x08u},\r
1805                         {0xB3u, 0x20u},\r
1806                         {0xB4u, 0x04u},\r
1807                         {0xC0u, 0xB0u},\r
1808                         {0xC2u, 0xF0u},\r
1809                         {0xC4u, 0xD0u},\r
1810                         {0xCAu, 0xFFu},\r
1811                         {0xCCu, 0xEEu},\r
1812                         {0xCEu, 0x6Fu},\r
1813                         {0xD0u, 0x0Fu},\r
1814                         {0xD2u, 0x04u},\r
1815                         {0xD8u, 0x0Fu},\r
1816                         {0xE2u, 0x44u},\r
1817                         {0xE4u, 0x02u},\r
1818                         {0xE8u, 0x01u},\r
1819                         {0x00u, 0x03u},\r
1820                         {0x01u, 0xC0u},\r
1821                         {0x02u, 0x0Cu},\r
1822                         {0x03u, 0x01u},\r
1823                         {0x04u, 0x05u},\r
1824                         {0x06u, 0x0Au},\r
1825                         {0x07u, 0xFFu},\r
1826                         {0x08u, 0x40u},\r
1827                         {0x09u, 0xC0u},\r
1828                         {0x0Au, 0x1Fu},\r
1829                         {0x0Bu, 0x08u},\r
1830                         {0x0Cu, 0x10u},\r
1831                         {0x0Du, 0x80u},\r
1832                         {0x0Eu, 0x2Fu},\r
1833                         {0x13u, 0x9Fu},\r
1834                         {0x14u, 0x06u},\r
1835                         {0x15u, 0x7Fu},\r
1836                         {0x16u, 0x09u},\r
1837                         {0x17u, 0x80u},\r
1838                         {0x19u, 0x1Fu},\r
1839                         {0x1Au, 0x70u},\r
1840                         {0x1Bu, 0x20u},\r
1841                         {0x1Fu, 0x60u},\r
1842                         {0x21u, 0xC0u},\r
1843                         {0x23u, 0x02u},\r
1844                         {0x24u, 0x20u},\r
1845                         {0x25u, 0xC0u},\r
1846                         {0x26u, 0x4Fu},\r
1847                         {0x27u, 0x04u},\r
1848                         {0x28u, 0x0Fu},\r
1849                         {0x2Du, 0x90u},\r
1850                         {0x2Fu, 0x40u},\r
1851                         {0x31u, 0xFFu},\r
1852                         {0x34u, 0x7Fu},\r
1853                         {0x3Fu, 0x01u},\r
1854                         {0x58u, 0x04u},\r
1855                         {0x59u, 0x04u},\r
1856                         {0x5Cu, 0x01u},\r
1857                         {0x5Fu, 0x01u},\r
1858                         {0x80u, 0xFFu},\r
1859                         {0x81u, 0x04u},\r
1860                         {0x83u, 0x20u},\r
1861                         {0x84u, 0x33u},\r
1862                         {0x85u, 0x39u},\r
1863                         {0x86u, 0xCCu},\r
1864                         {0x87u, 0x06u},\r
1865                         {0x88u, 0x0Fu},\r
1866                         {0x8Au, 0xF0u},\r
1867                         {0x8Bu, 0x46u},\r
1868                         {0x8Du, 0x46u},\r
1869                         {0x8Eu, 0xFFu},\r
1870                         {0x90u, 0x69u},\r
1871                         {0x92u, 0x96u},\r
1872                         {0x95u, 0x01u},\r
1873                         {0x97u, 0x5Eu},\r
1874                         {0x98u, 0x55u},\r
1875                         {0x99u, 0x42u},\r
1876                         {0x9Au, 0xAAu},\r
1877                         {0x9Bu, 0x04u},\r
1878                         {0x9Du, 0x46u},\r
1879                         {0xA1u, 0x46u},\r
1880                         {0xA2u, 0xFFu},\r
1881                         {0xA4u, 0xFFu},\r
1882                         {0xA5u, 0x77u},\r
1883                         {0xA7u, 0x08u},\r
1884                         {0xAAu, 0xFFu},\r
1885                         {0xADu, 0x42u},\r
1886                         {0xB3u, 0x70u},\r
1887                         {0xB4u, 0xFFu},\r
1888                         {0xB5u, 0x0Fu},\r
1889                         {0xB9u, 0x20u},\r
1890                         {0xBAu, 0x20u},\r
1891                         {0xBBu, 0x0Cu},\r
1892                         {0xD6u, 0x02u},\r
1893                         {0xD7u, 0x20u},\r
1894                         {0xD8u, 0x04u},\r
1895                         {0xD9u, 0x04u},\r
1896                         {0xDBu, 0x04u},\r
1897                         {0xDCu, 0x01u},\r
1898                         {0xDFu, 0x01u},\r
1899                         {0x00u, 0x01u},\r
1900                         {0x01u, 0x20u},\r
1901                         {0x02u, 0x10u},\r
1902                         {0x03u, 0x01u},\r
1903                         {0x04u, 0x2Au},\r
1904                         {0x06u, 0x04u},\r
1905                         {0x07u, 0x01u},\r
1906                         {0x08u, 0x02u},\r
1907                         {0x09u, 0x20u},\r
1908                         {0x0Eu, 0x28u},\r
1909                         {0x11u, 0x05u},\r
1910                         {0x12u, 0x04u},\r
1911                         {0x15u, 0x04u},\r
1912                         {0x17u, 0x10u},\r
1913                         {0x18u, 0x08u},\r
1914                         {0x19u, 0x20u},\r
1915                         {0x1Eu, 0x08u},\r
1916                         {0x1Fu, 0x20u},\r
1917                         {0x20u, 0x2Cu},\r
1918                         {0x21u, 0x08u},\r
1919                         {0x22u, 0x08u},\r
1920                         {0x26u, 0x01u},\r
1921                         {0x28u, 0x10u},\r
1922                         {0x2Au, 0x82u},\r
1923                         {0x2Cu, 0xA0u},\r
1924                         {0x2Du, 0x40u},\r
1925                         {0x30u, 0xA0u},\r
1926                         {0x31u, 0x08u},\r
1927                         {0x34u, 0x10u},\r
1928                         {0x35u, 0x02u},\r
1929                         {0x36u, 0xA8u},\r
1930                         {0x37u, 0x08u},\r
1931                         {0x38u, 0x04u},\r
1932                         {0x39u, 0x50u},\r
1933                         {0x3Au, 0x01u},\r
1934                         {0x3Bu, 0x01u},\r
1935                         {0x3Cu, 0x04u},\r
1936                         {0x3Eu, 0x92u},\r
1937                         {0x3Fu, 0x48u},\r
1938                         {0x63u, 0x02u},\r
1939                         {0x68u, 0xA8u},\r
1940                         {0x69u, 0x50u},\r
1941                         {0x6Au, 0x10u},\r
1942                         {0x72u, 0x02u},\r
1943                         {0x88u, 0x80u},\r
1944                         {0x8Bu, 0x04u},\r
1945                         {0x90u, 0x23u},\r
1946                         {0x91u, 0x07u},\r
1947                         {0x95u, 0x40u},\r
1948                         {0x98u, 0x02u},\r
1949                         {0x9Au, 0x10u},\r
1950                         {0x9Bu, 0x11u},\r
1951                         {0x9Eu, 0x02u},\r
1952                         {0x9Fu, 0x08u},\r
1953                         {0xA1u, 0x20u},\r
1954                         {0xA2u, 0x10u},\r
1955                         {0xA3u, 0x01u},\r
1956                         {0xA4u, 0xACu},\r
1957                         {0xA6u, 0x20u},\r
1958                         {0xABu, 0x58u},\r
1959                         {0xB1u, 0x01u},\r
1960                         {0xB3u, 0x04u},\r
1961                         {0xB4u, 0x80u},\r
1962                         {0xB6u, 0x10u},\r
1963                         {0xC0u, 0xFFu},\r
1964                         {0xC2u, 0x6Au},\r
1965                         {0xC4u, 0x6Eu},\r
1966                         {0xCAu, 0xDBu},\r
1967                         {0xCCu, 0xFEu},\r
1968                         {0xCEu, 0xFFu},\r
1969                         {0xD8u, 0x08u},\r
1970                         {0xE2u, 0x28u},\r
1971                         {0xE8u, 0x04u},\r
1972                         {0xEEu, 0x01u},\r
1973                         {0x39u, 0x20u},\r
1974                         {0x3Fu, 0x10u},\r
1975                         {0x59u, 0x04u},\r
1976                         {0x5Fu, 0x01u},\r
1977                         {0x27u, 0x08u},\r
1978                         {0x87u, 0x08u},\r
1979                         {0x88u, 0x08u},\r
1980                         {0x90u, 0x04u},\r
1981                         {0x96u, 0x10u},\r
1982                         {0x97u, 0x80u},\r
1983                         {0x9Cu, 0x18u},\r
1984                         {0x9Du, 0xC0u},\r
1985                         {0xA6u, 0x20u},\r
1986                         {0xA7u, 0x40u},\r
1987                         {0xA8u, 0x04u},\r
1988                         {0xA9u, 0x04u},\r
1989                         {0xAAu, 0x01u},\r
1990                         {0xB0u, 0x02u},\r
1991                         {0xB1u, 0x02u},\r
1992                         {0xB5u, 0x10u},\r
1993                         {0xE0u, 0x80u},\r
1994                         {0xE8u, 0xE0u},\r
1995                         {0xEAu, 0x10u},\r
1996                         {0x80u, 0x04u},\r
1997                         {0x84u, 0x10u},\r
1998                         {0x86u, 0x20u},\r
1999                         {0x90u, 0x04u},\r
2000                         {0x9Cu, 0x10u},\r
2001                         {0xA6u, 0x20u},\r
2002                         {0xAAu, 0x10u},\r
2003                         {0xB1u, 0xC0u},\r
2004                         {0xB3u, 0x40u},\r
2005                         {0xB7u, 0x40u},\r
2006                         {0xE8u, 0x80u},\r
2007                         {0xECu, 0xC0u},\r
2008                         {0x12u, 0x08u},\r
2009                         {0x16u, 0x80u},\r
2010                         {0x17u, 0x80u},\r
2011                         {0x33u, 0x04u},\r
2012                         {0x35u, 0x08u},\r
2013                         {0x36u, 0x80u},\r
2014                         {0x3Au, 0x81u},\r
2015                         {0x3Du, 0x04u},\r
2016                         {0x3Fu, 0x20u},\r
2017                         {0x43u, 0x20u},\r
2018                         {0x52u, 0x20u},\r
2019                         {0x5Bu, 0x01u},\r
2020                         {0x60u, 0x20u},\r
2021                         {0x64u, 0x08u},\r
2022                         {0x65u, 0x40u},\r
2023                         {0x82u, 0x01u},\r
2024                         {0x85u, 0x40u},\r
2025                         {0x87u, 0x01u},\r
2026                         {0xC4u, 0xE0u},\r
2027                         {0xCCu, 0xE0u},\r
2028                         {0xCEu, 0xF0u},\r
2029                         {0xD0u, 0x10u},\r
2030                         {0xD4u, 0x20u},\r
2031                         {0xD6u, 0xC0u},\r
2032                         {0xD8u, 0xC0u},\r
2033                         {0xE2u, 0x60u},\r
2034                         {0xE6u, 0x10u},\r
2035                         {0x33u, 0x18u},\r
2036                         {0x35u, 0x04u},\r
2037                         {0x37u, 0x80u},\r
2038                         {0x39u, 0x80u},\r
2039                         {0x54u, 0x02u},\r
2040                         {0x57u, 0x10u},\r
2041                         {0x5Bu, 0x40u},\r
2042                         {0x63u, 0x80u},\r
2043                         {0x95u, 0x04u},\r
2044                         {0x9Bu, 0xD0u},\r
2045                         {0x9Cu, 0x20u},\r
2046                         {0x9Du, 0x08u},\r
2047                         {0x9Fu, 0x04u},\r
2048                         {0xA6u, 0x80u},\r
2049                         {0xA7u, 0x20u},\r
2050                         {0xA8u, 0x08u},\r
2051                         {0xAAu, 0x08u},\r
2052                         {0xABu, 0x50u},\r
2053                         {0xAEu, 0x20u},\r
2054                         {0xB7u, 0x10u},\r
2055                         {0xCCu, 0xF0u},\r
2056                         {0xCEu, 0x10u},\r
2057                         {0xD4u, 0xC0u},\r
2058                         {0xD6u, 0x20u},\r
2059                         {0xD8u, 0x40u},\r
2060                         {0xEEu, 0xE0u},\r
2061                         {0x12u, 0x80u},\r
2062                         {0x32u, 0x10u},\r
2063                         {0x82u, 0x10u},\r
2064                         {0x83u, 0x50u},\r
2065                         {0x85u, 0x08u},\r
2066                         {0x8Bu, 0x08u},\r
2067                         {0x8Cu, 0x20u},\r
2068                         {0x95u, 0x84u},\r
2069                         {0x9Du, 0x0Cu},\r
2070                         {0x9Fu, 0x04u},\r
2071                         {0xA6u, 0x80u},\r
2072                         {0xA7u, 0x78u},\r
2073                         {0xA8u, 0x22u},\r
2074                         {0xC4u, 0x10u},\r
2075                         {0xCCu, 0x10u},\r
2076                         {0xE2u, 0x20u},\r
2077                         {0xE6u, 0xB0u},\r
2078                         {0xEAu, 0x20u},\r
2079                         {0xEEu, 0x20u},\r
2080                         {0x81u, 0x44u},\r
2081                         {0x95u, 0x84u},\r
2082                         {0x9Du, 0x04u},\r
2083                         {0xA0u, 0x20u},\r
2084                         {0xABu, 0x04u},\r
2085                         {0xAFu, 0x20u},\r
2086                         {0xE2u, 0x80u},\r
2087                         {0xE6u, 0x80u},\r
2088                         {0xEAu, 0x80u},\r
2089                         {0xEEu, 0x10u},\r
2090                         {0x08u, 0x04u},\r
2091                         {0x09u, 0x80u},\r
2092                         {0x0Fu, 0x20u},\r
2093                         {0x12u, 0x20u},\r
2094                         {0x17u, 0x01u},\r
2095                         {0x50u, 0x04u},\r
2096                         {0x57u, 0x20u},\r
2097                         {0x58u, 0x20u},\r
2098                         {0x5Fu, 0x40u},\r
2099                         {0x80u, 0x40u},\r
2100                         {0xC2u, 0x0Eu},\r
2101                         {0xC4u, 0x0Cu},\r
2102                         {0xD4u, 0x07u},\r
2103                         {0xD6u, 0x04u},\r
2104                         {0x00u, 0x40u},\r
2105                         {0x02u, 0x10u},\r
2106                         {0x05u, 0x20u},\r
2107                         {0x07u, 0x20u},\r
2108                         {0x08u, 0x02u},\r
2109                         {0x09u, 0x20u},\r
2110                         {0x0Du, 0x01u},\r
2111                         {0x0Eu, 0x02u},\r
2112                         {0x83u, 0x10u},\r
2113                         {0x8Au, 0x10u},\r
2114                         {0x8Bu, 0x60u},\r
2115                         {0x94u, 0x40u},\r
2116                         {0x97u, 0x40u},\r
2117                         {0x9Bu, 0x01u},\r
2118                         {0xA2u, 0x20u},\r
2119                         {0xA3u, 0x10u},\r
2120                         {0xA7u, 0x20u},\r
2121                         {0xA8u, 0x04u},\r
2122                         {0xACu, 0x20u},\r
2123                         {0xB0u, 0x04u},\r
2124                         {0xB5u, 0x80u},\r
2125                         {0xC0u, 0x0Fu},\r
2126                         {0xC2u, 0x0Fu},\r
2127                         {0xE0u, 0x05u},\r
2128                         {0xE6u, 0x04u},\r
2129                         {0xEAu, 0x08u},\r
2130                         {0xEEu, 0x01u},\r
2131                         {0x82u, 0x05u},\r
2132                         {0x84u, 0x02u},\r
2133                         {0x8Bu, 0x11u},\r
2134                         {0x91u, 0x02u},\r
2135                         {0x98u, 0x02u},\r
2136                         {0x99u, 0x20u},\r
2137                         {0x9Bu, 0x21u},\r
2138                         {0xA1u, 0x20u},\r
2139                         {0xA2u, 0x01u},\r
2140                         {0xAEu, 0x20u},\r
2141                         {0xE2u, 0x04u},\r
2142                         {0xE6u, 0x04u},\r
2143                         {0x0Bu, 0x21u},\r
2144                         {0x0Eu, 0x08u},\r
2145                         {0x0Fu, 0x20u},\r
2146                         {0x83u, 0x11u},\r
2147                         {0x85u, 0x01u},\r
2148                         {0x8Cu, 0x04u},\r
2149                         {0x91u, 0x02u},\r
2150                         {0x97u, 0x20u},\r
2151                         {0x99u, 0x20u},\r
2152                         {0xA6u, 0x04u},\r
2153                         {0xAFu, 0x20u},\r
2154                         {0xB5u, 0x20u},\r
2155                         {0xC2u, 0x0Fu},\r
2156                         {0xE6u, 0x02u},\r
2157                         {0xEEu, 0x02u},\r
2158                         {0x67u, 0x80u},\r
2159                         {0x87u, 0x40u},\r
2160                         {0x89u, 0x04u},\r
2161                         {0x95u, 0x04u},\r
2162                         {0xA0u, 0x20u},\r
2163                         {0xD8u, 0x80u},\r
2164                         {0xE2u, 0x10u},\r
2165                         {0x06u, 0x40u},\r
2166                         {0x50u, 0x20u},\r
2167                         {0x57u, 0x80u},\r
2168                         {0x86u, 0x40u},\r
2169                         {0x8Fu, 0x80u},\r
2170                         {0xA0u, 0x20u},\r
2171                         {0xC0u, 0x20u},\r
2172                         {0xD4u, 0x60u},\r
2173                         {0xE0u, 0x10u},\r
2174                         {0x94u, 0x04u},\r
2175                         {0xB5u, 0x20u},\r
2176                         {0xEAu, 0x08u},\r
2177                         {0x00u, 0x04u},\r
2178                         {0x94u, 0x04u},\r
2179                         {0xC0u, 0x08u},\r
2180                         {0x10u, 0x03u},\r
2181                         {0x1Au, 0x03u},\r
2182                         {0x00u, 0xFDu},\r
2183                         {0x01u, 0xBFu},\r
2184                         {0x02u, 0x2Au},\r
2185                         {0x10u, 0x95u},\r
2186                 };\r
2187 \r
2188 \r
2189 \r
2190                 CYPACKED typedef struct {\r
2191                         void CYFAR *address;\r
2192                         uint16 size;\r
2193                 } CYPACKED_ATTR cfg_memset_t;\r
2194 \r
2195 \r
2196                 CYPACKED typedef struct {\r
2197                         void CYFAR *dest;\r
2198                         const void CYCODE *src;\r
2199                         uint16 size;\r
2200                 } CYPACKED_ATTR cfg_memcpy_t;\r
2201 \r
2202                 static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
2203                         /* address, size */\r
2204                         {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
2205                         {(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
2206                         {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
2207                         {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
2208                         {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
2209                         {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
2210                         {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
2211                 };\r
2212 \r
2213                 /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
2214                 static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
2215                         0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};\r
2216 \r
2217                 static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
2218                         /* dest, src, size */\r
2219                         {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
2220                 };\r
2221 \r
2222                 uint8 CYDATA i;\r
2223 \r
2224                 /* Zero out critical memory blocks before beginning configuration */\r
2225                 for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)\r
2226                 {\r
2227                         const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];\r
2228                         CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));\r
2229                 }\r
2230 \r
2231                 /* Copy device configuration data into registers */\r
2232                 for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)\r
2233                 {\r
2234                         const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];\r
2235                         void * CYDATA destPtr = mc->dest;\r
2236                         const void CYCODE * CYDATA srcPtr = mc->src;\r
2237                         uint16 CYDATA numBytes = mc->size;\r
2238                         CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);\r
2239                 }\r
2240 \r
2241                 cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);\r
2242 \r
2243                 /* Perform normal device configuration. Order is not critical for these items. */\r
2244                 CYMEMZERO((void CYFAR *)(CYREG_PHUB_CFGMEM0_CFG0), 4u);\r
2245                 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM1_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM1_VAL), 4u);\r
2246                 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM2_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM2_VAL), 4u);\r
2247                 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM3_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM3_VAL), 4u);\r
2248 \r
2249                 /* Enable digital routing */\r
2250                 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);\r
2251                 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);\r
2252 \r
2253                 /* Enable UDB array */\r
2254                 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u);\r
2255                 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);\r
2256         }\r
2257 \r
2258 \r
2259         /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */\r
2260         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u);\r
2261         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u);\r
2262         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR + 0x0000000Bu), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u);\r
2263         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);\r
2264         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u);\r
2265         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u);\r
2266         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);\r
2267         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u);\r
2268         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);\r
2269         /* Switch Boost to the precision bandgap reference from its internal reference */\r
2270         CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));\r
2271 \r
2272         /* Perform basic analog initialization to defaults */\r
2273         AnalogSetDefault();\r
2274 \r
2275         /* Configure alternate active mode */\r
2276         CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u);\r
2277 }\r