Adding configurable geometry support to firmware.
[SCSI2SD-V6.git] / software / SCSI2SD / v3 / SCSI2SD.cydsn / Generated_Source / PSoC5 / cyfitter_cfg.c
1 /*******************************************************************************\r
2 * FILENAME: cyfitter_cfg.c\r
3 * PSoC Creator  3.1\r
4 *\r
5 * Description:\r
6 * This file is automatically generated by PSoC Creator with device \r
7 * initialization code.  Except for the user defined sections in\r
8 * CyClockStartupError(), this file should not be modified.\r
9 *\r
10 ********************************************************************************\r
11 * Copyright 2013, Cypress Semiconductor Corporation.  All rights reserved.\r
12 * You may use this file only in accordance with the license, terms, conditions, \r
13 * disclaimers, and limitations in the end user license agreement accompanying \r
14 * the software package with which this file was provided.\r
15 ********************************************************************************/\r
16 \r
17 #include <string.h>\r
18 #include <cytypes.h>\r
19 #include <cydevice_trm.h>\r
20 #include <cyfitter.h>\r
21 #include <CyLib.h>\r
22 #include <cyfitter_cfg.h>\r
23 \r
24 #define CY_NEED_CYCLOCKSTARTUPERROR 1\r
25 \r
26 \r
27 #if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
28     #define CYPACKED \r
29     #define CYPACKED_ATTR __attribute__ ((packed))\r
30     #define CYALIGNED __attribute__ ((aligned))\r
31     #define CY_CFG_UNUSED __attribute__ ((unused))\r
32     #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))\r
33     \r
34     #if defined(__ARMCC_VERSION)\r
35         #define CY_CFG_MEMORY_BARRIER() __memory_changed()\r
36     #else\r
37         #define CY_CFG_MEMORY_BARRIER() __sync_synchronize()\r
38     #endif\r
39     \r
40 #elif defined(__ICCARM__)\r
41     #include <intrinsics.h>\r
42 \r
43     #define CYPACKED __packed\r
44     #define CYPACKED_ATTR \r
45     #define CYALIGNED _Pragma("data_alignment=4")\r
46     #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")\r
47     #define CY_CFG_SECTION _Pragma("location=\".psocinit\"")\r
48     \r
49     #define CY_CFG_MEMORY_BARRIER() __DMB()\r
50     \r
51 #else\r
52     #error Unsupported toolchain\r
53 #endif\r
54 \r
55 \r
56 CY_CFG_UNUSED\r
57 static void CYMEMZERO(void *s, size_t n);\r
58 CY_CFG_UNUSED\r
59 static void CYMEMZERO(void *s, size_t n)\r
60 {\r
61         (void)memset(s, 0, n);\r
62 }\r
63 CY_CFG_UNUSED\r
64 static void CYCONFIGCPY(void *dest, const void *src, size_t n);\r
65 CY_CFG_UNUSED\r
66 static void CYCONFIGCPY(void *dest, const void *src, size_t n)\r
67 {\r
68         (void)memcpy(dest, src, n);\r
69 }\r
70 CY_CFG_UNUSED\r
71 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);\r
72 CY_CFG_UNUSED\r
73 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)\r
74 {\r
75         (void)memcpy(dest, src, n);\r
76 }\r
77 \r
78 \r
79 \r
80 /* Clock startup error codes                                                   */\r
81 #define CYCLOCKSTART_NO_ERROR    0u\r
82 #define CYCLOCKSTART_XTAL_ERROR  1u\r
83 #define CYCLOCKSTART_32KHZ_ERROR 2u\r
84 #define CYCLOCKSTART_PLL_ERROR   3u\r
85 \r
86 #ifdef CY_NEED_CYCLOCKSTARTUPERROR\r
87 /*******************************************************************************\r
88 * Function Name: CyClockStartupError\r
89 ********************************************************************************\r
90 * Summary:\r
91 *  If an error is encountered during clock configuration (crystal startup error,\r
92 *  PLL lock error, etc.), the system will end up here.  Unless reimplemented by\r
93 *  the customer, this function will stop in an infinite loop.\r
94 *\r
95 * Parameters:\r
96 *   void\r
97 *\r
98 * Return:\r
99 *   void\r
100 *\r
101 *******************************************************************************/\r
102 CY_CFG_UNUSED\r
103 static void CyClockStartupError(uint8 errorCode);\r
104 CY_CFG_UNUSED\r
105 static void CyClockStartupError(uint8 errorCode)\r
106 {\r
107     /* To remove the compiler warning if errorCode not used.                */\r
108     errorCode = errorCode;\r
109 \r
110     /* `#START CyClockStartupError` */\r
111 \r
112     /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */\r
113     /* we will end up here to allow the customer to implement something to  */\r
114     /* deal with the clock condition.                                       */\r
115 \r
116     /* `#END` */\r
117 \r
118     /* If nothing else, stop here since the clocks have not started         */\r
119     /* correctly.                                                           */\r
120     while(1) {}\r
121 }\r
122 #endif\r
123 \r
124 #define CY_CFG_BASE_ADDR_COUNT 40u\r
125 CYPACKED typedef struct\r
126 {\r
127         uint8 offset;\r
128         uint8 value;\r
129 } CYPACKED_ATTR cy_cfg_addrvalue_t;\r
130 \r
131 \r
132 \r
133 /*******************************************************************************\r
134 * Function Name: cfg_write_bytes32\r
135 ********************************************************************************\r
136 * Summary:\r
137 *  This function is used for setting up the chip configuration areas that\r
138 *  contain relatively sparse data.\r
139 *\r
140 * Parameters:\r
141 *   void\r
142 *\r
143 * Return:\r
144 *   void\r
145 *\r
146 *******************************************************************************/\r
147 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]);\r
148 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[])\r
149 {\r
150         /* For 32-bit little-endian architectures */\r
151         uint32 i, j = 0u;\r
152         for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++)\r
153         {\r
154                 uint32 baseAddr = addr_table[i];\r
155                 uint8 count = (uint8)baseAddr;\r
156                 baseAddr &= 0xFFFFFF00u;\r
157                 while (count != 0u)\r
158                 {\r
159                         CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value);\r
160                         j++;\r
161                         count--;\r
162                 }\r
163         }\r
164 }\r
165 \r
166 /*******************************************************************************\r
167 * Function Name: ClockSetup\r
168 ********************************************************************************\r
169 *\r
170 * Summary:\r
171 *  Performs the initialization of all of the clocks in the device based on the\r
172 *  settings in the Clock tab of the DWR.  This includes enabling the requested\r
173 *  clocks and setting the necessary dividers to produce the desired frequency. \r
174 *\r
175 * Parameters:\r
176 *  void\r
177 *\r
178 * Return:\r
179 *  void\r
180 *\r
181 *******************************************************************************/\r
182 static void ClockSetup(void);\r
183 static void ClockSetup(void)\r
184 {\r
185         uint32 timeout;\r
186         uint8 pllLock;\r
187 \r
188 \r
189         /* Configure Digital Clocks based on settings from Clock DWR */\r
190         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u);\r
191         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u);\r
192         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u);\r
193         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u);\r
194         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);\r
195         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);\r
196 \r
197         /* Configure ILO based on settings from Clock DWR */\r
198         CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);\r
199 \r
200         /* Configure IMO based on settings from Clock DWR */\r
201         CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u);\r
202         CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));\r
203 \r
204         /* Configure PLL based on settings from Clock DWR */\r
205         CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0B19u);\r
206         CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);\r
207         /* Wait up to 250us for the PLL to lock */\r
208         pllLock = 0u;\r
209         for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--)\r
210         { \r
211                 pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));\r
212                 CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */\r
213         }\r
214         /* If we ran out of time the PLL didn't lock so go to the error function */\r
215         if (timeout == 0u)\r
216         {\r
217                 CyClockStartupError(CYCLOCKSTART_PLL_ERROR);\r
218         }\r
219 \r
220         /* Configure Bus/Master Clock based on settings from Clock DWR */\r
221         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);\r
222         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u);\r
223         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u);\r
224         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u);\r
225         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u);\r
226 \r
227         /* Configure USB Clock based on settings from Clock DWR */\r
228         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);\r
229         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);\r
230 \r
231         CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x07u)));\r
232 }\r
233 \r
234 \r
235 /* Analog API Functions */\r
236 \r
237 \r
238 /*******************************************************************************\r
239 * Function Name: AnalogSetDefault\r
240 ********************************************************************************\r
241 *\r
242 * Summary:\r
243 *  Sets up the analog portions of the chip to default values based on chip\r
244 *  configuration options from the project.\r
245 *\r
246 * Parameters:\r
247 *  void\r
248 *\r
249 * Return:\r
250 *  void\r
251 *\r
252 *******************************************************************************/\r
253 static void AnalogSetDefault(void);\r
254 static void AnalogSetDefault(void)\r
255 {\r
256         uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));\r
257         CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));\r
258         CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));\r
259         CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);\r
260 }\r
261 \r
262 \r
263 /*******************************************************************************\r
264 * Function Name: SetAnalogRoutingPumps\r
265 ********************************************************************************\r
266 *\r
267 * Summary:\r
268 * Enables or disables the analog pumps feeding analog routing switches.\r
269 * Intended to be called at startup, based on the Vdda system configuration;\r
270 * may be called during operation when the user informs us that the Vdda voltage\r
271 * crossed the pump threshold.\r
272 *\r
273 * Parameters:\r
274 *  enabled - 1 to enable the pumps, 0 to disable the pumps\r
275 *\r
276 * Return:\r
277 *  void\r
278 *\r
279 *******************************************************************************/\r
280 void SetAnalogRoutingPumps(uint8 enabled)\r
281 {\r
282         uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0);\r
283         if (enabled != 0u)\r
284         {\r
285                 regValue |= 0x00u;\r
286         }\r
287         else\r
288         {\r
289                 regValue &= (uint8)~0x00u;\r
290         }\r
291         CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);\r
292 }\r
293 \r
294 #define CY_AMUX_UNUSED CYREG_BOOST_SR\r
295 \r
296 \r
297 /*******************************************************************************\r
298 * Function Name: cyfitter_cfg\r
299 ********************************************************************************\r
300 * Summary:\r
301 *  This function is called by the start-up code for the selected device. It\r
302 *  performs all of the necessary device configuration based on the design\r
303 *  settings.  This includes settings from the Design Wide Resources (DWR) such\r
304 *  as Clocks and Pins as well as any component configuration that is necessary.\r
305 *\r
306 * Parameters:  \r
307 *   void\r
308 *\r
309 * Return:\r
310 *   void\r
311 *\r
312 *******************************************************************************/\r
313 \r
314 void cyfitter_cfg(void)\r
315 {\r
316         /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */\r
317         static const uint8 CYCODE BS_IOPINS0_0_VAL[] = {\r
318                 0x00u, 0xFFu, 0xFFu, 0x00u, 0x17u, 0x00u, 0x00u, 0x00u};\r
319 \r
320         /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */\r
321         static const uint8 CYCODE BS_IOPINS0_7_VAL[] = {\r
322                 0x08u, 0x00u, 0x30u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
323 \r
324         /* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */\r
325         static const uint8 CYCODE BS_IOPINS1_7_VAL[] = {\r
326                 0x00u, 0x00u, 0x00u, 0x00u, 0x10u};\r
327 \r
328         /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */\r
329         static const uint8 CYCODE BS_IOPINS0_8_VAL[] = {\r
330                 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u};\r
331 \r
332         /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */\r
333         static const uint8 CYCODE BS_IOPINS0_2_VAL[] = {\r
334                 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u};\r
335 \r
336         /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */\r
337         static const uint8 CYCODE BS_IOPINS0_3_VAL[] = {\r
338                 0x10u, 0x00u, 0x63u, 0x1Cu, 0x1Cu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x01u};\r
339 \r
340         /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */\r
341         static const uint8 CYCODE BS_IOPINS0_4_VAL[] = {\r
342                 0x00u, 0xFCu, 0xFCu, 0x00u, 0xF8u, 0x00u, 0x00u, 0x00u};\r
343 \r
344         /* IOPINS0_5 Address: CYREG_PRT5_DM0 Size (bytes): 8 */\r
345         static const uint8 CYCODE BS_IOPINS0_5_VAL[] = {\r
346                 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u};\r
347 \r
348         /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */\r
349         static const uint8 CYCODE BS_IOPINS0_6_VAL[] = {\r
350                 0xF0u, 0x0Fu, 0x0Fu, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x01u};\r
351 \r
352         /* PHUB_CFGMEM1 Address: CYREG_PHUB_CFGMEM1_CFG0 Size (bytes): 4 */\r
353         static const uint8 CYCODE BS_PHUB_CFGMEM1_VAL[] = {\r
354                 0x00u, 0x01u, 0x00u, 0x00u};\r
355 \r
356         /* PHUB_CFGMEM2 Address: CYREG_PHUB_CFGMEM2_CFG0 Size (bytes): 4 */\r
357         static const uint8 CYCODE BS_PHUB_CFGMEM2_VAL[] = {\r
358                 0x00u, 0x02u, 0x00u, 0x00u};\r
359 \r
360         /* PHUB_CFGMEM3 Address: CYREG_PHUB_CFGMEM3_CFG0 Size (bytes): 4 */\r
361         static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = {\r
362                 0x00u, 0x03u, 0x00u, 0x00u};\r
363 \r
364 #ifdef CYGlobalIntDisable\r
365         /* Disable interrupts by default. Let user enable if/when they want. */\r
366         CYGlobalIntDisable\r
367 #endif\r
368 \r
369 \r
370         /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */\r
371         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));\r
372         /* Setup clocks based on selections from Clock DWR */\r
373         ClockSetup();\r
374         /* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */\r
375         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0xC1u : 0xC0u));\r
376         /* Enable/Disable Debug functionality based on settings from System DWR */\r
377         CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u));\r
378 \r
379         {\r
380                 static const uint32 CYCODE cy_cfg_addr_table[] = {\r
381                         0x40004501u, /* Base address: 0x40004500 Count: 1 */\r
382                         0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
383                         0x4000520Cu, /* Base address: 0x40005200 Count: 12 */\r
384                         0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
385                         0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
386                         0x40010036u, /* Base address: 0x40010000 Count: 54 */\r
387                         0x4001013Du, /* Base address: 0x40010100 Count: 61 */\r
388                         0x40010243u, /* Base address: 0x40010200 Count: 67 */\r
389                         0x40010358u, /* Base address: 0x40010300 Count: 88 */\r
390                         0x40010448u, /* Base address: 0x40010400 Count: 72 */\r
391                         0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
392                         0x4001064Cu, /* Base address: 0x40010600 Count: 76 */\r
393                         0x40010746u, /* Base address: 0x40010700 Count: 70 */\r
394                         0x4001083Fu, /* Base address: 0x40010800 Count: 63 */\r
395                         0x40010948u, /* Base address: 0x40010900 Count: 72 */\r
396                         0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */\r
397                         0x40010B4Au, /* Base address: 0x40010B00 Count: 74 */\r
398                         0x40010C42u, /* Base address: 0x40010C00 Count: 66 */\r
399                         0x40010D4Cu, /* Base address: 0x40010D00 Count: 76 */\r
400                         0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */\r
401                         0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */\r
402                         0x4001142Cu, /* Base address: 0x40011400 Count: 44 */\r
403                         0x40011550u, /* Base address: 0x40011500 Count: 80 */\r
404                         0x4001163Eu, /* Base address: 0x40011600 Count: 62 */\r
405                         0x4001173Fu, /* Base address: 0x40011700 Count: 63 */\r
406                         0x40011904u, /* Base address: 0x40011900 Count: 4 */\r
407                         0x40011B02u, /* Base address: 0x40011B00 Count: 2 */\r
408                         0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
409                         0x4001411Bu, /* Base address: 0x40014100 Count: 27 */\r
410                         0x40014211u, /* Base address: 0x40014200 Count: 17 */\r
411                         0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
412                         0x40014411u, /* Base address: 0x40014400 Count: 17 */\r
413                         0x40014517u, /* Base address: 0x40014500 Count: 23 */\r
414                         0x40014608u, /* Base address: 0x40014600 Count: 8 */\r
415                         0x4001470Du, /* Base address: 0x40014700 Count: 13 */\r
416                         0x40014806u, /* Base address: 0x40014800 Count: 6 */\r
417                         0x40014908u, /* Base address: 0x40014900 Count: 8 */\r
418                         0x40014D04u, /* Base address: 0x40014D00 Count: 4 */\r
419                         0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
420                         0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
421                 };\r
422 \r
423                 static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
424                         {0x7Eu, 0x02u},\r
425                         {0x01u, 0x20u},\r
426                         {0x0Au, 0x4Bu},\r
427                         {0x00u, 0x11u},\r
428                         {0x01u, 0x02u},\r
429                         {0x18u, 0x08u},\r
430                         {0x19u, 0x04u},\r
431                         {0x1Cu, 0x71u},\r
432                         {0x20u, 0xA0u},\r
433                         {0x21u, 0x68u},\r
434                         {0x2Cu, 0x0Eu},\r
435                         {0x30u, 0x0Au},\r
436                         {0x31u, 0x0Cu},\r
437                         {0x34u, 0x80u},\r
438                         {0x7Cu, 0x40u},\r
439                         {0x20u, 0x02u},\r
440                         {0x84u, 0x0Fu},\r
441                         {0x00u, 0x80u},\r
442                         {0x04u, 0x10u},\r
443                         {0x0Cu, 0x02u},\r
444                         {0x0Du, 0x02u},\r
445                         {0x0Eu, 0x28u},\r
446                         {0x10u, 0x01u},\r
447                         {0x14u, 0x32u},\r
448                         {0x15u, 0x04u},\r
449                         {0x16u, 0x44u},\r
450                         {0x1Au, 0x04u},\r
451                         {0x1Du, 0x08u},\r
452                         {0x24u, 0x4Cu},\r
453                         {0x26u, 0x32u},\r
454                         {0x29u, 0x01u},\r
455                         {0x2Eu, 0x7Eu},\r
456                         {0x30u, 0x0Eu},\r
457                         {0x31u, 0x08u},\r
458                         {0x32u, 0x70u},\r
459                         {0x33u, 0x04u},\r
460                         {0x34u, 0x01u},\r
461                         {0x35u, 0x01u},\r
462                         {0x36u, 0x80u},\r
463                         {0x37u, 0x02u},\r
464                         {0x3Eu, 0x50u},\r
465                         {0x3Fu, 0x55u},\r
466                         {0x40u, 0x42u},\r
467                         {0x41u, 0x03u},\r
468                         {0x42u, 0x50u},\r
469                         {0x45u, 0xF2u},\r
470                         {0x46u, 0xCDu},\r
471                         {0x47u, 0x0Eu},\r
472                         {0x48u, 0x1Fu},\r
473                         {0x49u, 0xFFu},\r
474                         {0x4Au, 0xFFu},\r
475                         {0x4Bu, 0xFFu},\r
476                         {0x4Fu, 0x2Cu},\r
477                         {0x56u, 0x01u},\r
478                         {0x58u, 0x04u},\r
479                         {0x59u, 0x04u},\r
480                         {0x5Au, 0x04u},\r
481                         {0x5Bu, 0x04u},\r
482                         {0x5Cu, 0x01u},\r
483                         {0x5Du, 0x01u},\r
484                         {0x5Fu, 0x01u},\r
485                         {0x62u, 0xC0u},\r
486                         {0x66u, 0x80u},\r
487                         {0x68u, 0x40u},\r
488                         {0x69u, 0x40u},\r
489                         {0x6Eu, 0x08u},\r
490                         {0x88u, 0x01u},\r
491                         {0xB6u, 0x01u},\r
492                         {0xBEu, 0x40u},\r
493                         {0xD8u, 0x04u},\r
494                         {0xDFu, 0x01u},\r
495                         {0x00u, 0x41u},\r
496                         {0x03u, 0x10u},\r
497                         {0x05u, 0x10u},\r
498                         {0x0Au, 0x10u},\r
499                         {0x0Bu, 0x44u},\r
500                         {0x11u, 0x40u},\r
501                         {0x12u, 0x20u},\r
502                         {0x18u, 0x40u},\r
503                         {0x19u, 0x48u},\r
504                         {0x1Au, 0x10u},\r
505                         {0x1Bu, 0x12u},\r
506                         {0x1Du, 0x80u},\r
507                         {0x20u, 0x04u},\r
508                         {0x21u, 0x02u},\r
509                         {0x23u, 0x22u},\r
510                         {0x2Bu, 0x04u},\r
511                         {0x31u, 0x04u},\r
512                         {0x32u, 0x80u},\r
513                         {0x3Au, 0x40u},\r
514                         {0x41u, 0x10u},\r
515                         {0x42u, 0x10u},\r
516                         {0x43u, 0x02u},\r
517                         {0x48u, 0x01u},\r
518                         {0x49u, 0x02u},\r
519                         {0x4Bu, 0x04u},\r
520                         {0x50u, 0x10u},\r
521                         {0x52u, 0x04u},\r
522                         {0x53u, 0x80u},\r
523                         {0x59u, 0x40u},\r
524                         {0x5Au, 0x08u},\r
525                         {0x5Bu, 0x22u},\r
526                         {0x60u, 0x04u},\r
527                         {0x61u, 0x82u},\r
528                         {0x63u, 0x20u},\r
529                         {0x68u, 0x90u},\r
530                         {0x69u, 0x10u},\r
531                         {0x6Au, 0x80u},\r
532                         {0x70u, 0x60u},\r
533                         {0x72u, 0x40u},\r
534                         {0x73u, 0x10u},\r
535                         {0x81u, 0x02u},\r
536                         {0x83u, 0x10u},\r
537                         {0x85u, 0x40u},\r
538                         {0x88u, 0x40u},\r
539                         {0x89u, 0x08u},\r
540                         {0x8Cu, 0x40u},\r
541                         {0x8Eu, 0x10u},\r
542                         {0xC0u, 0x4Du},\r
543                         {0xC2u, 0x0Eu},\r
544                         {0xC4u, 0x05u},\r
545                         {0xCAu, 0x04u},\r
546                         {0xCCu, 0x0Au},\r
547                         {0xCEu, 0x08u},\r
548                         {0xD0u, 0x07u},\r
549                         {0xD2u, 0x08u},\r
550                         {0xD6u, 0x0Fu},\r
551                         {0xD8u, 0x0Fu},\r
552                         {0xE0u, 0x06u},\r
553                         {0xE2u, 0x10u},\r
554                         {0xE4u, 0x04u},\r
555                         {0xE6u, 0x20u},\r
556                         {0x09u, 0x05u},\r
557                         {0x0Bu, 0x0Au},\r
558                         {0x0Du, 0x0Fu},\r
559                         {0x0Eu, 0x01u},\r
560                         {0x0Fu, 0xF0u},\r
561                         {0x10u, 0x01u},\r
562                         {0x12u, 0x02u},\r
563                         {0x15u, 0x60u},\r
564                         {0x17u, 0x90u},\r
565                         {0x19u, 0x30u},\r
566                         {0x1Bu, 0xC0u},\r
567                         {0x1Du, 0x06u},\r
568                         {0x1Fu, 0x09u},\r
569                         {0x21u, 0x03u},\r
570                         {0x23u, 0x0Cu},\r
571                         {0x25u, 0x50u},\r
572                         {0x26u, 0x02u},\r
573                         {0x27u, 0xA0u},\r
574                         {0x30u, 0x03u},\r
575                         {0x37u, 0xFFu},\r
576                         {0x3Eu, 0x01u},\r
577                         {0x3Fu, 0x40u},\r
578                         {0x56u, 0x08u},\r
579                         {0x58u, 0x04u},\r
580                         {0x59u, 0x04u},\r
581                         {0x5Bu, 0x04u},\r
582                         {0x5Du, 0x90u},\r
583                         {0x5Fu, 0x01u},\r
584                         {0x83u, 0x1Fu},\r
585                         {0x85u, 0x3Fu},\r
586                         {0x86u, 0x70u},\r
587                         {0x87u, 0x40u},\r
588                         {0x89u, 0x03u},\r
589                         {0x8Cu, 0x44u},\r
590                         {0x8Du, 0x20u},\r
591                         {0x8Eu, 0x88u},\r
592                         {0x8Fu, 0x5Cu},\r
593                         {0x94u, 0x99u},\r
594                         {0x95u, 0x18u},\r
595                         {0x96u, 0x22u},\r
596                         {0x97u, 0x03u},\r
597                         {0x98u, 0xAAu},\r
598                         {0x9Au, 0x55u},\r
599                         {0x9Bu, 0x01u},\r
600                         {0x9Du, 0x10u},\r
601                         {0x9Eu, 0x07u},\r
602                         {0x9Fu, 0x60u},\r
603                         {0xA1u, 0x02u},\r
604                         {0xA5u, 0x27u},\r
605                         {0xA6u, 0x08u},\r
606                         {0xA7u, 0x50u},\r
607                         {0xA9u, 0x80u},\r
608                         {0xAAu, 0x80u},\r
609                         {0xB3u, 0x80u},\r
610                         {0xB4u, 0xF0u},\r
611                         {0xB5u, 0x0Fu},\r
612                         {0xB6u, 0x0Fu},\r
613                         {0xB7u, 0x70u},\r
614                         {0xBBu, 0x80u},\r
615                         {0xBFu, 0x04u},\r
616                         {0xD6u, 0x08u},\r
617                         {0xD8u, 0x04u},\r
618                         {0xD9u, 0x04u},\r
619                         {0xDBu, 0x04u},\r
620                         {0xDCu, 0x11u},\r
621                         {0xDDu, 0x90u},\r
622                         {0xDFu, 0x01u},\r
623                         {0x00u, 0x40u},\r
624                         {0x03u, 0x20u},\r
625                         {0x05u, 0x40u},\r
626                         {0x09u, 0x20u},\r
627                         {0x0Au, 0x12u},\r
628                         {0x0Cu, 0x02u},\r
629                         {0x0Fu, 0x80u},\r
630                         {0x10u, 0x20u},\r
631                         {0x13u, 0x10u},\r
632                         {0x17u, 0x04u},\r
633                         {0x19u, 0x40u},\r
634                         {0x1Au, 0x02u},\r
635                         {0x1Bu, 0x30u},\r
636                         {0x1Cu, 0x80u},\r
637                         {0x20u, 0x06u},\r
638                         {0x21u, 0xB0u},\r
639                         {0x22u, 0x24u},\r
640                         {0x23u, 0x08u},\r
641                         {0x25u, 0x40u},\r
642                         {0x28u, 0x08u},\r
643                         {0x29u, 0x08u},\r
644                         {0x2Bu, 0x80u},\r
645                         {0x2Du, 0x01u},\r
646                         {0x2Eu, 0x04u},\r
647                         {0x31u, 0x80u},\r
648                         {0x32u, 0x08u},\r
649                         {0x33u, 0x10u},\r
650                         {0x34u, 0x10u},\r
651                         {0x35u, 0x40u},\r
652                         {0x37u, 0x04u},\r
653                         {0x38u, 0x64u},\r
654                         {0x3Au, 0x02u},\r
655                         {0x3Fu, 0xA0u},\r
656                         {0x58u, 0x66u},\r
657                         {0x5Du, 0x80u},\r
658                         {0x5Fu, 0x20u},\r
659                         {0x61u, 0x04u},\r
660                         {0x62u, 0x80u},\r
661                         {0x63u, 0x48u},\r
662                         {0x65u, 0x30u},\r
663                         {0x66u, 0x40u},\r
664                         {0x67u, 0x02u},\r
665                         {0x6Du, 0x28u},\r
666                         {0x6Eu, 0x80u},\r
667                         {0x6Fu, 0x10u},\r
668                         {0x80u, 0x30u},\r
669                         {0x85u, 0x80u},\r
670                         {0x86u, 0x40u},\r
671                         {0x87u, 0xA0u},\r
672                         {0x88u, 0x42u},\r
673                         {0x8Au, 0x0Au},\r
674                         {0x8Du, 0x04u},\r
675                         {0x90u, 0x60u},\r
676                         {0x91u, 0x10u},\r
677                         {0x92u, 0xF0u},\r
678                         {0x93u, 0x14u},\r
679                         {0x94u, 0x01u},\r
680                         {0x95u, 0x60u},\r
681                         {0x96u, 0x08u},\r
682                         {0x97u, 0x40u},\r
683                         {0x99u, 0x08u},\r
684                         {0x9Du, 0x14u},\r
685                         {0x9Eu, 0x40u},\r
686                         {0x9Fu, 0x10u},\r
687                         {0xA0u, 0xA0u},\r
688                         {0xA3u, 0x82u},\r
689                         {0xA4u, 0x45u},\r
690                         {0xA5u, 0x40u},\r
691                         {0xA6u, 0xA0u},\r
692                         {0xA7u, 0x04u},\r
693                         {0xAAu, 0x04u},\r
694                         {0xACu, 0x14u},\r
695                         {0xADu, 0x10u},\r
696                         {0xB7u, 0x02u},\r
697                         {0xC0u, 0x85u},\r
698                         {0xC2u, 0x17u},\r
699                         {0xC4u, 0x26u},\r
700                         {0xCAu, 0xC7u},\r
701                         {0xCCu, 0x7Eu},\r
702                         {0xCEu, 0x3Fu},\r
703                         {0xD6u, 0x3Fu},\r
704                         {0xD8u, 0x3Fu},\r
705                         {0xE0u, 0x04u},\r
706                         {0xE2u, 0x0Au},\r
707                         {0xE4u, 0x08u},\r
708                         {0xE6u, 0x24u},\r
709                         {0xE8u, 0x0Bu},\r
710                         {0xEEu, 0x01u},\r
711                         {0x02u, 0x07u},\r
712                         {0x07u, 0x10u},\r
713                         {0x09u, 0x0Au},\r
714                         {0x0Bu, 0x05u},\r
715                         {0x0Cu, 0x44u},\r
716                         {0x0Du, 0x04u},\r
717                         {0x0Eu, 0x88u},\r
718                         {0x0Fu, 0x08u},\r
719                         {0x11u, 0x10u},\r
720                         {0x13u, 0x20u},\r
721                         {0x14u, 0x99u},\r
722                         {0x16u, 0x22u},\r
723                         {0x17u, 0x07u},\r
724                         {0x1Eu, 0x70u},\r
725                         {0x1Fu, 0x08u},\r
726                         {0x22u, 0x80u},\r
727                         {0x23u, 0x20u},\r
728                         {0x24u, 0xAAu},\r
729                         {0x25u, 0x09u},\r
730                         {0x26u, 0x55u},\r
731                         {0x27u, 0x02u},\r
732                         {0x2Au, 0x08u},\r
733                         {0x30u, 0x0Fu},\r
734                         {0x33u, 0x0Fu},\r
735                         {0x35u, 0x30u},\r
736                         {0x36u, 0xF0u},\r
737                         {0x3Fu, 0x10u},\r
738                         {0x56u, 0x08u},\r
739                         {0x58u, 0x04u},\r
740                         {0x59u, 0x04u},\r
741                         {0x5Bu, 0x04u},\r
742                         {0x5Cu, 0x11u},\r
743                         {0x5Du, 0x90u},\r
744                         {0x5Fu, 0x01u},\r
745                         {0x84u, 0x10u},\r
746                         {0x85u, 0x69u},\r
747                         {0x86u, 0x20u},\r
748                         {0x87u, 0x96u},\r
749                         {0x88u, 0x06u},\r
750                         {0x8Au, 0x09u},\r
751                         {0x8Bu, 0xFFu},\r
752                         {0x8Cu, 0x07u},\r
753                         {0x8Eu, 0x08u},\r
754                         {0x8Fu, 0xFFu},\r
755                         {0x90u, 0x03u},\r
756                         {0x91u, 0x0Fu},\r
757                         {0x92u, 0x0Cu},\r
758                         {0x93u, 0xF0u},\r
759                         {0x94u, 0x05u},\r
760                         {0x95u, 0xFFu},\r
761                         {0x96u, 0x0Au},\r
762                         {0x99u, 0xFFu},\r
763                         {0x9Au, 0x02u},\r
764                         {0xA2u, 0x10u},\r
765                         {0xA3u, 0xFFu},\r
766                         {0xA6u, 0x20u},\r
767                         {0xA8u, 0x01u},\r
768                         {0xA9u, 0x55u},\r
769                         {0xABu, 0xAAu},\r
770                         {0xADu, 0x33u},\r
771                         {0xAEu, 0x03u},\r
772                         {0xAFu, 0xCCu},\r
773                         {0xB0u, 0x0Fu},\r
774                         {0xB4u, 0x30u},\r
775                         {0xB7u, 0xFFu},\r
776                         {0xBAu, 0x02u},\r
777                         {0xBBu, 0x80u},\r
778                         {0xBEu, 0x10u},\r
779                         {0xD8u, 0x04u},\r
780                         {0xD9u, 0x04u},\r
781                         {0xDCu, 0x11u},\r
782                         {0xDFu, 0x01u},\r
783                         {0x00u, 0x40u},\r
784                         {0x01u, 0x02u},\r
785                         {0x04u, 0x40u},\r
786                         {0x06u, 0x20u},\r
787                         {0x07u, 0x08u},\r
788                         {0x0Au, 0x12u},\r
789                         {0x0Eu, 0x90u},\r
790                         {0x0Fu, 0x04u},\r
791                         {0x10u, 0x80u},\r
792                         {0x11u, 0x10u},\r
793                         {0x13u, 0x08u},\r
794                         {0x14u, 0x10u},\r
795                         {0x15u, 0x01u},\r
796                         {0x16u, 0x12u},\r
797                         {0x17u, 0x10u},\r
798                         {0x19u, 0x02u},\r
799                         {0x1Au, 0x02u},\r
800                         {0x1Du, 0x20u},\r
801                         {0x1Eu, 0x80u},\r
802                         {0x20u, 0x08u},\r
803                         {0x21u, 0x08u},\r
804                         {0x27u, 0x01u},\r
805                         {0x29u, 0x08u},\r
806                         {0x2Bu, 0x40u},\r
807                         {0x2Du, 0x20u},\r
808                         {0x2Eu, 0x02u},\r
809                         {0x2Fu, 0x01u},\r
810                         {0x30u, 0x02u},\r
811                         {0x31u, 0x08u},\r
812                         {0x32u, 0x40u},\r
813                         {0x36u, 0x28u},\r
814                         {0x37u, 0x01u},\r
815                         {0x38u, 0x48u},\r
816                         {0x39u, 0x20u},\r
817                         {0x3Cu, 0x40u},\r
818                         {0x3Eu, 0x10u},\r
819                         {0x3Fu, 0x08u},\r
820                         {0x5Bu, 0xA0u},\r
821                         {0x60u, 0x09u},\r
822                         {0x68u, 0x02u},\r
823                         {0x80u, 0x01u},\r
824                         {0x83u, 0x10u},\r
825                         {0x85u, 0x02u},\r
826                         {0x89u, 0x10u},\r
827                         {0x8Au, 0x40u},\r
828                         {0x8Cu, 0x24u},\r
829                         {0x8Du, 0x10u},\r
830                         {0x8Eu, 0x02u},\r
831                         {0x90u, 0x40u},\r
832                         {0x91u, 0x30u},\r
833                         {0x92u, 0xF0u},\r
834                         {0x93u, 0x46u},\r
835                         {0x94u, 0x01u},\r
836                         {0x95u, 0x01u},\r
837                         {0x99u, 0x28u},\r
838                         {0x9Bu, 0x98u},\r
839                         {0x9Cu, 0x18u},\r
840                         {0x9Fu, 0x04u},\r
841                         {0xA0u, 0x80u},\r
842                         {0xA1u, 0x04u},\r
843                         {0xA2u, 0xA8u},\r
844                         {0xA3u, 0x06u},\r
845                         {0xA4u, 0x06u},\r
846                         {0xA6u, 0x02u},\r
847                         {0xABu, 0xB0u},\r
848                         {0xACu, 0x04u},\r
849                         {0xB2u, 0x04u},\r
850                         {0xB3u, 0x08u},\r
851                         {0xB5u, 0x50u},\r
852                         {0xB6u, 0x02u},\r
853                         {0xC0u, 0xE9u},\r
854                         {0xC2u, 0x75u},\r
855                         {0xC4u, 0xFEu},\r
856                         {0xCAu, 0xB3u},\r
857                         {0xCCu, 0xEBu},\r
858                         {0xCEu, 0x7Eu},\r
859                         {0xD6u, 0x0Cu},\r
860                         {0xD8u, 0x0Cu},\r
861                         {0xE0u, 0x05u},\r
862                         {0xE2u, 0x20u},\r
863                         {0xE4u, 0x08u},\r
864                         {0xE6u, 0x80u},\r
865                         {0xEAu, 0x09u},\r
866                         {0xECu, 0x04u},\r
867                         {0xEEu, 0x10u},\r
868                         {0x00u, 0x0Du},\r
869                         {0x04u, 0x01u},\r
870                         {0x05u, 0x0Fu},\r
871                         {0x06u, 0x32u},\r
872                         {0x08u, 0x62u},\r
873                         {0x09u, 0x03u},\r
874                         {0x0Au, 0x08u},\r
875                         {0x0Bu, 0x0Cu},\r
876                         {0x10u, 0x02u},\r
877                         {0x11u, 0x05u},\r
878                         {0x12u, 0x0Du},\r
879                         {0x13u, 0x0Au},\r
880                         {0x14u, 0x0Du},\r
881                         {0x15u, 0x20u},\r
882                         {0x17u, 0x4Fu},\r
883                         {0x1Au, 0x10u},\r
884                         {0x1Cu, 0x02u},\r
885                         {0x1Eu, 0x54u},\r
886                         {0x1Fu, 0x70u},\r
887                         {0x20u, 0x0Du},\r
888                         {0x24u, 0x0Du},\r
889                         {0x25u, 0x06u},\r
890                         {0x27u, 0x09u},\r
891                         {0x29u, 0x10u},\r
892                         {0x2Bu, 0x2Fu},\r
893                         {0x2Cu, 0x0Du},\r
894                         {0x2Du, 0x40u},\r
895                         {0x2Fu, 0x1Fu},\r
896                         {0x30u, 0x0Fu},\r
897                         {0x31u, 0x7Fu},\r
898                         {0x34u, 0x70u},\r
899                         {0x3Au, 0x02u},\r
900                         {0x54u, 0x01u},\r
901                         {0x58u, 0x04u},\r
902                         {0x59u, 0x04u},\r
903                         {0x5Bu, 0x04u},\r
904                         {0x5Cu, 0x10u},\r
905                         {0x5Du, 0x10u},\r
906                         {0x5Fu, 0x01u},\r
907                         {0x80u, 0x96u},\r
908                         {0x82u, 0x69u},\r
909                         {0x85u, 0x02u},\r
910                         {0x87u, 0x11u},\r
911                         {0x88u, 0x0Fu},\r
912                         {0x8Au, 0xF0u},\r
913                         {0x8Du, 0x01u},\r
914                         {0x8Eu, 0xFFu},\r
915                         {0x8Fu, 0x02u},\r
916                         {0x90u, 0x55u},\r
917                         {0x92u, 0xAAu},\r
918                         {0x95u, 0x02u},\r
919                         {0x96u, 0xFFu},\r
920                         {0x97u, 0x05u},\r
921                         {0x99u, 0x02u},\r
922                         {0x9Au, 0xFFu},\r
923                         {0x9Bu, 0x09u},\r
924                         {0x9Cu, 0x33u},\r
925                         {0x9Du, 0x02u},\r
926                         {0x9Eu, 0xCCu},\r
927                         {0x9Fu, 0x01u},\r
928                         {0xA4u, 0xFFu},\r
929                         {0xA8u, 0xFFu},\r
930                         {0xB1u, 0x03u},\r
931                         {0xB3u, 0x08u},\r
932                         {0xB4u, 0xFFu},\r
933                         {0xB5u, 0x10u},\r
934                         {0xB7u, 0x04u},\r
935                         {0xBAu, 0x20u},\r
936                         {0xBBu, 0x02u},\r
937                         {0xD6u, 0x08u},\r
938                         {0xD8u, 0x04u},\r
939                         {0xD9u, 0x04u},\r
940                         {0xDBu, 0x04u},\r
941                         {0xDCu, 0x91u},\r
942                         {0xDDu, 0x90u},\r
943                         {0xDFu, 0x01u},\r
944                         {0x01u, 0x20u},\r
945                         {0x02u, 0x80u},\r
946                         {0x03u, 0x02u},\r
947                         {0x04u, 0x08u},\r
948                         {0x05u, 0x10u},\r
949                         {0x07u, 0x40u},\r
950                         {0x08u, 0x20u},\r
951                         {0x0Au, 0x10u},\r
952                         {0x0Bu, 0x41u},\r
953                         {0x0Cu, 0x08u},\r
954                         {0x0Eu, 0x8Au},\r
955                         {0x12u, 0x08u},\r
956                         {0x13u, 0x08u},\r
957                         {0x15u, 0x06u},\r
958                         {0x16u, 0x02u},\r
959                         {0x19u, 0x20u},\r
960                         {0x1Bu, 0x20u},\r
961                         {0x1Eu, 0x88u},\r
962                         {0x20u, 0x40u},\r
963                         {0x21u, 0x28u},\r
964                         {0x22u, 0x40u},\r
965                         {0x27u, 0x80u},\r
966                         {0x2Eu, 0x10u},\r
967                         {0x2Fu, 0x22u},\r
968                         {0x31u, 0x28u},\r
969                         {0x32u, 0x40u},\r
970                         {0x37u, 0x89u},\r
971                         {0x38u, 0x44u},\r
972                         {0x39u, 0x80u},\r
973                         {0x3Du, 0x28u},\r
974                         {0x58u, 0x80u},\r
975                         {0x5Au, 0x20u},\r
976                         {0x5Fu, 0x80u},\r
977                         {0x60u, 0x04u},\r
978                         {0x63u, 0x01u},\r
979                         {0x83u, 0x40u},\r
980                         {0x8Au, 0x11u},\r
981                         {0x8Fu, 0x04u},\r
982                         {0x92u, 0x72u},\r
983                         {0x93u, 0x40u},\r
984                         {0x95u, 0x01u},\r
985                         {0x98u, 0xA0u},\r
986                         {0x99u, 0x08u},\r
987                         {0x9Bu, 0x09u},\r
988                         {0x9Eu, 0x10u},\r
989                         {0x9Fu, 0x04u},\r
990                         {0xA1u, 0x14u},\r
991                         {0xA2u, 0x88u},\r
992                         {0xA3u, 0x02u},\r
993                         {0xA6u, 0x02u},\r
994                         {0xA7u, 0x40u},\r
995                         {0xA8u, 0x02u},\r
996                         {0xAAu, 0x20u},\r
997                         {0xABu, 0x20u},\r
998                         {0xACu, 0x80u},\r
999                         {0xB1u, 0x28u},\r
1000                         {0xB4u, 0x08u},\r
1001                         {0xC0u, 0x7Bu},\r
1002                         {0xC2u, 0xFFu},\r
1003                         {0xC4u, 0xB6u},\r
1004                         {0xCAu, 0x70u},\r
1005                         {0xCCu, 0xDEu},\r
1006                         {0xCEu, 0x6Au},\r
1007                         {0xD6u, 0x1Cu},\r
1008                         {0xD8u, 0x0Cu},\r
1009                         {0xE2u, 0x44u},\r
1010                         {0xE6u, 0xCAu},\r
1011                         {0xE8u, 0x04u},\r
1012                         {0xEAu, 0x01u},\r
1013                         {0xEEu, 0x86u},\r
1014                         {0x00u, 0x01u},\r
1015                         {0x01u, 0x02u},\r
1016                         {0x02u, 0x02u},\r
1017                         {0x03u, 0x01u},\r
1018                         {0x08u, 0x02u},\r
1019                         {0x0Au, 0x01u},\r
1020                         {0x0Cu, 0x04u},\r
1021                         {0x0Eu, 0x08u},\r
1022                         {0x15u, 0x02u},\r
1023                         {0x16u, 0x20u},\r
1024                         {0x17u, 0x01u},\r
1025                         {0x19u, 0x02u},\r
1026                         {0x1Au, 0x10u},\r
1027                         {0x1Bu, 0x01u},\r
1028                         {0x1Du, 0x01u},\r
1029                         {0x1Eu, 0x40u},\r
1030                         {0x1Fu, 0x02u},\r
1031                         {0x20u, 0x08u},\r
1032                         {0x22u, 0x04u},\r
1033                         {0x28u, 0x03u},\r
1034                         {0x2Au, 0x0Cu},\r
1035                         {0x2Du, 0x02u},\r
1036                         {0x2Fu, 0x01u},\r
1037                         {0x30u, 0x10u},\r
1038                         {0x32u, 0x40u},\r
1039                         {0x34u, 0x20u},\r
1040                         {0x36u, 0x0Fu},\r
1041                         {0x37u, 0x03u},\r
1042                         {0x3Bu, 0x80u},\r
1043                         {0x3Eu, 0x40u},\r
1044                         {0x58u, 0x04u},\r
1045                         {0x59u, 0x04u},\r
1046                         {0x5Bu, 0x04u},\r
1047                         {0x5Cu, 0x99u},\r
1048                         {0x5Fu, 0x01u},\r
1049                         {0x87u, 0x10u},\r
1050                         {0x89u, 0x02u},\r
1051                         {0x8Bu, 0x01u},\r
1052                         {0x8Du, 0x02u},\r
1053                         {0x8Fu, 0x01u},\r
1054                         {0x91u, 0x01u},\r
1055                         {0x93u, 0x02u},\r
1056                         {0x95u, 0x10u},\r
1057                         {0x97u, 0x20u},\r
1058                         {0x9Du, 0x04u},\r
1059                         {0xA3u, 0x20u},\r
1060                         {0xA5u, 0x08u},\r
1061                         {0xA9u, 0x02u},\r
1062                         {0xABu, 0x01u},\r
1063                         {0xADu, 0x02u},\r
1064                         {0xAFu, 0x01u},\r
1065                         {0xB1u, 0x03u},\r
1066                         {0xB3u, 0x08u},\r
1067                         {0xB5u, 0x04u},\r
1068                         {0xB7u, 0x30u},\r
1069                         {0xBBu, 0x02u},\r
1070                         {0xBFu, 0x40u},\r
1071                         {0xD6u, 0x08u},\r
1072                         {0xD9u, 0x04u},\r
1073                         {0xDBu, 0x04u},\r
1074                         {0xDCu, 0x90u},\r
1075                         {0xDDu, 0x90u},\r
1076                         {0xDFu, 0x01u},\r
1077                         {0x05u, 0x01u},\r
1078                         {0x06u, 0x09u},\r
1079                         {0x0Eu, 0x28u},\r
1080                         {0x0Fu, 0x02u},\r
1081                         {0x14u, 0x04u},\r
1082                         {0x15u, 0x01u},\r
1083                         {0x1Du, 0x40u},\r
1084                         {0x1Eu, 0x28u},\r
1085                         {0x1Fu, 0x01u},\r
1086                         {0x21u, 0x42u},\r
1087                         {0x22u, 0x04u},\r
1088                         {0x23u, 0x48u},\r
1089                         {0x25u, 0x80u},\r
1090                         {0x26u, 0x80u},\r
1091                         {0x28u, 0x02u},\r
1092                         {0x29u, 0x10u},\r
1093                         {0x2Bu, 0xA0u},\r
1094                         {0x2Fu, 0x01u},\r
1095                         {0x30u, 0x04u},\r
1096                         {0x31u, 0x82u},\r
1097                         {0x32u, 0x08u},\r
1098                         {0x36u, 0x94u},\r
1099                         {0x38u, 0x90u},\r
1100                         {0x3Au, 0x08u},\r
1101                         {0x3Fu, 0x02u},\r
1102                         {0x58u, 0x80u},\r
1103                         {0x5Du, 0x06u},\r
1104                         {0x5Fu, 0x60u},\r
1105                         {0x63u, 0x02u},\r
1106                         {0x65u, 0x80u},\r
1107                         {0x6Cu, 0x16u},\r
1108                         {0x6Du, 0x41u},\r
1109                         {0x6Fu, 0x80u},\r
1110                         {0x74u, 0x80u},\r
1111                         {0x76u, 0x95u},\r
1112                         {0x80u, 0x80u},\r
1113                         {0x86u, 0x04u},\r
1114                         {0x8Au, 0x88u},\r
1115                         {0x8Bu, 0x08u},\r
1116                         {0x8Eu, 0x04u},\r
1117                         {0x90u, 0x90u},\r
1118                         {0x94u, 0x28u},\r
1119                         {0x95u, 0xC0u},\r
1120                         {0x98u, 0x02u},\r
1121                         {0x99u, 0x91u},\r
1122                         {0x9Du, 0x40u},\r
1123                         {0x9Eu, 0x10u},\r
1124                         {0xA2u, 0x08u},\r
1125                         {0xA3u, 0x20u},\r
1126                         {0xA4u, 0x02u},\r
1127                         {0xA8u, 0x80u},\r
1128                         {0xAAu, 0x08u},\r
1129                         {0xABu, 0x01u},\r
1130                         {0xB0u, 0x40u},\r
1131                         {0xB1u, 0x10u},\r
1132                         {0xB2u, 0x80u},\r
1133                         {0xB7u, 0x80u},\r
1134                         {0xC0u, 0xD0u},\r
1135                         {0xC2u, 0xE0u},\r
1136                         {0xC4u, 0x50u},\r
1137                         {0xCAu, 0x1Fu},\r
1138                         {0xCCu, 0x7Bu},\r
1139                         {0xCEu, 0x8Eu},\r
1140                         {0xD6u, 0xF8u},\r
1141                         {0xD8u, 0x18u},\r
1142                         {0xE0u, 0x20u},\r
1143                         {0xE2u, 0x40u},\r
1144                         {0xE6u, 0xF2u},\r
1145                         {0xE8u, 0x40u},\r
1146                         {0xEAu, 0x01u},\r
1147                         {0xECu, 0x20u},\r
1148                         {0xEEu, 0x02u},\r
1149                         {0x03u, 0xFFu},\r
1150                         {0x05u, 0x50u},\r
1151                         {0x07u, 0xA0u},\r
1152                         {0x09u, 0x30u},\r
1153                         {0x0Bu, 0xC0u},\r
1154                         {0x0Du, 0x06u},\r
1155                         {0x0Eu, 0x01u},\r
1156                         {0x0Fu, 0x09u},\r
1157                         {0x11u, 0x60u},\r
1158                         {0x12u, 0x04u},\r
1159                         {0x13u, 0x90u},\r
1160                         {0x17u, 0xFFu},\r
1161                         {0x19u, 0x03u},\r
1162                         {0x1Au, 0x08u},\r
1163                         {0x1Bu, 0x0Cu},\r
1164                         {0x1Du, 0x0Fu},\r
1165                         {0x1Eu, 0x10u},\r
1166                         {0x1Fu, 0xF0u},\r
1167                         {0x20u, 0x01u},\r
1168                         {0x21u, 0x05u},\r
1169                         {0x22u, 0x02u},\r
1170                         {0x23u, 0x0Au},\r
1171                         {0x2Du, 0xFFu},\r
1172                         {0x2Eu, 0x02u},\r
1173                         {0x30u, 0x10u},\r
1174                         {0x32u, 0x08u},\r
1175                         {0x34u, 0x04u},\r
1176                         {0x35u, 0xFFu},\r
1177                         {0x36u, 0x03u},\r
1178                         {0x3Eu, 0x40u},\r
1179                         {0x3Fu, 0x10u},\r
1180                         {0x56u, 0x08u},\r
1181                         {0x58u, 0x04u},\r
1182                         {0x59u, 0x04u},\r
1183                         {0x5Bu, 0x04u},\r
1184                         {0x5Cu, 0x09u},\r
1185                         {0x5Du, 0x90u},\r
1186                         {0x5Fu, 0x01u},\r
1187                         {0x84u, 0x50u},\r
1188                         {0x85u, 0xFFu},\r
1189                         {0x86u, 0xA0u},\r
1190                         {0x88u, 0x30u},\r
1191                         {0x89u, 0x33u},\r
1192                         {0x8Au, 0xC0u},\r
1193                         {0x8Bu, 0xCCu},\r
1194                         {0x8Cu, 0xFFu},\r
1195                         {0x8Fu, 0xFFu},\r
1196                         {0x90u, 0x90u},\r
1197                         {0x91u, 0x0Fu},\r
1198                         {0x92u, 0x60u},\r
1199                         {0x93u, 0xF0u},\r
1200                         {0x94u, 0x05u},\r
1201                         {0x96u, 0x0Au},\r
1202                         {0x97u, 0xFFu},\r
1203                         {0x99u, 0x55u},\r
1204                         {0x9Bu, 0xAAu},\r
1205                         {0x9Cu, 0x0Fu},\r
1206                         {0x9Du, 0xFFu},\r
1207                         {0x9Eu, 0xF0u},\r
1208                         {0xA0u, 0x09u},\r
1209                         {0xA1u, 0x69u},\r
1210                         {0xA2u, 0x06u},\r
1211                         {0xA3u, 0x96u},\r
1212                         {0xA4u, 0x03u},\r
1213                         {0xA6u, 0x0Cu},\r
1214                         {0xA7u, 0xFFu},\r
1215                         {0xA8u, 0xFFu},\r
1216                         {0xAEu, 0xFFu},\r
1217                         {0xB1u, 0xFFu},\r
1218                         {0xB6u, 0xFFu},\r
1219                         {0xB8u, 0x02u},\r
1220                         {0xBBu, 0x02u},\r
1221                         {0xBEu, 0x41u},\r
1222                         {0xD8u, 0x04u},\r
1223                         {0xD9u, 0x04u},\r
1224                         {0xDCu, 0x10u},\r
1225                         {0xDFu, 0x01u},\r
1226                         {0x00u, 0x80u},\r
1227                         {0x04u, 0x28u},\r
1228                         {0x05u, 0x41u},\r
1229                         {0x07u, 0x40u},\r
1230                         {0x09u, 0x80u},\r
1231                         {0x0Au, 0x44u},\r
1232                         {0x0Cu, 0x82u},\r
1233                         {0x0Eu, 0x20u},\r
1234                         {0x10u, 0x80u},\r
1235                         {0x11u, 0x40u},\r
1236                         {0x14u, 0x14u},\r
1237                         {0x16u, 0x81u},\r
1238                         {0x18u, 0x92u},\r
1239                         {0x19u, 0x10u},\r
1240                         {0x1Au, 0x44u},\r
1241                         {0x1Fu, 0x41u},\r
1242                         {0x22u, 0x20u},\r
1243                         {0x26u, 0x02u},\r
1244                         {0x29u, 0x40u},\r
1245                         {0x2Au, 0x02u},\r
1246                         {0x2Fu, 0xA0u},\r
1247                         {0x30u, 0x9Eu},\r
1248                         {0x31u, 0x20u},\r
1249                         {0x34u, 0x08u},\r
1250                         {0x35u, 0xA0u},\r
1251                         {0x36u, 0x02u},\r
1252                         {0x38u, 0x28u},\r
1253                         {0x3Au, 0x81u},\r
1254                         {0x3Du, 0x20u},\r
1255                         {0x3Fu, 0x84u},\r
1256                         {0x58u, 0x80u},\r
1257                         {0x60u, 0x02u},\r
1258                         {0x61u, 0x80u},\r
1259                         {0x81u, 0x10u},\r
1260                         {0x82u, 0x01u},\r
1261                         {0x84u, 0x80u},\r
1262                         {0x86u, 0x12u},\r
1263                         {0x8Bu, 0x04u},\r
1264                         {0x8Cu, 0x40u},\r
1265                         {0x8Eu, 0x02u},\r
1266                         {0x8Fu, 0x60u},\r
1267                         {0x90u, 0x40u},\r
1268                         {0x94u, 0x2Au},\r
1269                         {0x95u, 0xE0u},\r
1270                         {0x97u, 0x80u},\r
1271                         {0x98u, 0x08u},\r
1272                         {0x99u, 0xA0u},\r
1273                         {0x9Bu, 0x40u},\r
1274                         {0x9Du, 0x40u},\r
1275                         {0x9Eu, 0x10u},\r
1276                         {0xA0u, 0x08u},\r
1277                         {0xA1u, 0x20u},\r
1278                         {0xA3u, 0x40u},\r
1279                         {0xA4u, 0x80u},\r
1280                         {0xA6u, 0x30u},\r
1281                         {0xABu, 0x04u},\r
1282                         {0xB2u, 0x10u},\r
1283                         {0xB3u, 0x02u},\r
1284                         {0xB4u, 0x40u},\r
1285                         {0xB6u, 0x80u},\r
1286                         {0xC0u, 0xE1u},\r
1287                         {0xC2u, 0xBBu},\r
1288                         {0xC4u, 0xF9u},\r
1289                         {0xCAu, 0xC9u},\r
1290                         {0xCCu, 0xFFu},\r
1291                         {0xCEu, 0x7Fu},\r
1292                         {0xD6u, 0x08u},\r
1293                         {0xD8u, 0x08u},\r
1294                         {0xE2u, 0x50u},\r
1295                         {0xE4u, 0x20u},\r
1296                         {0xE6u, 0x92u},\r
1297                         {0xEAu, 0x49u},\r
1298                         {0xECu, 0x80u},\r
1299                         {0xEEu, 0x20u},\r
1300                         {0x02u, 0x02u},\r
1301                         {0x06u, 0x08u},\r
1302                         {0x0Bu, 0x08u},\r
1303                         {0x0Du, 0x04u},\r
1304                         {0x0Fu, 0x08u},\r
1305                         {0x15u, 0x09u},\r
1306                         {0x17u, 0x02u},\r
1307                         {0x1Au, 0x04u},\r
1308                         {0x1Eu, 0x01u},\r
1309                         {0x1Fu, 0x07u},\r
1310                         {0x20u, 0x04u},\r
1311                         {0x22u, 0x08u},\r
1312                         {0x2Du, 0x0Au},\r
1313                         {0x2Fu, 0x05u},\r
1314                         {0x30u, 0x01u},\r
1315                         {0x31u, 0x0Fu},\r
1316                         {0x32u, 0x0Cu},\r
1317                         {0x34u, 0x02u},\r
1318                         {0x3Eu, 0x04u},\r
1319                         {0x58u, 0x04u},\r
1320                         {0x59u, 0x04u},\r
1321                         {0x5Bu, 0x04u},\r
1322                         {0x5Cu, 0x19u},\r
1323                         {0x5Fu, 0x01u},\r
1324                         {0x80u, 0x01u},\r
1325                         {0x82u, 0x02u},\r
1326                         {0x84u, 0x08u},\r
1327                         {0x86u, 0x04u},\r
1328                         {0x8Bu, 0x02u},\r
1329                         {0x8Cu, 0x08u},\r
1330                         {0x8Eu, 0x04u},\r
1331                         {0x90u, 0x02u},\r
1332                         {0x92u, 0x01u},\r
1333                         {0x94u, 0x02u},\r
1334                         {0x96u, 0x01u},\r
1335                         {0x97u, 0x08u},\r
1336                         {0x9Bu, 0x01u},\r
1337                         {0x9Cu, 0x04u},\r
1338                         {0x9Du, 0x01u},\r
1339                         {0x9Eu, 0x08u},\r
1340                         {0x9Fu, 0x02u},\r
1341                         {0xA0u, 0x08u},\r
1342                         {0xA2u, 0x04u},\r
1343                         {0xA4u, 0x02u},\r
1344                         {0xA6u, 0x01u},\r
1345                         {0xA7u, 0x10u},\r
1346                         {0xA8u, 0x02u},\r
1347                         {0xAAu, 0x01u},\r
1348                         {0xABu, 0x04u},\r
1349                         {0xACu, 0x08u},\r
1350                         {0xAEu, 0x04u},\r
1351                         {0xB0u, 0x03u},\r
1352                         {0xB1u, 0x04u},\r
1353                         {0xB3u, 0x10u},\r
1354                         {0xB5u, 0x08u},\r
1355                         {0xB6u, 0x0Cu},\r
1356                         {0xB7u, 0x03u},\r
1357                         {0xBAu, 0x82u},\r
1358                         {0xBFu, 0x40u},\r
1359                         {0xD6u, 0x08u},\r
1360                         {0xD8u, 0x04u},\r
1361                         {0xD9u, 0x04u},\r
1362                         {0xDBu, 0x04u},\r
1363                         {0xDCu, 0x99u},\r
1364                         {0xDDu, 0x90u},\r
1365                         {0xDFu, 0x01u},\r
1366                         {0x00u, 0x88u},\r
1367                         {0x02u, 0x80u},\r
1368                         {0x05u, 0x01u},\r
1369                         {0x06u, 0x10u},\r
1370                         {0x08u, 0x02u},\r
1371                         {0x0Au, 0x22u},\r
1372                         {0x0Fu, 0x0Au},\r
1373                         {0x12u, 0x4Au},\r
1374                         {0x13u, 0x04u},\r
1375                         {0x14u, 0x40u},\r
1376                         {0x18u, 0x40u},\r
1377                         {0x19u, 0x80u},\r
1378                         {0x1Au, 0x03u},\r
1379                         {0x1Cu, 0x88u},\r
1380                         {0x1Du, 0x15u},\r
1381                         {0x22u, 0x0Au},\r
1382                         {0x23u, 0x06u},\r
1383                         {0x27u, 0x40u},\r
1384                         {0x28u, 0x10u},\r
1385                         {0x29u, 0x10u},\r
1386                         {0x2Fu, 0x02u},\r
1387                         {0x30u, 0xC0u},\r
1388                         {0x31u, 0x20u},\r
1389                         {0x32u, 0x08u},\r
1390                         {0x34u, 0x08u},\r
1391                         {0x37u, 0x40u},\r
1392                         {0x38u, 0x20u},\r
1393                         {0x3Eu, 0x10u},\r
1394                         {0x3Fu, 0x80u},\r
1395                         {0x58u, 0x10u},\r
1396                         {0x5Au, 0x60u},\r
1397                         {0x5Cu, 0x24u},\r
1398                         {0x5Du, 0x02u},\r
1399                         {0x5Fu, 0x80u},\r
1400                         {0x62u, 0x40u},\r
1401                         {0x63u, 0x02u},\r
1402                         {0x64u, 0x01u},\r
1403                         {0x80u, 0x04u},\r
1404                         {0x81u, 0x40u},\r
1405                         {0x85u, 0x02u},\r
1406                         {0x8Au, 0x01u},\r
1407                         {0x8Cu, 0x01u},\r
1408                         {0x8Du, 0x20u},\r
1409                         {0x92u, 0x70u},\r
1410                         {0x94u, 0x2Cu},\r
1411                         {0x95u, 0x60u},\r
1412                         {0x97u, 0x80u},\r
1413                         {0x98u, 0x2Bu},\r
1414                         {0x9Bu, 0x80u},\r
1415                         {0x9Du, 0xC4u},\r
1416                         {0x9Fu, 0x02u},\r
1417                         {0xA0u, 0x08u},\r
1418                         {0xA1u, 0x20u},\r
1419                         {0xA3u, 0x40u},\r
1420                         {0xA4u, 0x80u},\r
1421                         {0xA6u, 0x30u},\r
1422                         {0xA8u, 0x10u},\r
1423                         {0xAAu, 0x40u},\r
1424                         {0xABu, 0x80u},\r
1425                         {0xACu, 0x20u},\r
1426                         {0xADu, 0x01u},\r
1427                         {0xB6u, 0x60u},\r
1428                         {0xB7u, 0x40u},\r
1429                         {0xC0u, 0x3Du},\r
1430                         {0xC2u, 0xCDu},\r
1431                         {0xC4u, 0x1Fu},\r
1432                         {0xCAu, 0x16u},\r
1433                         {0xCCu, 0x5Eu},\r
1434                         {0xCEu, 0x34u},\r
1435                         {0xD6u, 0xF8u},\r
1436                         {0xD8u, 0x18u},\r
1437                         {0xE0u, 0x11u},\r
1438                         {0xE2u, 0xAAu},\r
1439                         {0xE6u, 0x84u},\r
1440                         {0xEAu, 0x04u},\r
1441                         {0xECu, 0x40u},\r
1442                         {0x07u, 0x02u},\r
1443                         {0x08u, 0x30u},\r
1444                         {0x0Au, 0xC0u},\r
1445                         {0x0Cu, 0x60u},\r
1446                         {0x0Eu, 0x90u},\r
1447                         {0x10u, 0xFFu},\r
1448                         {0x14u, 0x05u},\r
1449                         {0x16u, 0x0Au},\r
1450                         {0x17u, 0x01u},\r
1451                         {0x18u, 0x03u},\r
1452                         {0x1Au, 0x0Cu},\r
1453                         {0x1Du, 0x01u},\r
1454                         {0x1Eu, 0xFFu},\r
1455                         {0x1Fu, 0x02u},\r
1456                         {0x20u, 0x0Fu},\r
1457                         {0x22u, 0xF0u},\r
1458                         {0x24u, 0x50u},\r
1459                         {0x26u, 0xA0u},\r
1460                         {0x28u, 0x06u},\r
1461                         {0x2Au, 0x09u},\r
1462                         {0x2Eu, 0xFFu},\r
1463                         {0x2Fu, 0x04u},\r
1464                         {0x30u, 0xFFu},\r
1465                         {0x33u, 0x03u},\r
1466                         {0x35u, 0x04u},\r
1467                         {0x3Eu, 0x01u},\r
1468                         {0x3Fu, 0x04u},\r
1469                         {0x56u, 0x08u},\r
1470                         {0x58u, 0x04u},\r
1471                         {0x59u, 0x04u},\r
1472                         {0x5Bu, 0x04u},\r
1473                         {0x5Cu, 0x90u},\r
1474                         {0x5Du, 0x90u},\r
1475                         {0x5Fu, 0x01u},\r
1476                         {0x83u, 0x10u},\r
1477                         {0x84u, 0x50u},\r
1478                         {0x86u, 0xA0u},\r
1479                         {0x87u, 0x20u},\r
1480                         {0x88u, 0x30u},\r
1481                         {0x8Au, 0xC0u},\r
1482                         {0x8Bu, 0x0Eu},\r
1483                         {0x8Du, 0x01u},\r
1484                         {0x8Eu, 0xFFu},\r
1485                         {0x94u, 0x05u},\r
1486                         {0x95u, 0x32u},\r
1487                         {0x96u, 0x0Au},\r
1488                         {0x97u, 0x04u},\r
1489                         {0x98u, 0x03u},\r
1490                         {0x99u, 0x01u},\r
1491                         {0x9Au, 0x0Cu},\r
1492                         {0x9Cu, 0x0Fu},\r
1493                         {0x9Du, 0x01u},\r
1494                         {0x9Eu, 0xF0u},\r
1495                         {0xA1u, 0x01u},\r
1496                         {0xA2u, 0xFFu},\r
1497                         {0xA5u, 0x34u},\r
1498                         {0xA6u, 0xFFu},\r
1499                         {0xA7u, 0x0Au},\r
1500                         {0xA8u, 0x09u},\r
1501                         {0xA9u, 0x28u},\r
1502                         {0xAAu, 0x06u},\r
1503                         {0xABu, 0x10u},\r
1504                         {0xACu, 0x90u},\r
1505                         {0xAEu, 0x60u},\r
1506                         {0xAFu, 0x20u},\r
1507                         {0xB0u, 0xFFu},\r
1508                         {0xB3u, 0x01u},\r
1509                         {0xB5u, 0x1Eu},\r
1510                         {0xB7u, 0x20u},\r
1511                         {0xB9u, 0x08u},\r
1512                         {0xBEu, 0x01u},\r
1513                         {0xBFu, 0x44u},\r
1514                         {0xD8u, 0x04u},\r
1515                         {0xD9u, 0x04u},\r
1516                         {0xDCu, 0x10u},\r
1517                         {0xDFu, 0x01u},\r
1518                         {0x01u, 0x40u},\r
1519                         {0x02u, 0x04u},\r
1520                         {0x04u, 0x28u},\r
1521                         {0x05u, 0x40u},\r
1522                         {0x06u, 0x14u},\r
1523                         {0x09u, 0x1Au},\r
1524                         {0x0Bu, 0x02u},\r
1525                         {0x0Cu, 0x80u},\r
1526                         {0x0Du, 0x28u},\r
1527                         {0x0Eu, 0x20u},\r
1528                         {0x10u, 0x86u},\r
1529                         {0x12u, 0x10u},\r
1530                         {0x14u, 0x04u},\r
1531                         {0x15u, 0x60u},\r
1532                         {0x17u, 0x09u},\r
1533                         {0x18u, 0x40u},\r
1534                         {0x1Eu, 0x80u},\r
1535                         {0x22u, 0x10u},\r
1536                         {0x23u, 0x20u},\r
1537                         {0x24u, 0x10u},\r
1538                         {0x25u, 0x30u},\r
1539                         {0x26u, 0x80u},\r
1540                         {0x28u, 0x02u},\r
1541                         {0x2Cu, 0x20u},\r
1542                         {0x2Du, 0x80u},\r
1543                         {0x2Eu, 0x20u},\r
1544                         {0x2Fu, 0x40u},\r
1545                         {0x30u, 0x80u},\r
1546                         {0x31u, 0x08u},\r
1547                         {0x34u, 0x08u},\r
1548                         {0x36u, 0x60u},\r
1549                         {0x38u, 0x08u},\r
1550                         {0x3Cu, 0x44u},\r
1551                         {0x3Du, 0x21u},\r
1552                         {0x5Au, 0x80u},\r
1553                         {0x60u, 0x02u},\r
1554                         {0x65u, 0x40u},\r
1555                         {0x67u, 0x02u},\r
1556                         {0x78u, 0x01u},\r
1557                         {0x7Au, 0x80u},\r
1558                         {0x80u, 0x22u},\r
1559                         {0x83u, 0x2Au},\r
1560                         {0x84u, 0x08u},\r
1561                         {0x85u, 0x02u},\r
1562                         {0x87u, 0x01u},\r
1563                         {0x88u, 0x08u},\r
1564                         {0x8Du, 0x04u},\r
1565                         {0x8Eu, 0x10u},\r
1566                         {0xC0u, 0xE3u},\r
1567                         {0xC2u, 0xEFu},\r
1568                         {0xC4u, 0xFFu},\r
1569                         {0xCAu, 0xF8u},\r
1570                         {0xCCu, 0x7Au},\r
1571                         {0xCEu, 0xF2u},\r
1572                         {0xD6u, 0x08u},\r
1573                         {0xD8u, 0x08u},\r
1574                         {0xE0u, 0x81u},\r
1575                         {0xE2u, 0x50u},\r
1576                         {0xE4u, 0x11u},\r
1577                         {0x81u, 0x5Cu},\r
1578                         {0x84u, 0x14u},\r
1579                         {0x85u, 0x24u},\r
1580                         {0x87u, 0x10u},\r
1581                         {0x88u, 0x3Fu},\r
1582                         {0x89u, 0x50u},\r
1583                         {0x8Au, 0x40u},\r
1584                         {0x8Bu, 0x0Cu},\r
1585                         {0x8Cu, 0x34u},\r
1586                         {0x90u, 0x34u},\r
1587                         {0x91u, 0x21u},\r
1588                         {0x93u, 0x1Eu},\r
1589                         {0x94u, 0x20u},\r
1590                         {0x95u, 0x11u},\r
1591                         {0x96u, 0x02u},\r
1592                         {0x97u, 0x22u},\r
1593                         {0x98u, 0x08u},\r
1594                         {0x99u, 0x30u},\r
1595                         {0x9Au, 0x75u},\r
1596                         {0x9Bu, 0x0Fu},\r
1597                         {0x9Cu, 0x4Bu},\r
1598                         {0x9Eu, 0x30u},\r
1599                         {0xA0u, 0x34u},\r
1600                         {0xA1u, 0x5Cu},\r
1601                         {0xA5u, 0x54u},\r
1602                         {0xA6u, 0x34u},\r
1603                         {0xA7u, 0x08u},\r
1604                         {0xA8u, 0x14u},\r
1605                         {0xA9u, 0x08u},\r
1606                         {0xAAu, 0x20u},\r
1607                         {0xADu, 0x0Cu},\r
1608                         {0xAFu, 0x50u},\r
1609                         {0xB3u, 0x30u},\r
1610                         {0xB4u, 0x07u},\r
1611                         {0xB5u, 0x0Fu},\r
1612                         {0xB6u, 0x78u},\r
1613                         {0xB7u, 0x40u},\r
1614                         {0xB8u, 0x80u},\r
1615                         {0xBAu, 0x30u},\r
1616                         {0xBBu, 0x08u},\r
1617                         {0xBFu, 0x40u},\r
1618                         {0xD8u, 0x04u},\r
1619                         {0xD9u, 0x04u},\r
1620                         {0xDFu, 0x01u},\r
1621                         {0x00u, 0x04u},\r
1622                         {0x01u, 0x01u},\r
1623                         {0x03u, 0x06u},\r
1624                         {0x06u, 0x02u},\r
1625                         {0x07u, 0x14u},\r
1626                         {0x09u, 0x20u},\r
1627                         {0x0Bu, 0xA2u},\r
1628                         {0x0Cu, 0x02u},\r
1629                         {0x0Du, 0x08u},\r
1630                         {0x0Eu, 0x06u},\r
1631                         {0x10u, 0x82u},\r
1632                         {0x11u, 0x04u},\r
1633                         {0x12u, 0x08u},\r
1634                         {0x15u, 0x01u},\r
1635                         {0x17u, 0x28u},\r
1636                         {0x18u, 0x04u},\r
1637                         {0x19u, 0x80u},\r
1638                         {0x1Bu, 0x03u},\r
1639                         {0x1Du, 0x10u},\r
1640                         {0x1Eu, 0x06u},\r
1641                         {0x1Fu, 0x70u},\r
1642                         {0x21u, 0x20u},\r
1643                         {0x24u, 0x29u},\r
1644                         {0x25u, 0x04u},\r
1645                         {0x26u, 0x08u},\r
1646                         {0x27u, 0x15u},\r
1647                         {0x29u, 0x01u},\r
1648                         {0x2Bu, 0x21u},\r
1649                         {0x2Cu, 0x02u},\r
1650                         {0x2Du, 0x05u},\r
1651                         {0x2Fu, 0x04u},\r
1652                         {0x30u, 0x82u},\r
1653                         {0x32u, 0x10u},\r
1654                         {0x33u, 0x04u},\r
1655                         {0x35u, 0x10u},\r
1656                         {0x36u, 0x01u},\r
1657                         {0x37u, 0x04u},\r
1658                         {0x38u, 0x20u},\r
1659                         {0x39u, 0x05u},\r
1660                         {0x3Bu, 0x80u},\r
1661                         {0x3Du, 0x08u},\r
1662                         {0x3Eu, 0x12u},\r
1663                         {0x40u, 0x01u},\r
1664                         {0x43u, 0x24u},\r
1665                         {0x49u, 0x05u},\r
1666                         {0x4Au, 0x05u},\r
1667                         {0x4Bu, 0x02u},\r
1668                         {0x51u, 0x08u},\r
1669                         {0x52u, 0x50u},\r
1670                         {0x53u, 0x04u},\r
1671                         {0x60u, 0x20u},\r
1672                         {0x61u, 0x0Au},\r
1673                         {0x68u, 0x0Au},\r
1674                         {0x69u, 0x05u},\r
1675                         {0x6Au, 0x30u},\r
1676                         {0x6Bu, 0x68u},\r
1677                         {0x70u, 0x80u},\r
1678                         {0x72u, 0x02u},\r
1679                         {0x8Eu, 0x04u},\r
1680                         {0x94u, 0x08u},\r
1681                         {0x95u, 0x04u},\r
1682                         {0x96u, 0x10u},\r
1683                         {0x97u, 0x82u},\r
1684                         {0x9Cu, 0x20u},\r
1685                         {0x9Du, 0x94u},\r
1686                         {0x9Eu, 0x52u},\r
1687                         {0x9Fu, 0x45u},\r
1688                         {0xA1u, 0x02u},\r
1689                         {0xA4u, 0x0Au},\r
1690                         {0xA6u, 0x01u},\r
1691                         {0xC0u, 0xEFu},\r
1692                         {0xC2u, 0xFFu},\r
1693                         {0xC4u, 0x7Fu},\r
1694                         {0xCAu, 0xFBu},\r
1695                         {0xCCu, 0xEFu},\r
1696                         {0xCEu, 0xEFu},\r
1697                         {0xD0u, 0x0Eu},\r
1698                         {0xD2u, 0x0Cu},\r
1699                         {0xD8u, 0x01u},\r
1700                         {0xE0u, 0x40u},\r
1701                         {0x00u, 0x08u},\r
1702                         {0x03u, 0x01u},\r
1703                         {0x04u, 0x01u},\r
1704                         {0x07u, 0x0Cu},\r
1705                         {0x08u, 0x04u},\r
1706                         {0x09u, 0x60u},\r
1707                         {0x11u, 0x14u},\r
1708                         {0x12u, 0x08u},\r
1709                         {0x13u, 0x43u},\r
1710                         {0x14u, 0x08u},\r
1711                         {0x15u, 0x11u},\r
1712                         {0x17u, 0x22u},\r
1713                         {0x18u, 0x07u},\r
1714                         {0x19u, 0x28u},\r
1715                         {0x1Bu, 0x13u},\r
1716                         {0x1Eu, 0x02u},\r
1717                         {0x22u, 0x08u},\r
1718                         {0x24u, 0x08u},\r
1719                         {0x2Au, 0x07u},\r
1720                         {0x2Cu, 0x08u},\r
1721                         {0x2Fu, 0x82u},\r
1722                         {0x30u, 0x07u},\r
1723                         {0x33u, 0x0Fu},\r
1724                         {0x34u, 0x08u},\r
1725                         {0x35u, 0x70u},\r
1726                         {0x37u, 0x80u},\r
1727                         {0x39u, 0x20u},\r
1728                         {0x3Eu, 0x11u},\r
1729                         {0x54u, 0x40u},\r
1730                         {0x56u, 0x04u},\r
1731                         {0x58u, 0x04u},\r
1732                         {0x59u, 0x04u},\r
1733                         {0x5Bu, 0x04u},\r
1734                         {0x5Fu, 0x01u},\r
1735                         {0x82u, 0x07u},\r
1736                         {0x84u, 0x09u},\r
1737                         {0x85u, 0x09u},\r
1738                         {0x86u, 0x02u},\r
1739                         {0x87u, 0x06u},\r
1740                         {0x8Cu, 0x04u},\r
1741                         {0x8Du, 0x0Bu},\r
1742                         {0x8Eu, 0x08u},\r
1743                         {0x8Fu, 0x04u},\r
1744                         {0x91u, 0x04u},\r
1745                         {0x92u, 0x08u},\r
1746                         {0x93u, 0x03u},\r
1747                         {0xA4u, 0x0Au},\r
1748                         {0xA6u, 0x05u},\r
1749                         {0xA9u, 0x0Du},\r
1750                         {0xABu, 0x02u},\r
1751                         {0xB0u, 0x0Fu},\r
1752                         {0xB1u, 0x07u},\r
1753                         {0xB7u, 0x08u},\r
1754                         {0xBBu, 0x02u},\r
1755                         {0xBFu, 0x40u},\r
1756                         {0xD4u, 0x09u},\r
1757                         {0xD6u, 0x04u},\r
1758                         {0xD8u, 0x04u},\r
1759                         {0xD9u, 0x04u},\r
1760                         {0xDBu, 0x04u},\r
1761                         {0xDCu, 0x01u},\r
1762                         {0xDFu, 0x01u},\r
1763                         {0x01u, 0x0Bu},\r
1764                         {0x03u, 0x02u},\r
1765                         {0x04u, 0x08u},\r
1766                         {0x05u, 0x10u},\r
1767                         {0x07u, 0x40u},\r
1768                         {0x0Au, 0x40u},\r
1769                         {0x0Cu, 0x02u},\r
1770                         {0x0Du, 0x21u},\r
1771                         {0x0Eu, 0x12u},\r
1772                         {0x13u, 0x08u},\r
1773                         {0x15u, 0x04u},\r
1774                         {0x16u, 0x42u},\r
1775                         {0x17u, 0x20u},\r
1776                         {0x19u, 0x02u},\r
1777                         {0x1Du, 0x01u},\r
1778                         {0x1Fu, 0x10u},\r
1779                         {0x21u, 0x02u},\r
1780                         {0x23u, 0x01u},\r
1781                         {0x24u, 0x01u},\r
1782                         {0x25u, 0x34u},\r
1783                         {0x27u, 0x20u},\r
1784                         {0x29u, 0x10u},\r
1785                         {0x2Fu, 0x01u},\r
1786                         {0x31u, 0x02u},\r
1787                         {0x35u, 0x10u},\r
1788                         {0x36u, 0x01u},\r
1789                         {0x37u, 0x04u},\r
1790                         {0x38u, 0x08u},\r
1791                         {0x3Bu, 0x80u},\r
1792                         {0x3Cu, 0x01u},\r
1793                         {0x3Du, 0x28u},\r
1794                         {0x58u, 0x20u},\r
1795                         {0x59u, 0x84u},\r
1796                         {0x5Bu, 0x01u},\r
1797                         {0x62u, 0x02u},\r
1798                         {0x63u, 0x01u},\r
1799                         {0x66u, 0x51u},\r
1800                         {0x67u, 0x20u},\r
1801                         {0x81u, 0x01u},\r
1802                         {0x92u, 0x40u},\r
1803                         {0x94u, 0x08u},\r
1804                         {0x95u, 0x07u},\r
1805                         {0x99u, 0x08u},\r
1806                         {0x9Bu, 0x08u},\r
1807                         {0x9Du, 0x10u},\r
1808                         {0x9Eu, 0x03u},\r
1809                         {0x9Fu, 0x40u},\r
1810                         {0xA3u, 0x02u},\r
1811                         {0xA4u, 0x08u},\r
1812                         {0xA6u, 0x03u},\r
1813                         {0xA9u, 0x40u},\r
1814                         {0xAAu, 0x04u},\r
1815                         {0xB6u, 0x01u},\r
1816                         {0xC0u, 0x7Du},\r
1817                         {0xC2u, 0xF8u},\r
1818                         {0xC4u, 0xF4u},\r
1819                         {0xCAu, 0x14u},\r
1820                         {0xCCu, 0xE1u},\r
1821                         {0xCEu, 0xEAu},\r
1822                         {0xD6u, 0x0Fu},\r
1823                         {0xD8u, 0xF9u},\r
1824                         {0xE8u, 0x01u},\r
1825                         {0xEEu, 0x40u},\r
1826                         {0x9Cu, 0x80u},\r
1827                         {0xABu, 0x20u},\r
1828                         {0xB1u, 0x86u},\r
1829                         {0xB3u, 0x20u},\r
1830                         {0x88u, 0x80u},\r
1831                         {0x9Cu, 0x80u},\r
1832                         {0x12u, 0x08u},\r
1833                         {0x16u, 0x80u},\r
1834                         {0x17u, 0x20u},\r
1835                         {0x32u, 0x04u},\r
1836                         {0x36u, 0x80u},\r
1837                         {0x37u, 0x08u},\r
1838                         {0x38u, 0x01u},\r
1839                         {0x3Au, 0x80u},\r
1840                         {0x3Cu, 0x04u},\r
1841                         {0x3Du, 0x40u},\r
1842                         {0x41u, 0x10u},\r
1843                         {0x5Au, 0x01u},\r
1844                         {0x5Bu, 0x40u},\r
1845                         {0x5Cu, 0x02u},\r
1846                         {0x62u, 0x02u},\r
1847                         {0x65u, 0x04u},\r
1848                         {0x81u, 0x40u},\r
1849                         {0x8Au, 0x02u},\r
1850                         {0x8Du, 0x04u},\r
1851                         {0xC4u, 0xE0u},\r
1852                         {0xCCu, 0xE0u},\r
1853                         {0xCEu, 0xF0u},\r
1854                         {0xD0u, 0x10u},\r
1855                         {0xD4u, 0x80u},\r
1856                         {0xD6u, 0xC0u},\r
1857                         {0xD8u, 0xC0u},\r
1858                         {0xE6u, 0x20u},\r
1859                         {0x33u, 0x18u},\r
1860                         {0x36u, 0x08u},\r
1861                         {0x37u, 0x20u},\r
1862                         {0x38u, 0x20u},\r
1863                         {0x51u, 0x08u},\r
1864                         {0x56u, 0x20u},\r
1865                         {0x58u, 0x10u},\r
1866                         {0x5Cu, 0x02u},\r
1867                         {0x84u, 0x02u},\r
1868                         {0x89u, 0x10u},\r
1869                         {0x94u, 0x04u},\r
1870                         {0x95u, 0x20u},\r
1871                         {0x96u, 0x09u},\r
1872                         {0x9Bu, 0x30u},\r
1873                         {0x9Fu, 0x08u},\r
1874                         {0xA6u, 0x80u},\r
1875                         {0xA8u, 0x01u},\r
1876                         {0xAAu, 0x08u},\r
1877                         {0xABu, 0x50u},\r
1878                         {0xACu, 0x02u},\r
1879                         {0xCCu, 0xF0u},\r
1880                         {0xCEu, 0x10u},\r
1881                         {0xD4u, 0xE0u},\r
1882                         {0xD6u, 0x80u},\r
1883                         {0xE6u, 0x40u},\r
1884                         {0xEAu, 0x80u},\r
1885                         {0xEEu, 0xC0u},\r
1886                         {0x12u, 0x80u},\r
1887                         {0x32u, 0x10u},\r
1888                         {0x58u, 0x08u},\r
1889                         {0x88u, 0x10u},\r
1890                         {0x8Au, 0x08u},\r
1891                         {0x94u, 0x24u},\r
1892                         {0x96u, 0x09u},\r
1893                         {0x9Cu, 0x10u},\r
1894                         {0x9Fu, 0x08u},\r
1895                         {0xA6u, 0x88u},\r
1896                         {0xA7u, 0x08u},\r
1897                         {0xAAu, 0x20u},\r
1898                         {0xB5u, 0x08u},\r
1899                         {0xC4u, 0x10u},\r
1900                         {0xCCu, 0x10u},\r
1901                         {0xD6u, 0x40u},\r
1902                         {0xEAu, 0x20u},\r
1903                         {0x86u, 0x04u},\r
1904                         {0x87u, 0x08u},\r
1905                         {0x8Bu, 0x08u},\r
1906                         {0x8Cu, 0x10u},\r
1907                         {0x8Eu, 0x10u},\r
1908                         {0x94u, 0x24u},\r
1909                         {0x96u, 0x28u},\r
1910                         {0x9Fu, 0x08u},\r
1911                         {0xA7u, 0x08u},\r
1912                         {0xA8u, 0x08u},\r
1913                         {0xB2u, 0x01u},\r
1914                         {0xE6u, 0x50u},\r
1915                         {0xEEu, 0x20u},\r
1916                         {0x09u, 0x80u},\r
1917                         {0x0Au, 0x20u},\r
1918                         {0x0Cu, 0x02u},\r
1919                         {0x10u, 0x20u},\r
1920                         {0x15u, 0x04u},\r
1921                         {0x50u, 0x08u},\r
1922                         {0x52u, 0x02u},\r
1923                         {0x57u, 0x08u},\r
1924                         {0x5Cu, 0x40u},\r
1925                         {0x82u, 0x02u},\r
1926                         {0x83u, 0x08u},\r
1927                         {0x8Eu, 0x10u},\r
1928                         {0xC2u, 0x0Eu},\r
1929                         {0xC4u, 0x0Cu},\r
1930                         {0xD4u, 0x07u},\r
1931                         {0xD6u, 0x04u},\r
1932                         {0xE2u, 0x02u},\r
1933                         {0x00u, 0x08u},\r
1934                         {0x03u, 0x08u},\r
1935                         {0x05u, 0x02u},\r
1936                         {0x06u, 0x02u},\r
1937                         {0x09u, 0x12u},\r
1938                         {0x0Du, 0x24u},\r
1939                         {0x80u, 0x08u},\r
1940                         {0x82u, 0x02u},\r
1941                         {0x85u, 0x06u},\r
1942                         {0x89u, 0x02u},\r
1943                         {0x8Bu, 0x08u},\r
1944                         {0x8Cu, 0x40u},\r
1945                         {0x91u, 0x04u},\r
1946                         {0x94u, 0x40u},\r
1947                         {0xA0u, 0x20u},\r
1948                         {0xA4u, 0x08u},\r
1949                         {0xA8u, 0x02u},\r
1950                         {0xB5u, 0x80u},\r
1951                         {0xC0u, 0x0Fu},\r
1952                         {0xC2u, 0x0Fu},\r
1953                         {0xE0u, 0x02u},\r
1954                         {0xE2u, 0x05u},\r
1955                         {0xEAu, 0x08u},\r
1956                         {0x85u, 0x04u},\r
1957                         {0x88u, 0x02u},\r
1958                         {0x91u, 0x04u},\r
1959                         {0xA0u, 0x04u},\r
1960                         {0xA1u, 0x10u},\r
1961                         {0xA8u, 0x20u},\r
1962                         {0xADu, 0x20u},\r
1963                         {0xE6u, 0x01u},\r
1964                         {0x09u, 0x20u},\r
1965                         {0x0Bu, 0x20u},\r
1966                         {0x0Cu, 0x02u},\r
1967                         {0x0Eu, 0x08u},\r
1968                         {0x87u, 0x10u},\r
1969                         {0x8Du, 0x20u},\r
1970                         {0x8Eu, 0x04u},\r
1971                         {0xA4u, 0x02u},\r
1972                         {0xA9u, 0x10u},\r
1973                         {0xACu, 0x04u},\r
1974                         {0xC2u, 0x0Fu},\r
1975                         {0xE2u, 0x02u},\r
1976                         {0xE6u, 0x02u},\r
1977                         {0x83u, 0x40u},\r
1978                         {0x98u, 0x20u},\r
1979                         {0xA8u, 0x20u},\r
1980                         {0xB4u, 0x04u},\r
1981                         {0xE2u, 0x20u},\r
1982                         {0xEEu, 0x20u},\r
1983                         {0x04u, 0x02u},\r
1984                         {0x57u, 0x40u},\r
1985                         {0x58u, 0x20u},\r
1986                         {0x8Cu, 0x01u},\r
1987                         {0x98u, 0x20u},\r
1988                         {0xA3u, 0x40u},\r
1989                         {0xC0u, 0x20u},\r
1990                         {0xD4u, 0xC0u},\r
1991                         {0x01u, 0x04u},\r
1992                         {0x89u, 0x04u},\r
1993                         {0xC0u, 0x08u},\r
1994                         {0xE2u, 0x04u},\r
1995                         {0x10u, 0x03u},\r
1996                         {0x1Au, 0x03u},\r
1997                         {0x00u, 0xFDu},\r
1998                         {0x01u, 0xBFu},\r
1999                         {0x02u, 0x2Au},\r
2000                         {0x10u, 0x55u},\r
2001                 };\r
2002 \r
2003 \r
2004 \r
2005                 CYPACKED typedef struct {\r
2006                         void CYFAR *address;\r
2007                         uint16 size;\r
2008                 } CYPACKED_ATTR cfg_memset_t;\r
2009 \r
2010 \r
2011                 CYPACKED typedef struct {\r
2012                         void CYFAR *dest;\r
2013                         const void CYCODE *src;\r
2014                         uint16 size;\r
2015                 } CYPACKED_ATTR cfg_memcpy_t;\r
2016 \r
2017                 static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
2018                         /* address, size */\r
2019                         {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
2020                         {(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
2021                         {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
2022                         {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},\r
2023                         {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
2024                         {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
2025                         {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
2026                 };\r
2027 \r
2028                 /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
2029                 static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
2030                         0x01u, 0xC0u, 0x00u, 0x02u, 0x40u, 0xC0u, 0x00u, 0x04u, 0x07u, 0x80u, 0x18u, 0x00u, 0x04u, 0x00u, 0x00u, 0xFFu, \r
2031                         0x08u, 0x90u, 0x21u, 0x40u, 0x22u, 0x1Fu, 0x08u, 0x20u, 0x40u, 0xC0u, 0x00u, 0x08u, 0x10u, 0xC0u, 0x00u, 0x01u, \r
2032                         0x01u, 0x00u, 0x00u, 0x9Fu, 0x01u, 0x7Fu, 0x00u, 0x80u, 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x60u, \r
2033                         0x40u, 0x00u, 0x00u, 0x00u, 0x3Fu, 0xFFu, 0x08u, 0x00u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x10u, \r
2034                         0x52u, 0x03u, 0x10u, 0x00u, 0x06u, 0xBEu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
2035                         0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, \r
2036                         0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
2037                         0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
2038 \r
2039                 /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
2040                 static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
2041                         0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};\r
2042 \r
2043                 static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
2044                         /* dest, src, size */\r
2045                         {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},\r
2046                         {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
2047                 };\r
2048 \r
2049                 uint8 CYDATA i;\r
2050 \r
2051                 /* Zero out critical memory blocks before beginning configuration */\r
2052                 for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)\r
2053                 {\r
2054                         const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];\r
2055                         CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));\r
2056                 }\r
2057 \r
2058                 /* Copy device configuration data into registers */\r
2059                 for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)\r
2060                 {\r
2061                         const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];\r
2062                         void * CYDATA destPtr = mc->dest;\r
2063                         const void CYCODE * CYDATA srcPtr = mc->src;\r
2064                         uint16 CYDATA numBytes = mc->size;\r
2065                         CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);\r
2066                 }\r
2067 \r
2068                 cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);\r
2069 \r
2070                 /* Perform normal device configuration. Order is not critical for these items. */\r
2071                 CYMEMZERO((void CYFAR *)(CYREG_PHUB_CFGMEM0_CFG0), 4u);\r
2072                 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM1_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM1_VAL), 4u);\r
2073                 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM2_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM2_VAL), 4u);\r
2074                 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM3_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM3_VAL), 4u);\r
2075 \r
2076                 /* Enable digital routing */\r
2077                 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);\r
2078                 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);\r
2079 \r
2080                 /* Enable UDB array */\r
2081                 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u);\r
2082                 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);\r
2083         }\r
2084 \r
2085         /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */\r
2086         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u);\r
2087         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u);\r
2088         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR + 0x0000000Bu), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u);\r
2089         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);\r
2090         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u);\r
2091         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u);\r
2092         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);\r
2093         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u);\r
2094         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);\r
2095 \r
2096         /* Switch Boost to the precision bandgap reference from its internal reference */\r
2097         CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));\r
2098 \r
2099         /* Perform basic analog initialization to defaults */\r
2100         AnalogSetDefault();\r
2101 \r
2102         /* Configure alternate active mode */\r
2103         CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u);\r
2104 }\r