1 /*******************************************************************************
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2 * FILENAME: cyfitter_cfg.c
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6 * This file is automatically generated by PSoC Creator with device
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7 * initialization code. Except for the user defined sections in
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8 * CyClockStartupError(), this file should not be modified.
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10 ********************************************************************************
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11 * Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
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12 * You may use this file only in accordance with the license, terms, conditions,
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13 * disclaimers, and limitations in the end user license agreement accompanying
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14 * the software package with which this file was provided.
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15 ********************************************************************************/
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18 #include <cytypes.h>
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19 #include <cydevice_trm.h>
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20 #include <cyfitter.h>
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22 #include <cyfitter_cfg.h>
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24 #define CY_NEED_CYCLOCKSTARTUPERROR 1
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27 #if defined(__GNUC__) || defined(__ARMCC_VERSION)
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29 #define CYPACKED_ATTR __attribute__ ((packed))
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30 #define CYALIGNED __attribute__ ((aligned))
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31 #define CY_CFG_UNUSED __attribute__ ((unused))
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32 #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))
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34 #if defined(__ARMCC_VERSION)
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35 #define CY_CFG_MEMORY_BARRIER() __memory_changed()
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37 #define CY_CFG_MEMORY_BARRIER() __sync_synchronize()
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40 #elif defined(__ICCARM__)
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41 #include <intrinsics.h>
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43 #define CYPACKED __packed
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44 #define CYPACKED_ATTR
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45 #define CYALIGNED _Pragma("data_alignment=4")
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46 #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")
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47 #define CY_CFG_SECTION _Pragma("location=\".psocinit\"")
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49 #define CY_CFG_MEMORY_BARRIER() __DMB()
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52 #error Unsupported toolchain
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57 static void CYMEMZERO(void *s, size_t n);
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59 static void CYMEMZERO(void *s, size_t n)
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61 (void)memset(s, 0, n);
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64 static void CYCONFIGCPY(void *dest, const void *src, size_t n);
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66 static void CYCONFIGCPY(void *dest, const void *src, size_t n)
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68 (void)memcpy(dest, src, n);
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71 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);
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73 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
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75 (void)memcpy(dest, src, n);
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80 /* Clock startup error codes */
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81 #define CYCLOCKSTART_NO_ERROR 0u
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82 #define CYCLOCKSTART_XTAL_ERROR 1u
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83 #define CYCLOCKSTART_32KHZ_ERROR 2u
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84 #define CYCLOCKSTART_PLL_ERROR 3u
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86 #ifdef CY_NEED_CYCLOCKSTARTUPERROR
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87 /*******************************************************************************
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88 * Function Name: CyClockStartupError
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89 ********************************************************************************
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91 * If an error is encountered during clock configuration (crystal startup error,
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92 * PLL lock error, etc.), the system will end up here. Unless reimplemented by
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93 * the customer, this function will stop in an infinite loop.
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101 *******************************************************************************/
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103 static void CyClockStartupError(uint8 errorCode);
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105 static void CyClockStartupError(uint8 errorCode)
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107 /* To remove the compiler warning if errorCode not used. */
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108 errorCode = errorCode;
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110 /* `#START CyClockStartupError` */
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112 /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */
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113 /* we will end up here to allow the customer to implement something to */
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114 /* deal with the clock condition. */
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118 /* If nothing else, stop here since the clocks have not started */
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124 #define CY_CFG_BASE_ADDR_COUNT 41u
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125 CYPACKED typedef struct
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129 } CYPACKED_ATTR cy_cfg_addrvalue_t;
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133 /*******************************************************************************
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134 * Function Name: cfg_write_bytes32
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135 ********************************************************************************
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137 * This function is used for setting up the chip configuration areas that
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138 * contain relatively sparse data.
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146 *******************************************************************************/
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147 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]);
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148 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[])
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150 /* For 32-bit little-endian architectures */
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152 for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++)
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154 uint32 baseAddr = addr_table[i];
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155 uint8 count = (uint8)baseAddr;
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156 baseAddr &= 0xFFFFFF00u;
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157 while (count != 0u)
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159 CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value);
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166 /*******************************************************************************
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167 * Function Name: ClockSetup
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168 ********************************************************************************
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171 * Performs the initialization of all of the clocks in the device based on the
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172 * settings in the Clock tab of the DWR. This includes enabling the requested
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173 * clocks and setting the necessary dividers to produce the desired frequency.
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181 *******************************************************************************/
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182 static void ClockSetup(void);
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183 static void ClockSetup(void)
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189 /* Configure Digital Clocks based on settings from Clock DWR */
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190 CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u);
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191 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u);
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192 CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u);
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193 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u);
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194 CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);
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195 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);
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197 /* Configure ILO based on settings from Clock DWR */
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198 CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);
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200 /* Configure IMO based on settings from Clock DWR */
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201 CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u);
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202 CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));
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204 /* Configure PLL based on settings from Clock DWR */
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205 CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0B19u);
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206 CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);
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207 /* Wait up to 250us for the PLL to lock */
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209 for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--)
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211 pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));
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212 CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */
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214 /* If we ran out of time the PLL didn't lock so go to the error function */
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217 CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
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220 /* Configure Bus/Master Clock based on settings from Clock DWR */
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221 CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);
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222 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u);
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223 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u);
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224 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u);
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225 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u);
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227 /* Configure USB Clock based on settings from Clock DWR */
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228 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);
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229 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);
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231 CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x07u)));
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235 /* Analog API Functions */
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238 /*******************************************************************************
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239 * Function Name: AnalogSetDefault
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240 ********************************************************************************
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243 * Sets up the analog portions of the chip to default values based on chip
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244 * configuration options from the project.
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252 *******************************************************************************/
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253 static void AnalogSetDefault(void);
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254 static void AnalogSetDefault(void)
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256 uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));
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257 CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));
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258 CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));
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259 CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);
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263 /*******************************************************************************
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264 * Function Name: SetAnalogRoutingPumps
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265 ********************************************************************************
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268 * Enables or disables the analog pumps feeding analog routing switches.
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269 * Intended to be called at startup, based on the Vdda system configuration;
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270 * may be called during operation when the user informs us that the Vdda voltage
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271 * crossed the pump threshold.
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274 * enabled - 1 to enable the pumps, 0 to disable the pumps
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279 *******************************************************************************/
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280 void SetAnalogRoutingPumps(uint8 enabled)
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282 uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0);
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289 regValue &= (uint8)~0x00u;
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291 CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);
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294 #define CY_AMUX_UNUSED CYREG_BOOST_SR
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297 /*******************************************************************************
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298 * Function Name: cyfitter_cfg
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299 ********************************************************************************
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301 * This function is called by the start-up code for the selected device. It
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302 * performs all of the necessary device configuration based on the design
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303 * settings. This includes settings from the Design Wide Resources (DWR) such
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304 * as Clocks and Pins as well as any component configuration that is necessary.
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312 *******************************************************************************/
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314 void cyfitter_cfg(void)
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316 /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */
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317 static const uint8 CYCODE BS_IOPINS0_0_VAL[] = {
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318 0x00u, 0xFFu, 0xFFu, 0x00u, 0x17u, 0x00u, 0x00u, 0x00u};
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320 /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */
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321 static const uint8 CYCODE BS_IOPINS0_7_VAL[] = {
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322 0x08u, 0x00u, 0x30u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
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324 /* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */
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325 static const uint8 CYCODE BS_IOPINS1_7_VAL[] = {
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326 0x00u, 0x00u, 0x00u, 0x00u, 0x10u};
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328 /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */
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329 static const uint8 CYCODE BS_IOPINS0_8_VAL[] = {
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330 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u};
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332 /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */
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333 static const uint8 CYCODE BS_IOPINS0_2_VAL[] = {
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334 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u};
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336 /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */
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337 static const uint8 CYCODE BS_IOPINS0_3_VAL[] = {
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338 0x10u, 0x00u, 0x63u, 0x1Cu, 0x1Cu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x01u};
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340 /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */
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341 static const uint8 CYCODE BS_IOPINS0_4_VAL[] = {
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342 0x00u, 0xFCu, 0xFCu, 0x00u, 0xF8u, 0x00u, 0x00u, 0x00u};
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344 /* IOPINS0_5 Address: CYREG_PRT5_DM0 Size (bytes): 8 */
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345 static const uint8 CYCODE BS_IOPINS0_5_VAL[] = {
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346 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u};
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348 /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */
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349 static const uint8 CYCODE BS_IOPINS0_6_VAL[] = {
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350 0xF0u, 0x0Fu, 0x0Fu, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x01u};
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352 /* PHUB_CFGMEM1 Address: CYREG_PHUB_CFGMEM1_CFG0 Size (bytes): 4 */
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353 static const uint8 CYCODE BS_PHUB_CFGMEM1_VAL[] = {
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354 0x00u, 0x01u, 0x00u, 0x00u};
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356 /* PHUB_CFGMEM2 Address: CYREG_PHUB_CFGMEM2_CFG0 Size (bytes): 4 */
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357 static const uint8 CYCODE BS_PHUB_CFGMEM2_VAL[] = {
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358 0x00u, 0x02u, 0x00u, 0x00u};
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360 /* PHUB_CFGMEM3 Address: CYREG_PHUB_CFGMEM3_CFG0 Size (bytes): 4 */
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361 static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = {
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362 0x00u, 0x03u, 0x00u, 0x00u};
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364 #ifdef CYGlobalIntDisable
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365 /* Disable interrupts by default. Let user enable if/when they want. */
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370 /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
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371 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));
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372 /* Setup clocks based on selections from Clock DWR */
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374 /* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */
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375 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0xC1u : 0xC0u));
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376 /* Enable/Disable Debug functionality based on settings from System DWR */
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377 CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u));
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380 static const uint32 CYCODE cy_cfg_addr_table[] = {
\r
381 0x40004501u, /* Base address: 0x40004500 Count: 1 */
\r
382 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
\r
383 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */
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384 0x40006401u, /* Base address: 0x40006400 Count: 1 */
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385 0x40006501u, /* Base address: 0x40006500 Count: 1 */
\r
386 0x4001004Eu, /* Base address: 0x40010000 Count: 78 */
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387 0x40010137u, /* Base address: 0x40010100 Count: 55 */
\r
388 0x4001024Du, /* Base address: 0x40010200 Count: 77 */
\r
389 0x40010353u, /* Base address: 0x40010300 Count: 83 */
\r
390 0x40010439u, /* Base address: 0x40010400 Count: 57 */
\r
391 0x4001054Cu, /* Base address: 0x40010500 Count: 76 */
\r
392 0x40010621u, /* Base address: 0x40010600 Count: 33 */
\r
393 0x40010754u, /* Base address: 0x40010700 Count: 84 */
\r
394 0x40010918u, /* Base address: 0x40010900 Count: 24 */
\r
395 0x40010A42u, /* Base address: 0x40010A00 Count: 66 */
\r
396 0x40010B4Eu, /* Base address: 0x40010B00 Count: 78 */
\r
397 0x40010C43u, /* Base address: 0x40010C00 Count: 67 */
\r
398 0x40010D53u, /* Base address: 0x40010D00 Count: 83 */
\r
399 0x40010E55u, /* Base address: 0x40010E00 Count: 85 */
\r
400 0x40010F35u, /* Base address: 0x40010F00 Count: 53 */
\r
401 0x40011451u, /* Base address: 0x40011400 Count: 81 */
\r
402 0x4001154Bu, /* Base address: 0x40011500 Count: 75 */
\r
403 0x4001164Cu, /* Base address: 0x40011600 Count: 76 */
\r
404 0x40011750u, /* Base address: 0x40011700 Count: 80 */
\r
405 0x40011804u, /* Base address: 0x40011800 Count: 4 */
\r
406 0x40011910u, /* Base address: 0x40011900 Count: 16 */
\r
407 0x40011B07u, /* Base address: 0x40011B00 Count: 7 */
\r
408 0x40014016u, /* Base address: 0x40014000 Count: 22 */
\r
409 0x4001411Cu, /* Base address: 0x40014100 Count: 28 */
\r
410 0x4001420Cu, /* Base address: 0x40014200 Count: 12 */
\r
411 0x4001430Du, /* Base address: 0x40014300 Count: 13 */
\r
412 0x40014411u, /* Base address: 0x40014400 Count: 17 */
\r
413 0x4001451Au, /* Base address: 0x40014500 Count: 26 */
\r
414 0x4001460Eu, /* Base address: 0x40014600 Count: 14 */
\r
415 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */
\r
416 0x4001480Bu, /* Base address: 0x40014800 Count: 11 */
\r
417 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */
\r
418 0x40014C05u, /* Base address: 0x40014C00 Count: 5 */
\r
419 0x40014D03u, /* Base address: 0x40014D00 Count: 3 */
\r
420 0x40015002u, /* Base address: 0x40015000 Count: 2 */
\r
421 0x40015104u, /* Base address: 0x40015100 Count: 4 */
\r
424 static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
\r
1963 CYPACKED typedef struct {
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1964 void CYFAR *address;
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1966 } CYPACKED_ATTR cfg_memset_t;
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1969 CYPACKED typedef struct {
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1971 const void CYCODE *src;
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1973 } CYPACKED_ATTR cfg_memcpy_t;
\r
1975 static const cfg_memset_t CYCODE cfg_memset_list [] = {
\r
1976 /* address, size */
\r
1977 {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
\r
1978 {(void CYFAR *)(CYREG_PRT1_DR), 16u},
\r
1979 {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1664u},
\r
1980 {(void CYFAR *)(CYDEV_UCFG_B0_P3_ROUTE_BASE), 2304u},
\r
1981 {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
\r
1982 {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
\r
1983 {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
\r
1984 {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},
\r
1987 /* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */
\r
1988 static const uint8 CYCODE BS_UDB_1_2_0_CONFIG_VAL[] = {
\r
1989 0x04u, 0x00u, 0x00u, 0x9Fu, 0x04u, 0xC0u, 0x00u, 0x04u, 0x00u, 0x7Fu, 0x00u, 0x80u, 0x00u, 0x90u, 0x00u, 0x40u,
\r
1990 0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0xC0u, 0x00u, 0x08u, 0x00u, 0x00u, 0x01u, 0x60u, 0x00u, 0xC0u, 0x02u, 0x02u,
\r
1991 0x00u, 0xC0u, 0x00u, 0x01u, 0x01u, 0x00u, 0x02u, 0x00u, 0x00u, 0x1Fu, 0x00u, 0x20u, 0x00u, 0x80u, 0x00u, 0x00u,
\r
1992 0x00u, 0x00u, 0x03u, 0x00u, 0x04u, 0xFFu, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x10u,
\r
1993 0x53u, 0x06u, 0x40u, 0x00u, 0x02u, 0xCEu, 0xFDu, 0xBDu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
\r
1994 0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x04u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u,
\r
1995 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
\r
1996 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
\r
1998 /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
\r
1999 static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
\r
2000 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u};
\r
2002 static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
\r
2003 /* dest, src, size */
\r
2004 {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), BS_UDB_1_2_0_CONFIG_VAL, 128u},
\r
2005 {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},
\r
2010 /* Zero out critical memory blocks before beginning configuration */
\r
2011 for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
\r
2013 const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
\r
2014 CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
\r
2017 /* Copy device configuration data into registers */
\r
2018 for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
\r
2020 const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
\r
2021 void * CYDATA destPtr = mc->dest;
\r
2022 const void CYCODE * CYDATA srcPtr = mc->src;
\r
2023 uint16 CYDATA numBytes = mc->size;
\r
2024 CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);
\r
2027 cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
\r
2029 /* Perform normal device configuration. Order is not critical for these items. */
\r
2030 CYMEMZERO((void CYFAR *)(CYREG_PHUB_CFGMEM0_CFG0), 4u);
\r
2031 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM1_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM1_VAL), 4u);
\r
2032 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM2_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM2_VAL), 4u);
\r
2033 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM3_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM3_VAL), 4u);
\r
2035 /* Enable digital routing */
\r
2036 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);
\r
2037 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);
\r
2039 /* Enable UDB array */
\r
2040 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u);
\r
2041 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);
\r
2044 /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
\r
2045 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u);
\r
2046 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u);
\r
2047 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR + 0x0000000Bu), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u);
\r
2048 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);
\r
2049 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u);
\r
2050 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u);
\r
2051 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);
\r
2052 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u);
\r
2053 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);
\r
2055 /* Switch Boost to the precision bandgap reference from its internal reference */
\r
2056 CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));
\r
2058 /* Perform basic analog initialization to defaults */
\r
2059 AnalogSetDefault();
\r
2061 /* Configure alternate active mode */
\r
2062 CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u);
\r
projects / SCSI2SD-V6.git / blob