Implement WRITE BUFFER and WRITE WITH VERIFY commands
[SCSI2SD-V6.git] / software / SCSI2SD / v3 / SCSI2SD.cydsn / SCSI2SD.cycdx
1 <?xml version="1.0" encoding="utf-8"?>\r
2 <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
3   <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
4   <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
5   <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
6   <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
7   <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
8   <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
9   <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
10     <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />\r
11   </block>\r
12   <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
13   <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
14     <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />\r
15   </block>\r
16   <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
17   <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
18     <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
19     <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
20     <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
21     <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
22     <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
23     <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
24     <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">\r
25       <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
26     </register>\r
27     <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">\r
28       <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
29       <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
30         <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
31         <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
32       </field>\r
33       <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
34       <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
35       <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
36       <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
37         <value name="Timer" value="0" desc="CMP and TC are output." />\r
38         <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
39       </field>\r
40       <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
41     </register>\r
42     <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">\r
43       <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
44       <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
45         <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
46         <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
47       </field>\r
48       <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
49       <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
50       <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
51       <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
52     </register>\r
53     <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">\r
54       <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
55         <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
56         <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
57         <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
58         <value name="Irq" value="11" desc="Timer runs until IRQ." />\r
59       </field>\r
60       <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
61       <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
62       <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
63         <value name="Equal" value="0" desc="Compare Equal " />\r
64         <value name="Less than" value="1" desc="Compare Less Than " />\r
65         <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
66         <value name="Greater" value="11" desc="Compare Greater Than ." />\r
67         <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
68       </field>\r
69       <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
70     </register>\r
71     <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
72     <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
73   </block>\r
74   <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
75   <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
76   <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
77   <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
78   <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
79   <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
80   <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
81   <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
82   <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
83   <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
84   <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
85     <register name="SCSI_Filtered_STATUS_REG" address="0x4000646D" bitWidth="8" desc="" />\r
86     <register name="SCSI_Filtered_MASK_REG" address="0x4000648D" bitWidth="8" desc="" />\r
87     <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649D" bitWidth="8" desc="">\r
88       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
89         <value name="ENABLED" value="1" desc="Enable counter" />\r
90         <value name="DISABLED" value="0" desc="Disable counter" />\r
91       </field>\r
92       <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
93         <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
94         <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
95       </field>\r
96       <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
97         <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
98         <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
99       </field>\r
100       <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
101         <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
102         <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
103       </field>\r
104       <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
105         <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
106         <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
107       </field>\r
108       <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
109         <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
110         <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
111       </field>\r
112     </register>\r
113   </block>\r
114   <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
115     <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" />\r
116     <register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" />\r
117     <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="">\r
118       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
119         <value name="ENABLED" value="1" desc="Enable counter" />\r
120         <value name="DISABLED" value="0" desc="Disable counter" />\r
121       </field>\r
122       <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
123         <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
124         <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
125       </field>\r
126       <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
127         <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
128         <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
129       </field>\r
130       <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
131         <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
132         <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
133       </field>\r
134       <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
135         <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
136         <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
137       </field>\r
138       <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
139         <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
140         <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
141       </field>\r
142     </register>\r
143   </block>\r
144   <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
145   <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
146   <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
147     <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
148   </block>\r
149   <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
150   <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
151   <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
152   <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
153   <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
154   <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
155   <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
156   <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
157   <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
158   <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
159   <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
160   <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
161   <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
162     <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
163     <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
164     <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
165     <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
166     <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
167   </block>\r
168   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
169     <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
170     <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
171     <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
172     <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
173     <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
174     <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
175     <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
176     <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
177     <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
178     <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
179     <block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
180     <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
181     <block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
182     <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
183     <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
184     <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
185     <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
186     <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
187     <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
188     <block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
189     <block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
190     <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
191     <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
192     <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
193     <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
194     <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
195     <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
196     <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
197     <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
198     <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">\r
199       <field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />\r
200       <field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />\r
201       <field name="fsusbio_pd_pullup_n" from="2" to="2" access="RW" resetVal="" desc="" />\r
202     </register>\r
203     <register name="USBFS_PM_ACT_CFG" address="0x400043A5" bitWidth="8" desc="Active Power Mode Configuration Register" />\r
204     <register name="USBFS_PM_STBY_CFG" address="0x400043B5" bitWidth="8" desc="Standby Power Mode Configuration Register" />\r
205     <register name="USBFS_PRT.PS" address="0x400051F1" bitWidth="8" desc="Port Pin State Register">\r
206       <field name="PinState_DP" from="6" to="6" access="R" resetVal="" desc="" />\r
207       <field name="PinState_DM" from="7" to="7" access="R" resetVal="" desc="" />\r
208     </register>\r
209     <register name="USBFS_PRT_DM0" address="0x400051F2" bitWidth="8" desc="Port Drive Mode Register">\r
210       <field name="DriveMode_DP" from="6" to="6" access="RW" resetVal="" desc="" />\r
211       <field name="DriveMode_DM" from="7" to="7" access="RW" resetVal="" desc="" />\r
212     </register>\r
213     <register name="USBFS_PRT_DM1" address="0x400051F3" bitWidth="8" desc="Port Drive Mode Register">\r
214       <field name="PullUp_en_DP" from="6" to="6" access="RW" resetVal="" desc="" />\r
215       <field name="PullUp_en_DM" from="7" to="7" access="RW" resetVal="" desc="" />\r
216     </register>\r
217     <register name="USBFS_PRT.INP_DIS" address="0x400051F8" bitWidth="8" desc="Input buffer disable override">\r
218       <field name="seinput_dis_dp" from="6" to="6" access="RW" resetVal="" desc="" />\r
219       <field name="seinput_dis_dm" from="7" to="7" access="RW" resetVal="" desc="" />\r
220     </register>\r
221     <register name="USBFS_EP0_DR0" address="0x40006000" bitWidth="8" desc="bmRequestType" />\r
222     <register name="USBFS_EP0_DR1" address="0x40006001" bitWidth="8" desc="bRequest" />\r
223     <register name="USBFS_EP0_DR2" address="0x40006002" bitWidth="8" desc="wValueLo" />\r
224     <register name="USBFS_EP0_DR3" address="0x40006003" bitWidth="8" desc="wValueHi" />\r
225     <register name="USBFS_EP0_DR4" address="0x40006004" bitWidth="8" desc="wIndexLo" />\r
226     <register name="USBFS_EP0_DR5" address="0x40006005" bitWidth="8" desc="wIndexHi" />\r
227     <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" />\r
228     <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" />\r
229     <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0">\r
230       <field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />\r
231       <field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />\r
232     </register>\r
233     <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1">\r
234       <field name="reg_enable" from="0" to="0" access="RW" resetVal="" desc="" />\r
235       <field name="enable_lock" from="1" to="1" access="RW" resetVal="" desc="" />\r
236       <field name="bus_activity" from="2" to="2" access="RW" resetVal="" desc="" />\r
237       <field name="trim_offset_msb" from="3" to="3" access="RW" resetVal="" desc="" />\r
238     </register>\r
239     <register name="USBFS_SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="The Endpoint1 Control Register" />\r
240     <register name="USBFS_USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control Register 0">\r
241       <field name="rd" from="0" to="0" access="R" resetVal="" desc="" />\r
242       <field name="td" from="5" to="5" access="RW" resetVal="" desc="" />\r
243       <field name="tse0" from="6" to="6" access="RW" resetVal="" desc="" />\r
244       <field name="ten" from="7" to="7" access="RW" resetVal="" desc="" />\r
245     </register>\r
246     <register name="USBFS_USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control Register 1">\r
247       <field name="dmo" from="0" to="0" access="R" resetVal="" desc="" />\r
248       <field name="dpo" from="1" to="1" access="R" resetVal="" desc="" />\r
249       <field name="usbpuen" from="2" to="2" access="RW" resetVal="" desc="" />\r
250       <field name="iomode" from="5" to="5" access="RW" resetVal="" desc="" />\r
251     </register>\r
252     <register name="USBFS_SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="The Endpoint2 Control Register" />\r
253     <register name="USBFS_SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="The Endpoint3 Control Register" />\r
254     <register name="USBFS_SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="The Endpoint4 Control Register" />\r
255     <register name="USBFS_SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="The Endpoint5 Control Register" />\r
256     <register name="USBFS_SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="The Endpoint6 Control Register" />\r
257     <register name="USBFS_SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="The Endpoint7 Control Register" />\r
258     <register name="USBFS_SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="The Endpoint8 Control Register" />\r
259     <register name="USBFS_BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" />\r
260     <register name="USBFS_EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" />\r
261     <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />\r
262     <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
263   </block>\r
264   <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
265   <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
266   <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
267   <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
268   <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
269   <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
270   <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
271 </blockRegMap>