1 // Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
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3 // This file is part of SCSI2SD.
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5 // SCSI2SD is free software: you can redistribute it and/or modify
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6 // it under the terms of the GNU General Public License as published by
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7 // the Free Software Foundation, either version 3 of the License, or
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8 // (at your option) any later version.
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10 // SCSI2SD is distributed in the hope that it will be useful,
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11 // but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 // GNU General Public License for more details.
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15 // You should have received a copy of the GNU General Public License
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16 // along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
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18 #include "stm32f2xx.h"
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19 #include "stm32f2xx_hal.h"
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20 #include "stm32f2xx_hal_dma.h"
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23 #include "scsiPhy.h"
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29 // Private DMA variables.
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30 static int dmaInProgress = 0;
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32 static DMA_HandleTypeDef memToFSMC;
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33 static DMA_HandleTypeDef fsmcToMem;
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36 volatile uint8_t scsiRxDMAComplete;
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37 volatile uint8_t scsiTxDMAComplete;
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40 CY_ISR_PROTO(scsiRxCompleteISR);
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41 CY_ISR(scsiRxCompleteISR)
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43 traceIrq(trace_scsiRxCompleteISR);
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44 scsiRxDMAComplete = 1;
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47 CY_ISR_PROTO(scsiTxCompleteISR);
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48 CY_ISR(scsiTxCompleteISR)
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50 traceIrq(trace_scsiTxCompleteISR);
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51 scsiTxDMAComplete = 1;
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55 uint8_t scsiPhyFifoSel = 0; // global
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57 // scsi IRQ handler is initialised by the STM32 HAL. Connected to
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59 // Note: naming is important to ensure this function is listed in the
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61 void EXTI4_IRQHandler()
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63 traceIrq(trace_scsiResetISR);
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65 // Make sure that interrupt flag is set
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66 if (__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_4) != RESET) {
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68 // Clear interrupt flag
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69 __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_4);
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71 scsiDev.resetFlag = scsiDev.resetFlag || scsiStatusRST();
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72 // TODO grab SEL status as well
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82 (SCSI_ReadPin(SCSI_In_DBx_DB7) << 7) |
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83 (SCSI_ReadPin(SCSI_In_DBx_DB6) << 6) |
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84 (SCSI_ReadPin(SCSI_In_DBx_DB5) << 5) |
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85 (SCSI_ReadPin(SCSI_In_DBx_DB4) << 4) |
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86 (SCSI_ReadPin(SCSI_In_DBx_DB3) << 3) |
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87 (SCSI_ReadPin(SCSI_In_DBx_DB2) << 2) |
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88 (SCSI_ReadPin(SCSI_In_DBx_DB1) << 1) |
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89 SCSI_ReadPin(SCSI_In_DBx_DB0);
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94 startScsiRx(uint32_t count)
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96 *SCSI_DATA_CNT_HI = count >> 8;
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97 *SCSI_DATA_CNT_LO = count & 0xff;
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98 *SCSI_DATA_CNT_SET = 1;
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106 trace(trace_spinPhyRxFifo);
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107 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag)) {}
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109 uint8_t val = scsiPhyRx();
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110 // TODO scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
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117 scsiReadPIO(uint8_t* data, uint32_t count)
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119 for (int i = 0; i < count; ++i)
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121 data[i] = scsiPhyRx();
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123 // TODO scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
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127 scsiReadDMA(uint8_t* data, uint32_t count)
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129 // Prepare DMA transfer
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131 trace(trace_doRxSingleDMA);
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133 scsiTxDMAComplete = 1; // TODO not used much
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134 scsiRxDMAComplete = 0; // TODO not used much
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136 HAL_DMA_Start(&fsmcToMem, (uint32_t) SCSI_FIFO_DATA, (uint32_t) data, count); // TODO MM count/4 for tx
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142 int complete = __HAL_DMA_GET_COUNTER(&fsmcToMem) == 0;
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143 complete = complete && (HAL_DMA_PollForTransfer(&fsmcToMem, HAL_DMA_FULL_TRANSFER, 0xffffffff) == HAL_OK);
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146 scsiTxDMAComplete = 1; // TODO MM FIX IRQ
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147 scsiRxDMAComplete = 1;
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151 // TODO MM scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
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163 scsiRead(uint8_t* data, uint32_t count)
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166 while (i < count && likely(!scsiDev.resetFlag))
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168 uint32_t chunk = ((count - i) > SCSI_FIFO_DEPTH)
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169 ? SCSI_FIFO_DEPTH : (count - i);
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173 // DMA is doing 32bit transfers.
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174 chunk = chunk & 0xFFFFFFF8;
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177 startScsiRx(chunk);
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178 // Wait for the next scsi interrupt (or the 1ms systick)
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181 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag)) {}
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186 scsiReadPIO(data + i, chunk);
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190 scsiReadDMA(data + i, chunk);
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192 // Wait for the next DMA interrupt (or the 1ms systick)
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193 // It's beneficial to halt the processor to
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194 // give the DMA controller more memory bandwidth to work with.
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198 trace(trace_spinReadDMAPoll);
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200 while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag))
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203 // TODO NEED SCSI DMA IRQs
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214 scsiWriteByte(uint8_t value)
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216 trace(trace_spinPhyTxFifo);
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220 trace(trace_spinTxComplete);
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221 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag)) {}
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225 scsiWritePIO(const uint8_t* data, uint32_t count)
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227 for (int i = 0; i < count; ++i)
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229 scsiPhyTx(data[i]);
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234 scsiWriteDMA(const uint8_t* data, uint32_t count)
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236 // Prepare DMA transfer
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238 trace(trace_doTxSingleDMA);
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240 scsiTxDMAComplete = 0;
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241 scsiRxDMAComplete = 1;
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246 (uint32_t) SCSI_FIFO_DATA,
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253 int complete = __HAL_DMA_GET_COUNTER(&memToFSMC) == 0;
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254 complete = complete && (HAL_DMA_PollForTransfer(&memToFSMC, HAL_DMA_FULL_TRANSFER, 0xffffffff) == HAL_OK);
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257 scsiTxDMAComplete = 1; // TODO MM FIX IRQ
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258 scsiRxDMAComplete = 1;
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270 scsiWrite(const uint8_t* data, uint32_t count)
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273 while (i < count && likely(!scsiDev.resetFlag))
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275 uint32_t chunk = ((count - i) > SCSI_FIFO_DEPTH)
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276 ? SCSI_FIFO_DEPTH : (count - i);
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280 scsiWritePIO(data + i, chunk);
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284 // DMA is doing 32bit transfers.
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285 chunk = chunk & 0xFFFFFFF8;
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286 scsiWriteDMA(data + i, chunk);
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288 // Wait for the next DMA interrupt (or the 1ms systick)
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289 // It's beneficial to halt the processor to
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290 // give the DMA controller more memory bandwidth to work with.
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294 trace(trace_spinReadDMAPoll);
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296 while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag))
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299 // TODO NEED SCSI DMA IRQs
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305 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag)) {}
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308 // TODO NEED SCSI IRQs
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314 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag)) {}
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317 static inline void busSettleDelay(void)
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319 // Data Release time (switching IO) = 400ns
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320 // + Bus Settle time (switching phase) = 400ns.
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321 s2s_delay_us(1); // Close enough.
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324 void scsiEnterBusFree()
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326 *SCSI_CTRL_PHASE = 0;
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327 *SCSI_CTRL_BSY = 0x00;
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330 void scsiEnterPhase(int phase)
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332 // ANSI INCITS 362-2002 SPI-3 10.7.1:
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333 // Phase changes are not allowed while REQ or ACK is asserted.
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335 while (likely(!scsiDev.resetFlag) &&
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336 (SCSI_ReadPin(SCSI_In_REQ) || SCSI_ReadFilt(SCSI_Filt_ACK))
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340 int newPhase = phase > 0 ? phase : 0;
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341 if (newPhase != *SCSI_CTRL_PHASE)
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343 *SCSI_CTRL_PHASE = newPhase;
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346 if (scsiDev.compatMode < COMPAT_SCSI2)
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353 void scsiPhyReset()
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355 trace(trace_scsiPhyReset);
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358 trace(trace_spinDMAReset);
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359 HAL_DMA_Abort(&memToFSMC);
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360 HAL_DMA_Abort(&fsmcToMem);
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366 // Set the Clear bits for both SCSI device FIFOs
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367 scsiTarget_AUX_CTL = scsiTarget_AUX_CTL | 0x03;
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369 // Trigger RST outselves. It is connected to the datapath and will
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370 // ensure it returns to the idle state. The datapath runs at the BUS clk
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371 // speed (ie. same as the CPU), so we can be sure it is active for a sufficient
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373 SCSI_RST_ISR_Disable();
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374 SCSI_SetPin(SCSI_Out_RST);
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376 SCSI_CTL_PHASE_Write(0);
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377 SCSI_ClearPin(SCSI_Out_ATN);
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378 SCSI_ClearPin(SCSI_Out_BSY);
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379 SCSI_ClearPin(SCSI_Out_ACK);
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380 SCSI_ClearPin(SCSI_Out_RST);
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381 SCSI_ClearPin(SCSI_Out_SEL);
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382 SCSI_ClearPin(SCSI_Out_REQ);
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384 // Allow the FIFOs to fill up again.
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385 SCSI_ClearPin(SCSI_Out_RST);
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386 SCSI_RST_ISR_Enable();
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387 scsiTarget_AUX_CTL = scsiTarget_AUX_CTL & ~(0x03);
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389 SCSI_Parity_Error_Read(); // clear sticky bits
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392 *SCSI_CTRL_PHASE = 0x00;
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393 *SCSI_CTRL_BSY = 0x00;
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394 s2s_fpgaReset(); // Clears fifos etc.
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396 scsiPhyFifoSel = 0;
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397 *SCSI_FIFO_SEL = 0;
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399 // DMA Benchmark code
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400 // Currently 10MB/s. Assume 20MB/s is achievable with 16 bits.
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401 #ifdef DMA_BENCHMARK
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406 for (int i = 0; i < (100LL * 1024 * 1024 / SCSI_FIFO_DEPTH); ++i)
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410 (uint32_t) &scsiDev.data[0],
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411 (uint32_t) SCSI_FIFO_DATA,
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412 SCSI_FIFO_DEPTH / 4);
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414 HAL_DMA_PollForTransfer(
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416 HAL_DMA_FULL_TRANSFER,
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423 for(int i = 0; i < 10; ++i) s2s_delay_ms(1000);
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429 static void scsiPhyInitDMA()
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431 // One-time init only.
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432 static uint8_t init = 0;
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437 // Memory to memory transfers can only be done using DMA2
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438 __DMA2_CLK_ENABLE();
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440 // Transmit SCSI data. The source data is treated as the
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441 // peripheral (even though this is memory-to-memory)
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442 memToFSMC.Instance = DMA2_Stream0;
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443 memToFSMC.Init.Channel = DMA_CHANNEL_0;
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444 memToFSMC.Init.Direction = DMA_MEMORY_TO_MEMORY;
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445 memToFSMC.Init.PeriphInc = DMA_PINC_ENABLE;
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446 memToFSMC.Init.MemInc = DMA_MINC_DISABLE;
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447 memToFSMC.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
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448 memToFSMC.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
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449 memToFSMC.Init.Mode = DMA_NORMAL;
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450 memToFSMC.Init.Priority = DMA_PRIORITY_LOW;
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451 // FIFO mode is needed to allow conversion from 32bit words to the
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452 // 8bit FSMC interface.
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453 memToFSMC.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
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455 // We only use 1 word (4 bytes) in the fifo at a time. Normally it's
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456 // better to let the DMA fifo fill up then do burst transfers, but
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457 // bursting out the FSMC interface will be very slow and may starve
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458 // other (faster) transfers. We don't want to risk the SDIO transfers
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459 // from overrun/underrun conditions.
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460 memToFSMC.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL;
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461 memToFSMC.Init.MemBurst = DMA_MBURST_SINGLE;
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462 memToFSMC.Init.PeriphBurst = DMA_PBURST_SINGLE;
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463 HAL_DMA_Init(&memToFSMC);
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465 // Receive SCSI data. The source data (fsmc) is treated as the
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466 // peripheral (even though this is memory-to-memory)
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467 fsmcToMem.Instance = DMA2_Stream1;
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468 fsmcToMem.Init.Channel = DMA_CHANNEL_0;
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469 fsmcToMem.Init.Direction = DMA_MEMORY_TO_MEMORY;
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470 fsmcToMem.Init.PeriphInc = DMA_PINC_DISABLE;
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471 fsmcToMem.Init.MemInc = DMA_MINC_ENABLE;
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472 fsmcToMem.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
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473 fsmcToMem.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
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474 fsmcToMem.Init.Mode = DMA_NORMAL;
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475 fsmcToMem.Init.Priority = DMA_PRIORITY_LOW;
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476 fsmcToMem.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
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477 fsmcToMem.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL;
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478 fsmcToMem.Init.MemBurst = DMA_MBURST_SINGLE;
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479 fsmcToMem.Init.PeriphBurst = DMA_PBURST_SINGLE;
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480 HAL_DMA_Init(&fsmcToMem);
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482 // TODO configure IRQs
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491 *SCSI_CTRL_IDMASK = 0x00; // Reset in scsiPhyConfig
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492 *SCSI_CTRL_PHASE = 0x00;
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493 *SCSI_CTRL_BSY = 0x00;
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494 scsiPhyFifoSel = 0;
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495 *SCSI_FIFO_SEL = 0;
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499 void scsiPhyConfig()
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501 if (scsiDev.boardCfg.flags6 & S2S_CFG_ENABLE_TERMINATOR)
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503 HAL_GPIO_WritePin(nTERM_EN_GPIO_Port, nTERM_EN_Pin, GPIO_PIN_RESET);
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507 HAL_GPIO_WritePin(nTERM_EN_GPIO_Port, nTERM_EN_Pin, GPIO_PIN_SET);
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511 uint8_t idMask = 0;
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512 for (int i = 0; i < 8; ++i)
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514 const S2S_TargetCfg* cfg = s2s_getConfigById(i);
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515 if (cfg && (cfg->scsiId & S2S_CFG_TARGET_ENABLED))
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517 idMask |= (1 << i);
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520 *SCSI_CTRL_IDMASK = idMask;
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525 // 2 = Parity error
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529 // 32 = other error
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536 // TEST DBx and DBp
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538 SCSI_Out_Ctl_Write(1); // Write bits manually.
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539 SCSI_CTL_PHASE_Write(__scsiphase_io); // Needed for parity generation
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540 for (i = 0; i < 256; ++i)
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542 SCSI_Out_Bits_Write(i);
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544 if (scsiReadDBxPins() != (i & 0xff))
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548 if (Lookup_OddParity[i & 0xff] != SCSI_ReadPin(SCSI_In_DBP))
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553 SCSI_Out_Ctl_Write(0); // Write bits normally.
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555 // TEST MSG, CD, IO
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556 for (i = 0; i < 8; ++i)
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558 SCSI_CTL_PHASE_Write(i);
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561 if (SCSI_ReadPin(SCSI_In_MSG) != !!(i & __scsiphase_msg))
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565 if (SCSI_ReadPin(SCSI_In_CD) != !!(i & __scsiphase_cd))
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569 if (SCSI_ReadPin(SCSI_In_IO) != !!(i & __scsiphase_io))
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574 SCSI_CTL_PHASE_Write(0);
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576 uint32_t signalsOut[] = { SCSI_Out_ATN, SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL };
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577 uint32_t signalsIn[] = { SCSI_Filt_ATN, SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL };
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579 for (i = 0; i < 4; ++i)
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581 SCSI_SetPin(signalsOut[i]);
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585 for (j = 0; j < 4; ++j)
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589 if (! SCSI_ReadFilt(signalsIn[j]))
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596 if (SCSI_ReadFilt(signalsIn[j]))
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602 SCSI_ClearPin(signalsOut[i]);
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