1 // Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
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3 // This file is part of SCSI2SD.
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5 // SCSI2SD is free software: you can redistribute it and/or modify
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6 // it under the terms of the GNU General Public License as published by
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7 // the Free Software Foundation, either version 3 of the License, or
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8 // (at your option) any later version.
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10 // SCSI2SD is distributed in the hope that it will be useful,
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11 // but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 // GNU General Public License for more details.
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15 // You should have received a copy of the GNU General Public License
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16 // along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
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18 #include "stm32f2xx.h"
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19 #include "stm32f2xx_hal.h"
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20 #include "stm32f2xx_hal_dma.h"
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23 #include "scsiPhy.h"
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31 // Private DMA variables.
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32 static int dmaInProgress = 0;
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34 static DMA_HandleTypeDef memToFSMC;
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35 static DMA_HandleTypeDef fsmcToMem;
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38 volatile uint8_t scsiRxDMAComplete;
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39 volatile uint8_t scsiTxDMAComplete;
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42 CY_ISR_PROTO(scsiRxCompleteISR);
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43 CY_ISR(scsiRxCompleteISR)
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45 traceIrq(trace_scsiRxCompleteISR);
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46 scsiRxDMAComplete = 1;
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49 CY_ISR_PROTO(scsiTxCompleteISR);
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50 CY_ISR(scsiTxCompleteISR)
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52 traceIrq(trace_scsiTxCompleteISR);
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53 scsiTxDMAComplete = 1;
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57 uint8_t scsiPhyFifoSel = 0; // global
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59 // scsi IRQ handler is initialised by the STM32 HAL. Connected to
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61 // Note: naming is important to ensure this function is listed in the
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63 void EXTI4_IRQHandler()
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65 traceIrq(trace_scsiResetISR);
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67 // Make sure that interrupt flag is set
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68 if (__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_4) != RESET) {
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70 // Clear interrupt flag
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71 __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_4);
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73 scsiDev.resetFlag = scsiDev.resetFlag || scsiStatusRST();
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74 // TODO grab SEL status as well
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79 static void assertFail()
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91 startScsiRx(uint32_t count)
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93 *SCSI_DATA_CNT_HI = count >> 8;
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94 *SCSI_DATA_CNT_LO = count & 0xff;
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95 *SCSI_DATA_CNT_SET = 1;
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102 if (!scsiPhyFifoAltEmpty()) {
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103 // Force a lock-up.
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109 trace(trace_spinPhyRxFifo);
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110 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag)) {}
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112 uint8_t val = scsiPhyRx();
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113 // TODO scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
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116 if (!scsiPhyFifoEmpty()) {
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118 uint8_t k __attribute((unused));
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119 while (!scsiPhyFifoEmpty()) { k = scsiPhyRx(); ++j; }
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121 // Force a lock-up.
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130 scsiReadPIO(uint8_t* data, uint32_t count)
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132 for (int i = 0; i < count; ++i)
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134 data[i] = scsiPhyRx();
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136 // TODO scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
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140 scsiReadDMA(uint8_t* data, uint32_t count)
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142 // Prepare DMA transfer
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144 trace(trace_doRxSingleDMA);
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146 scsiTxDMAComplete = 1; // TODO not used much
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147 scsiRxDMAComplete = 0; // TODO not used much
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149 HAL_DMA_Start(&fsmcToMem, (uint32_t) SCSI_FIFO_DATA, (uint32_t) data, count);
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155 int complete = __HAL_DMA_GET_COUNTER(&fsmcToMem) == 0;
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156 complete = complete && (HAL_DMA_PollForTransfer(&fsmcToMem, HAL_DMA_FULL_TRANSFER, 0xffffffff) == HAL_OK);
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159 scsiTxDMAComplete = 1; // TODO MM FIX IRQ
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160 scsiRxDMAComplete = 1;
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164 // TODO MM scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
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176 scsiRead(uint8_t* data, uint32_t count)
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179 while (i < count && likely(!scsiDev.resetFlag))
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181 uint32_t chunk = ((count - i) > SCSI_FIFO_DEPTH)
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182 ? SCSI_FIFO_DEPTH : (count - i);
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186 // DMA is doing 32bit transfers.
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187 chunk = chunk & 0xFFFFFFF8;
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191 if (!scsiPhyFifoAltEmpty()) {
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192 // Force a lock-up.
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197 startScsiRx(chunk);
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198 // Wait for the next scsi interrupt (or the 1ms systick)
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201 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag)) {}
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206 scsiReadPIO(data + i, chunk);
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210 scsiReadDMA(data + i, chunk);
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212 // Wait for the next DMA interrupt (or the 1ms systick)
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213 // It's beneficial to halt the processor to
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214 // give the DMA controller more memory bandwidth to work with.
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218 trace(trace_spinReadDMAPoll);
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220 while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag))
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223 // TODO NEED SCSI DMA IRQs
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230 if (!scsiPhyFifoEmpty()) {
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232 while (!scsiPhyFifoEmpty()) { scsiPhyRx(); ++j; }
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233 // Force a lock-up.
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242 scsiWriteByte(uint8_t value)
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245 if (!scsiPhyFifoEmpty()) {
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246 // Force a lock-up.
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250 trace(trace_spinPhyTxFifo);
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254 trace(trace_spinTxComplete);
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255 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag)) {}
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258 if (!scsiPhyFifoAltEmpty()) {
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259 // Force a lock-up.
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266 scsiWritePIO(const uint8_t* data, uint32_t count)
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268 for (int i = 0; i < count; ++i)
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270 scsiPhyTx(data[i]);
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275 scsiWriteDMA(const uint8_t* data, uint32_t count)
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277 // Prepare DMA transfer
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279 trace(trace_doTxSingleDMA);
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281 scsiTxDMAComplete = 0;
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282 scsiRxDMAComplete = 1;
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287 (uint32_t) SCSI_FIFO_DATA,
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294 int complete = __HAL_DMA_GET_COUNTER(&memToFSMC) == 0;
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295 complete = complete && (HAL_DMA_PollForTransfer(&memToFSMC, HAL_DMA_FULL_TRANSFER, 0xffffffff) == HAL_OK);
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298 scsiTxDMAComplete = 1; // TODO MM FIX IRQ
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299 scsiRxDMAComplete = 1;
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311 scsiWrite(const uint8_t* data, uint32_t count)
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314 while (i < count && likely(!scsiDev.resetFlag))
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316 uint32_t chunk = ((count - i) > SCSI_FIFO_DEPTH)
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317 ? SCSI_FIFO_DEPTH : (count - i);
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320 if (!scsiPhyFifoEmpty()) {
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321 // Force a lock-up.
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328 scsiWritePIO(data + i, chunk);
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332 // DMA is doing 32bit transfers.
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333 chunk = chunk & 0xFFFFFFF8;
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334 scsiWriteDMA(data + i, chunk);
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336 // Wait for the next DMA interrupt (or the 1ms systick)
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337 // It's beneficial to halt the processor to
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338 // give the DMA controller more memory bandwidth to work with.
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342 trace(trace_spinReadDMAPoll);
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344 while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag))
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347 // TODO NEED SCSI DMA IRQs
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353 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag)) {}
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356 if (!scsiPhyFifoAltEmpty()) {
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357 // Force a lock-up.
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364 // TODO NEED SCSI IRQs
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370 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag)) {}
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373 if (!scsiPhyFifoAltEmpty()) {
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374 // Force a lock-up.
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380 static inline void busSettleDelay(void)
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382 // Data Release time (switching IO) = 400ns
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383 // + Bus Settle time (switching phase) = 400ns.
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384 s2s_delay_us(1); // Close enough.
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387 void scsiEnterBusFree()
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389 *SCSI_CTRL_BSY = 0x00;
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390 // We now have a Bus Clear Delay of 800ns to release remaining signals.
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391 *SCSI_CTRL_PHASE = 0;
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394 void scsiEnterPhase(int phase)
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396 // ANSI INCITS 362-2002 SPI-3 10.7.1:
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397 // Phase changes are not allowed while REQ or ACK is asserted.
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398 while (likely(!scsiDev.resetFlag) && scsiStatusACK()) {}
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400 int newPhase = phase > 0 ? phase : 0;
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401 int oldPhase = *SCSI_CTRL_PHASE;
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403 if (!scsiPhyFifoEmpty() || !scsiPhyFifoAltEmpty()) {
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404 // Force a lock-up.
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407 if (newPhase != oldPhase)
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409 *SCSI_CTRL_PHASE = newPhase;
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412 if (scsiDev.compatMode < COMPAT_SCSI2)
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420 void scsiPhyReset()
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422 trace(trace_scsiPhyReset);
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425 trace(trace_spinDMAReset);
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426 HAL_DMA_Abort(&memToFSMC);
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427 HAL_DMA_Abort(&fsmcToMem);
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433 // Set the Clear bits for both SCSI device FIFOs
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434 scsiTarget_AUX_CTL = scsiTarget_AUX_CTL | 0x03;
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436 // Trigger RST outselves. It is connected to the datapath and will
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437 // ensure it returns to the idle state. The datapath runs at the BUS clk
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438 // speed (ie. same as the CPU), so we can be sure it is active for a sufficient
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440 SCSI_RST_ISR_Disable();
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441 SCSI_SetPin(SCSI_Out_RST);
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443 SCSI_CTL_PHASE_Write(0);
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444 SCSI_ClearPin(SCSI_Out_ATN);
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445 SCSI_ClearPin(SCSI_Out_BSY);
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446 SCSI_ClearPin(SCSI_Out_ACK);
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447 SCSI_ClearPin(SCSI_Out_RST);
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448 SCSI_ClearPin(SCSI_Out_SEL);
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449 SCSI_ClearPin(SCSI_Out_REQ);
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451 // Allow the FIFOs to fill up again.
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452 SCSI_ClearPin(SCSI_Out_RST);
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453 SCSI_RST_ISR_Enable();
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454 scsiTarget_AUX_CTL = scsiTarget_AUX_CTL & ~(0x03);
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456 SCSI_Parity_Error_Read(); // clear sticky bits
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459 *SCSI_CTRL_PHASE = 0x00;
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460 *SCSI_CTRL_BSY = 0x00;
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461 s2s_fpgaReset(); // Clears fifos etc.
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463 scsiPhyFifoSel = 0;
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464 *SCSI_FIFO_SEL = 0;
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466 // DMA Benchmark code
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467 // Currently 10MB/s. Assume 20MB/s is achievable with 16 bits.
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468 #ifdef DMA_BENCHMARK
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473 for (int i = 0; i < (100LL * 1024 * 1024 / SCSI_FIFO_DEPTH); ++i)
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477 (uint32_t) &scsiDev.data[0],
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478 (uint32_t) SCSI_FIFO_DATA,
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479 SCSI_FIFO_DEPTH / 4);
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481 HAL_DMA_PollForTransfer(
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483 HAL_DMA_FULL_TRANSFER,
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490 for(int i = 0; i < 10; ++i) s2s_delay_ms(1000);
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494 // FPGA comms test code
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499 for (int j = 0; j < SCSI_FIFO_DEPTH; ++j)
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501 scsiDev.data[j] = j;
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504 *SCSI_CTRL_PHASE = DATA_IN;
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507 (uint32_t) &scsiDev.data[0],
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508 (uint32_t) SCSI_FIFO_DATA,
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509 SCSI_FIFO_DEPTH / 4);
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511 HAL_DMA_PollForTransfer(
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513 HAL_DMA_FULL_TRANSFER,
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516 memset(&scsiDev.data[0], 0, SCSI_FIFO_DEPTH);
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518 *SCSI_CTRL_PHASE = DATA_OUT;
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521 (uint32_t) SCSI_FIFO_DATA,
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522 (uint32_t) &scsiDev.data[0],
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525 HAL_DMA_PollForTransfer(
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527 HAL_DMA_FULL_TRANSFER,
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530 for (int j = 0; j < SCSI_FIFO_DEPTH; ++j)
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532 if (scsiDev.data[j] != (uint8_t) j)
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545 static void scsiPhyInitDMA()
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547 // One-time init only.
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548 static uint8_t init = 0;
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553 // Memory to memory transfers can only be done using DMA2
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554 __DMA2_CLK_ENABLE();
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556 // Transmit SCSI data. The source data is treated as the
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557 // peripheral (even though this is memory-to-memory)
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558 memToFSMC.Instance = DMA2_Stream0;
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559 memToFSMC.Init.Channel = DMA_CHANNEL_0;
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560 memToFSMC.Init.Direction = DMA_MEMORY_TO_MEMORY;
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561 memToFSMC.Init.PeriphInc = DMA_PINC_ENABLE;
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562 memToFSMC.Init.MemInc = DMA_MINC_DISABLE;
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563 memToFSMC.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
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564 memToFSMC.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
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565 memToFSMC.Init.Mode = DMA_NORMAL;
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566 memToFSMC.Init.Priority = DMA_PRIORITY_LOW;
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567 // FIFO mode is needed to allow conversion from 32bit words to the
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568 // 8bit FSMC interface.
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569 memToFSMC.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
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571 // We only use 1 word (4 bytes) in the fifo at a time. Normally it's
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572 // better to let the DMA fifo fill up then do burst transfers, but
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573 // bursting out the FSMC interface will be very slow and may starve
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574 // other (faster) transfers. We don't want to risk the SDIO transfers
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575 // from overrun/underrun conditions.
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576 memToFSMC.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL;
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577 memToFSMC.Init.MemBurst = DMA_MBURST_SINGLE;
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578 memToFSMC.Init.PeriphBurst = DMA_PBURST_SINGLE;
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579 HAL_DMA_Init(&memToFSMC);
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581 // Receive SCSI data. The source data (fsmc) is treated as the
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582 // peripheral (even though this is memory-to-memory)
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583 fsmcToMem.Instance = DMA2_Stream1;
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584 fsmcToMem.Init.Channel = DMA_CHANNEL_0;
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585 fsmcToMem.Init.Direction = DMA_MEMORY_TO_MEMORY;
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586 fsmcToMem.Init.PeriphInc = DMA_PINC_DISABLE;
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587 fsmcToMem.Init.MemInc = DMA_MINC_ENABLE;
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588 fsmcToMem.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
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589 fsmcToMem.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
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590 fsmcToMem.Init.Mode = DMA_NORMAL;
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591 fsmcToMem.Init.Priority = DMA_PRIORITY_LOW;
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592 fsmcToMem.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
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593 fsmcToMem.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL;
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594 fsmcToMem.Init.MemBurst = DMA_MBURST_SINGLE;
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595 fsmcToMem.Init.PeriphBurst = DMA_PBURST_SINGLE;
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596 HAL_DMA_Init(&fsmcToMem);
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598 // TODO configure IRQs
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607 *SCSI_CTRL_IDMASK = 0x00; // Reset in scsiPhyConfig
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608 *SCSI_CTRL_PHASE = 0x00;
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609 *SCSI_CTRL_BSY = 0x00;
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610 scsiPhyFifoSel = 0;
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611 *SCSI_FIFO_SEL = 0;
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615 void scsiPhyConfig()
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617 if (scsiDev.boardCfg.flags6 & S2S_CFG_ENABLE_TERMINATOR)
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619 HAL_GPIO_WritePin(nTERM_EN_GPIO_Port, nTERM_EN_Pin, GPIO_PIN_RESET);
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623 HAL_GPIO_WritePin(nTERM_EN_GPIO_Port, nTERM_EN_Pin, GPIO_PIN_SET);
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627 uint8_t idMask = 0;
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628 for (int i = 0; i < 8; ++i)
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630 const S2S_TargetCfg* cfg = s2s_getConfigById(i);
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631 if (cfg && (cfg->scsiId & S2S_CFG_TARGET_ENABLED))
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633 idMask |= (1 << i);
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636 *SCSI_CTRL_IDMASK = idMask;
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641 // 2 = Parity error
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645 // 32 = other error
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652 // TEST DBx and DBp
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654 SCSI_Out_Ctl_Write(1); // Write bits manually.
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655 SCSI_CTL_PHASE_Write(__scsiphase_io); // Needed for parity generation
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656 for (i = 0; i < 256; ++i)
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658 SCSI_Out_Bits_Write(i);
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660 if (scsiReadDBxPins() != (i & 0xff))
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664 if (Lookup_OddParity[i & 0xff] != SCSI_ReadPin(SCSI_In_DBP))
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669 SCSI_Out_Ctl_Write(0); // Write bits normally.
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671 // TEST MSG, CD, IO
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672 for (i = 0; i < 8; ++i)
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674 SCSI_CTL_PHASE_Write(i);
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677 if (SCSI_ReadPin(SCSI_In_MSG) != !!(i & __scsiphase_msg))
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681 if (SCSI_ReadPin(SCSI_In_CD) != !!(i & __scsiphase_cd))
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685 if (SCSI_ReadPin(SCSI_In_IO) != !!(i & __scsiphase_io))
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690 SCSI_CTL_PHASE_Write(0);
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692 uint32_t signalsOut[] = { SCSI_Out_ATN, SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL };
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693 uint32_t signalsIn[] = { SCSI_Filt_ATN, SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL };
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695 for (i = 0; i < 4; ++i)
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697 SCSI_SetPin(signalsOut[i]);
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701 for (j = 0; j < 4; ++j)
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705 if (! SCSI_ReadFilt(signalsIn[j]))
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712 if (SCSI_ReadFilt(signalsIn[j]))
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718 SCSI_ClearPin(signalsOut[i]);
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