Implement WRITE BUFFER and WRITE WITH VERIFY commands
[SCSI2SD-V6.git] / software / SCSI2SD / v3 / SCSI2SD.cydsn / Generated_Source / PSoC5 / cyfitter.h
index a110bfa..0db6988 100644 (file)
 #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
 \r
 /* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
 #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
 #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
 #define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
 #define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
 #define SDCard_BSPIM_TxStsReg__0__POS 0\r
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
 #define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
 #define SDCard_BSPIM_TxStsReg__2__POS 2\r
 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_TxStsReg__4__POS 4\r
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST\r
 \r
 /* SD_SCK */\r
 #define SD_SCK__0__MASK 0x04u\r
 /* SCSI_Out_Ctl */\r
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
 #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
 \r
 /* SCSI_Out_DBx */\r
 #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
 #define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
 #define SD_RX_DMA__DRQ_NUMBER 2u\r
 #define SD_RX_DMA__NUMBEROF_TDS 0u\r
-#define SD_RX_DMA__PRIORITY 2u\r
+#define SD_RX_DMA__PRIORITY 0u\r
 #define SD_RX_DMA__TERMIN_EN 0u\r
 #define SD_RX_DMA__TERMIN_SEL 0u\r
 #define SD_RX_DMA__TERMOUT0_EN 1u\r
 #define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
 #define SD_TX_DMA__DRQ_NUMBER 3u\r
 #define SD_TX_DMA__NUMBEROF_TDS 0u\r
-#define SD_TX_DMA__PRIORITY 2u\r
+#define SD_TX_DMA__PRIORITY 1u\r
 #define SD_TX_DMA__TERMIN_EN 0u\r
 #define SD_TX_DMA__TERMIN_SEL 0u\r
 #define SD_TX_DMA__TERMOUT0_EN 1u\r
 #define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW\r
 \r
 /* scsiTarget */\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB05_06_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB05_06_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB05_06_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB05_06_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB05_06_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB05_06_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB05_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB05_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB05_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB05_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB05_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB05_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB05_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB05_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB05_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB05_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB05_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB05_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB05_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB05_MSK\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB00_01_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB00_01_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB00_01_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB00_01_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB00_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB00_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB00_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB00_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB00_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB00_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB00_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB00_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB00_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB00_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB00_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB00_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB00_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB00_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB00_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB00_MSK\r
 #define scsiTarget_StatusReg__0__MASK 0x01u\r
 #define scsiTarget_StatusReg__0__POS 0\r
 #define scsiTarget_StatusReg__1__MASK 0x02u\r
 #define scsiTarget_StatusReg__1__POS 1\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
 #define scsiTarget_StatusReg__2__MASK 0x04u\r
 #define scsiTarget_StatusReg__2__POS 2\r
 #define scsiTarget_StatusReg__3__MASK 0x08u\r
 #define scsiTarget_StatusReg__4__MASK 0x10u\r
 #define scsiTarget_StatusReg__4__POS 4\r
 #define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK\r
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
 \r
 /* Debug_Timer_Interrupt */\r
 #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define SCSI_Filtered_sts_sts_reg__0__POS 0\r
 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
 #define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST\r
 #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
 #define SCSI_Filtered_sts_sts_reg__2__POS 2\r
 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
 #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
 #define SCSI_Filtered_sts_sts_reg__4__POS 4\r
 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK\r
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST\r
 \r
 /* SCSI_CTL_PHASE */\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
 \r
 /* SCSI_Parity_Error */\r
 #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
 #define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
 #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST\r
 \r
 /* Miscellaneous */\r
 #define BCLK__BUS_CLK__HZ 50000000U\r