Final tweaks for v4.5
[SCSI2SD-V6.git] / software / SCSI2SD / v4 / SCSI2SD.cydsn / Generated_Source / PSoC5 / cyfitterrv.inc
index 98aa696..c639021 100755 (executable)
@@ -426,34 +426,34 @@ EXTLED__SHIFT EQU 0
 EXTLED__SLW EQU CYREG_PRT0_SLW\r
 \r
 ; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
@@ -461,9 +461,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
 SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
@@ -481,12 +481,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
 SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
 SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
 SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
 SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
@@ -494,9 +496,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
 \r
 ; SD_SCK\r
 SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
@@ -1906,15 +1908,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
@@ -1927,37 +1929,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
 SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
 \r
 ; SCSI_Out_Ctl\r
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
 \r
 ; SCSI_Out_DBx\r
 SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
@@ -2785,8 +2787,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0\r
 scsiTarget_StatusReg__1__MASK EQU 0x02\r
 scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
 scsiTarget_StatusReg__2__MASK EQU 0x04\r
 scsiTarget_StatusReg__2__POS EQU 2\r
 scsiTarget_StatusReg__3__MASK EQU 0x08\r
@@ -2794,9 +2796,13 @@ scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__4__MASK EQU 0x10\r
 scsiTarget_StatusReg__4__POS EQU 4\r
 scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
 \r
 ; Debug_Timer_Interrupt\r
 Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
@@ -2917,8 +2923,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
@@ -2926,13 +2932,9 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
 \r
 ; SCSI_CTL_PHASE\r
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
@@ -2985,12 +2987,12 @@ SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
 ; SCSI_Parity_Error\r
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
 \r
 ; Miscellaneous\r
 BCLK__BUS_CLK__HZ EQU 50000000\r