Added glitch filter to ACK, RST, SEL, BSY and ATN lines. v3.6-RC1
authorMichael McMaster <michael@codesrc.com>
Fri, 29 Aug 2014 12:35:05 +0000 (22:35 +1000)
committerMichael McMaster <michael@codesrc.com>
Fri, 29 Aug 2014 12:35:05 +0000 (22:35 +1000)
41 files changed:
CHANGELOG
software/SCSI2SD/src/config.c
software/SCSI2SD/src/scsi.c
software/SCSI2SD/src/scsiPhy.c
software/SCSI2SD/src/scsiPhy.h
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c [new file with mode: 0644]
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h [new file with mode: 0644]
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h [changed mode: 0755->0644]
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h [new file with mode: 0644]
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c [new file with mode: 0644]
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h [new file with mode: 0644]
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h [new file with mode: 0644]
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch

index 656e944..bd1346d 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,6 +1,6 @@
 201408XX               3.6
        - Fix handling requests for LUNs other than 0 from SCSI-2 hosts.
-       - Handle glitches of the ACK line to improve stability and operate with
+       - Handle glitches of the scsi signals to improve stability and operate with
        multiple devices on the SCSI bus.
        - Re-add parity checking. This can be disabled using scsi2sd-config if
        required.
index 12600de..0488522 100755 (executable)
@@ -275,10 +275,10 @@ void debugPoll()
                debugBuffer[14] = scsiDev.lastStatus;\r
                debugBuffer[15] = scsiDev.lastSense;\r
                debugBuffer[16] = scsiDev.phase;\r
-               debugBuffer[17] = SCSI_ReadPin(SCSI_In_BSY);\r
-               debugBuffer[18] = SCSI_ReadPin(SCSI_In_SEL);\r
-               debugBuffer[19] = SCSI_ReadPin(SCSI_ATN_INT);\r
-               debugBuffer[20] = SCSI_ReadPin(SCSI_RST_INT);\r
+               debugBuffer[17] = SCSI_ReadFilt(SCSI_Filt_BSY);\r
+               debugBuffer[18] = SCSI_ReadFilt(SCSI_Filt_SEL);\r
+               debugBuffer[19] = SCSI_ReadFilt(SCSI_Filt_ATN);\r
+               debugBuffer[20] = SCSI_ReadFilt(SCSI_Filt_RST);\r
                debugBuffer[21] = scsiDev.rstCount;\r
                debugBuffer[22] = scsiDev.selCount;\r
                debugBuffer[23] = scsiDev.msgCount;\r
index 74fe177..eb09721 100755 (executable)
@@ -473,8 +473,8 @@ static void enter_SelectionPhase()
 \r
 static void process_SelectionPhase()\r
 {\r
-       int sel = SCSI_ReadPin(SCSI_In_SEL);\r
-       int bsy = SCSI_ReadPin(SCSI_In_BSY);\r
+       int sel = SCSI_ReadFilt(SCSI_Filt_SEL);\r
+       int bsy = SCSI_ReadFilt(SCSI_Filt_BSY);\r
 \r
        // Only read these pins AFTER SEL and BSY - we don't want to catch them\r
        // during a transition period.\r
@@ -489,7 +489,7 @@ static void process_SelectionPhase()
                // Do we enter MESSAGE OUT immediately ? SCSI 1 and 2 standards says\r
                // move to MESSAGE OUT if ATN is true before we assert BSY.\r
                // The initiator should assert ATN with SEL.\r
-               scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT);\r
+               scsiDev.atnFlag = SCSI_ReadFilt(SCSI_Filt_ATN);\r
                \r
                // Unit attention breaks many older SCSI hosts. Disable it completely for\r
                // SCSI-1 (and older) hosts, regardless of our configured setting.\r
@@ -512,7 +512,7 @@ static void process_SelectionPhase()
                // Wait until the end of the selection phase.\r
                while (!scsiDev.resetFlag)\r
                {\r
-                       if (!SCSI_ReadPin(SCSI_In_SEL))\r
+                       if (!SCSI_ReadFilt(SCSI_Filt_SEL))\r
                        {\r
                                break;\r
                        }\r
@@ -562,7 +562,7 @@ static void process_MessageOut()
                // Skip the remaining message bytes, and then start the MESSAGE_OUT\r
                // phase again from the start. The initiator will re-send the\r
                // same set of messages.\r
-               while (SCSI_ReadPin(SCSI_ATN_INT) && !scsiDev.resetFlag)\r
+               while (SCSI_ReadFilt(SCSI_Filt_ATN) && !scsiDev.resetFlag)\r
                {\r
                        scsiReadByte();\r
                }\r
@@ -673,7 +673,7 @@ static void process_MessageOut()
        }\r
 \r
        // Re-check the ATN flag in case it stays asserted.\r
-       scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
+       scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN);\r
 }\r
 \r
 void scsiPoll(void)\r
@@ -681,7 +681,7 @@ void scsiPoll(void)
        if (scsiDev.resetFlag)\r
        {\r
                scsiReset();\r
-               if ((scsiDev.resetFlag = SCSI_ReadPin(SCSI_RST_INT)))\r
+               if ((scsiDev.resetFlag = SCSI_ReadFilt(SCSI_Filt_RST)))\r
                {\r
                        // Still in reset phase. Do not try and process any commands.\r
                        return;\r
@@ -691,7 +691,7 @@ void scsiPoll(void)
        switch (scsiDev.phase)\r
        {\r
        case BUS_FREE:\r
-               if (SCSI_ReadPin(SCSI_In_BSY))\r
+               if (SCSI_ReadFilt(SCSI_Filt_BSY))\r
                {\r
                        scsiDev.phase = BUS_BUSY;\r
                }\r
@@ -699,7 +699,7 @@ void scsiPoll(void)
                // one initiator in the chain. Support this by moving\r
                // straight to selection if SEL is asserted.\r
                // ie. the initiator won't assert BSY and it's own ID before moving to selection.\r
-               else if (SCSI_ReadPin(SCSI_In_SEL))\r
+               else if (SCSI_ReadFilt(SCSI_Filt_SEL))\r
                {\r
                        enter_SelectionPhase();\r
                }\r
@@ -708,11 +708,11 @@ void scsiPoll(void)
        case BUS_BUSY:\r
                // Someone is using the bus. Perhaps they are trying to\r
                // select us.\r
-               if (SCSI_ReadPin(SCSI_In_SEL))\r
+               if (SCSI_ReadFilt(SCSI_Filt_SEL))\r
                {\r
                        enter_SelectionPhase();\r
                }\r
-               else if (!SCSI_ReadPin(SCSI_In_BSY))\r
+               else if (!SCSI_ReadFilt(SCSI_Filt_BSY))\r
                {\r
                        scsiDev.phase = BUS_FREE;\r
                }\r
@@ -745,7 +745,7 @@ void scsiPoll(void)
        break;\r
 \r
        case DATA_IN:\r
-               scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
+               scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN);\r
                if (scsiDev.atnFlag)\r
                {\r
                        process_MessageOut();\r
@@ -757,7 +757,7 @@ void scsiPoll(void)
        break;\r
 \r
        case DATA_OUT:\r
-               scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
+               scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN);\r
                if (scsiDev.atnFlag)\r
                {\r
                        process_MessageOut();\r
@@ -769,7 +769,7 @@ void scsiPoll(void)
        break;\r
 \r
        case STATUS:\r
-               scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
+               scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN);\r
                if (scsiDev.atnFlag)\r
                {\r
                        process_MessageOut();\r
@@ -781,7 +781,7 @@ void scsiPoll(void)
        break;\r
 \r
        case MESSAGE_IN:\r
-               scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
+               scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN);\r
                if (scsiDev.atnFlag)\r
                {\r
                        process_MessageOut();\r
index 46852fb..b6c4e64 100755 (executable)
@@ -61,7 +61,6 @@ CY_ISR_PROTO(scsiResetISR);
 CY_ISR(scsiResetISR)\r
 {\r
        scsiDev.resetFlag = 1;\r
-       SCSI_RST_ClearInterrupt();\r
 }\r
 \r
 uint8_t\r
@@ -425,8 +424,4 @@ void scsiPhyInit()
        scsiPhyInitDMA();\r
 \r
        SCSI_RST_ISR_StartEx(scsiResetISR);\r
-\r
-       // Interrupts may have already been directed to the (empty)\r
-       // standard ISR generated by PSoC Creator.\r
-       SCSI_RST_ClearInterrupt();\r
 }\r
index b6a1426..97e5f45 100755 (executable)
@@ -47,6 +47,19 @@ typedef enum
 #define SCSI_ReadPin(pin) \
        (CyPins_ReadPin((pin)) == 0)
 
+// These signals go through a glitch filter - we do not access the pin
+// directly
+enum FilteredInputs
+{
+       SCSI_Filt_ATN = 0x01,
+       SCSI_Filt_BSY = 0x02,
+       SCSI_Filt_SEL = 0x04,
+       SCSI_Filt_RST = 0x08,
+       SCSI_Filt_ACK = 0x10            
+};
+#define SCSI_ReadFilt(filt) \
+       ((SCSI_Filtered_Read() & (filt)) == 0)
+
 // Contains the odd-parity flag for a given 8-bit value.
 extern const uint8_t Lookup_OddParity[256];
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c
new file mode 100644 (file)
index 0000000..2fc815b
--- /dev/null
@@ -0,0 +1,134 @@
+/*******************************************************************************
+* File Name: SCSI_Filtered.c  
+* Version 1.80
+*
+* Description:
+*  This file contains API to enable firmware to read the value of a Status 
+*  Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Filtered.h"
+
+#if !defined(SCSI_Filtered_sts_sts_reg__REMOVED) /* Check for removal by optimization */
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Status Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  The current value in the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Filtered_Read(void) 
+{ 
+    return SCSI_Filtered_Status;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_InterruptEnable
+********************************************************************************
+*
+* Summary:
+*  Enables the Status Register interrupt.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Filtered_InterruptEnable(void) 
+{
+    uint8 interruptState;
+    interruptState = CyEnterCriticalSection();
+    SCSI_Filtered_Status_Aux_Ctrl |= SCSI_Filtered_STATUS_INTR_ENBL;
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_InterruptDisable
+********************************************************************************
+*
+* Summary:
+*  Disables the Status Register interrupt.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Filtered_InterruptDisable(void) 
+{
+    uint8 interruptState;
+    interruptState = CyEnterCriticalSection();
+    SCSI_Filtered_Status_Aux_Ctrl &= (uint8)(~SCSI_Filtered_STATUS_INTR_ENBL);
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_WriteMask
+********************************************************************************
+*
+* Summary:
+*  Writes the current mask value assigned to the Status Register.
+*
+* Parameters:
+*  mask:  Value to write into the mask register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Filtered_WriteMask(uint8 mask) 
+{
+    #if(SCSI_Filtered_INPUTS < 8u)
+       mask &= (uint8)((((uint8)1u) << SCSI_Filtered_INPUTS) - 1u);
+       #endif /* End SCSI_Filtered_INPUTS < 8u */
+    SCSI_Filtered_Status_Mask = mask;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_ReadMask
+********************************************************************************
+*
+* Summary:
+*  Reads the current interrupt mask assigned to the Status Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  The value of the interrupt mask of the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Filtered_ReadMask(void) 
+{
+    return SCSI_Filtered_Status_Mask;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h
new file mode 100644 (file)
index 0000000..759a85b
--- /dev/null
@@ -0,0 +1,63 @@
+/*******************************************************************************
+* File Name: SCSI_Filtered.h  
+* Version 1.80
+*
+* Description:
+*  This file containts Status Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */
+#define CY_STATUS_REG_SCSI_Filtered_H
+
+#include "cytypes.h"
+#include "CyLib.h"
+
+
+/***************************************
+*        Function Prototypes
+***************************************/
+
+uint8 SCSI_Filtered_Read(void) ;
+void SCSI_Filtered_InterruptEnable(void) ;
+void SCSI_Filtered_InterruptDisable(void) ;
+void SCSI_Filtered_WriteMask(uint8 mask) ;
+uint8 SCSI_Filtered_ReadMask(void) ;
+
+
+/***************************************
+*           API Constants
+***************************************/
+
+#define SCSI_Filtered_STATUS_INTR_ENBL    0x10u
+
+
+/***************************************
+*         Parameter Constants
+***************************************/
+
+/* Status Register Inputs */
+#define SCSI_Filtered_INPUTS              5
+
+
+/***************************************
+*             Registers
+***************************************/
+
+/* Status Register */
+#define SCSI_Filtered_Status             (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG )
+#define SCSI_Filtered_Status_PTR         (  (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG )
+#define SCSI_Filtered_Status_Mask        (* (reg8 *) SCSI_Filtered_sts_sts_reg__MASK_REG )
+#define SCSI_Filtered_Status_Aux_Ctrl    (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG )
+
+#endif /* End CY_STATUS_REG_SCSI_Filtered_H */
+
+
+/* [] END OF FILE */
old mode 100755 (executable)
new mode 100644 (file)
index 729fd56..ca51951
 #define SCSI_In_2              SCSI_In__2__PC\r
 #define SCSI_In_3              SCSI_In__3__PC\r
 #define SCSI_In_4              SCSI_In__4__PC\r
-#define SCSI_In_5              SCSI_In__5__PC\r
-#define SCSI_In_6              SCSI_In__6__PC\r
-#define SCSI_In_7              SCSI_In__7__PC\r
 \r
 #define SCSI_In_DBP            SCSI_In__DBP__PC\r
-#define SCSI_In_BSY            SCSI_In__BSY__PC\r
-#define SCSI_In_ACK            SCSI_In__ACK__PC\r
 #define SCSI_In_MSG            SCSI_In__MSG__PC\r
-#define SCSI_In_SEL            SCSI_In__SEL__PC\r
 #define SCSI_In_CD             SCSI_In__CD__PC\r
 #define SCSI_In_REQ            SCSI_In__REQ__PC\r
 #define SCSI_In_IO             SCSI_In__IO__PC\r
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h
new file mode 100644 (file)
index 0000000..ffd841d
--- /dev/null
@@ -0,0 +1,42 @@
+/*******************************************************************************
+* File Name: SCSI_Noise.h  
+* Version 1.90
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SCSI_Noise_ALIASES_H) /* Pins SCSI_Noise_ALIASES_H */
+#define CY_PINS_SCSI_Noise_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SCSI_Noise_0           SCSI_Noise__0__PC
+#define SCSI_Noise_1           SCSI_Noise__1__PC
+#define SCSI_Noise_2           SCSI_Noise__2__PC
+#define SCSI_Noise_3           SCSI_Noise__3__PC
+#define SCSI_Noise_4           SCSI_Noise__4__PC
+
+#define SCSI_Noise_ATN         SCSI_Noise__ATN__PC
+#define SCSI_Noise_BSY         SCSI_Noise__BSY__PC
+#define SCSI_Noise_SEL         SCSI_Noise__SEL__PC
+#define SCSI_Noise_RST         SCSI_Noise__RST__PC
+#define SCSI_Noise_ACK         SCSI_Noise__ACK__PC
+
+#endif /* End Pins SCSI_Noise_ALIASES_H */
+
+/* [] END OF FILE */
index 1335c5f..2ee57e0 100644 (file)
 /* SCSI_TX_DMA_COMPLETE */\r
 #define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x04u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 2u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u\r
 #define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
 #define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 /* SD_RX_DMA_COMPLETE */\r
 #define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x08u\r
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 3u\r
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u\r
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u\r
 #define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
 #define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 /* SD_TX_DMA_COMPLETE */\r
 #define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x10u\r
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 4u\r
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u\r
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u\r
 #define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
 #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 /* SCSI_Parity_Error */\r
 #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
 #define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
 #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST\r
 \r
 /* USBFS_bus_reset */\r
 #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 /* SCSI_CTL_PHASE */\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+\r
+/* SCSI_Filtered */\r
+#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u\r
+#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST\r
+#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
+#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
+#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
+#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
+#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
+#define SCSI_Filtered_sts_sts_reg__3__POS 3\r
+#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
+#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
+#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB00_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB00_ST\r
 \r
 /* SCSI_Out_Bits */\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
 \r
 /* USBFS_arb_int */\r
 #define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 /* SCSI_Out_Ctl */\r
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
 #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
 \r
 /* SCSI_Out_DBx */\r
 #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
 /* SCSI_RST_ISR */\r
 #define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_RST_ISR__INTC_MASK 0x400u\r
-#define SCSI_RST_ISR__INTC_NUMBER 10u\r
+#define SCSI_RST_ISR__INTC_MASK 0x04u\r
+#define SCSI_RST_ISR__INTC_NUMBER 2u\r
 #define SCSI_RST_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_10\r
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
 #define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 /* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
 #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
 #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB05_ST\r
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
 #define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
 #define SDCard_BSPIM_TxStsReg__1__POS 1\r
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_TxStsReg__4__POS 4\r
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB06_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB05_06_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB05_06_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB05_06_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB05_06_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB05_06_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB05_06_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB05_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB05_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB05_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB05_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB05_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB05_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB05_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB05_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB05_F1\r
 \r
 /* USBFS_dp_int */\r
 #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
 #define timer_clock__PM_STBY_MSK 0x04u\r
 \r
+/* SCSI_Noise */\r
+#define SCSI_Noise__0__AG CYREG_PRT12_AG\r
+#define SCSI_Noise__0__BIE CYREG_PRT12_BIE\r
+#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_Noise__0__BYP CYREG_PRT12_BYP\r
+#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0\r
+#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1\r
+#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2\r
+#define SCSI_Noise__0__DR CYREG_PRT12_DR\r
+#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_Noise__0__MASK 0x20u\r
+#define SCSI_Noise__0__PC CYREG_PRT12_PC5\r
+#define SCSI_Noise__0__PORT 12u\r
+#define SCSI_Noise__0__PRT CYREG_PRT12_PRT\r
+#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_Noise__0__PS CYREG_PRT12_PS\r
+#define SCSI_Noise__0__SHIFT 5\r
+#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_Noise__0__SLW CYREG_PRT12_SLW\r
+#define SCSI_Noise__1__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__1__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__1__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__1__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__1__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__1__MASK 0x10u\r
+#define SCSI_Noise__1__PC CYREG_PRT6_PC4\r
+#define SCSI_Noise__1__PORT 6u\r
+#define SCSI_Noise__1__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__1__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__1__SHIFT 4\r
+#define SCSI_Noise__1__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__2__AG CYREG_PRT5_AG\r
+#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_Noise__2__BIE CYREG_PRT5_BIE\r
+#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_Noise__2__BYP CYREG_PRT5_BYP\r
+#define SCSI_Noise__2__CTL CYREG_PRT5_CTL\r
+#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0\r
+#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1\r
+#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2\r
+#define SCSI_Noise__2__DR CYREG_PRT5_DR\r
+#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_Noise__2__MASK 0x01u\r
+#define SCSI_Noise__2__PC CYREG_PRT5_PC0\r
+#define SCSI_Noise__2__PORT 5u\r
+#define SCSI_Noise__2__PRT CYREG_PRT5_PRT\r
+#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_Noise__2__PS CYREG_PRT5_PS\r
+#define SCSI_Noise__2__SHIFT 0\r
+#define SCSI_Noise__2__SLW CYREG_PRT5_SLW\r
+#define SCSI_Noise__3__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__3__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__3__MASK 0x40u\r
+#define SCSI_Noise__3__PC CYREG_PRT6_PC6\r
+#define SCSI_Noise__3__PORT 6u\r
+#define SCSI_Noise__3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__3__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__3__SHIFT 6\r
+#define SCSI_Noise__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__4__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__4__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__4__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__4__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__4__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__4__MASK 0x20u\r
+#define SCSI_Noise__4__PC CYREG_PRT6_PC5\r
+#define SCSI_Noise__4__PORT 6u\r
+#define SCSI_Noise__4__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__4__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__4__SHIFT 5\r
+#define SCSI_Noise__4__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__ACK__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__ACK__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__ACK__MASK 0x20u\r
+#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5\r
+#define SCSI_Noise__ACK__PORT 6u\r
+#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__ACK__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__ACK__SHIFT 5\r
+#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__ATN__AG CYREG_PRT12_AG\r
+#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE\r
+#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP\r
+#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0\r
+#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1\r
+#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2\r
+#define SCSI_Noise__ATN__DR CYREG_PRT12_DR\r
+#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_Noise__ATN__MASK 0x20u\r
+#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5\r
+#define SCSI_Noise__ATN__PORT 12u\r
+#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT\r
+#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_Noise__ATN__PS CYREG_PRT12_PS\r
+#define SCSI_Noise__ATN__SHIFT 5\r
+#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW\r
+#define SCSI_Noise__BSY__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__BSY__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__BSY__MASK 0x10u\r
+#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4\r
+#define SCSI_Noise__BSY__PORT 6u\r
+#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__BSY__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__BSY__SHIFT 4\r
+#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__RST__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__RST__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__RST__MASK 0x40u\r
+#define SCSI_Noise__RST__PC CYREG_PRT6_PC6\r
+#define SCSI_Noise__RST__PORT 6u\r
+#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__RST__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__RST__SHIFT 6\r
+#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__SEL__AG CYREG_PRT5_AG\r
+#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE\r
+#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP\r
+#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL\r
+#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0\r
+#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1\r
+#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2\r
+#define SCSI_Noise__SEL__DR CYREG_PRT5_DR\r
+#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_Noise__SEL__MASK 0x01u\r
+#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0\r
+#define SCSI_Noise__SEL__PORT 5u\r
+#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT\r
+#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_Noise__SEL__PS CYREG_PRT5_PS\r
+#define SCSI_Noise__SEL__SHIFT 0\r
+#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW\r
+\r
 /* scsiTarget */\r
 #define scsiTarget_StatusReg__0__MASK 0x01u\r
 #define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
 #define scsiTarget_StatusReg__1__MASK 0x02u\r
 #define scsiTarget_StatusReg__1__POS 1\r
 #define scsiTarget_StatusReg__2__MASK 0x04u\r
 #define scsiTarget_StatusReg__4__MASK 0x10u\r
 #define scsiTarget_StatusReg__4__POS 4\r
 #define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK\r
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB04_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB04_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB04_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB04_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB04_MSK\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB04_05_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB04_05_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB04_05_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB04_05_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB04_05_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB04_05_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB04_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB04_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB04_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB04_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB04_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB04_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB04_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB04_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB04_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK\r
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB12_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB12_13_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB12_13_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB12_13_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB12_13_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB12_13_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB12_13_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB12_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB12_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB12_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB12_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB12_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB12_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB12_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB12_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB12_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
 \r
 /* USBFS_ep_0 */\r
 #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 /* USBFS_ep_1 */\r
 #define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_1__INTC_MASK 0x20u\r
-#define USBFS_ep_1__INTC_NUMBER 5u\r
+#define USBFS_ep_1__INTC_MASK 0x40u\r
+#define USBFS_ep_1__INTC_NUMBER 6u\r
 #define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
 #define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 /* USBFS_ep_2 */\r
 #define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_2__INTC_MASK 0x40u\r
-#define USBFS_ep_2__INTC_NUMBER 6u\r
+#define USBFS_ep_2__INTC_MASK 0x80u\r
+#define USBFS_ep_2__INTC_NUMBER 7u\r
 #define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
 #define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 /* USBFS_ep_3 */\r
 #define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_3__INTC_MASK 0x80u\r
-#define USBFS_ep_3__INTC_NUMBER 7u\r
+#define USBFS_ep_3__INTC_MASK 0x100u\r
+#define USBFS_ep_3__INTC_NUMBER 8u\r
 #define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
 #define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 /* USBFS_ep_4 */\r
 #define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_4__INTC_MASK 0x100u\r
-#define USBFS_ep_4__INTC_NUMBER 8u\r
+#define USBFS_ep_4__INTC_MASK 0x200u\r
+#define USBFS_ep_4__INTC_NUMBER 9u\r
 #define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9\r
 #define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
 #define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN\r
 \r
-/* SCSI_ATN */\r
-#define SCSI_ATN__0__MASK 0x20u\r
-#define SCSI_ATN__0__PC CYREG_PRT12_PC5\r
-#define SCSI_ATN__0__PORT 12u\r
-#define SCSI_ATN__0__SHIFT 5\r
-#define SCSI_ATN__AG CYREG_PRT12_AG\r
-#define SCSI_ATN__BIE CYREG_PRT12_BIE\r
-#define SCSI_ATN__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_ATN__BYP CYREG_PRT12_BYP\r
-#define SCSI_ATN__DM0 CYREG_PRT12_DM0\r
-#define SCSI_ATN__DM1 CYREG_PRT12_DM1\r
-#define SCSI_ATN__DM2 CYREG_PRT12_DM2\r
-#define SCSI_ATN__DR CYREG_PRT12_DR\r
-#define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_ATN__INT__MASK 0x20u\r
-#define SCSI_ATN__INT__PC CYREG_PRT12_PC5\r
-#define SCSI_ATN__INT__PORT 12u\r
-#define SCSI_ATN__INT__SHIFT 5\r
-#define SCSI_ATN__MASK 0x20u\r
-#define SCSI_ATN__PORT 12u\r
-#define SCSI_ATN__PRT CYREG_PRT12_PRT\r
-#define SCSI_ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_ATN__PS CYREG_PRT12_PS\r
-#define SCSI_ATN__SHIFT 5\r
-#define SCSI_ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_ATN__SLW CYREG_PRT12_SLW\r
-\r
 /* SCSI_CLK */\r
 #define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
 #define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
 #define SCSI_Out__SEL__SHIFT 3\r
 #define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
 \r
-/* SCSI_RST */\r
-#define SCSI_RST__0__MASK 0x40u\r
-#define SCSI_RST__0__PC CYREG_PRT6_PC6\r
-#define SCSI_RST__0__PORT 6u\r
-#define SCSI_RST__0__SHIFT 6\r
-#define SCSI_RST__AG CYREG_PRT6_AG\r
-#define SCSI_RST__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_RST__BIE CYREG_PRT6_BIE\r
-#define SCSI_RST__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_RST__BYP CYREG_PRT6_BYP\r
-#define SCSI_RST__CTL CYREG_PRT6_CTL\r
-#define SCSI_RST__DM0 CYREG_PRT6_DM0\r
-#define SCSI_RST__DM1 CYREG_PRT6_DM1\r
-#define SCSI_RST__DM2 CYREG_PRT6_DM2\r
-#define SCSI_RST__DR CYREG_PRT6_DR\r
-#define SCSI_RST__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_RST__INTSTAT CYREG_PICU6_INTSTAT\r
-#define SCSI_RST__INT__MASK 0x40u\r
-#define SCSI_RST__INT__PC CYREG_PRT6_PC6\r
-#define SCSI_RST__INT__PORT 6u\r
-#define SCSI_RST__INT__SHIFT 6\r
-#define SCSI_RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_RST__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_RST__MASK 0x40u\r
-#define SCSI_RST__PORT 6u\r
-#define SCSI_RST__PRT CYREG_PRT6_PRT\r
-#define SCSI_RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_RST__PS CYREG_PRT6_PS\r
-#define SCSI_RST__SHIFT 6\r
-#define SCSI_RST__SLW CYREG_PRT6_SLW\r
-#define SCSI_RST__SNAP CYREG_PICU6_SNAP\r
-\r
 /* USBFS_Dm */\r
 #define USBFS_Dm__0__MASK 0x80u\r
 #define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
 #define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS\r
 #define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
 #define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__1__MASK 0x10u\r
-#define SCSI_In__1__PC CYREG_PRT6_PC4\r
+#define SCSI_In__1__MASK 0x80u\r
+#define SCSI_In__1__PC CYREG_PRT6_PC7\r
 #define SCSI_In__1__PORT 6u\r
 #define SCSI_In__1__PRT CYREG_PRT6_PRT\r
 #define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
 #define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
 #define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
 #define SCSI_In__1__PS CYREG_PRT6_PS\r
-#define SCSI_In__1__SHIFT 4\r
+#define SCSI_In__1__SHIFT 7\r
 #define SCSI_In__1__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__2__AG CYREG_PRT6_AG\r
-#define SCSI_In__2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__2__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__2__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__2__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__2__DR CYREG_PRT6_DR\r
-#define SCSI_In__2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__2__MASK 0x20u\r
-#define SCSI_In__2__PC CYREG_PRT6_PC5\r
-#define SCSI_In__2__PORT 6u\r
-#define SCSI_In__2__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__2__PS CYREG_PRT6_PS\r
-#define SCSI_In__2__SHIFT 5\r
-#define SCSI_In__2__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__3__AG CYREG_PRT6_AG\r
-#define SCSI_In__3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__3__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__3__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__3__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__3__DR CYREG_PRT6_DR\r
-#define SCSI_In__3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__3__MASK 0x80u\r
-#define SCSI_In__3__PC CYREG_PRT6_PC7\r
-#define SCSI_In__3__PORT 6u\r
-#define SCSI_In__3__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__3__PS CYREG_PRT6_PS\r
-#define SCSI_In__3__SHIFT 7\r
-#define SCSI_In__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__2__AG CYREG_PRT5_AG\r
+#define SCSI_In__2__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__2__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__2__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__2__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__2__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__2__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__2__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__2__DR CYREG_PRT5_DR\r
+#define SCSI_In__2__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__2__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__2__MASK 0x02u\r
+#define SCSI_In__2__PC CYREG_PRT5_PC1\r
+#define SCSI_In__2__PORT 5u\r
+#define SCSI_In__2__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__2__PS CYREG_PRT5_PS\r
+#define SCSI_In__2__SHIFT 1\r
+#define SCSI_In__2__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__3__AG CYREG_PRT5_AG\r
+#define SCSI_In__3__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__3__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__3__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__3__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__3__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__3__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__3__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__3__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__3__DR CYREG_PRT5_DR\r
+#define SCSI_In__3__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__3__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__3__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__3__MASK 0x04u\r
+#define SCSI_In__3__PC CYREG_PRT5_PC2\r
+#define SCSI_In__3__PORT 5u\r
+#define SCSI_In__3__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__3__PS CYREG_PRT5_PS\r
+#define SCSI_In__3__SHIFT 2\r
+#define SCSI_In__3__SLW CYREG_PRT5_SLW\r
 #define SCSI_In__4__AG CYREG_PRT5_AG\r
 #define SCSI_In__4__AMUX CYREG_PRT5_AMUX\r
 #define SCSI_In__4__BIE CYREG_PRT5_BIE\r
 #define SCSI_In__4__INP_DIS CYREG_PRT5_INP_DIS\r
 #define SCSI_In__4__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
 #define SCSI_In__4__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__4__MASK 0x01u\r
-#define SCSI_In__4__PC CYREG_PRT5_PC0\r
+#define SCSI_In__4__MASK 0x08u\r
+#define SCSI_In__4__PC CYREG_PRT5_PC3\r
 #define SCSI_In__4__PORT 5u\r
 #define SCSI_In__4__PRT CYREG_PRT5_PRT\r
 #define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
 #define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
 #define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
 #define SCSI_In__4__PS CYREG_PRT5_PS\r
-#define SCSI_In__4__SHIFT 0\r
+#define SCSI_In__4__SHIFT 3\r
 #define SCSI_In__4__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__5__AG CYREG_PRT5_AG\r
-#define SCSI_In__5__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__5__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__5__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__5__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__5__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__5__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__5__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__5__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__5__DR CYREG_PRT5_DR\r
-#define SCSI_In__5__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__5__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__5__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__5__MASK 0x02u\r
-#define SCSI_In__5__PC CYREG_PRT5_PC1\r
-#define SCSI_In__5__PORT 5u\r
-#define SCSI_In__5__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__5__PS CYREG_PRT5_PS\r
-#define SCSI_In__5__SHIFT 1\r
-#define SCSI_In__5__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__6__AG CYREG_PRT5_AG\r
-#define SCSI_In__6__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__6__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__6__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__6__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__6__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__6__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__6__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__6__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__6__DR CYREG_PRT5_DR\r
-#define SCSI_In__6__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__6__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__6__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__6__MASK 0x04u\r
-#define SCSI_In__6__PC CYREG_PRT5_PC2\r
-#define SCSI_In__6__PORT 5u\r
-#define SCSI_In__6__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__6__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__6__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__6__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__6__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__6__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__6__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__6__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__6__PS CYREG_PRT5_PS\r
-#define SCSI_In__6__SHIFT 2\r
-#define SCSI_In__6__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__7__AG CYREG_PRT5_AG\r
-#define SCSI_In__7__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__7__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__7__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__7__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__7__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__7__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__7__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__7__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__7__DR CYREG_PRT5_DR\r
-#define SCSI_In__7__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__7__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__7__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__7__MASK 0x08u\r
-#define SCSI_In__7__PC CYREG_PRT5_PC3\r
-#define SCSI_In__7__PORT 5u\r
-#define SCSI_In__7__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__7__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__7__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__7__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__7__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__7__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__7__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__7__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__7__PS CYREG_PRT5_PS\r
-#define SCSI_In__7__SHIFT 3\r
-#define SCSI_In__7__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__ACK__AG CYREG_PRT6_AG\r
-#define SCSI_In__ACK__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__ACK__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__ACK__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__ACK__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__ACK__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__ACK__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__ACK__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__ACK__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__ACK__DR CYREG_PRT6_DR\r
-#define SCSI_In__ACK__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__ACK__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__ACK__MASK 0x20u\r
-#define SCSI_In__ACK__PC CYREG_PRT6_PC5\r
-#define SCSI_In__ACK__PORT 6u\r
-#define SCSI_In__ACK__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__ACK__PS CYREG_PRT6_PS\r
-#define SCSI_In__ACK__SHIFT 5\r
-#define SCSI_In__ACK__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__BSY__AG CYREG_PRT6_AG\r
-#define SCSI_In__BSY__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__BSY__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__BSY__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__BSY__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__BSY__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__BSY__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__BSY__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__BSY__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__BSY__DR CYREG_PRT6_DR\r
-#define SCSI_In__BSY__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__BSY__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__BSY__MASK 0x10u\r
-#define SCSI_In__BSY__PC CYREG_PRT6_PC4\r
-#define SCSI_In__BSY__PORT 6u\r
-#define SCSI_In__BSY__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__BSY__PS CYREG_PRT6_PS\r
-#define SCSI_In__BSY__SHIFT 4\r
-#define SCSI_In__BSY__SLW CYREG_PRT6_SLW\r
 #define SCSI_In__CD__AG CYREG_PRT5_AG\r
 #define SCSI_In__CD__AMUX CYREG_PRT5_AMUX\r
 #define SCSI_In__CD__BIE CYREG_PRT5_BIE\r
 #define SCSI_In__REQ__PS CYREG_PRT5_PS\r
 #define SCSI_In__REQ__SHIFT 2\r
 #define SCSI_In__REQ__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__SEL__AG CYREG_PRT5_AG\r
-#define SCSI_In__SEL__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__SEL__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__SEL__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__SEL__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__SEL__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__SEL__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__SEL__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__SEL__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__SEL__DR CYREG_PRT5_DR\r
-#define SCSI_In__SEL__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__SEL__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__SEL__MASK 0x01u\r
-#define SCSI_In__SEL__PC CYREG_PRT5_PC0\r
-#define SCSI_In__SEL__PORT 5u\r
-#define SCSI_In__SEL__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__SEL__PS CYREG_PRT5_PS\r
-#define SCSI_In__SEL__SHIFT 0\r
-#define SCSI_In__SEL__SLW CYREG_PRT5_SLW\r
 \r
 /* SD_DAT1 */\r
 #define SD_DAT1__0__MASK 0x01u\r
 #define CYDEV_ECC_ENABLE 0\r
 #define CYDEV_HEAP_SIZE 0x0400\r
 #define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x0000001Eu\r
+#define CYDEV_INTR_RISING 0x0000003Eu\r
 #define CYDEV_PROJ_TYPE 2\r
 #define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
 #define CYDEV_PROJ_TYPE_LOADABLE 2\r
index 365ce1d..ff81377 100644 (file)
@@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode)
 }\r
 #endif\r
 \r
-#define CY_CFG_BASE_ADDR_COUNT 37u\r
+#define CY_CFG_BASE_ADDR_COUNT 41u\r
 CYPACKED typedef struct\r
 {\r
        uint8 offset;\r
@@ -378,1035 +378,1140 @@ void cyfitter_cfg(void)
 \r
        {\r
                static const uint32 CYCODE cy_cfg_addr_table[] = {\r
-                       0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
+                       0x40004501u, /* Base address: 0x40004500 Count: 1 */\r
                        0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
-                       0x4000520Cu, /* Base address: 0x40005200 Count: 12 */\r
-                       0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
-                       0x4001004Au, /* Base address: 0x40010000 Count: 74 */\r
-                       0x40010137u, /* Base address: 0x40010100 Count: 55 */\r
-                       0x4001024Au, /* Base address: 0x40010200 Count: 74 */\r
-                       0x4001035Cu, /* Base address: 0x40010300 Count: 92 */\r
-                       0x4001043Au, /* Base address: 0x40010400 Count: 58 */\r
-                       0x4001055Cu, /* Base address: 0x40010500 Count: 92 */\r
-                       0x4001064Eu, /* Base address: 0x40010600 Count: 78 */\r
-                       0x40010757u, /* Base address: 0x40010700 Count: 87 */\r
-                       0x4001091Au, /* Base address: 0x40010900 Count: 26 */\r
-                       0x40010A3Bu, /* Base address: 0x40010A00 Count: 59 */\r
-                       0x40010B51u, /* Base address: 0x40010B00 Count: 81 */\r
-                       0x40010D23u, /* Base address: 0x40010D00 Count: 35 */\r
-                       0x40010E49u, /* Base address: 0x40010E00 Count: 73 */\r
-                       0x40010F35u, /* Base address: 0x40010F00 Count: 53 */\r
-                       0x4001145Bu, /* Base address: 0x40011400 Count: 91 */\r
-                       0x40011543u, /* Base address: 0x40011500 Count: 67 */\r
-                       0x4001161Eu, /* Base address: 0x40011600 Count: 30 */\r
-                       0x40011750u, /* Base address: 0x40011700 Count: 80 */\r
-                       0x4001190Du, /* Base address: 0x40011900 Count: 13 */\r
-                       0x40011B03u, /* Base address: 0x40011B00 Count: 3 */\r
-                       0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
-                       0x40014119u, /* Base address: 0x40014100 Count: 25 */\r
-                       0x4001420Cu, /* Base address: 0x40014200 Count: 12 */\r
-                       0x4001430Eu, /* Base address: 0x40014300 Count: 14 */\r
-                       0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
+                       0x4000520Bu, /* Base address: 0x40005200 Count: 11 */\r
+                       0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
+                       0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
+                       0x40010047u, /* Base address: 0x40010000 Count: 71 */\r
+                       0x4001013Fu, /* Base address: 0x40010100 Count: 63 */\r
+                       0x40010249u, /* Base address: 0x40010200 Count: 73 */\r
+                       0x40010354u, /* Base address: 0x40010300 Count: 84 */\r
+                       0x40010453u, /* Base address: 0x40010400 Count: 83 */\r
+                       0x4001054Fu, /* Base address: 0x40010500 Count: 79 */\r
+                       0x40010651u, /* Base address: 0x40010600 Count: 81 */\r
+                       0x40010747u, /* Base address: 0x40010700 Count: 71 */\r
+                       0x4001090Bu, /* Base address: 0x40010900 Count: 11 */\r
+                       0x40010A4Au, /* Base address: 0x40010A00 Count: 74 */\r
+                       0x40010B4Au, /* Base address: 0x40010B00 Count: 74 */\r
+                       0x40010C39u, /* Base address: 0x40010C00 Count: 57 */\r
+                       0x40010D5Cu, /* Base address: 0x40010D00 Count: 92 */\r
+                       0x40010E44u, /* Base address: 0x40010E00 Count: 68 */\r
+                       0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */\r
+                       0x40011465u, /* Base address: 0x40011400 Count: 101 */\r
+                       0x4001154Fu, /* Base address: 0x40011500 Count: 79 */\r
+                       0x40011650u, /* Base address: 0x40011600 Count: 80 */\r
+                       0x40011744u, /* Base address: 0x40011700 Count: 68 */\r
+                       0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
+                       0x40011907u, /* Base address: 0x40011900 Count: 7 */\r
+                       0x40011B09u, /* Base address: 0x40011B00 Count: 9 */\r
+                       0x40014018u, /* Base address: 0x40014000 Count: 24 */\r
+                       0x4001411Du, /* Base address: 0x40014100 Count: 29 */\r
+                       0x40014210u, /* Base address: 0x40014200 Count: 16 */\r
+                       0x4001430Bu, /* Base address: 0x40014300 Count: 11 */\r
+                       0x40014411u, /* Base address: 0x40014400 Count: 17 */\r
                        0x40014514u, /* Base address: 0x40014500 Count: 20 */\r
-                       0x40014609u, /* Base address: 0x40014600 Count: 9 */\r
+                       0x4001460Du, /* Base address: 0x40014600 Count: 13 */\r
                        0x4001470Cu, /* Base address: 0x40014700 Count: 12 */\r
-                       0x40014805u, /* Base address: 0x40014800 Count: 5 */\r
-                       0x4001490Fu, /* Base address: 0x40014900 Count: 15 */\r
-                       0x40014C04u, /* Base address: 0x40014C00 Count: 4 */\r
-                       0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
+                       0x40014809u, /* Base address: 0x40014800 Count: 9 */\r
+                       0x40014910u, /* Base address: 0x40014900 Count: 16 */\r
+                       0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
+                       0x40014D04u, /* Base address: 0x40014D00 Count: 4 */\r
+                       0x40015004u, /* Base address: 0x40015000 Count: 4 */\r
                        0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
                };\r
 \r
                static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
-                       {0x36u, 0x02u},\r
                        {0x7Eu, 0x02u},\r
                        {0x01u, 0x20u},\r
-                       {0x0Au, 0x27u},\r
-                       {0x00u, 0x04u},\r
-                       {0x01u, 0x11u},\r
-                       {0x18u, 0x04u},\r
+                       {0x0Au, 0x36u},\r
+                       {0x00u, 0x12u},\r
+                       {0x01u, 0x04u},\r
+                       {0x18u, 0x08u},\r
                        {0x1Cu, 0x61u},\r
-                       {0x20u, 0x68u},\r
-                       {0x21u, 0xC0u},\r
-                       {0x2Cu, 0x0Fu},\r
-                       {0x30u, 0x09u},\r
-                       {0x31u, 0x0Au},\r
-                       {0x34u, 0x90u},\r
-                       {0x64u, 0x20u},\r
+                       {0x20u, 0x50u},\r
+                       {0x21u, 0x90u},\r
+                       {0x2Cu, 0x0Eu},\r
+                       {0x30u, 0x0Au},\r
+                       {0x31u, 0x09u},\r
+                       {0x34u, 0x80u},\r
                        {0x7Cu, 0x40u},\r
-                       {0x24u, 0x02u},\r
+                       {0x2Cu, 0x02u},\r
                        {0x86u, 0x0Fu},\r
-                       {0x03u, 0x80u},\r
-                       {0x06u, 0x80u},\r
+                       {0x02u, 0x10u},\r
+                       {0x03u, 0x08u},\r
+                       {0x04u, 0x01u},\r
+                       {0x06u, 0x02u},\r
                        {0x07u, 0x07u},\r
-                       {0x09u, 0x44u},\r
-                       {0x0Bu, 0x88u},\r
-                       {0x0Eu, 0x07u},\r
-                       {0x10u, 0xAAu},\r
-                       {0x11u, 0xAAu},\r
-                       {0x12u, 0x55u},\r
-                       {0x13u, 0x55u},\r
-                       {0x14u, 0x99u},\r
+                       {0x0Bu, 0x70u},\r
+                       {0x0Cu, 0x02u},\r
+                       {0x0Du, 0x44u},\r
+                       {0x0Eu, 0x01u},\r
+                       {0x0Fu, 0x88u},\r
+                       {0x14u, 0x02u},\r
                        {0x15u, 0x99u},\r
-                       {0x16u, 0x22u},\r
+                       {0x16u, 0x05u},\r
                        {0x17u, 0x22u},\r
-                       {0x1Au, 0x70u},\r
-                       {0x1Bu, 0x70u},\r
-                       {0x27u, 0x08u},\r
-                       {0x28u, 0x44u},\r
-                       {0x2Au, 0x88u},\r
-                       {0x2Eu, 0x08u},\r
-                       {0x30u, 0x0Fu},\r
+                       {0x18u, 0x02u},\r
+                       {0x1Au, 0x09u},\r
+                       {0x1Cu, 0x10u},\r
+                       {0x1Du, 0xAAu},\r
+                       {0x1Eu, 0x20u},\r
+                       {0x1Fu, 0x55u},\r
+                       {0x26u, 0x20u},\r
+                       {0x28u, 0x02u},\r
+                       {0x2Au, 0x01u},\r
+                       {0x2Bu, 0x80u},\r
+                       {0x30u, 0x04u},\r
+                       {0x32u, 0x08u},\r
                        {0x33u, 0x0Fu},\r
-                       {0x34u, 0xF0u},\r
+                       {0x34u, 0x03u},\r
                        {0x35u, 0xF0u},\r
-                       {0x56u, 0x08u},\r
+                       {0x36u, 0x30u},\r
+                       {0x3Au, 0x20u},\r
+                       {0x3Eu, 0x40u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x11u},\r
-                       {0x5Du, 0x90u},\r
+                       {0x5Cu, 0x19u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x82u, 0x20u},\r
-                       {0x84u, 0x02u},\r
-                       {0x85u, 0x08u},\r
-                       {0x86u, 0x0Du},\r
-                       {0x88u, 0x02u},\r
-                       {0x8Au, 0x04u},\r
-                       {0x8Bu, 0x19u},\r
-                       {0x8Cu, 0x0Du},\r
-                       {0x8Du, 0x33u},\r
-                       {0x8Fu, 0x4Cu},\r
-                       {0x90u, 0x10u},\r
-                       {0x91u, 0x18u},\r
-                       {0x92u, 0x20u},\r
-                       {0x93u, 0x60u},\r
-                       {0x94u, 0x0Du},\r
-                       {0x99u, 0x2Au},\r
-                       {0x9Au, 0x10u},\r
-                       {0x9Bu, 0x55u},\r
-                       {0x9Cu, 0x0Du},\r
-                       {0x9Du, 0x01u},\r
-                       {0x9Fu, 0x06u},\r
-                       {0xA0u, 0x02u},\r
-                       {0xA2u, 0x08u},\r
-                       {0xA3u, 0x10u},\r
-                       {0xA4u, 0x0Du},\r
-                       {0xA5u, 0x3Au},\r
-                       {0xA7u, 0x45u},\r
-                       {0xA8u, 0x01u},\r
-                       {0xAAu, 0x02u},\r
-                       {0xABu, 0x01u},\r
-                       {0xACu, 0x0Du},\r
-                       {0xB1u, 0x07u},\r
-                       {0xB2u, 0x0Fu},\r
-                       {0xB6u, 0x30u},\r
-                       {0xB7u, 0x78u},\r
-                       {0xBAu, 0x08u},\r
-                       {0xBBu, 0x82u},\r
-                       {0xBEu, 0x40u},\r
+                       {0x81u, 0x02u},\r
+                       {0x83u, 0x01u},\r
+                       {0x87u, 0x04u},\r
+                       {0x8Du, 0x02u},\r
+                       {0x8Fu, 0x01u},\r
+                       {0x91u, 0x01u},\r
+                       {0x92u, 0x02u},\r
+                       {0x93u, 0x02u},\r
+                       {0x9Au, 0x04u},\r
+                       {0x9Cu, 0x04u},\r
+                       {0x9Du, 0x02u},\r
+                       {0x9Eu, 0x08u},\r
+                       {0x9Fu, 0x01u},\r
+                       {0xA2u, 0x01u},\r
+                       {0xA5u, 0x02u},\r
+                       {0xA7u, 0x11u},\r
+                       {0xAAu, 0x08u},\r
+                       {0xAFu, 0x08u},\r
+                       {0xB0u, 0x01u},\r
+                       {0xB1u, 0x10u},\r
+                       {0xB2u, 0x0Cu},\r
+                       {0xB3u, 0x04u},\r
+                       {0xB4u, 0x02u},\r
+                       {0xB5u, 0x08u},\r
+                       {0xB7u, 0x03u},\r
+                       {0xBBu, 0x80u},\r
+                       {0xBEu, 0x04u},\r
+                       {0xD6u, 0x08u},\r
+                       {0xD8u, 0x04u},\r
+                       {0xD9u, 0x04u},\r
+                       {0xDBu, 0x04u},\r
+                       {0xDCu, 0x99u},\r
+                       {0xDDu, 0x90u},\r
+                       {0xDFu, 0x01u},\r
+                       {0x00u, 0x04u},\r
+                       {0x01u, 0x01u},\r
+                       {0x03u, 0x02u},\r
+                       {0x08u, 0x10u},\r
+                       {0x0Au, 0x22u},\r
+                       {0x0Bu, 0x01u},\r
+                       {0x0Du, 0x10u},\r
+                       {0x0Eu, 0x80u},\r
+                       {0x0Fu, 0x01u},\r
+                       {0x11u, 0x24u},\r
+                       {0x16u, 0x88u},\r
+                       {0x18u, 0x04u},\r
+                       {0x19u, 0x10u},\r
+                       {0x1Au, 0x21u},\r
+                       {0x1Bu, 0x12u},\r
+                       {0x1Cu, 0x20u},\r
+                       {0x1Eu, 0x80u},\r
+                       {0x1Fu, 0x10u},\r
+                       {0x20u, 0x08u},\r
+                       {0x21u, 0x14u},\r
+                       {0x22u, 0x08u},\r
+                       {0x24u, 0x02u},\r
+                       {0x25u, 0x91u},\r
+                       {0x27u, 0x12u},\r
+                       {0x2Bu, 0x08u},\r
+                       {0x2Fu, 0x12u},\r
+                       {0x30u, 0x80u},\r
+                       {0x31u, 0x04u},\r
+                       {0x36u, 0x40u},\r
+                       {0x37u, 0x02u},\r
+                       {0x38u, 0x80u},\r
+                       {0x39u, 0x28u},\r
+                       {0x3Bu, 0x02u},\r
+                       {0x3Du, 0x02u},\r
+                       {0x3Eu, 0x80u},\r
+                       {0x3Fu, 0x04u},\r
+                       {0x58u, 0x40u},\r
+                       {0x5Au, 0x18u},\r
+                       {0x5Bu, 0x02u},\r
+                       {0x5Cu, 0x80u},\r
+                       {0x5Du, 0x20u},\r
+                       {0x62u, 0x80u},\r
+                       {0x66u, 0xA0u},\r
+                       {0x67u, 0x04u},\r
+                       {0x80u, 0x80u},\r
+                       {0x81u, 0x90u},\r
+                       {0x82u, 0x80u},\r
+                       {0x84u, 0x10u},\r
+                       {0x88u, 0x10u},\r
+                       {0x89u, 0x20u},\r
+                       {0x8Au, 0x02u},\r
+                       {0x8Du, 0x40u},\r
+                       {0xC0u, 0x0Du},\r
+                       {0xC2u, 0xD7u},\r
+                       {0xC4u, 0x56u},\r
+                       {0xCAu, 0x54u},\r
+                       {0xCCu, 0x9Au},\r
+                       {0xCEu, 0xDFu},\r
+                       {0xD6u, 0x3Fu},\r
+                       {0xD8u, 0x38u},\r
+                       {0xE2u, 0x04u},\r
+                       {0xE4u, 0x05u},\r
+                       {0xE6u, 0xA2u},\r
+                       {0x01u, 0x02u},\r
+                       {0x02u, 0x10u},\r
+                       {0x03u, 0x01u},\r
+                       {0x04u, 0x05u},\r
+                       {0x05u, 0x02u},\r
+                       {0x06u, 0x02u},\r
+                       {0x07u, 0x05u},\r
+                       {0x0Du, 0x02u},\r
+                       {0x0Fu, 0x09u},\r
+                       {0x10u, 0x04u},\r
+                       {0x11u, 0x01u},\r
+                       {0x12u, 0x03u},\r
+                       {0x13u, 0x02u},\r
+                       {0x14u, 0x01u},\r
+                       {0x16u, 0x06u},\r
+                       {0x19u, 0x02u},\r
+                       {0x1Bu, 0x11u},\r
+                       {0x1Eu, 0x08u},\r
+                       {0x28u, 0x03u},\r
+                       {0x2Au, 0x04u},\r
+                       {0x2Cu, 0x08u},\r
+                       {0x2Eu, 0x10u},\r
+                       {0x30u, 0x07u},\r
+                       {0x31u, 0x04u},\r
+                       {0x33u, 0x10u},\r
+                       {0x34u, 0x18u},\r
+                       {0x35u, 0x08u},\r
+                       {0x36u, 0x07u},\r
+                       {0x37u, 0x03u},\r
+                       {0x3Au, 0x82u},\r
+                       {0x3Bu, 0x80u},\r
+                       {0x3Eu, 0x10u},\r
+                       {0x58u, 0x04u},\r
+                       {0x59u, 0x04u},\r
+                       {0x5Bu, 0x04u},\r
+                       {0x5Cu, 0x90u},\r
+                       {0x5Fu, 0x01u},\r
+                       {0x80u, 0x05u},\r
+                       {0x82u, 0x0Au},\r
+                       {0x83u, 0xFFu},\r
+                       {0x84u, 0x06u},\r
+                       {0x86u, 0x09u},\r
+                       {0x89u, 0x55u},\r
+                       {0x8Bu, 0xAAu},\r
+                       {0x90u, 0x0Fu},\r
+                       {0x92u, 0xF0u},\r
+                       {0x97u, 0xFFu},\r
+                       {0x98u, 0x60u},\r
+                       {0x99u, 0x0Fu},\r
+                       {0x9Au, 0x90u},\r
+                       {0x9Bu, 0xF0u},\r
+                       {0x9Cu, 0x03u},\r
+                       {0x9Du, 0xFFu},\r
+                       {0x9Eu, 0x0Cu},\r
+                       {0xA1u, 0x69u},\r
+                       {0xA3u, 0x96u},\r
+                       {0xA7u, 0xFFu},\r
+                       {0xA8u, 0x50u},\r
+                       {0xA9u, 0xFFu},\r
+                       {0xAAu, 0xA0u},\r
+                       {0xACu, 0x30u},\r
+                       {0xADu, 0x33u},\r
+                       {0xAEu, 0xC0u},\r
+                       {0xAFu, 0xCCu},\r
+                       {0xB2u, 0xFFu},\r
+                       {0xB5u, 0xFFu},\r
+                       {0xBBu, 0x20u},\r
+                       {0xBEu, 0x04u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
                        {0xDCu, 0x10u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x48u},\r
-                       {0x05u, 0x56u},\r
-                       {0x09u, 0x0Au},\r
-                       {0x0Au, 0x04u},\r
-                       {0x0Du, 0x20u},\r
-                       {0x0Eu, 0x11u},\r
-                       {0x0Fu, 0x40u},\r
-                       {0x11u, 0x50u},\r
-                       {0x15u, 0x24u},\r
-                       {0x16u, 0x02u},\r
-                       {0x17u, 0x01u},\r
-                       {0x18u, 0x40u},\r
-                       {0x1Au, 0x0Cu},\r
-                       {0x1Bu, 0x01u},\r
-                       {0x1Cu, 0x02u},\r
-                       {0x1Du, 0x04u},\r
-                       {0x21u, 0x24u},\r
-                       {0x27u, 0x42u},\r
-                       {0x2Au, 0x08u},\r
-                       {0x2Fu, 0x54u},\r
-                       {0x31u, 0x2Au},\r
-                       {0x36u, 0x10u},\r
-                       {0x37u, 0x42u},\r
+                       {0x00u, 0x08u},\r
+                       {0x03u, 0x80u},\r
+                       {0x04u, 0x04u},\r
+                       {0x06u, 0x80u},\r
+                       {0x08u, 0x01u},\r
+                       {0x0Au, 0x01u},\r
+                       {0x0Bu, 0x04u},\r
+                       {0x0Eu, 0xA1u},\r
+                       {0x0Fu, 0x02u},\r
+                       {0x10u, 0x40u},\r
+                       {0x13u, 0x52u},\r
+                       {0x14u, 0x01u},\r
+                       {0x17u, 0x20u},\r
+                       {0x18u, 0x10u},\r
+                       {0x1Eu, 0x80u},\r
+                       {0x1Fu, 0x60u},\r
+                       {0x21u, 0x20u},\r
+                       {0x25u, 0x05u},\r
+                       {0x26u, 0x20u},\r
+                       {0x27u, 0x02u},\r
+                       {0x29u, 0x90u},\r
+                       {0x2Au, 0x06u},\r
+                       {0x30u, 0x81u},\r
+                       {0x31u, 0x24u},\r
+                       {0x32u, 0x01u},\r
+                       {0x36u, 0x20u},\r
+                       {0x37u, 0x02u},\r
                        {0x38u, 0x02u},\r
-                       {0x39u, 0x18u},\r
-                       {0x3Bu, 0x24u},\r
-                       {0x3Du, 0x08u},\r
-                       {0x3Eu, 0x40u},\r
-                       {0x3Fu, 0x20u},\r
-                       {0x59u, 0x80u},\r
-                       {0x5Bu, 0x20u},\r
-                       {0x60u, 0x04u},\r
+                       {0x39u, 0x20u},\r
+                       {0x3Cu, 0x40u},\r
+                       {0x3Du, 0x0Au},\r
+                       {0x44u, 0x10u},\r
+                       {0x45u, 0x08u},\r
+                       {0x58u, 0x10u},\r
+                       {0x59u, 0x01u},\r
+                       {0x5Au, 0x40u},\r
+                       {0x5Bu, 0x08u},\r
                        {0x62u, 0x80u},\r
-                       {0x63u, 0x08u},\r
-                       {0x6Cu, 0x02u},\r
-                       {0x6Du, 0x08u},\r
-                       {0x6Fu, 0x18u},\r
-                       {0x83u, 0x18u},\r
-                       {0x84u, 0x50u},\r
-                       {0x88u, 0x01u},\r
-                       {0x89u, 0x04u},\r
-                       {0x8Au, 0x04u},\r
-                       {0x8Bu, 0x02u},\r
-                       {0x8Fu, 0x04u},\r
-                       {0xC0u, 0xF5u},\r
-                       {0xC2u, 0xFEu},\r
-                       {0xC4u, 0xF3u},\r
-                       {0xCAu, 0xE2u},\r
-                       {0xCCu, 0xB7u},\r
-                       {0xCEu, 0x77u},\r
-                       {0xD6u, 0x0Cu},\r
-                       {0xD8u, 0x0Cu},\r
+                       {0x69u, 0x55u},\r
+                       {0x6Cu, 0x10u},\r
+                       {0x6Du, 0xA0u},\r
+                       {0x71u, 0x80u},\r
+                       {0x72u, 0x88u},\r
+                       {0x73u, 0x54u},\r
+                       {0x80u, 0x10u},\r
+                       {0x81u, 0x10u},\r
+                       {0x85u, 0x80u},\r
+                       {0x89u, 0x40u},\r
+                       {0x8Bu, 0x10u},\r
+                       {0x8Cu, 0xC0u},\r
+                       {0x8Fu, 0x0Au},\r
+                       {0x90u, 0x02u},\r
+                       {0x92u, 0x40u},\r
+                       {0x94u, 0x80u},\r
+                       {0x95u, 0x44u},\r
+                       {0x96u, 0x1Au},\r
+                       {0x97u, 0x02u},\r
+                       {0x99u, 0x10u},\r
+                       {0x9Au, 0x22u},\r
+                       {0x9Bu, 0x10u},\r
+                       {0x9Cu, 0x40u},\r
+                       {0x9Du, 0x04u},\r
+                       {0x9Eu, 0x08u},\r
+                       {0xA0u, 0x04u},\r
+                       {0xA2u, 0x08u},\r
+                       {0xA3u, 0x10u},\r
+                       {0xA7u, 0x08u},\r
+                       {0xACu, 0x80u},\r
+                       {0xAEu, 0x01u},\r
+                       {0xB1u, 0x01u},\r
+                       {0xB6u, 0x40u},\r
+                       {0xC0u, 0x3Cu},\r
+                       {0xC2u, 0xBBu},\r
+                       {0xC4u, 0xC3u},\r
+                       {0xCAu, 0x0Fu},\r
+                       {0xCCu, 0xAEu},\r
+                       {0xCEu, 0xD5u},\r
+                       {0xD6u, 0x0Fu},\r
+                       {0xD8u, 0x08u},\r
                        {0xE0u, 0x04u},\r
-                       {0xE2u, 0xA0u},\r
-                       {0xE6u, 0x02u},\r
-                       {0x01u, 0x60u},\r
-                       {0x04u, 0x06u},\r
-                       {0x06u, 0x01u},\r
-                       {0x08u, 0x04u},\r
-                       {0x09u, 0x04u},\r
-                       {0x0Bu, 0x03u},\r
-                       {0x10u, 0x1Fu},\r
-                       {0x11u, 0x2Du},\r
-                       {0x13u, 0x12u},\r
-                       {0x16u, 0x1Eu},\r
-                       {0x18u, 0x01u},\r
-                       {0x19u, 0x1Bu},\r
-                       {0x1Au, 0x18u},\r
-                       {0x1Bu, 0x44u},\r
-                       {0x24u, 0x07u},\r
-                       {0x26u, 0x08u},\r
-                       {0x29u, 0x19u},\r
-                       {0x2Au, 0x02u},\r
-                       {0x2Bu, 0x26u},\r
-                       {0x2Cu, 0x17u},\r
-                       {0x30u, 0x1Eu},\r
-                       {0x31u, 0x70u},\r
-                       {0x33u, 0x07u},\r
-                       {0x34u, 0x01u},\r
-                       {0x35u, 0x08u},\r
-                       {0x39u, 0x02u},\r
-                       {0x3Bu, 0x08u},\r
-                       {0x3Eu, 0x10u},\r
-                       {0x3Fu, 0x10u},\r
+                       {0xE2u, 0x08u},\r
+                       {0xE6u, 0x28u},\r
+                       {0xE8u, 0x08u},\r
+                       {0xEEu, 0x42u},\r
+                       {0x04u, 0x30u},\r
+                       {0x06u, 0xC0u},\r
+                       {0x07u, 0x80u},\r
+                       {0x08u, 0xFFu},\r
+                       {0x09u, 0x0Fu},\r
+                       {0x0Cu, 0x05u},\r
+                       {0x0Du, 0xC0u},\r
+                       {0x0Eu, 0x0Au},\r
+                       {0x0Fu, 0x1Fu},\r
+                       {0x10u, 0x03u},\r
+                       {0x12u, 0x0Cu},\r
+                       {0x13u, 0x70u},\r
+                       {0x15u, 0x90u},\r
+                       {0x16u, 0xFFu},\r
+                       {0x17u, 0x2Fu},\r
+                       {0x18u, 0xFFu},\r
+                       {0x19u, 0x05u},\r
+                       {0x1Bu, 0x0Au},\r
+                       {0x1Cu, 0x0Fu},\r
+                       {0x1Eu, 0xF0u},\r
+                       {0x20u, 0x09u},\r
+                       {0x21u, 0x03u},\r
+                       {0x22u, 0x06u},\r
+                       {0x23u, 0x0Cu},\r
+                       {0x27u, 0x80u},\r
+                       {0x28u, 0x50u},\r
+                       {0x29u, 0x06u},\r
+                       {0x2Au, 0xA0u},\r
+                       {0x2Bu, 0x09u},\r
+                       {0x2Cu, 0x90u},\r
+                       {0x2Du, 0xA0u},\r
+                       {0x2Eu, 0x60u},\r
+                       {0x2Fu, 0x4Fu},\r
+                       {0x31u, 0x7Fu},\r
+                       {0x36u, 0xFFu},\r
+                       {0x37u, 0x80u},\r
+                       {0x3Eu, 0x40u},\r
+                       {0x3Fu, 0x40u},\r
                        {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x01u},\r
+                       {0x5Cu, 0x10u},\r
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x40u},\r
-                       {0x81u, 0x02u},\r
-                       {0x85u, 0x01u},\r
-                       {0x8Au, 0x07u},\r
-                       {0x8Du, 0x04u},\r
-                       {0x8Eu, 0x20u},\r
-                       {0x8Fu, 0x08u},\r
-                       {0x90u, 0x0Au},\r
-                       {0x92u, 0x05u},\r
-                       {0x94u, 0x09u},\r
+                       {0x82u, 0x70u},\r
+                       {0x84u, 0x02u},\r
+                       {0x85u, 0xC8u},\r
+                       {0x86u, 0x05u},\r
+                       {0x87u, 0x03u},\r
+                       {0x88u, 0x40u},\r
+                       {0x8Cu, 0x70u},\r
+                       {0x8Fu, 0x0Cu},\r
+                       {0x93u, 0x01u},\r
+                       {0x94u, 0x01u},\r
                        {0x96u, 0x02u},\r
-                       {0x97u, 0x04u},\r
-                       {0x98u, 0x04u},\r
-                       {0x99u, 0x02u},\r
-                       {0x9Au, 0x08u},\r
-                       {0xA1u, 0x02u},\r
-                       {0xA2u, 0x08u},\r
-                       {0xA6u, 0x10u},\r
-                       {0xABu, 0x08u},\r
+                       {0x97u, 0x20u},\r
+                       {0x98u, 0x02u},\r
+                       {0x99u, 0x04u},\r
+                       {0x9Au, 0x09u},\r
+                       {0x9Bu, 0xA3u},\r
+                       {0x9Cu, 0x02u},\r
+                       {0x9Eu, 0x01u},\r
+                       {0xA4u, 0x02u},\r
+                       {0xA6u, 0x01u},\r
+                       {0xA9u, 0x01u},\r
+                       {0xAAu, 0x20u},\r
+                       {0xABu, 0x62u},\r
                        {0xACu, 0x10u},\r
-                       {0xADu, 0x02u},\r
-                       {0xAEu, 0x20u},\r
-                       {0xB0u, 0x30u},\r
-                       {0xB1u, 0x02u},\r
-                       {0xB2u, 0x0Fu},\r
-                       {0xB3u, 0x01u},\r
-                       {0xB4u, 0x40u},\r
-                       {0xB7u, 0x0Cu},\r
-                       {0xB9u, 0x02u},\r
-                       {0xBEu, 0x11u},\r
-                       {0xBFu, 0x45u},\r
-                       {0xD6u, 0x08u},\r
+                       {0xAFu, 0x12u},\r
+                       {0xB0u, 0x70u},\r
+                       {0xB1u, 0x10u},\r
+                       {0xB2u, 0x03u},\r
+                       {0xB4u, 0x04u},\r
+                       {0xB5u, 0xE0u},\r
+                       {0xB6u, 0x08u},\r
+                       {0xB7u, 0x0Fu},\r
+                       {0xBAu, 0x08u},\r
+                       {0xBEu, 0x01u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
-                       {0xDBu, 0x04u},\r
-                       {0xDCu, 0x01u},\r
-                       {0xDDu, 0x90u},\r
+                       {0xDCu, 0x09u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x20u},\r
-                       {0x02u, 0x82u},\r
-                       {0x03u, 0x08u},\r
-                       {0x04u, 0x20u},\r
-                       {0x05u, 0x08u},\r
-                       {0x09u, 0x0Au},\r
-                       {0x0Au, 0x04u},\r
-                       {0x0Eu, 0x44u},\r
-                       {0x0Fu, 0x20u},\r
-                       {0x11u, 0x01u},\r
-                       {0x13u, 0x44u},\r
-                       {0x14u, 0x21u},\r
-                       {0x17u, 0x10u},\r
-                       {0x19u, 0x20u},\r
-                       {0x1Au, 0x80u},\r
-                       {0x1Bu, 0x08u},\r
-                       {0x1Du, 0x02u},\r
-                       {0x1Eu, 0x40u},\r
-                       {0x1Fu, 0x20u},\r
-                       {0x20u, 0x12u},\r
-                       {0x22u, 0x01u},\r
-                       {0x24u, 0x80u},\r
-                       {0x25u, 0x01u},\r
-                       {0x27u, 0x28u},\r
-                       {0x28u, 0x04u},\r
-                       {0x29u, 0x01u},\r
-                       {0x2Bu, 0x02u},\r
-                       {0x2Eu, 0x20u},\r
-                       {0x32u, 0x28u},\r
-                       {0x35u, 0x10u},\r
-                       {0x37u, 0x01u},\r
-                       {0x38u, 0x04u},\r
-                       {0x39u, 0x22u},\r
-                       {0x3Au, 0x20u},\r
-                       {0x3Bu, 0x40u},\r
-                       {0x3Du, 0x02u},\r
-                       {0x3Fu, 0x10u},\r
-                       {0x45u, 0x40u},\r
-                       {0x46u, 0x02u},\r
-                       {0x58u, 0x98u},\r
-                       {0x5Cu, 0x40u},\r
-                       {0x5Fu, 0x30u},\r
-                       {0x60u, 0x02u},\r
-                       {0x62u, 0x14u},\r
-                       {0x66u, 0x80u},\r
-                       {0x80u, 0x02u},\r
-                       {0x81u, 0x02u},\r
-                       {0x82u, 0x40u},\r
-                       {0x84u, 0x01u},\r
-                       {0x85u, 0x80u},\r
-                       {0x88u, 0x04u},\r
-                       {0x8Au, 0x01u},\r
-                       {0x8Bu, 0x20u},\r
-                       {0x8Cu, 0x0Au},\r
-                       {0x90u, 0x04u},\r
-                       {0x92u, 0x08u},\r
-                       {0x93u, 0x04u},\r
-                       {0x94u, 0x02u},\r
-                       {0x95u, 0x64u},\r
-                       {0x96u, 0x51u},\r
-                       {0x97u, 0xE8u},\r
-                       {0x98u, 0x10u},\r
-                       {0x99u, 0x01u},\r
-                       {0x9Bu, 0x50u},\r
-                       {0x9Cu, 0x40u},\r
-                       {0x9Du, 0xD2u},\r
-                       {0x9Eu, 0x0Au},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA0u, 0x02u},\r
-                       {0xA1u, 0x04u},\r
-                       {0xA2u, 0x80u},\r
-                       {0xA3u, 0x11u},\r
-                       {0xA4u, 0x04u},\r
-                       {0xA5u, 0x0Au},\r
-                       {0xA6u, 0x10u},\r
-                       {0xABu, 0x10u},\r
+                       {0x00u, 0x90u},\r
+                       {0x01u, 0x04u},\r
+                       {0x05u, 0x80u},\r
+                       {0x06u, 0x88u},\r
+                       {0x07u, 0x10u},\r
+                       {0x09u, 0x01u},\r
+                       {0x0Au, 0x06u},\r
+                       {0x0Bu, 0x20u},\r
+                       {0x0Eu, 0x1Au},\r
+                       {0x11u, 0x50u},\r
+                       {0x12u, 0x40u},\r
+                       {0x16u, 0x22u},\r
+                       {0x17u, 0x20u},\r
+                       {0x1Bu, 0x40u},\r
+                       {0x1Du, 0x01u},\r
+                       {0x1Eu, 0x1Au},\r
+                       {0x21u, 0x02u},\r
+                       {0x22u, 0x80u},\r
+                       {0x23u, 0x80u},\r
+                       {0x25u, 0x40u},\r
+                       {0x26u, 0x02u},\r
+                       {0x27u, 0x08u},\r
+                       {0x28u, 0x88u},\r
+                       {0x2Bu, 0x12u},\r
+                       {0x2Cu, 0x02u},\r
+                       {0x2Fu, 0x04u},\r
+                       {0x31u, 0x26u},\r
+                       {0x36u, 0x02u},\r
+                       {0x37u, 0x28u},\r
+                       {0x38u, 0xA0u},\r
+                       {0x39u, 0x08u},\r
+                       {0x3Bu, 0x20u},\r
+                       {0x3Cu, 0x04u},\r
+                       {0x3Du, 0x80u},\r
+                       {0x3Eu, 0x88u},\r
+                       {0x58u, 0x40u},\r
+                       {0x63u, 0x01u},\r
+                       {0x87u, 0x01u},\r
+                       {0x88u, 0x80u},\r
+                       {0x89u, 0x10u},\r
+                       {0x8Au, 0x02u},\r
+                       {0x8Bu, 0x04u},\r
+                       {0x8Fu, 0x08u},\r
+                       {0x90u, 0xB2u},\r
+                       {0x91u, 0x5Du},\r
+                       {0x93u, 0x80u},\r
+                       {0x94u, 0x04u},\r
+                       {0x95u, 0x20u},\r
+                       {0x96u, 0x1Au},\r
+                       {0x99u, 0x04u},\r
+                       {0x9Au, 0x20u},\r
+                       {0x9Bu, 0x10u},\r
+                       {0x9Fu, 0x20u},\r
+                       {0xA1u, 0xA0u},\r
+                       {0xA2u, 0x08u},\r
+                       {0xA3u, 0x12u},\r
+                       {0xA6u, 0x90u},\r
+                       {0xA7u, 0x01u},\r
+                       {0xA9u, 0x05u},\r
+                       {0xABu, 0x01u},\r
+                       {0xADu, 0x08u},\r
                        {0xAFu, 0x20u},\r
-                       {0xB1u, 0x20u},\r
+                       {0xB1u, 0x04u},\r
+                       {0xB3u, 0x08u},\r
                        {0xB4u, 0x40u},\r
-                       {0xB5u, 0x01u},\r
-                       {0xC0u, 0x6Bu},\r
-                       {0xC2u, 0x7Eu},\r
-                       {0xC4u, 0xEDu},\r
-                       {0xCAu, 0x2Du},\r
-                       {0xCCu, 0xA6u},\r
-                       {0xCEu, 0xABu},\r
-                       {0xD6u, 0x1Eu},\r
-                       {0xD8u, 0x1Eu},\r
-                       {0xE0u, 0x01u},\r
-                       {0xE2u, 0x28u},\r
-                       {0xEAu, 0x02u},\r
-                       {0xEEu, 0x01u},\r
-                       {0x00u, 0x02u},\r
+                       {0xB6u, 0x04u},\r
+                       {0xB7u, 0x80u},\r
+                       {0xC0u, 0xF7u},\r
+                       {0xC2u, 0xEFu},\r
+                       {0xC4u, 0xEBu},\r
+                       {0xCAu, 0x3Fu},\r
+                       {0xCCu, 0xE7u},\r
+                       {0xCEu, 0x5Eu},\r
+                       {0xD6u, 0x08u},\r
+                       {0xD8u, 0x08u},\r
+                       {0xE2u, 0x18u},\r
+                       {0xE6u, 0x48u},\r
+                       {0xEAu, 0x06u},\r
+                       {0xEEu, 0x05u},\r
+                       {0x01u, 0x0Du},\r
+                       {0x04u, 0x7Fu},\r
+                       {0x05u, 0x02u},\r
+                       {0x06u, 0x80u},\r
+                       {0x07u, 0x08u},\r
                        {0x09u, 0x01u},\r
-                       {0x14u, 0x01u},\r
-                       {0x28u, 0x04u},\r
-                       {0x2Du, 0x02u},\r
-                       {0x30u, 0x02u},\r
-                       {0x31u, 0x01u},\r
-                       {0x34u, 0x04u},\r
-                       {0x36u, 0x01u},\r
-                       {0x37u, 0x02u},\r
-                       {0x3Eu, 0x51u},\r
-                       {0x3Fu, 0x41u},\r
-                       {0x40u, 0x24u},\r
-                       {0x41u, 0x03u},\r
-                       {0x42u, 0x10u},\r
-                       {0x45u, 0xFCu},\r
-                       {0x46u, 0xD2u},\r
-                       {0x47u, 0x0Eu},\r
-                       {0x48u, 0x1Fu},\r
-                       {0x49u, 0xFFu},\r
-                       {0x4Au, 0xFFu},\r
-                       {0x4Bu, 0xFFu},\r
-                       {0x4Fu, 0x2Cu},\r
-                       {0x56u, 0x01u},\r
+                       {0x0Au, 0xFFu},\r
+                       {0x0Bu, 0x02u},\r
+                       {0x0Du, 0x02u},\r
+                       {0x0Eu, 0x9Fu},\r
+                       {0x0Fu, 0x0Du},\r
+                       {0x10u, 0x80u},\r
+                       {0x11u, 0x0Du},\r
+                       {0x14u, 0xC0u},\r
+                       {0x15u, 0x10u},\r
+                       {0x16u, 0x08u},\r
+                       {0x18u, 0xC0u},\r
+                       {0x19u, 0x02u},\r
+                       {0x1Au, 0x04u},\r
+                       {0x1Bu, 0x04u},\r
+                       {0x1Cu, 0xC0u},\r
+                       {0x1Du, 0x10u},\r
+                       {0x1Eu, 0x02u},\r
+                       {0x20u, 0x90u},\r
+                       {0x21u, 0x0Du},\r
+                       {0x22u, 0x40u},\r
+                       {0x25u, 0x0Du},\r
+                       {0x26u, 0x60u},\r
+                       {0x28u, 0x1Fu},\r
+                       {0x29u, 0x0Du},\r
+                       {0x2Au, 0x20u},\r
+                       {0x2Cu, 0xC0u},\r
+                       {0x2Eu, 0x01u},\r
+                       {0x35u, 0x10u},\r
+                       {0x36u, 0xFFu},\r
+                       {0x37u, 0x0Fu},\r
+                       {0x39u, 0x20u},\r
+                       {0x3Bu, 0x80u},\r
+                       {0x3Eu, 0x40u},\r
+                       {0x54u, 0x09u},\r
+                       {0x56u, 0x04u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
-                       {0x5Au, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Du, 0x01u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x62u, 0xC0u},\r
-                       {0x66u, 0x80u},\r
-                       {0x68u, 0x40u},\r
-                       {0x69u, 0x40u},\r
-                       {0x6Eu, 0x08u},\r
-                       {0x84u, 0x0Bu},\r
-                       {0x86u, 0x14u},\r
-                       {0x8Du, 0x01u},\r
-                       {0x90u, 0x34u},\r
-                       {0x92u, 0x0Bu},\r
-                       {0x96u, 0x3Fu},\r
-                       {0x98u, 0x08u},\r
-                       {0x9Au, 0x22u},\r
-                       {0x9Eu, 0x10u},\r
-                       {0xA8u, 0x01u},\r
-                       {0xAFu, 0x02u},\r
-                       {0xB2u, 0x07u},\r
-                       {0xB3u, 0x02u},\r
-                       {0xB4u, 0x38u},\r
-                       {0xB5u, 0x01u},\r
-                       {0xBFu, 0x10u},\r
-                       {0xD4u, 0x09u},\r
-                       {0xD6u, 0x04u},\r
+                       {0x80u, 0x20u},\r
+                       {0x81u, 0x02u},\r
+                       {0x82u, 0x90u},\r
+                       {0x83u, 0x11u},\r
+                       {0x88u, 0x4Du},\r
+                       {0x8Au, 0xB2u},\r
+                       {0x8Du, 0x02u},\r
+                       {0x8Fu, 0x01u},\r
+                       {0x94u, 0x08u},\r
+                       {0x95u, 0x01u},\r
+                       {0x96u, 0x44u},\r
+                       {0x97u, 0x02u},\r
+                       {0x99u, 0x02u},\r
+                       {0x9Bu, 0x09u},\r
+                       {0x9Cu, 0x10u},\r
+                       {0x9Du, 0x02u},\r
+                       {0x9Eu, 0x22u},\r
+                       {0x9Fu, 0x05u},\r
+                       {0xA8u, 0x04u},\r
+                       {0xAAu, 0x09u},\r
+                       {0xB0u, 0xC0u},\r
+                       {0xB1u, 0x04u},\r
+                       {0xB2u, 0x03u},\r
+                       {0xB3u, 0x03u},\r
+                       {0xB4u, 0x3Cu},\r
+                       {0xB5u, 0x10u},\r
+                       {0xB7u, 0x08u},\r
+                       {0xBBu, 0x08u},\r
+                       {0xBEu, 0x15u},\r
+                       {0xD4u, 0x01u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x01u},\r
+                       {0xDCu, 0x90u},\r
+                       {0xDDu, 0x10u},\r
                        {0xDFu, 0x01u},\r
-                       {0x02u, 0x40u},\r
-                       {0x05u, 0x04u},\r
-                       {0x08u, 0x08u},\r
-                       {0x0Du, 0x42u},\r
-                       {0x0Eu, 0x04u},\r
-                       {0x0Fu, 0x20u},\r
-                       {0x12u, 0x04u},\r
-                       {0x17u, 0x10u},\r
-                       {0x18u, 0x04u},\r
-                       {0x19u, 0x01u},\r
-                       {0x1Bu, 0x40u},\r
-                       {0x1Du, 0x0Cu},\r
-                       {0x1Eu, 0x24u},\r
-                       {0x1Fu, 0x30u},\r
-                       {0x23u, 0x81u},\r
-                       {0x27u, 0x24u},\r
-                       {0x28u, 0x06u},\r
-                       {0x2Au, 0x10u},\r
-                       {0x2Cu, 0x02u},\r
-                       {0x3Au, 0x10u},\r
-                       {0x3Eu, 0x80u},\r
-                       {0x41u, 0x0Au},\r
-                       {0x42u, 0x04u},\r
-                       {0x43u, 0x40u},\r
-                       {0x49u, 0x08u},\r
-                       {0x4Bu, 0x02u},\r
-                       {0x50u, 0x10u},\r
-                       {0x51u, 0x40u},\r
-                       {0x52u, 0x08u},\r
-                       {0x53u, 0x40u},\r
-                       {0x59u, 0x21u},\r
-                       {0x5Bu, 0x84u},\r
+                       {0x01u, 0x01u},\r
+                       {0x03u, 0x08u},\r
+                       {0x04u, 0xA4u},\r
+                       {0x09u, 0x84u},\r
+                       {0x0Cu, 0x10u},\r
+                       {0x0Eu, 0x99u},\r
+                       {0x12u, 0x08u},\r
+                       {0x16u, 0x06u},\r
+                       {0x17u, 0x05u},\r
+                       {0x19u, 0x08u},\r
+                       {0x1Au, 0x04u},\r
+                       {0x1Bu, 0x02u},\r
+                       {0x1Du, 0x40u},\r
+                       {0x21u, 0x28u},\r
+                       {0x22u, 0x84u},\r
+                       {0x23u, 0x40u},\r
+                       {0x25u, 0x40u},\r
+                       {0x27u, 0x04u},\r
+                       {0x2Cu, 0x10u},\r
+                       {0x2Eu, 0x12u},\r
+                       {0x31u, 0x28u},\r
+                       {0x32u, 0x80u},\r
+                       {0x35u, 0x40u},\r
+                       {0x37u, 0x29u},\r
+                       {0x3Bu, 0x41u},\r
+                       {0x3Cu, 0x04u},\r
+                       {0x3Du, 0x80u},\r
+                       {0x3Eu, 0x21u},\r
+                       {0x5Bu, 0x80u},\r
                        {0x5Cu, 0x40u},\r
-                       {0x5Du, 0x10u},\r
+                       {0x5Du, 0x20u},\r
                        {0x5Eu, 0x02u},\r
                        {0x5Fu, 0x04u},\r
-                       {0x60u, 0x14u},\r
-                       {0x63u, 0x81u},\r
-                       {0x64u, 0x40u},\r
-                       {0x65u, 0x80u},\r
-                       {0x68u, 0x04u},\r
-                       {0x69u, 0x49u},\r
-                       {0x70u, 0x09u},\r
-                       {0x72u, 0x0Au},\r
-                       {0x83u, 0x01u},\r
-                       {0x86u, 0x08u},\r
-                       {0x88u, 0x20u},\r
-                       {0x8Au, 0x04u},\r
-                       {0x8Bu, 0x04u},\r
-                       {0x8Cu, 0x98u},\r
-                       {0x90u, 0x90u},\r
+                       {0x66u, 0x01u},\r
+                       {0x67u, 0x02u},\r
+                       {0x82u, 0x01u},\r
+                       {0x8Au, 0x01u},\r
+                       {0x8Bu, 0x08u},\r
+                       {0x8Du, 0x01u},\r
+                       {0x90u, 0x12u},\r
+                       {0x91u, 0x55u},\r
+                       {0x93u, 0xA1u},\r
+                       {0x94u, 0x04u},\r
+                       {0x96u, 0x0Eu},\r
+                       {0x97u, 0x08u},\r
+                       {0x99u, 0x01u},\r
+                       {0x9Bu, 0x80u},\r
+                       {0x9Cu, 0x40u},\r
+                       {0x9Du, 0x80u},\r
+                       {0x9Eu, 0x40u},\r
+                       {0x9Fu, 0x20u},\r
+                       {0xA1u, 0x84u},\r
+                       {0xA2u, 0x08u},\r
+                       {0xA3u, 0x40u},\r
+                       {0xA4u, 0x42u},\r
+                       {0xA5u, 0x01u},\r
+                       {0xA6u, 0x10u},\r
+                       {0xA9u, 0x04u},\r
+                       {0xB1u, 0x10u},\r
+                       {0xB4u, 0x08u},\r
+                       {0xC0u, 0xEAu},\r
+                       {0xC2u, 0xF5u},\r
+                       {0xC4u, 0xF2u},\r
+                       {0xCAu, 0xE0u},\r
+                       {0xCCu, 0xFEu},\r
+                       {0xCEu, 0xF9u},\r
+                       {0xD6u, 0xF8u},\r
+                       {0xD8u, 0x90u},\r
+                       {0xE2u, 0x08u},\r
+                       {0xE6u, 0x48u},\r
+                       {0xEAu, 0x04u},\r
+                       {0x91u, 0x40u},\r
                        {0x92u, 0x08u},\r
-                       {0x93u, 0x10u},\r
-                       {0x94u, 0x22u},\r
-                       {0x95u, 0x67u},\r
-                       {0x96u, 0x15u},\r
-                       {0x97u, 0xE8u},\r
-                       {0x98u, 0x02u},\r
-                       {0x99u, 0x20u},\r
-                       {0x9Au, 0x94u},\r
-                       {0x9Bu, 0x58u},\r
-                       {0x9Cu, 0x60u},\r
-                       {0x9Du, 0x58u},\r
-                       {0x9Eu, 0x08u},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA0u, 0x10u},\r
-                       {0xA1u, 0x06u},\r
-                       {0xA2u, 0x80u},\r
-                       {0xA3u, 0x11u},\r
-                       {0xA4u, 0x04u},\r
-                       {0xA5u, 0x48u},\r
-                       {0xA6u, 0x30u},\r
-                       {0xA7u, 0x02u},\r
-                       {0xA8u, 0x40u},\r
-                       {0xAAu, 0x02u},\r
-                       {0xACu, 0x01u},\r
-                       {0xADu, 0x0Au},\r
-                       {0xAEu, 0x08u},\r
-                       {0xB0u, 0x80u},\r
-                       {0xB6u, 0x04u},\r
-                       {0xC0u, 0x28u},\r
-                       {0xC2u, 0xF4u},\r
-                       {0xC4u, 0x42u},\r
-                       {0xCAu, 0x18u},\r
-                       {0xCEu, 0x14u},\r
-                       {0xD0u, 0x0Fu},\r
-                       {0xD6u, 0xFFu},\r
-                       {0xD8u, 0x9Fu},\r
-                       {0xE0u, 0x08u},\r
-                       {0xE4u, 0x04u},\r
-                       {0xEAu, 0x09u},\r
-                       {0xEEu, 0x0Cu},\r
-                       {0x08u, 0x14u},\r
-                       {0x0Au, 0x43u},\r
-                       {0x0Bu, 0xFFu},\r
-                       {0x0Cu, 0xE0u},\r
-                       {0x0Du, 0x69u},\r
-                       {0x0Fu, 0x96u},\r
-                       {0x11u, 0x0Fu},\r
-                       {0x12u, 0x02u},\r
-                       {0x13u, 0xF0u},\r
-                       {0x15u, 0x33u},\r
-                       {0x17u, 0xCCu},\r
-                       {0x18u, 0x21u},\r
-                       {0x1Au, 0x12u},\r
-                       {0x1Bu, 0xFFu},\r
-                       {0x1Du, 0x55u},\r
-                       {0x1Eu, 0xECu},\r
-                       {0x1Fu, 0xAAu},\r
-                       {0x20u, 0x88u},\r
+                       {0x93u, 0x80u},\r
+                       {0xA1u, 0x40u},\r
+                       {0xABu, 0x10u},\r
+                       {0xB1u, 0x88u},\r
+                       {0xB4u, 0x81u},\r
+                       {0xE2u, 0x08u},\r
+                       {0xE6u, 0x08u},\r
+                       {0xE8u, 0x80u},\r
+                       {0xEAu, 0x40u},\r
+                       {0x00u, 0xFFu},\r
+                       {0x01u, 0x55u},\r
+                       {0x03u, 0xAAu},\r
+                       {0x09u, 0xFFu},\r
+                       {0x0Au, 0xFFu},\r
+                       {0x0Du, 0x0Fu},\r
+                       {0x0Eu, 0xFFu},\r
+                       {0x0Fu, 0xF0u},\r
+                       {0x10u, 0x33u},\r
+                       {0x12u, 0xCCu},\r
+                       {0x13u, 0xFFu},\r
+                       {0x17u, 0xFFu},\r
+                       {0x18u, 0x55u},\r
+                       {0x19u, 0x69u},\r
+                       {0x1Au, 0xAAu},\r
+                       {0x1Bu, 0x96u},\r
+                       {0x1Cu, 0x0Fu},\r
+                       {0x1Eu, 0xF0u},\r
+                       {0x1Fu, 0xFFu},\r
                        {0x21u, 0xFFu},\r
-                       {0x22u, 0x13u},\r
-                       {0x27u, 0xFFu},\r
-                       {0x2Au, 0x01u},\r
-                       {0x2Bu, 0xFFu},\r
-                       {0x30u, 0x10u},\r
+                       {0x22u, 0xFFu},\r
+                       {0x24u, 0xFFu},\r
+                       {0x2Cu, 0x96u},\r
+                       {0x2Du, 0x33u},\r
+                       {0x2Eu, 0x69u},\r
+                       {0x2Fu, 0xCCu},\r
                        {0x31u, 0xFFu},\r
-                       {0x34u, 0xE0u},\r
-                       {0x36u, 0x0Fu},\r
+                       {0x36u, 0xFFu},\r
+                       {0x3Au, 0x80u},\r
                        {0x3Bu, 0x02u},\r
-                       {0x3Eu, 0x11u},\r
-                       {0x56u, 0x02u},\r
-                       {0x57u, 0x28u},\r
+                       {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x10u},\r
+                       {0x5Cu, 0x11u},\r
+                       {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x84u, 0x40u},\r
-                       {0x85u, 0x03u},\r
-                       {0x86u, 0x1Fu},\r
-                       {0x87u, 0x0Cu},\r
-                       {0x89u, 0x50u},\r
-                       {0x8Au, 0x70u},\r
-                       {0x8Bu, 0xA0u},\r
-                       {0x8Cu, 0x03u},\r
-                       {0x8Du, 0x0Fu},\r
-                       {0x8Eu, 0x0Cu},\r
-                       {0x8Fu, 0xF0u},\r
-                       {0x90u, 0x20u},\r
-                       {0x92u, 0x4Fu},\r
-                       {0x94u, 0x10u},\r
-                       {0x95u, 0x05u},\r
-                       {0x96u, 0x2Fu},\r
-                       {0x97u, 0x0Au},\r
-                       {0x98u, 0x05u},\r
-                       {0x9Au, 0x0Au},\r
-                       {0x9Bu, 0xFFu},\r
-                       {0x9Fu, 0xFFu},\r
-                       {0xA1u, 0x60u},\r
-                       {0xA3u, 0x90u},\r
-                       {0xA4u, 0x0Fu},\r
-                       {0xA5u, 0xFFu},\r
-                       {0xA9u, 0x30u},\r
-                       {0xABu, 0xC0u},\r
-                       {0xACu, 0x06u},\r
-                       {0xADu, 0x06u},\r
-                       {0xAEu, 0x09u},\r
-                       {0xAFu, 0x09u},\r
-                       {0xB4u, 0x7Fu},\r
-                       {0xB5u, 0xFFu},\r
-                       {0xB9u, 0x80u},\r
-                       {0xBFu, 0x50u},\r
+                       {0x82u, 0x08u},\r
+                       {0x83u, 0x80u},\r
+                       {0x85u, 0xAAu},\r
+                       {0x86u, 0x80u},\r
+                       {0x87u, 0x55u},\r
+                       {0x88u, 0x0Au},\r
+                       {0x8Au, 0x05u},\r
+                       {0x8Bu, 0x08u},\r
+                       {0x8Eu, 0x07u},\r
+                       {0x8Fu, 0x07u},\r
+                       {0x91u, 0x44u},\r
+                       {0x92u, 0x40u},\r
+                       {0x93u, 0x88u},\r
+                       {0x95u, 0x99u},\r
+                       {0x96u, 0x20u},\r
+                       {0x97u, 0x22u},\r
+                       {0x9Au, 0x10u},\r
+                       {0x9Bu, 0x70u},\r
+                       {0x9Cu, 0x04u},\r
+                       {0x9Eu, 0x08u},\r
+                       {0xA0u, 0x50u},\r
+                       {0xA2u, 0xA0u},\r
+                       {0xA4u, 0x09u},\r
+                       {0xA6u, 0x02u},\r
+                       {0xB0u, 0xC0u},\r
+                       {0xB2u, 0x30u},\r
+                       {0xB3u, 0xF0u},\r
+                       {0xB6u, 0x0Fu},\r
+                       {0xB7u, 0x0Fu},\r
+                       {0xBEu, 0x05u},\r
                        {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x01u},\r
+                       {0xDCu, 0x11u},\r
                        {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x20u},\r
                        {0x02u, 0x02u},\r
-                       {0x03u, 0x20u},\r
-                       {0x04u, 0x80u},\r
-                       {0x05u, 0x10u},\r
-                       {0x08u, 0x10u},\r
-                       {0x09u, 0x0Au},\r
-                       {0x0Bu, 0x80u},\r
-                       {0x0Cu, 0x02u},\r
-                       {0x0Du, 0x90u},\r
-                       {0x11u, 0x08u},\r
-                       {0x12u, 0x01u},\r
-                       {0x17u, 0x21u},\r
-                       {0x19u, 0x20u},\r
-                       {0x1Cu, 0x48u},\r
-                       {0x1Du, 0x80u},\r
-                       {0x21u, 0x40u},\r
-                       {0x22u, 0x20u},\r
-                       {0x26u, 0x02u},\r
-                       {0x28u, 0x40u},\r
-                       {0x29u, 0x02u},\r
-                       {0x2Au, 0x08u},\r
-                       {0x2Bu, 0x05u},\r
-                       {0x2Fu, 0x64u},\r
-                       {0x32u, 0x44u},\r
-                       {0x33u, 0x10u},\r
-                       {0x34u, 0x04u},\r
-                       {0x36u, 0x92u},\r
-                       {0x38u, 0x04u},\r
-                       {0x3Bu, 0x60u},\r
-                       {0x3Eu, 0x80u},\r
-                       {0x3Fu, 0x20u},\r
-                       {0x58u, 0xA0u},\r
-                       {0x60u, 0x08u},\r
-                       {0x62u, 0x40u},\r
-                       {0x67u, 0x10u},\r
-                       {0x6Du, 0xC4u},\r
-                       {0x6Eu, 0x15u},\r
-                       {0x75u, 0xC0u},\r
-                       {0x80u, 0x20u},\r
-                       {0x82u, 0x08u},\r
-                       {0x84u, 0x04u},\r
-                       {0x8Au, 0x40u},\r
-                       {0x8Bu, 0x40u},\r
-                       {0x8Cu, 0x08u},\r
-                       {0x8Du, 0x40u},\r
-                       {0x90u, 0x80u},\r
-                       {0x91u, 0x08u},\r
-                       {0x92u, 0x08u},\r
-                       {0x93u, 0x18u},\r
-                       {0x94u, 0x40u},\r
-                       {0x95u, 0x36u},\r
-                       {0x96u, 0x11u},\r
-                       {0x97u, 0x44u},\r
-                       {0x98u, 0x94u},\r
-                       {0x9Au, 0x83u},\r
-                       {0x9Bu, 0x30u},\r
-                       {0x9Cu, 0x08u},\r
-                       {0x9Du, 0x50u},\r
-                       {0x9Eu, 0x40u},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA0u, 0x10u},\r
-                       {0xA1u, 0x0Eu},\r
-                       {0xA2u, 0x90u},\r
-                       {0xA3u, 0x31u},\r
-                       {0xA4u, 0x02u},\r
-                       {0xA5u, 0x40u},\r
-                       {0xA6u, 0x21u},\r
-                       {0xA7u, 0x02u},\r
-                       {0xA9u, 0x08u},\r
-                       {0xAAu, 0x01u},\r
-                       {0xADu, 0x80u},\r
-                       {0xAFu, 0x08u},\r
-                       {0xB0u, 0x10u},\r
-                       {0xB5u, 0x08u},\r
-                       {0xC0u, 0xC7u},\r
-                       {0xC2u, 0xDEu},\r
-                       {0xC4u, 0x55u},\r
-                       {0xCAu, 0xEFu},\r
-                       {0xCCu, 0xFEu},\r
-                       {0xCEu, 0x3Eu},\r
-                       {0xD6u, 0x0Cu},\r
-                       {0xD8u, 0x4Cu},\r
-                       {0xE2u, 0x02u},\r
-                       {0xE6u, 0x1Du},\r
-                       {0xEAu, 0x06u},\r
-                       {0xECu, 0x04u},\r
-                       {0x81u, 0x80u},\r
-                       {0x8Bu, 0x0Au},\r
-                       {0x8Fu, 0x80u},\r
-                       {0x90u, 0x02u},\r
-                       {0x92u, 0x01u},\r
-                       {0x9Bu, 0x02u},\r
-                       {0x9Fu, 0x48u},\r
-                       {0xA0u, 0x80u},\r
-                       {0xA1u, 0x80u},\r
-                       {0xA2u, 0x04u},\r
-                       {0xA3u, 0x08u},\r
-                       {0xA4u, 0x10u},\r
-                       {0xA6u, 0x20u},\r
-                       {0xA7u, 0x80u},\r
-                       {0xA8u, 0x08u},\r
-                       {0xABu, 0x10u},\r
-                       {0xADu, 0x21u},\r
-                       {0xB3u, 0x10u},\r
-                       {0xB4u, 0x08u},\r
-                       {0xB5u, 0x02u},\r
-                       {0xE0u, 0x40u},\r
-                       {0xE2u, 0x22u},\r
-                       {0xE4u, 0x80u},\r
-                       {0xE6u, 0x0Cu},\r
-                       {0xEAu, 0x22u},\r
-                       {0xECu, 0x10u},\r
-                       {0x00u, 0x06u},\r
-                       {0x0Bu, 0x02u},\r
-                       {0x0Cu, 0x04u},\r
-                       {0x0Eu, 0x03u},\r
+                       {0x03u, 0x84u},\r
+                       {0x05u, 0x48u},\r
+                       {0x07u, 0x48u},\r
+                       {0x08u, 0x02u},\r
+                       {0x09u, 0x10u},\r
+                       {0x0Au, 0x01u},\r
+                       {0x0Du, 0x04u},\r
+                       {0x0Eu, 0x0Au},\r
+                       {0x0Fu, 0x80u},\r
+                       {0x10u, 0x01u},\r
                        {0x11u, 0x02u},\r
-                       {0x13u, 0x04u},\r
-                       {0x14u, 0x06u},\r
+                       {0x13u, 0x08u},\r
+                       {0x17u, 0x05u},\r
                        {0x18u, 0x02u},\r
-                       {0x1Au, 0x04u},\r
-                       {0x1Bu, 0x04u},\r
-                       {0x23u, 0x01u},\r
+                       {0x1Au, 0x01u},\r
+                       {0x1Du, 0x40u},\r
+                       {0x1Fu, 0x0Au},\r
+                       {0x23u, 0x40u},\r
+                       {0x25u, 0x40u},\r
+                       {0x27u, 0x10u},\r
+                       {0x2Bu, 0x81u},\r
+                       {0x31u, 0x20u},\r
+                       {0x32u, 0x42u},\r
+                       {0x33u, 0x04u},\r
+                       {0x36u, 0x03u},\r
+                       {0x37u, 0x14u},\r
+                       {0x3Au, 0x10u},\r
+                       {0x3Bu, 0x41u},\r
+                       {0x3Du, 0x89u},\r
+                       {0x3Eu, 0x10u},\r
+                       {0x3Fu, 0x80u},\r
+                       {0x59u, 0xA0u},\r
+                       {0x5Cu, 0x80u},\r
+                       {0x60u, 0x02u},\r
+                       {0x61u, 0x10u},\r
+                       {0x63u, 0x04u},\r
+                       {0x64u, 0x01u},\r
+                       {0x66u, 0x80u},\r
+                       {0x6Cu, 0x02u},\r
+                       {0x6Du, 0x40u},\r
+                       {0x6Fu, 0x01u},\r
+                       {0x85u, 0x60u},\r
+                       {0x8Bu, 0x44u},\r
+                       {0x8Fu, 0x0Au},\r
+                       {0x91u, 0x09u},\r
+                       {0x92u, 0x98u},\r
+                       {0x93u, 0x81u},\r
+                       {0x9Au, 0x10u},\r
+                       {0x9Bu, 0x4Cu},\r
+                       {0x9Du, 0x10u},\r
+                       {0x9Eu, 0x80u},\r
+                       {0xA1u, 0x35u},\r
+                       {0xA2u, 0x06u},\r
+                       {0xA3u, 0x81u},\r
+                       {0xA4u, 0x02u},\r
+                       {0xA8u, 0x04u},\r
+                       {0xAAu, 0x03u},\r
+                       {0xACu, 0x08u},\r
+                       {0xADu, 0x80u},\r
+                       {0xB0u, 0x80u},\r
+                       {0xB6u, 0x46u},\r
+                       {0xC0u, 0xFBu},\r
+                       {0xC2u, 0xFBu},\r
+                       {0xC4u, 0x3Du},\r
+                       {0xCAu, 0x09u},\r
+                       {0xCCu, 0xEFu},\r
+                       {0xCEu, 0xFDu},\r
+                       {0xD6u, 0x1Cu},\r
+                       {0xD8u, 0x1Cu},\r
+                       {0xE2u, 0x38u},\r
+                       {0xE6u, 0x22u},\r
+                       {0xEAu, 0x48u},\r
+                       {0xEEu, 0x90u},\r
+                       {0x00u, 0x01u},\r
+                       {0x03u, 0xE7u},\r
+                       {0x05u, 0x20u},\r
+                       {0x09u, 0x08u},\r
+                       {0x11u, 0x01u},\r
+                       {0x13u, 0x44u},\r
+                       {0x15u, 0x61u},\r
+                       {0x17u, 0x82u},\r
+                       {0x18u, 0x04u},\r
+                       {0x19u, 0x10u},\r
+                       {0x20u, 0x02u},\r
+                       {0x27u, 0x02u},\r
+                       {0x28u, 0x08u},\r
+                       {0x29u, 0x86u},\r
+                       {0x2Bu, 0x61u},\r
                        {0x30u, 0x01u},\r
-                       {0x31u, 0x06u},\r
-                       {0x33u, 0x01u},\r
-                       {0x34u, 0x06u},\r
-                       {0x3Au, 0x20u},\r
-                       {0x3Fu, 0x01u},\r
-                       {0x54u, 0x01u},\r
+                       {0x31u, 0x07u},\r
+                       {0x32u, 0x08u},\r
+                       {0x33u, 0x08u},\r
+                       {0x34u, 0x04u},\r
+                       {0x35u, 0xE0u},\r
+                       {0x36u, 0x02u},\r
+                       {0x37u, 0x10u},\r
+                       {0x3Eu, 0x55u},\r
+                       {0x3Fu, 0x44u},\r
+                       {0x40u, 0x53u},\r
+                       {0x41u, 0x06u},\r
+                       {0x42u, 0x40u},\r
+                       {0x45u, 0xC2u},\r
+                       {0x46u, 0x0Eu},\r
+                       {0x47u, 0xDFu},\r
+                       {0x48u, 0x37u},\r
+                       {0x49u, 0xFFu},\r
+                       {0x4Au, 0xFFu},\r
+                       {0x4Bu, 0xFFu},\r
+                       {0x4Fu, 0x2Cu},\r
+                       {0x56u, 0x01u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
+                       {0x5Au, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x11u},\r
-                       {0x5Du, 0x10u},\r
+                       {0x5Cu, 0x10u},\r
+                       {0x5Du, 0x01u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x82u, 0xFFu},\r
-                       {0x84u, 0x0Fu},\r
-                       {0x86u, 0xF0u},\r
-                       {0x87u, 0xFFu},\r
-                       {0x88u, 0x33u},\r
-                       {0x89u, 0xFFu},\r
-                       {0x8Au, 0xCCu},\r
-                       {0x92u, 0xFFu},\r
-                       {0x93u, 0xFFu},\r
-                       {0x94u, 0x55u},\r
-                       {0x95u, 0x0Fu},\r
-                       {0x96u, 0xAAu},\r
-                       {0x97u, 0xF0u},\r
-                       {0x9Au, 0xFFu},\r
-                       {0x9Cu, 0xFFu},\r
-                       {0x9Du, 0x33u},\r
-                       {0x9Fu, 0xCCu},\r
-                       {0xA1u, 0x96u},\r
-                       {0xA3u, 0x69u},\r
-                       {0xA4u, 0x69u},\r
-                       {0xA6u, 0x96u},\r
-                       {0xA7u, 0xFFu},\r
-                       {0xABu, 0xFFu},\r
-                       {0xADu, 0x55u},\r
-                       {0xAEu, 0xFFu},\r
-                       {0xAFu, 0xAAu},\r
-                       {0xB3u, 0xFFu},\r
-                       {0xB4u, 0xFFu},\r
-                       {0xBAu, 0x20u},\r
-                       {0xBBu, 0x08u},\r
-                       {0xD8u, 0x04u},\r
+                       {0x62u, 0xC0u},\r
+                       {0x66u, 0x80u},\r
+                       {0x68u, 0x40u},\r
+                       {0x69u, 0x40u},\r
+                       {0x6Eu, 0x08u},\r
+                       {0xADu, 0x01u},\r
+                       {0xB1u, 0x01u},\r
+                       {0xBFu, 0x01u},\r
+                       {0xD6u, 0x08u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x11u},\r
+                       {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x60u},\r
-                       {0x01u, 0x12u},\r
-                       {0x04u, 0x04u},\r
-                       {0x07u, 0x88u},\r
-                       {0x09u, 0x08u},\r
-                       {0x0Au, 0x08u},\r
-                       {0x0Du, 0x42u},\r
-                       {0x0Eu, 0x04u},\r
-                       {0x0Fu, 0x20u},\r
-                       {0x14u, 0x02u},\r
-                       {0x17u, 0x04u},\r
-                       {0x19u, 0x03u},\r
-                       {0x1Au, 0x0Cu},\r
-                       {0x1Cu, 0x04u},\r
-                       {0x1Fu, 0x10u},\r
-                       {0x21u, 0x08u},\r
+                       {0x06u, 0x80u},\r
+                       {0x0Du, 0x20u},\r
+                       {0x14u, 0x08u},\r
+                       {0x16u, 0x40u},\r
+                       {0x1Cu, 0x01u},\r
+                       {0x1Du, 0x01u},\r
+                       {0x1Eu, 0x04u},\r
+                       {0x1Fu, 0x04u},\r
                        {0x23u, 0x40u},\r
-                       {0x26u, 0x08u},\r
-                       {0x27u, 0x10u},\r
-                       {0x29u, 0x01u},\r
-                       {0x2Cu, 0x08u},\r
-                       {0x2Eu, 0x04u},\r
-                       {0x2Fu, 0x81u},\r
-                       {0x30u, 0x20u},\r
-                       {0x32u, 0x01u},\r
-                       {0x34u, 0x02u},\r
-                       {0x36u, 0x88u},\r
-                       {0x39u, 0x10u},\r
-                       {0x3Eu, 0x10u},\r
-                       {0x3Fu, 0x04u},\r
-                       {0x5Au, 0x02u},\r
-                       {0x5Bu, 0x42u},\r
-                       {0x5Cu, 0x28u},\r
-                       {0x5Du, 0x81u},\r
-                       {0x65u, 0x40u},\r
-                       {0x6Cu, 0x21u},\r
-                       {0x6Eu, 0x89u},\r
-                       {0x6Fu, 0x08u},\r
-                       {0x74u, 0x81u},\r
-                       {0x76u, 0x24u},\r
-                       {0x80u, 0x20u},\r
-                       {0x85u, 0x80u},\r
-                       {0x8Au, 0x04u},\r
-                       {0x8Bu, 0x84u},\r
-                       {0x8Cu, 0x01u},\r
-                       {0x8Du, 0x20u},\r
-                       {0x90u, 0x40u},\r
-                       {0x91u, 0x80u},\r
-                       {0x92u, 0x10u},\r
-                       {0x93u, 0x02u},\r
-                       {0x94u, 0x01u},\r
-                       {0x97u, 0x44u},\r
-                       {0x98u, 0x02u},\r
-                       {0x99u, 0x40u},\r
-                       {0x9Bu, 0x06u},\r
-                       {0x9Eu, 0x24u},\r
-                       {0xA1u, 0x80u},\r
-                       {0xA2u, 0x80u},\r
-                       {0xA3u, 0x10u},\r
-                       {0xA4u, 0x11u},\r
-                       {0xA5u, 0x02u},\r
-                       {0xA6u, 0x64u},\r
-                       {0xA7u, 0x08u},\r
-                       {0xAAu, 0x04u},\r
-                       {0xACu, 0x01u},\r
-                       {0xAEu, 0x03u},\r
-                       {0xB0u, 0x40u},\r
-                       {0xB7u, 0x04u},\r
-                       {0xC0u, 0x79u},\r
-                       {0xC2u, 0xF6u},\r
-                       {0xC4u, 0xA0u},\r
-                       {0xCAu, 0xF1u},\r
-                       {0xCCu, 0xD5u},\r
-                       {0xCEu, 0x64u},\r
-                       {0xD6u, 0xF8u},\r
-                       {0xD8u, 0x10u},\r
-                       {0xE2u, 0x90u},\r
-                       {0xE4u, 0x70u},\r
-                       {0xEAu, 0x20u},\r
-                       {0xECu, 0x10u},\r
-                       {0xEEu, 0x04u},\r
-                       {0x81u, 0x40u},\r
-                       {0x82u, 0x12u},\r
-                       {0x87u, 0x40u},\r
-                       {0x89u, 0x40u},\r
-                       {0x8Au, 0x20u},\r
-                       {0x8Fu, 0x10u},\r
-                       {0x90u, 0x40u},\r
-                       {0x92u, 0x01u},\r
-                       {0x93u, 0x02u},\r
-                       {0x94u, 0x01u},\r
-                       {0x97u, 0x04u},\r
-                       {0x98u, 0x02u},\r
-                       {0x9Bu, 0x02u},\r
-                       {0x9Cu, 0x40u},\r
-                       {0x9Eu, 0x26u},\r
-                       {0xA1u, 0x80u},\r
-                       {0xA2u, 0x80u},\r
-                       {0xA4u, 0x10u},\r
-                       {0xA5u, 0x02u},\r
-                       {0xA6u, 0x66u},\r
-                       {0xA7u, 0x08u},\r
-                       {0xA8u, 0x02u},\r
-                       {0xAEu, 0x04u},\r
+                       {0x24u, 0x08u},\r
+                       {0x25u, 0x88u},\r
+                       {0x26u, 0x12u},\r
+                       {0x27u, 0x04u},\r
+                       {0x2Bu, 0x01u},\r
+                       {0x2Du, 0x04u},\r
+                       {0x2Eu, 0x20u},\r
+                       {0x31u, 0xCCu},\r
+                       {0x35u, 0x10u},\r
+                       {0x36u, 0x02u},\r
+                       {0x37u, 0x04u},\r
+                       {0x3Cu, 0x04u},\r
+                       {0x3Du, 0x22u},\r
+                       {0x3Fu, 0x20u},\r
+                       {0x45u, 0x06u},\r
+                       {0x46u, 0x30u},\r
+                       {0x47u, 0x08u},\r
+                       {0x4Cu, 0x84u},\r
+                       {0x4Du, 0x04u},\r
+                       {0x4Eu, 0x82u},\r
+                       {0x54u, 0x08u},\r
+                       {0x56u, 0x01u},\r
+                       {0x57u, 0x42u},\r
+                       {0x58u, 0x20u},\r
+                       {0x59u, 0x80u},\r
+                       {0x5Cu, 0x01u},\r
+                       {0x5Du, 0x20u},\r
+                       {0x5Eu, 0x04u},\r
+                       {0x5Fu, 0x40u},\r
+                       {0x60u, 0x02u},\r
+                       {0x63u, 0x09u},\r
+                       {0x65u, 0x45u},\r
+                       {0x67u, 0x08u},\r
+                       {0x6Cu, 0x10u},\r
+                       {0x6Du, 0x41u},\r
+                       {0x6Eu, 0x10u},\r
+                       {0x75u, 0x08u},\r
+                       {0x76u, 0x0Au},\r
+                       {0x77u, 0x40u},\r
+                       {0x80u, 0x04u},\r
+                       {0x86u, 0x40u},\r
+                       {0x89u, 0x04u},\r
+                       {0x8Eu, 0x08u},\r
+                       {0x8Fu, 0x0Cu},\r
+                       {0x92u, 0x88u},\r
+                       {0x93u, 0x80u},\r
+                       {0x94u, 0x2Cu},\r
+                       {0x95u, 0x44u},\r
+                       {0x96u, 0x40u},\r
+                       {0x98u, 0x28u},\r
+                       {0x99u, 0x20u},\r
+                       {0x9Au, 0x40u},\r
+                       {0x9Bu, 0x08u},\r
+                       {0x9Cu, 0x02u},\r
+                       {0x9Du, 0x08u},\r
+                       {0xA1u, 0x23u},\r
+                       {0xA2u, 0x04u},\r
+                       {0xA3u, 0x91u},\r
+                       {0xA4u, 0x02u},\r
+                       {0xA6u, 0x92u},\r
+                       {0xA7u, 0x42u},\r
+                       {0xA9u, 0x01u},\r
+                       {0xAAu, 0x10u},\r
+                       {0xB0u, 0xA0u},\r
                        {0xB2u, 0x04u},\r
-                       {0xB3u, 0x08u},\r
-                       {0xB4u, 0x90u},\r
-                       {0xB7u, 0x04u},\r
-                       {0xE0u, 0x90u},\r
-                       {0xE2u, 0x48u},\r
-                       {0xE4u, 0x02u},\r
-                       {0xE6u, 0x80u},\r
-                       {0xE8u, 0x40u},\r
-                       {0xEAu, 0x02u},\r
-                       {0xECu, 0x88u},\r
-                       {0xEEu, 0x40u},\r
-                       {0x02u, 0x08u},\r
-                       {0x05u, 0x01u},\r
-                       {0x06u, 0x10u},\r
-                       {0x0Cu, 0x0Au},\r
-                       {0x0Du, 0x02u},\r
-                       {0x0Eu, 0x05u},\r
-                       {0x0Fu, 0x04u},\r
-                       {0x10u, 0x09u},\r
-                       {0x12u, 0x02u},\r
-                       {0x17u, 0x04u},\r
-                       {0x18u, 0x04u},\r
-                       {0x1Au, 0x08u},\r
-                       {0x1Bu, 0x02u},\r
-                       {0x1Eu, 0x07u},\r
-                       {0x20u, 0x20u},\r
-                       {0x22u, 0x40u},\r
-                       {0x26u, 0x20u},\r
-                       {0x2Eu, 0x40u},\r
-                       {0x30u, 0x10u},\r
-                       {0x33u, 0x06u},\r
-                       {0x34u, 0x60u},\r
-                       {0x35u, 0x01u},\r
-                       {0x36u, 0x0Fu},\r
-                       {0x3Eu, 0x10u},\r
-                       {0x3Fu, 0x04u},\r
+                       {0xB3u, 0x40u},\r
+                       {0xB7u, 0x40u},\r
+                       {0xC0u, 0x10u},\r
+                       {0xC2u, 0x40u},\r
+                       {0xC4u, 0x50u},\r
+                       {0xCAu, 0x68u},\r
+                       {0xCCu, 0xE0u},\r
+                       {0xCEu, 0xE0u},\r
+                       {0xD0u, 0xC0u},\r
+                       {0xD2u, 0x30u},\r
+                       {0xD6u, 0xFCu},\r
+                       {0xD8u, 0xFCu},\r
+                       {0xE2u, 0x50u},\r
+                       {0xE4u, 0x80u},\r
+                       {0xE6u, 0x48u},\r
+                       {0xE8u, 0x0Cu},\r
+                       {0xEAu, 0x01u},\r
+                       {0xEEu, 0xC2u},\r
+                       {0x01u, 0x01u},\r
+                       {0x02u, 0x04u},\r
+                       {0x03u, 0x06u},\r
+                       {0x05u, 0x4Au},\r
+                       {0x07u, 0x15u},\r
+                       {0x0Fu, 0x40u},\r
+                       {0x10u, 0x01u},\r
+                       {0x11u, 0x22u},\r
+                       {0x13u, 0x45u},\r
+                       {0x17u, 0x38u},\r
+                       {0x19u, 0x53u},\r
+                       {0x1Au, 0x02u},\r
+                       {0x1Bu, 0x2Cu},\r
+                       {0x21u, 0x01u},\r
+                       {0x27u, 0x01u},\r
+                       {0x2Cu, 0x02u},\r
+                       {0x2Eu, 0x04u},\r
+                       {0x30u, 0x06u},\r
+                       {0x31u, 0x07u},\r
+                       {0x33u, 0x78u},\r
+                       {0x34u, 0x01u},\r
+                       {0x3Bu, 0x02u},\r
+                       {0x3Eu, 0x11u},\r
                        {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x11u},\r
+                       {0x5Cu, 0x10u},\r
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x84u, 0x50u},\r
-                       {0x85u, 0x09u},\r
-                       {0x86u, 0xA0u},\r
-                       {0x87u, 0x06u},\r
-                       {0x88u, 0x60u},\r
-                       {0x89u, 0x03u},\r
-                       {0x8Au, 0x90u},\r
-                       {0x8Bu, 0x0Cu},\r
-                       {0x8Cu, 0x0Fu},\r
-                       {0x8Eu, 0xF0u},\r
-                       {0x8Fu, 0xFFu},\r
-                       {0x91u, 0x0Fu},\r
-                       {0x93u, 0xF0u},\r
-                       {0x95u, 0x30u},\r
-                       {0x97u, 0xC0u},\r
-                       {0x9Bu, 0xFFu},\r
-                       {0x9Cu, 0x05u},\r
-                       {0x9Du, 0x90u},\r
-                       {0x9Eu, 0x0Au},\r
-                       {0x9Fu, 0x60u},\r
-                       {0xA3u, 0xFFu},\r
-                       {0xA4u, 0x03u},\r
-                       {0xA5u, 0x05u},\r
-                       {0xA6u, 0x0Cu},\r
-                       {0xA7u, 0x0Au},\r
-                       {0xA8u, 0x06u},\r
-                       {0xA9u, 0x50u},\r
-                       {0xAAu, 0x09u},\r
-                       {0xABu, 0xA0u},\r
-                       {0xACu, 0x30u},\r
-                       {0xAEu, 0xC0u},\r
-                       {0xB3u, 0xFFu},\r
-                       {0xB6u, 0xFFu},\r
-                       {0xBEu, 0x40u},\r
-                       {0xBFu, 0x04u},\r
+                       {0x82u, 0x07u},\r
+                       {0x83u, 0x3Fu},\r
+                       {0x85u, 0x10u},\r
+                       {0x86u, 0x80u},\r
+                       {0x87u, 0x01u},\r
+                       {0x8Au, 0x08u},\r
+                       {0x8Du, 0x30u},\r
+                       {0x8Fu, 0xC0u},\r
+                       {0x91u, 0x70u},\r
+                       {0x93u, 0x8Cu},\r
+                       {0x94u, 0x99u},\r
+                       {0x95u, 0x6Fu},\r
+                       {0x96u, 0x22u},\r
+                       {0x97u, 0x90u},\r
+                       {0x99u, 0x57u},\r
+                       {0x9Au, 0x70u},\r
+                       {0x9Bu, 0xA0u},\r
+                       {0x9Cu, 0x44u},\r
+                       {0x9Du, 0x03u},\r
+                       {0x9Eu, 0x88u},\r
+                       {0xA1u, 0x08u},\r
+                       {0xA3u, 0x03u},\r
+                       {0xA4u, 0xAAu},\r
+                       {0xA6u, 0x55u},\r
+                       {0xA7u, 0x20u},\r
+                       {0xADu, 0x02u},\r
+                       {0xB4u, 0xF0u},\r
+                       {0xB5u, 0x0Fu},\r
+                       {0xB6u, 0x0Fu},\r
+                       {0xB7u, 0xF0u},\r
+                       {0xBBu, 0x80u},\r
                        {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
+                       {0xDCu, 0x11u},\r
                        {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x09u},\r
-                       {0x02u, 0x02u},\r
-                       {0x06u, 0x24u},\r
-                       {0x07u, 0x02u},\r
-                       {0x09u, 0x02u},\r
-                       {0x0Au, 0x01u},\r
-                       {0x0Bu, 0x04u},\r
-                       {0x0Eu, 0x01u},\r
-                       {0x11u, 0x04u},\r
-                       {0x13u, 0x82u},\r
-                       {0x14u, 0x04u},\r
-                       {0x16u, 0x02u},\r
+                       {0x01u, 0x02u},\r
+                       {0x04u, 0x21u},\r
+                       {0x05u, 0x08u},\r
+                       {0x08u, 0x02u},\r
+                       {0x0Au, 0x08u},\r
+                       {0x0Eu, 0x2Au},\r
+                       {0x10u, 0x02u},\r
                        {0x17u, 0x08u},\r
-                       {0x18u, 0x40u},\r
-                       {0x1Au, 0x05u},\r
-                       {0x1Du, 0x80u},\r
-                       {0x1Fu, 0x80u},\r
-                       {0x20u, 0x08u},\r
+                       {0x19u, 0x21u},\r
+                       {0x1Cu, 0x01u},\r
+                       {0x1Eu, 0x08u},\r
+                       {0x1Fu, 0x40u},\r
+                       {0x21u, 0x0Bu},\r
                        {0x22u, 0x04u},\r
-                       {0x24u, 0x20u},\r
-                       {0x2Cu, 0x20u},\r
-                       {0x2Fu, 0x88u},\r
-                       {0x30u, 0x20u},\r
-                       {0x33u, 0x08u},\r
-                       {0x36u, 0x64u},\r
-                       {0x37u, 0x82u},\r
-                       {0x38u, 0x04u},\r
-                       {0x39u, 0x40u},\r
-                       {0x3Cu, 0x20u},\r
-                       {0x3Du, 0x04u},\r
-                       {0x3Fu, 0x88u},\r
-                       {0x58u, 0x40u},\r
-                       {0x5Bu, 0x10u},\r
-                       {0x5Cu, 0x80u},\r
-                       {0x60u, 0x04u},\r
-                       {0x62u, 0x80u},\r
-                       {0x64u, 0x02u},\r
-                       {0x69u, 0x40u},\r
-                       {0x6Bu, 0x02u},\r
-                       {0x83u, 0x40u},\r
-                       {0x88u, 0x24u},\r
-                       {0x8Fu, 0x11u},\r
-                       {0xC0u, 0xEDu},\r
-                       {0xC2u, 0x8Bu},\r
-                       {0xC4u, 0xEDu},\r
-                       {0xCAu, 0xE0u},\r
-                       {0xCCu, 0xF6u},\r
-                       {0xCEu, 0x7Au},\r
-                       {0xD6u, 0x1Cu},\r
-                       {0xD8u, 0x1Cu},\r
+                       {0x25u, 0x40u},\r
+                       {0x26u, 0x20u},\r
+                       {0x27u, 0x08u},\r
+                       {0x2Au, 0x08u},\r
+                       {0x2Bu, 0x80u},\r
+                       {0x2Du, 0x04u},\r
+                       {0x2Fu, 0x82u},\r
+                       {0x31u, 0x08u},\r
+                       {0x32u, 0x22u},\r
+                       {0x36u, 0x93u},\r
+                       {0x37u, 0x08u},\r
+                       {0x38u, 0x08u},\r
+                       {0x39u, 0x42u},\r
+                       {0x3Cu, 0x04u},\r
+                       {0x3Du, 0x82u},\r
+                       {0x58u, 0x80u},\r
+                       {0x5Au, 0x10u},\r
+                       {0x5Bu, 0x04u},\r
+                       {0x5Eu, 0x44u},\r
+                       {0x5Fu, 0x10u},\r
+                       {0x61u, 0x20u},\r
+                       {0x63u, 0x22u},\r
+                       {0x64u, 0x08u},\r
+                       {0x66u, 0x40u},\r
+                       {0x67u, 0x20u},\r
+                       {0x81u, 0x01u},\r
+                       {0x82u, 0x48u},\r
+                       {0x83u, 0x88u},\r
+                       {0x87u, 0x10u},\r
+                       {0x88u, 0x08u},\r
+                       {0x89u, 0x40u},\r
+                       {0x8Bu, 0x10u},\r
+                       {0x8Du, 0x02u},\r
+                       {0x8Fu, 0x04u},\r
+                       {0xC0u, 0x78u},\r
+                       {0xC2u, 0xEAu},\r
+                       {0xC4u, 0x21u},\r
+                       {0xCAu, 0xD3u},\r
+                       {0xCCu, 0xF7u},\r
+                       {0xCEu, 0xDBu},\r
+                       {0xD6u, 0x7Eu},\r
+                       {0xD8u, 0x7Eu},\r
                        {0xE0u, 0x40u},\r
-                       {0xE4u, 0xA0u},\r
-                       {0xE6u, 0x02u},\r
+                       {0xE2u, 0xA0u},\r
+                       {0xE6u, 0x20u},\r
                        {0x00u, 0x09u},\r
                        {0x02u, 0x06u},\r
-                       {0x04u, 0x03u},\r
-                       {0x05u, 0x03u},\r
-                       {0x06u, 0x0Cu},\r
-                       {0x07u, 0x0Cu},\r
-                       {0x08u, 0x05u},\r
+                       {0x04u, 0x30u},\r
+                       {0x05u, 0x30u},\r
+                       {0x06u, 0xC0u},\r
+                       {0x07u, 0xC0u},\r
                        {0x09u, 0x50u},\r
-                       {0x0Au, 0x0Au},\r
+                       {0x0Au, 0xFFu},\r
                        {0x0Bu, 0xA0u},\r
-                       {0x0Du, 0x0Fu},\r
-                       {0x0Fu, 0xF0u},\r
-                       {0x10u, 0x0Fu},\r
-                       {0x12u, 0xF0u},\r
-                       {0x15u, 0x05u},\r
+                       {0x0Cu, 0x05u},\r
+                       {0x0Du, 0x06u},\r
+                       {0x0Eu, 0x0Au},\r
+                       {0x0Fu, 0x09u},\r
+                       {0x11u, 0x0Fu},\r
+                       {0x13u, 0xF0u},\r
                        {0x16u, 0xFFu},\r
-                       {0x17u, 0x0Au},\r
-                       {0x18u, 0xFFu},\r
+                       {0x1Au, 0xFFu},\r
                        {0x1Bu, 0xFFu},\r
-                       {0x1Cu, 0x90u},\r
-                       {0x1Du, 0xFFu},\r
-                       {0x1Eu, 0x60u},\r
-                       {0x20u, 0xFFu},\r
-                       {0x21u, 0x60u},\r
-                       {0x23u, 0x90u},\r
-                       {0x24u, 0x50u},\r
-                       {0x26u, 0xA0u},\r
-                       {0x27u, 0xFFu},\r
-                       {0x28u, 0x30u},\r
-                       {0x29u, 0x30u},\r
-                       {0x2Au, 0xC0u},\r
-                       {0x2Bu, 0xC0u},\r
-                       {0x2Du, 0x06u},\r
-                       {0x2Fu, 0x09u},\r
+                       {0x1Cu, 0x0Fu},\r
+                       {0x1Du, 0x03u},\r
+                       {0x1Eu, 0xF0u},\r
+                       {0x1Fu, 0x0Cu},\r
+                       {0x20u, 0x03u},\r
+                       {0x21u, 0x05u},\r
+                       {0x22u, 0x0Cu},\r
+                       {0x23u, 0x0Au},\r
+                       {0x25u, 0xFFu},\r
+                       {0x28u, 0x50u},\r
+                       {0x2Au, 0xA0u},\r
+                       {0x2Bu, 0xFFu},\r
+                       {0x2Cu, 0x90u},\r
+                       {0x2Du, 0x60u},\r
+                       {0x2Eu, 0x60u},\r
+                       {0x2Fu, 0x90u},\r
                        {0x30u, 0xFFu},\r
                        {0x31u, 0xFFu},\r
                        {0x3Eu, 0x01u},\r
@@ -1414,411 +1519,492 @@ void cyfitter_cfg(void)
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x22u},\r
-                       {0x82u, 0x10u},\r
-                       {0x83u, 0x9Fu},\r
-                       {0x84u, 0x17u},\r
-                       {0x85u, 0xC0u},\r
-                       {0x86u, 0x28u},\r
-                       {0x87u, 0x04u},\r
-                       {0x88u, 0x29u},\r
-                       {0x89u, 0xC0u},\r
-                       {0x8Au, 0x16u},\r
-                       {0x8Bu, 0x08u},\r
-                       {0x8Cu, 0x16u},\r
-                       {0x8Du, 0x80u},\r
-                       {0x90u, 0x04u},\r
-                       {0x91u, 0x7Fu},\r
-                       {0x93u, 0x80u},\r
-                       {0x94u, 0x40u},\r
-                       {0x97u, 0x60u},\r
-                       {0x98u, 0x12u},\r
-                       {0x99u, 0x1Fu},\r
-                       {0x9Au, 0x04u},\r
-                       {0x9Bu, 0x20u},\r
-                       {0x9Cu, 0x16u},\r
-                       {0x9Du, 0xC0u},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA0u, 0x31u},\r
-                       {0xA1u, 0xC0u},\r
-                       {0xA2u, 0x0Eu},\r
-                       {0xA3u, 0x02u},\r
-                       {0xA4u, 0x40u},\r
-                       {0xA7u, 0xFFu},\r
-                       {0xA8u, 0x10u},\r
-                       {0xAAu, 0x06u},\r
-                       {0xACu, 0x06u},\r
-                       {0xADu, 0x90u},\r
-                       {0xAEu, 0x10u},\r
-                       {0xAFu, 0x40u},\r
-                       {0xB0u, 0x30u},\r
-                       {0xB2u, 0x40u},\r
-                       {0xB4u, 0x0Fu},\r
-                       {0xB5u, 0xFFu},\r
-                       {0xB8u, 0x28u},\r
-                       {0xBAu, 0x02u},\r
+                       {0x80u, 0x01u},\r
+                       {0x81u, 0x68u},\r
+                       {0x85u, 0x12u},\r
+                       {0x87u, 0xE1u},\r
+                       {0x89u, 0x08u},\r
+                       {0x8Bu, 0x60u},\r
+                       {0x8Fu, 0x08u},\r
+                       {0x91u, 0x60u},\r
+                       {0x93u, 0x08u},\r
+                       {0x95u, 0x28u},\r
+                       {0x97u, 0x40u},\r
+                       {0x99u, 0x91u},\r
+                       {0x9Bu, 0x64u},\r
+                       {0x9Du, 0x06u},\r
+                       {0xA1u, 0x68u},\r
+                       {0xA5u, 0x40u},\r
+                       {0xA9u, 0x71u},\r
+                       {0xABu, 0x82u},\r
+                       {0xADu, 0x20u},\r
+                       {0xB1u, 0x07u},\r
+                       {0xB3u, 0xF0u},\r
+                       {0xB5u, 0x08u},\r
+                       {0xB6u, 0x01u},\r
+                       {0xB9u, 0x0Au},\r
                        {0xBFu, 0x10u},\r
+                       {0xC0u, 0x62u},\r
+                       {0xC1u, 0x03u},\r
+                       {0xC2u, 0x10u},\r
+                       {0xC4u, 0x04u},\r
+                       {0xC5u, 0xBEu},\r
+                       {0xC6u, 0xFDu},\r
+                       {0xC7u, 0xBCu},\r
+                       {0xC8u, 0x3Fu},\r
+                       {0xC9u, 0xFFu},\r
+                       {0xCAu, 0xFFu},\r
+                       {0xCBu, 0xFFu},\r
+                       {0xCCu, 0x22u},\r
+                       {0xCEu, 0xF0u},\r
+                       {0xCFu, 0x08u},\r
+                       {0xD0u, 0x04u},\r
                        {0xD4u, 0x40u},\r
                        {0xD6u, 0x04u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
+                       {0xDAu, 0x04u},\r
                        {0xDBu, 0x04u},\r
+                       {0xDCu, 0x09u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x04u},\r
-                       {0x02u, 0x48u},\r
-                       {0x05u, 0x91u},\r
-                       {0x07u, 0x20u},\r
-                       {0x08u, 0x50u},\r
-                       {0x0Au, 0x20u},\r
-                       {0x0Bu, 0x40u},\r
-                       {0x0Eu, 0x25u},\r
-                       {0x0Fu, 0x80u},\r
-                       {0x10u, 0x84u},\r
-                       {0x12u, 0x10u},\r
-                       {0x15u, 0x50u},\r
-                       {0x17u, 0x09u},\r
-                       {0x1Bu, 0x02u},\r
-                       {0x1Du, 0x15u},\r
-                       {0x1Eu, 0x40u},\r
-                       {0x1Fu, 0x20u},\r
-                       {0x21u, 0x01u},\r
-                       {0x27u, 0x08u},\r
-                       {0x28u, 0x54u},\r
-                       {0x2Au, 0x48u},\r
-                       {0x2Bu, 0x05u},\r
-                       {0x2Du, 0x40u},\r
-                       {0x2Eu, 0x01u},\r
-                       {0x2Fu, 0x20u},\r
+                       {0xE2u, 0xC0u},\r
+                       {0xE4u, 0x40u},\r
+                       {0xE5u, 0x01u},\r
+                       {0xE6u, 0x10u},\r
+                       {0xE7u, 0x11u},\r
+                       {0xE8u, 0xC0u},\r
+                       {0xE9u, 0x01u},\r
+                       {0xEBu, 0x11u},\r
+                       {0xECu, 0x40u},\r
+                       {0xEDu, 0x01u},\r
+                       {0xEEu, 0x40u},\r
+                       {0xEFu, 0x01u},\r
+                       {0x00u, 0x92u},\r
+                       {0x01u, 0x04u},\r
+                       {0x02u, 0x41u},\r
+                       {0x03u, 0x08u},\r
+                       {0x04u, 0x02u},\r
+                       {0x08u, 0x10u},\r
+                       {0x0Au, 0x26u},\r
+                       {0x0Bu, 0x22u},\r
+                       {0x10u, 0x81u},\r
+                       {0x11u, 0x50u},\r
+                       {0x1Bu, 0x01u},\r
+                       {0x1Fu, 0x40u},\r
+                       {0x21u, 0x02u},\r
+                       {0x24u, 0x20u},\r
+                       {0x26u, 0x18u},\r
+                       {0x27u, 0x60u},\r
+                       {0x28u, 0x11u},\r
+                       {0x2Au, 0x01u},\r
+                       {0x2Bu, 0x08u},\r
+                       {0x2Eu, 0x4Au},\r
+                       {0x2Fu, 0x04u},\r
                        {0x30u, 0x80u},\r
-                       {0x32u, 0x5Cu},\r
-                       {0x33u, 0x10u},\r
-                       {0x35u, 0x84u},\r
-                       {0x37u, 0x21u},\r
-                       {0x38u, 0x04u},\r
-                       {0x3Au, 0x10u},\r
-                       {0x3Bu, 0x60u},\r
-                       {0x3Du, 0x12u},\r
-                       {0x3Eu, 0x54u},\r
-                       {0x64u, 0xA0u},\r
-                       {0x66u, 0x20u},\r
-                       {0x67u, 0x01u},\r
-                       {0x84u, 0x80u},\r
-                       {0x8Eu, 0x04u},\r
-                       {0x90u, 0x04u},\r
-                       {0x91u, 0x40u},\r
-                       {0x92u, 0x9Du},\r
-                       {0x93u, 0x61u},\r
-                       {0x95u, 0x02u},\r
-                       {0x98u, 0x60u},\r
-                       {0x99u, 0x80u},\r
-                       {0x9Au, 0x28u},\r
-                       {0x9Bu, 0x31u},\r
-                       {0x9Du, 0x15u},\r
-                       {0xA1u, 0x01u},\r
-                       {0xA2u, 0x14u},\r
-                       {0xA3u, 0x45u},\r
-                       {0xA7u, 0x02u},\r
-                       {0xA8u, 0x05u},\r
-                       {0xAAu, 0x01u},\r
-                       {0xB1u, 0x30u},\r
-                       {0xB2u, 0x80u},\r
-                       {0xC0u, 0xFEu},\r
-                       {0xC2u, 0xFFu},\r
-                       {0xC4u, 0xFEu},\r
-                       {0xCAu, 0xDFu},\r
-                       {0xCCu, 0xFEu},\r
+                       {0x32u, 0x11u},\r
+                       {0x35u, 0x80u},\r
+                       {0x36u, 0x04u},\r
+                       {0x37u, 0x61u},\r
+                       {0x39u, 0x14u},\r
+                       {0x3Au, 0x40u},\r
+                       {0x3Cu, 0x04u},\r
+                       {0x3Eu, 0x91u},\r
+                       {0x44u, 0x80u},\r
+                       {0x45u, 0xA8u},\r
+                       {0x4Cu, 0x40u},\r
+                       {0x4Eu, 0x08u},\r
+                       {0x4Fu, 0x04u},\r
+                       {0x54u, 0x02u},\r
+                       {0x56u, 0x98u},\r
+                       {0x5Eu, 0x20u},\r
+                       {0x5Fu, 0x10u},\r
+                       {0x66u, 0x90u},\r
+                       {0x67u, 0x50u},\r
+                       {0x80u, 0x80u},\r
+                       {0x84u, 0x40u},\r
+                       {0x87u, 0x40u},\r
+                       {0x88u, 0xC0u},\r
+                       {0x8Bu, 0x40u},\r
+                       {0x8Fu, 0x01u},\r
+                       {0x90u, 0x16u},\r
+                       {0x91u, 0x54u},\r
+                       {0x92u, 0x55u},\r
+                       {0x93u, 0x28u},\r
+                       {0x94u, 0xA0u},\r
+                       {0x96u, 0x02u},\r
+                       {0x97u, 0x04u},\r
+                       {0x9Au, 0x02u},\r
+                       {0x9Bu, 0x01u},\r
+                       {0x9Cu, 0x40u},\r
+                       {0x9Du, 0x80u},\r
+                       {0x9Eu, 0x08u},\r
+                       {0x9Fu, 0x20u},\r
+                       {0xA0u, 0x01u},\r
+                       {0xA1u, 0xA8u},\r
+                       {0xA2u, 0x04u},\r
+                       {0xA4u, 0xC2u},\r
+                       {0xA5u, 0x02u},\r
+                       {0xA7u, 0x01u},\r
+                       {0xAAu, 0x10u},\r
+                       {0xACu, 0x01u},\r
+                       {0xC0u, 0x1Fu},\r
+                       {0xC2u, 0x07u},\r
+                       {0xC4u, 0x0Bu},\r
+                       {0xCAu, 0xFFu},\r
+                       {0xCCu, 0xFDu},\r
                        {0xCEu, 0xFEu},\r
+                       {0xD0u, 0xF0u},\r
+                       {0xD2u, 0x20u},\r
                        {0xD8u, 0xF0u},\r
-                       {0xE2u, 0x40u},\r
-                       {0xEAu, 0x04u},\r
-                       {0x80u, 0x08u},\r
-                       {0x82u, 0x84u},\r
-                       {0x87u, 0x80u},\r
-                       {0x88u, 0x02u},\r
-                       {0x8Au, 0x41u},\r
-                       {0x8Bu, 0x07u},\r
-                       {0x8Cu, 0x04u},\r
-                       {0x8Eu, 0x28u},\r
-                       {0x90u, 0x53u},\r
-                       {0x91u, 0xAAu},\r
-                       {0x92u, 0xACu},\r
-                       {0x93u, 0x55u},\r
-                       {0x94u, 0x01u},\r
-                       {0x95u, 0x99u},\r
-                       {0x96u, 0x12u},\r
-                       {0x97u, 0x22u},\r
-                       {0x9Bu, 0x70u},\r
-                       {0xA3u, 0x08u},\r
-                       {0xA5u, 0x44u},\r
-                       {0xA7u, 0x88u},\r
-                       {0xB0u, 0x0Fu},\r
-                       {0xB3u, 0x0Fu},\r
-                       {0xB4u, 0xC0u},\r
-                       {0xB5u, 0xF0u},\r
-                       {0xB6u, 0x30u},\r
-                       {0xBEu, 0x51u},\r
+                       {0xE2u, 0x22u},\r
+                       {0xEEu, 0x08u},\r
+                       {0x01u, 0x41u},\r
+                       {0x04u, 0x91u},\r
+                       {0x05u, 0x41u},\r
+                       {0x06u, 0x0Eu},\r
+                       {0x08u, 0x08u},\r
+                       {0x09u, 0x40u},\r
+                       {0x0Au, 0x10u},\r
+                       {0x0Cu, 0x6Cu},\r
+                       {0x10u, 0x24u},\r
+                       {0x11u, 0x01u},\r
+                       {0x13u, 0x40u},\r
+                       {0x14u, 0x40u},\r
+                       {0x15u, 0x04u},\r
+                       {0x16u, 0x2Cu},\r
+                       {0x18u, 0x80u},\r
+                       {0x19u, 0x88u},\r
+                       {0x1Au, 0x2Fu},\r
+                       {0x1Bu, 0x61u},\r
+                       {0x1Cu, 0x6Cu},\r
+                       {0x1Du, 0x81u},\r
+                       {0x1Fu, 0x40u},\r
+                       {0x20u, 0x2Cu},\r
+                       {0x21u, 0x41u},\r
+                       {0x22u, 0x40u},\r
+                       {0x24u, 0xB1u},\r
+                       {0x25u, 0xE2u},\r
+                       {0x26u, 0x02u},\r
+                       {0x27u, 0x08u},\r
+                       {0x28u, 0x64u},\r
+                       {0x29u, 0x47u},\r
+                       {0x2Au, 0x08u},\r
+                       {0x2Bu, 0x98u},\r
+                       {0x2Du, 0x10u},\r
+                       {0x30u, 0x80u},\r
+                       {0x31u, 0x08u},\r
+                       {0x32u, 0x0Fu},\r
+                       {0x34u, 0x31u},\r
+                       {0x35u, 0x3Fu},\r
+                       {0x36u, 0x40u},\r
+                       {0x37u, 0xC0u},\r
+                       {0x39u, 0x20u},\r
+                       {0x3Au, 0x30u},\r
+                       {0x3Bu, 0x80u},\r
+                       {0x3Eu, 0x41u},\r
+                       {0x3Fu, 0x11u},\r
+                       {0x56u, 0x02u},\r
+                       {0x57u, 0x2Cu},\r
+                       {0x58u, 0x04u},\r
+                       {0x59u, 0x04u},\r
+                       {0x5Bu, 0x04u},\r
+                       {0x5Fu, 0x01u},\r
+                       {0x80u, 0x06u},\r
+                       {0x82u, 0x09u},\r
+                       {0x84u, 0x30u},\r
+                       {0x86u, 0xC0u},\r
+                       {0x88u, 0xFFu},\r
+                       {0x8Cu, 0x05u},\r
+                       {0x8Eu, 0x0Au},\r
+                       {0x91u, 0x01u},\r
+                       {0x96u, 0xFFu},\r
+                       {0x9Au, 0xFFu},\r
+                       {0x9Cu, 0x0Fu},\r
+                       {0x9Eu, 0xF0u},\r
+                       {0xA0u, 0x03u},\r
+                       {0xA1u, 0x01u},\r
+                       {0xA2u, 0x0Cu},\r
+                       {0xA5u, 0x01u},\r
+                       {0xA8u, 0x50u},\r
+                       {0xAAu, 0xA0u},\r
+                       {0xACu, 0x60u},\r
+                       {0xADu, 0x01u},\r
+                       {0xAEu, 0x90u},\r
+                       {0xB4u, 0xFFu},\r
+                       {0xB5u, 0x01u},\r
+                       {0xB9u, 0x20u},\r
+                       {0xBEu, 0x10u},\r
+                       {0xBFu, 0x10u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
-                       {0xDCu, 0x10u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x20u},\r
-                       {0x01u, 0x01u},\r
-                       {0x02u, 0x01u},\r
-                       {0x05u, 0x95u},\r
-                       {0x07u, 0x08u},\r
-                       {0x08u, 0x20u},\r
-                       {0x09u, 0x10u},\r
-                       {0x0Bu, 0x50u},\r
-                       {0x0Cu, 0x02u},\r
-                       {0x0Eu, 0x09u},\r
-                       {0x15u, 0x64u},\r
-                       {0x17u, 0x21u},\r
-                       {0x18u, 0x02u},\r
-                       {0x19u, 0x20u},\r
-                       {0x1Au, 0x80u},\r
-                       {0x1Eu, 0x28u},\r
-                       {0x20u, 0x04u},\r
-                       {0x21u, 0x20u},\r
-                       {0x23u, 0x10u},\r
-                       {0x24u, 0x01u},\r
-                       {0x25u, 0x10u},\r
-                       {0x26u, 0x03u},\r
-                       {0x27u, 0x21u},\r
-                       {0x2Au, 0x02u},\r
-                       {0x2Bu, 0x20u},\r
-                       {0x2Eu, 0x85u},\r
-                       {0x31u, 0x2Au},\r
-                       {0x35u, 0x81u},\r
-                       {0x37u, 0x28u},\r
-                       {0x39u, 0x08u},\r
+                       {0x00u, 0x92u},\r
+                       {0x01u, 0x04u},\r
+                       {0x02u, 0x40u},\r
+                       {0x05u, 0x20u},\r
+                       {0x06u, 0x0Au},\r
+                       {0x07u, 0x20u},\r
+                       {0x0Au, 0x06u},\r
+                       {0x0Bu, 0x20u},\r
+                       {0x0Du, 0x20u},\r
+                       {0x0Eu, 0x91u},\r
+                       {0x10u, 0x80u},\r
+                       {0x11u, 0x52u},\r
+                       {0x16u, 0x20u},\r
+                       {0x17u, 0x11u},\r
+                       {0x1Bu, 0x10u},\r
+                       {0x1Cu, 0x04u},\r
+                       {0x1Du, 0xA8u},\r
+                       {0x1Eu, 0x22u},\r
+                       {0x1Fu, 0x25u},\r
+                       {0x22u, 0x10u},\r
+                       {0x24u, 0x40u},\r
+                       {0x26u, 0x40u},\r
+                       {0x27u, 0x08u},\r
+                       {0x2Bu, 0x51u},\r
+                       {0x2Cu, 0x02u},\r
+                       {0x2Eu, 0x22u},\r
+                       {0x2Fu, 0x24u},\r
+                       {0x31u, 0x02u},\r
+                       {0x36u, 0x40u},\r
+                       {0x37u, 0x25u},\r
+                       {0x3Au, 0x04u},\r
+                       {0x3Bu, 0x08u},\r
+                       {0x3Du, 0x08u},\r
+                       {0x3Eu, 0x11u},\r
+                       {0x5Eu, 0xC0u},\r
+                       {0x67u, 0x80u},\r
+                       {0x6Du, 0x08u},\r
+                       {0x6Eu, 0x19u},\r
+                       {0x6Fu, 0x11u},\r
+                       {0x76u, 0x02u},\r
+                       {0x90u, 0x12u},\r
+                       {0x91u, 0x54u},\r
+                       {0x92u, 0x04u},\r
+                       {0x93u, 0xA0u},\r
+                       {0x94u, 0xE4u},\r
+                       {0x96u, 0x13u},\r
+                       {0x97u, 0x0Eu},\r
+                       {0x9Bu, 0x04u},\r
+                       {0x9Cu, 0x40u},\r
+                       {0x9Du, 0xA0u},\r
+                       {0x9Eu, 0x66u},\r
+                       {0x9Fu, 0x29u},\r
+                       {0xA3u, 0x40u},\r
+                       {0xA4u, 0x42u},\r
+                       {0xA5u, 0x01u},\r
+                       {0xA6u, 0x55u},\r
+                       {0xAFu, 0x02u},\r
+                       {0xB5u, 0x08u},\r
+                       {0xC0u, 0xEFu},\r
+                       {0xC2u, 0xF7u},\r
+                       {0xC4u, 0x7Bu},\r
+                       {0xCAu, 0xFBu},\r
+                       {0xCCu, 0xF1u},\r
+                       {0xCEu, 0xE0u},\r
+                       {0xD8u, 0x80u},\r
+                       {0xE2u, 0x08u},\r
+                       {0xE8u, 0x08u},\r
+                       {0xEAu, 0x40u},\r
+                       {0x39u, 0x20u},\r
+                       {0x3Fu, 0x10u},\r
+                       {0x59u, 0x04u},\r
+                       {0x5Fu, 0x01u},\r
+                       {0x27u, 0x08u},\r
+                       {0x87u, 0x08u},\r
+                       {0x91u, 0x40u},\r
+                       {0x92u, 0x08u},\r
+                       {0x93u, 0x80u},\r
+                       {0xA1u, 0x40u},\r
+                       {0xE8u, 0x08u},\r
+                       {0x85u, 0x40u},\r
+                       {0x8Bu, 0x40u},\r
+                       {0x8Du, 0x40u},\r
+                       {0x91u, 0x40u},\r
+                       {0x93u, 0x80u},\r
+                       {0xA1u, 0x40u},\r
+                       {0xAEu, 0x04u},\r
+                       {0xE2u, 0xC0u},\r
+                       {0xE6u, 0x80u},\r
+                       {0x13u, 0x10u},\r
+                       {0x17u, 0x48u},\r
+                       {0x33u, 0x02u},\r
+                       {0x36u, 0x80u},\r
+                       {0x37u, 0x08u},\r
+                       {0x3Au, 0x01u},\r
                        {0x3Bu, 0x10u},\r
-                       {0x3Cu, 0x01u},\r
-                       {0x3Du, 0x48u},\r
-                       {0x3Eu, 0x10u},\r
-                       {0x47u, 0x29u},\r
-                       {0x4Cu, 0x04u},\r
-                       {0x4Eu, 0x02u},\r
-                       {0x4Fu, 0x05u},\r
-                       {0x54u, 0x02u},\r
-                       {0x55u, 0x05u},\r
-                       {0x56u, 0xA0u},\r
-                       {0x57u, 0x40u},\r
-                       {0x7Au, 0x80u},\r
-                       {0x7Bu, 0x40u},\r
-                       {0x89u, 0x20u},\r
-                       {0x8Eu, 0x40u},\r
-                       {0x91u, 0x4Du},\r
-                       {0x92u, 0x1Du},\r
-                       {0x93u, 0x60u},\r
-                       {0x94u, 0x04u},\r
-                       {0x95u, 0x32u},\r
-                       {0x96u, 0x80u},\r
-                       {0x97u, 0x04u},\r
-                       {0x98u, 0x40u},\r
-                       {0x99u, 0x80u},\r
-                       {0x9Au, 0x0Au},\r
-                       {0x9Bu, 0x10u},\r
-                       {0x9Du, 0x10u},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA0u, 0x10u},\r
-                       {0xA1u, 0x0Au},\r
-                       {0xA3u, 0x25u},\r
-                       {0xA4u, 0x02u},\r
-                       {0xA6u, 0x01u},\r
-                       {0xA7u, 0x02u},\r
-                       {0xA9u, 0x02u},\r
-                       {0xADu, 0x01u},\r
-                       {0xB3u, 0x10u},\r
-                       {0xB5u, 0x20u},\r
-                       {0xB7u, 0x04u},\r
-                       {0xC0u, 0xFBu},\r
-                       {0xC2u, 0xDCu},\r
-                       {0xC4u, 0xF0u},\r
-                       {0xCAu, 0xD3u},\r
-                       {0xCCu, 0xF7u},\r
-                       {0xCEu, 0xF6u},\r
-                       {0xD0u, 0xE0u},\r
-                       {0xD2u, 0x30u},\r
-                       {0xEAu, 0x08u},\r
-                       {0xEEu, 0x06u},\r
-                       {0x8Eu, 0x20u},\r
-                       {0xA0u, 0x80u},\r
-                       {0xA4u, 0x10u},\r
-                       {0xA6u, 0x20u},\r
-                       {0xA8u, 0x01u},\r
-                       {0xAEu, 0x01u},\r
-                       {0xB3u, 0x08u},\r
-                       {0xB6u, 0x04u},\r
-                       {0xB7u, 0x40u},\r
-                       {0xE0u, 0x30u},\r
-                       {0xE8u, 0x10u},\r
-                       {0xEAu, 0x60u},\r
-                       {0xEEu, 0x02u},\r
-                       {0xA8u, 0x80u},\r
-                       {0xB0u, 0x10u},\r
-                       {0xECu, 0x80u},\r
-                       {0x12u, 0x08u},\r
-                       {0x15u, 0x80u},\r
-                       {0x17u, 0x04u},\r
-                       {0x33u, 0x04u},\r
-                       {0x36u, 0x28u},\r
-                       {0x39u, 0x88u},\r
-                       {0x3Du, 0x44u},\r
-                       {0x43u, 0x80u},\r
-                       {0x56u, 0x08u},\r
-                       {0x5Au, 0x08u},\r
-                       {0x5Cu, 0x08u},\r
+                       {0x3Cu, 0x80u},\r
+                       {0x3Eu, 0x08u},\r
+                       {0x43u, 0x10u},\r
+                       {0x53u, 0x20u},\r
+                       {0x59u, 0x04u},\r
                        {0x61u, 0x10u},\r
-                       {0x65u, 0x04u},\r
-                       {0x81u, 0x80u},\r
-                       {0x83u, 0x10u},\r
-                       {0x87u, 0x80u},\r
-                       {0x89u, 0x80u},\r
-                       {0x8Au, 0x04u},\r
+                       {0x66u, 0x40u},\r
+                       {0x67u, 0x08u},\r
+                       {0x89u, 0x08u},\r
+                       {0x8Au, 0x40u},\r
                        {0xC4u, 0xE0u},\r
                        {0xCCu, 0xE0u},\r
                        {0xCEu, 0xF0u},\r
                        {0xD0u, 0x10u},\r
-                       {0xD4u, 0x40u},\r
+                       {0xD4u, 0x20u},\r
                        {0xD6u, 0xC0u},\r
                        {0xD8u, 0xC0u},\r
-                       {0xE2u, 0x20u},\r
-                       {0xE6u, 0x90u},\r
-                       {0x30u, 0x20u},\r
                        {0x32u, 0x04u},\r
-                       {0x34u, 0x01u},\r
-                       {0x36u, 0x40u},\r
-                       {0x51u, 0x80u},\r
-                       {0x57u, 0x10u},\r
-                       {0x59u, 0x80u},\r
-                       {0x62u, 0x08u},\r
-                       {0x81u, 0x04u},\r
-                       {0x82u, 0x08u},\r
+                       {0x33u, 0x40u},\r
+                       {0x34u, 0x08u},\r
+                       {0x35u, 0x80u},\r
+                       {0x3Au, 0x40u},\r
+                       {0x50u, 0x80u},\r
+                       {0x52u, 0x02u},\r
+                       {0x55u, 0x08u},\r
+                       {0x66u, 0x80u},\r
+                       {0x80u, 0x80u},\r
+                       {0x82u, 0x02u},\r
                        {0x84u, 0x08u},\r
-                       {0x8Au, 0x08u},\r
-                       {0x95u, 0x4Cu},\r
-                       {0x99u, 0x80u},\r
-                       {0x9Cu, 0x08u},\r
+                       {0x8Au, 0x80u},\r
+                       {0x97u, 0x08u},\r
+                       {0x9Bu, 0x40u},\r
                        {0x9Du, 0x14u},\r
                        {0x9Eu, 0x08u},\r
-                       {0xA1u, 0x80u},\r
-                       {0xA3u, 0x10u},\r
-                       {0xA6u, 0x20u},\r
+                       {0x9Fu, 0x10u},\r
+                       {0xA1u, 0x08u},\r
+                       {0xA4u, 0x40u},\r
+                       {0xA6u, 0x80u},\r
+                       {0xA7u, 0x22u},\r
+                       {0xB6u, 0x01u},\r
                        {0xCCu, 0xF0u},\r
+                       {0xCEu, 0x10u},\r
                        {0xD4u, 0xE0u},\r
-                       {0xD8u, 0x40u},\r
-                       {0xE2u, 0x20u},\r
-                       {0xE6u, 0x90u},\r
-                       {0x12u, 0x20u},\r
-                       {0x81u, 0x40u},\r
-                       {0x85u, 0x04u},\r
-                       {0x95u, 0x4Cu},\r
+                       {0xD6u, 0x80u},\r
+                       {0xE2u, 0xA0u},\r
+                       {0xE6u, 0x10u},\r
+                       {0x12u, 0x80u},\r
+                       {0x85u, 0x80u},\r
+                       {0x8Cu, 0x80u},\r
+                       {0x8Du, 0x04u},\r
                        {0x96u, 0x08u},\r
-                       {0x9Cu, 0x01u},\r
-                       {0x9Du, 0x10u},\r
-                       {0xA4u, 0x20u},\r
-                       {0xA6u, 0x60u},\r
+                       {0x9Du, 0x94u},\r
+                       {0x9Eu, 0x48u},\r
+                       {0x9Fu, 0x10u},\r
+                       {0xA6u, 0x80u},\r
+                       {0xA7u, 0x22u},\r
+                       {0xACu, 0x40u},\r
+                       {0xAFu, 0x04u},\r
                        {0xC4u, 0x10u},\r
                        {0xE2u, 0x10u},\r
-                       {0xE6u, 0x20u},\r
-                       {0x73u, 0x01u},\r
-                       {0x84u, 0x20u},\r
-                       {0x86u, 0x24u},\r
-                       {0x8Fu, 0x01u},\r
-                       {0x95u, 0x04u},\r
+                       {0xEAu, 0x40u},\r
+                       {0xEEu, 0x10u},\r
+                       {0x83u, 0x10u},\r
+                       {0x86u, 0x44u},\r
+                       {0x8Fu, 0x40u},\r
                        {0x96u, 0x08u},\r
                        {0x9Du, 0x10u},\r
-                       {0xA4u, 0x20u},\r
-                       {0xA6u, 0x40u},\r
-                       {0xACu, 0x01u},\r
-                       {0xDCu, 0x20u},\r
-                       {0xE2u, 0x40u},\r
-                       {0xE6u, 0x50u},\r
-                       {0xEAu, 0x40u},\r
-                       {0x09u, 0x80u},\r
-                       {0x0Fu, 0x80u},\r
+                       {0x9Eu, 0x48u},\r
+                       {0x9Fu, 0x10u},\r
+                       {0xA0u, 0x80u},\r
+                       {0xA7u, 0x22u},\r
+                       {0xE2u, 0x30u},\r
+                       {0xE6u, 0x10u},\r
+                       {0x08u, 0x80u},\r
+                       {0x0Bu, 0x20u},\r
+                       {0x0Cu, 0x01u},\r
                        {0x10u, 0x10u},\r
-                       {0x53u, 0x80u},\r
-                       {0x54u, 0x04u},\r
-                       {0x59u, 0x20u},\r
-                       {0x5Fu, 0x80u},\r
-                       {0x84u, 0x10u},\r
-                       {0x8Fu, 0x40u},\r
-                       {0xC2u, 0x06u},\r
-                       {0xC4u, 0x08u},\r
+                       {0x14u, 0x40u},\r
+                       {0x50u, 0x10u},\r
+                       {0x53u, 0x02u},\r
+                       {0x54u, 0x02u},\r
+                       {0x56u, 0x20u},\r
+                       {0x8Bu, 0x18u},\r
+                       {0x8Eu, 0x04u},\r
+                       {0xC2u, 0x0Eu},\r
+                       {0xC4u, 0x0Cu},\r
                        {0xD4u, 0x07u},\r
                        {0xD6u, 0x04u},\r
-                       {0xE6u, 0x02u},\r
-                       {0x00u, 0x02u},\r
-                       {0x03u, 0x01u},\r
-                       {0x04u, 0x42u},\r
-                       {0x0Bu, 0x22u},\r
-                       {0x0Eu, 0x01u},\r
-                       {0x0Fu, 0x20u},\r
-                       {0x85u, 0x20u},\r
-                       {0x86u, 0x01u},\r
-                       {0x8Cu, 0x40u},\r
-                       {0x9Du, 0x20u},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA4u, 0x04u},\r
-                       {0xAFu, 0x81u},\r
-                       {0xB3u, 0x80u},\r
-                       {0xB5u, 0x80u},\r
+                       {0xE2u, 0x04u},\r
+                       {0xE6u, 0x09u},\r
+                       {0x01u, 0x01u},\r
+                       {0x02u, 0x04u},\r
+                       {0x07u, 0x48u},\r
+                       {0x0Bu, 0x41u},\r
+                       {0x0Cu, 0x82u},\r
+                       {0x87u, 0x04u},\r
+                       {0x94u, 0x20u},\r
+                       {0x97u, 0x01u},\r
+                       {0x9Eu, 0x04u},\r
+                       {0x9Fu, 0x08u},\r
+                       {0xA7u, 0x02u},\r
+                       {0xA8u, 0x02u},\r
+                       {0xABu, 0x01u},\r
+                       {0xACu, 0x80u},\r
+                       {0xAEu, 0x20u},\r
+                       {0xB0u, 0x51u},\r
                        {0xC0u, 0x0Fu},\r
                        {0xC2u, 0x0Fu},\r
-                       {0xE2u, 0x02u},\r
-                       {0xEAu, 0x08u},\r
-                       {0xECu, 0x04u},\r
-                       {0x8Fu, 0x10u},\r
-                       {0x90u, 0x02u},\r
-                       {0xA3u, 0x10u},\r
-                       {0xA4u, 0x04u},\r
-                       {0xABu, 0x01u},\r
-                       {0xB0u, 0x01u},\r
-                       {0xB3u, 0x10u},\r
-                       {0xE2u, 0x08u},\r
                        {0xEAu, 0x05u},\r
-                       {0x09u, 0x02u},\r
+                       {0xEEu, 0x04u},\r
+                       {0x84u, 0x04u},\r
+                       {0x87u, 0x40u},\r
+                       {0x8Cu, 0x10u},\r
+                       {0x91u, 0x01u},\r
+                       {0x93u, 0x40u},\r
+                       {0x94u, 0x20u},\r
+                       {0x97u, 0x08u},\r
+                       {0x9Bu, 0x40u},\r
+                       {0xA7u, 0x02u},\r
+                       {0xACu, 0x80u},\r
+                       {0xB4u, 0x02u},\r
+                       {0xE4u, 0x02u},\r
+                       {0xEEu, 0x02u},\r
+                       {0x08u, 0x04u},\r
                        {0x0Bu, 0x08u},\r
-                       {0x0Eu, 0x04u},\r
-                       {0x0Fu, 0x40u},\r
-                       {0x80u, 0x01u},\r
-                       {0x85u, 0x02u},\r
-                       {0x87u, 0x04u},\r
-                       {0x90u, 0x02u},\r
-                       {0x96u, 0x04u},\r
-                       {0xA4u, 0x04u},\r
-                       {0xAEu, 0x04u},\r
+                       {0x0Eu, 0x21u},\r
+                       {0x86u, 0x11u},\r
+                       {0x97u, 0x08u},\r
+                       {0x9Cu, 0x04u},\r
+                       {0xA7u, 0x02u},\r
+                       {0xB1u, 0x01u},\r
+                       {0xB7u, 0x40u},\r
                        {0xC2u, 0x0Fu},\r
-                       {0x95u, 0x04u},\r
-                       {0x9Du, 0x10u},\r
-                       {0xA2u, 0x20u},\r
-                       {0xAEu, 0x40u},\r
-                       {0xEEu, 0x40u},\r
+                       {0xEAu, 0x08u},\r
+                       {0xEEu, 0x01u},\r
+                       {0x67u, 0x80u},\r
+                       {0x87u, 0x40u},\r
+                       {0x9Eu, 0x08u},\r
+                       {0xA0u, 0x80u},\r
+                       {0xA3u, 0x40u},\r
+                       {0xA7u, 0x22u},\r
+                       {0xB5u, 0x10u},\r
+                       {0xD8u, 0x80u},\r
+                       {0xE2u, 0x10u},\r
                        {0x07u, 0x40u},\r
-                       {0x52u, 0x20u},\r
-                       {0x57u, 0x80u},\r
-                       {0x85u, 0x04u},\r
-                       {0x8Fu, 0x80u},\r
-                       {0x95u, 0x04u},\r
-                       {0x9Fu, 0x40u},\r
-                       {0xA2u, 0x20u},\r
-                       {0xA9u, 0x10u},\r
-                       {0xABu, 0x40u},\r
+                       {0x50u, 0x80u},\r
+                       {0x57u, 0x40u},\r
+                       {0x83u, 0x40u},\r
+                       {0x87u, 0x02u},\r
+                       {0x8Au, 0x08u},\r
+                       {0x9Eu, 0x08u},\r
+                       {0xA0u, 0x80u},\r
+                       {0xA3u, 0x40u},\r
+                       {0xA7u, 0x02u},\r
+                       {0xABu, 0x20u},\r
                        {0xC0u, 0x20u},\r
                        {0xD4u, 0x60u},\r
-                       {0xE6u, 0x40u},\r
-                       {0xECu, 0x80u},\r
+                       {0xE2u, 0x10u},\r
+                       {0xE4u, 0x80u},\r
                        {0xEEu, 0x20u},\r
-                       {0x88u, 0x04u},\r
-                       {0xA4u, 0x04u},\r
-                       {0xAFu, 0x40u},\r
-                       {0xE0u, 0x04u},\r
-                       {0x10u, 0x03u},\r
-                       {0x1Au, 0x03u},\r
+                       {0xAFu, 0x02u},\r
+                       {0x01u, 0x02u},\r
+                       {0x89u, 0x02u},\r
+                       {0xC0u, 0x08u},\r
+                       {0xE2u, 0x01u},\r
+                       {0x10u, 0x01u},\r
+                       {0x11u, 0x01u},\r
+                       {0x1Au, 0x01u},\r
+                       {0x1Bu, 0x01u},\r
                        {0x00u, 0xFDu},\r
-                       {0x01u, 0xABu},\r
-                       {0x02u, 0x02u},\r
+                       {0x01u, 0xAFu},\r
+                       {0x02u, 0x0Au},\r
                        {0x10u, 0x55u},\r
                };\r
 \r
@@ -1841,31 +2027,18 @@ void cyfitter_cfg(void)
                        {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
                        {(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
                        {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
-                       {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 512u},\r
-                       {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), 1408u},\r
+                       {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
                        {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
                        {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
                        {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
                };\r
 \r
-               /* UDB_1_1_1_CONFIG Address: CYDEV_UCFG_B1_P3_U0_BASE Size (bytes): 128 */\r
-               static const uint8 CYCODE BS_UDB_1_1_1_CONFIG_VAL[] = {\r
-                       0x01u, 0x00u, 0x00u, 0x75u, 0x04u, 0x00u, 0x00u, 0x08u, 0x08u, 0x88u, 0x61u, 0x64u, 0x01u, 0x64u, 0x00u, 0x88u, \r
-                       0x10u, 0x24u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x70u, 0x00u, 0x07u, 0x40u, 0x10u, 0x01u, 0xECu, 0x00u, 0x00u, \r
-                       0xA2u, 0xECu, 0x08u, 0x00u, 0x01u, 0xACu, 0x00u, 0x40u, 0x07u, 0x00u, 0xD8u, 0x00u, 0x01u, 0x40u, 0x00u, 0x02u, \r
-                       0x00u, 0x80u, 0x3Fu, 0x71u, 0xE0u, 0x08u, 0x00u, 0x07u, 0x08u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0x04u, 0x11u, \r
-                       0x34u, 0x02u, 0x50u, 0x00u, 0x06u, 0xDEu, 0xFCu, 0xBDu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
-                       0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, \r
-                       0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
-                       0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
-\r
                /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
                static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
-                       0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x00u, 0x02u, 0x01u};\r
+                       0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};\r
 \r
                static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
                        /* dest, src, size */\r
-                       {(void CYFAR *)(CYDEV_UCFG_B1_P3_U0_BASE), BS_UDB_1_1_1_CONFIG_VAL, 128u},\r
                        {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
                };\r
 \r
index 3842dd2..c2cf04a 100644 (file)
 /* SCSI_TX_DMA_COMPLETE */\r
 .set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x04\r
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 2\r
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08\r
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3\r
 .set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
 .set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* SD_RX_DMA_COMPLETE */\r
 .set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x08\r
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 3\r
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10\r
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4\r
 .set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
 .set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* SD_TX_DMA_COMPLETE */\r
 .set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x10\r
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 4\r
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20\r
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5\r
 .set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
 .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* SCSI_Parity_Error */\r
 .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB10_11_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
 .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB10_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB10_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST\r
 \r
 /* USBFS_bus_reset */\r
 .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 /* SCSI_CTL_PHASE */\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+\r
+/* SCSI_Filtered */\r
+.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01\r
+.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST\r
+.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
+.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
+.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
+.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
+.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
+.set SCSI_Filtered_sts_sts_reg__3__POS, 3\r
+.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
+.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
+.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB00_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB00_ST\r
 \r
 /* SCSI_Out_Bits */\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
 \r
 /* USBFS_arb_int */\r
 .set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 /* SCSI_Out_Ctl */\r
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
 .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
 \r
 /* SCSI_Out_DBx */\r
 .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
 /* SCSI_RST_ISR */\r
 .set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_RST_ISR__INTC_MASK, 0x400\r
-.set SCSI_RST_ISR__INTC_NUMBER, 10\r
+.set SCSI_RST_ISR__INTC_MASK, 0x04\r
+.set SCSI_RST_ISR__INTC_NUMBER, 2\r
 .set SCSI_RST_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_10\r
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
 .set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
 .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
 .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
 .set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB05_ST\r
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
 .set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
 .set SDCard_BSPIM_TxStsReg__1__POS, 1\r
 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
 .set SDCard_BSPIM_TxStsReg__4__POS, 4\r
 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB06_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB06_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB06_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB06_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB06_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB06_F1\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB06_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB06_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB05_06_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB05_06_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB05_06_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB05_06_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB05_06_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB05_06_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB05_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB05_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB05_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB05_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB05_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB05_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB05_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB05_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB05_F1\r
 \r
 /* USBFS_dp_int */\r
 .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
 .set timer_clock__PM_STBY_MSK, 0x04\r
 \r
+/* SCSI_Noise */\r
+.set SCSI_Noise__0__AG, CYREG_PRT12_AG\r
+.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE\r
+.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP\r
+.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0\r
+.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1\r
+.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2\r
+.set SCSI_Noise__0__DR, CYREG_PRT12_DR\r
+.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_Noise__0__MASK, 0x20\r
+.set SCSI_Noise__0__PC, CYREG_PRT12_PC5\r
+.set SCSI_Noise__0__PORT, 12\r
+.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT\r
+.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_Noise__0__PS, CYREG_PRT12_PS\r
+.set SCSI_Noise__0__SHIFT, 5\r
+.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW\r
+.set SCSI_Noise__1__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__1__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__1__MASK, 0x10\r
+.set SCSI_Noise__1__PC, CYREG_PRT6_PC4\r
+.set SCSI_Noise__1__PORT, 6\r
+.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__1__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__1__SHIFT, 4\r
+.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__2__AG, CYREG_PRT5_AG\r
+.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE\r
+.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP\r
+.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL\r
+.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0\r
+.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1\r
+.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2\r
+.set SCSI_Noise__2__DR, CYREG_PRT5_DR\r
+.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_Noise__2__MASK, 0x01\r
+.set SCSI_Noise__2__PC, CYREG_PRT5_PC0\r
+.set SCSI_Noise__2__PORT, 5\r
+.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT\r
+.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_Noise__2__PS, CYREG_PRT5_PS\r
+.set SCSI_Noise__2__SHIFT, 0\r
+.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW\r
+.set SCSI_Noise__3__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__3__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__3__MASK, 0x40\r
+.set SCSI_Noise__3__PC, CYREG_PRT6_PC6\r
+.set SCSI_Noise__3__PORT, 6\r
+.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__3__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__3__SHIFT, 6\r
+.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__4__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__4__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__4__MASK, 0x20\r
+.set SCSI_Noise__4__PC, CYREG_PRT6_PC5\r
+.set SCSI_Noise__4__PORT, 6\r
+.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__4__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__4__SHIFT, 5\r
+.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__ACK__MASK, 0x20\r
+.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5\r
+.set SCSI_Noise__ACK__PORT, 6\r
+.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__ACK__SHIFT, 5\r
+.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG\r
+.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE\r
+.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP\r
+.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0\r
+.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1\r
+.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2\r
+.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR\r
+.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_Noise__ATN__MASK, 0x20\r
+.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5\r
+.set SCSI_Noise__ATN__PORT, 12\r
+.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT\r
+.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS\r
+.set SCSI_Noise__ATN__SHIFT, 5\r
+.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW\r
+.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__BSY__MASK, 0x10\r
+.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4\r
+.set SCSI_Noise__BSY__PORT, 6\r
+.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__BSY__SHIFT, 4\r
+.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__RST__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__RST__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__RST__MASK, 0x40\r
+.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6\r
+.set SCSI_Noise__RST__PORT, 6\r
+.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__RST__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__RST__SHIFT, 6\r
+.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG\r
+.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE\r
+.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP\r
+.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL\r
+.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0\r
+.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1\r
+.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2\r
+.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR\r
+.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_Noise__SEL__MASK, 0x01\r
+.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0\r
+.set SCSI_Noise__SEL__PORT, 5\r
+.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT\r
+.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS\r
+.set SCSI_Noise__SEL__SHIFT, 0\r
+.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW\r
+\r
 /* scsiTarget */\r
 .set scsiTarget_StatusReg__0__MASK, 0x01\r
 .set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
 .set scsiTarget_StatusReg__1__MASK, 0x02\r
 .set scsiTarget_StatusReg__1__POS, 1\r
 .set scsiTarget_StatusReg__2__MASK, 0x04\r
 .set scsiTarget_StatusReg__4__MASK, 0x10\r
 .set scsiTarget_StatusReg__4__POS, 4\r
 .set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK\r
-.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL\r
-.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB04_MSK\r
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB04_ST\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB04_CTL\r
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB04_CTL\r
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB04_MSK\r
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB04_05_A0\r
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB04_05_A1\r
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB04_05_D0\r
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB04_05_D1\r
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB04_05_F0\r
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB04_05_F1\r
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB04_A0_A1\r
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB04_A0\r
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB04_A1\r
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB04_D0_D1\r
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB04_D0\r
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB04_D1\r
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB04_F0_F1\r
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB04_F0\r
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB04_F1\r
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB12_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB12_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB12_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB12_13_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB12_13_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB12_13_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB12_13_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB12_13_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB12_13_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB12_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB12_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB12_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB12_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB12_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB12_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB12_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB12_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB12_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
 \r
 /* USBFS_ep_0 */\r
 .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 /* USBFS_ep_1 */\r
 .set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_1__INTC_MASK, 0x20\r
-.set USBFS_ep_1__INTC_NUMBER, 5\r
+.set USBFS_ep_1__INTC_MASK, 0x40\r
+.set USBFS_ep_1__INTC_NUMBER, 6\r
 .set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
 .set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* USBFS_ep_2 */\r
 .set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_2__INTC_MASK, 0x40\r
-.set USBFS_ep_2__INTC_NUMBER, 6\r
+.set USBFS_ep_2__INTC_MASK, 0x80\r
+.set USBFS_ep_2__INTC_NUMBER, 7\r
 .set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* USBFS_ep_3 */\r
 .set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_3__INTC_MASK, 0x80\r
-.set USBFS_ep_3__INTC_NUMBER, 7\r
+.set USBFS_ep_3__INTC_MASK, 0x100\r
+.set USBFS_ep_3__INTC_NUMBER, 8\r
 .set USBFS_ep_3__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
 .set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* USBFS_ep_4 */\r
 .set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_4__INTC_MASK, 0x100\r
-.set USBFS_ep_4__INTC_NUMBER, 8\r
+.set USBFS_ep_4__INTC_MASK, 0x200\r
+.set USBFS_ep_4__INTC_NUMBER, 9\r
 .set USBFS_ep_4__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9\r
 .set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
 .set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN\r
 \r
-/* SCSI_ATN */\r
-.set SCSI_ATN__0__MASK, 0x20\r
-.set SCSI_ATN__0__PC, CYREG_PRT12_PC5\r
-.set SCSI_ATN__0__PORT, 12\r
-.set SCSI_ATN__0__SHIFT, 5\r
-.set SCSI_ATN__AG, CYREG_PRT12_AG\r
-.set SCSI_ATN__BIE