Implement WRITE BUFFER and WRITE WITH VERIFY commands v4.01.01
authorMichael McMaster <michael@codesrc.com>
Fri, 20 Feb 2015 06:56:27 +0000 (16:56 +1000)
committerMichael McMaster <michael@codesrc.com>
Fri, 20 Feb 2015 06:56:27 +0000 (16:56 +1000)
Also fixes a problem with SD card initialisation not setting
the clock back to normal on an error condition. The next
initialisation attempt ends up running the card at a very slow
rate.

41 files changed:
CHANGELOG
readme.txt
software/SCSI2SD/src/bits.c
software/SCSI2SD/src/cdrom.c
software/SCSI2SD/src/config.c
software/SCSI2SD/src/debug.h
software/SCSI2SD/src/diagnostic.c
software/SCSI2SD/src/diagnostic.h
software/SCSI2SD/src/disk.c
software/SCSI2SD/src/inquiry.c
software/SCSI2SD/src/led.c
software/SCSI2SD/src/main.c
software/SCSI2SD/src/mode.c
software/SCSI2SD/src/scsi.c
software/SCSI2SD/src/scsi.h
software/SCSI2SD/src/scsiPhy.c
software/SCSI2SD/src/scsiPhy.h
software/SCSI2SD/src/sd.c
software/SCSI2SD/src/sd.h
software/SCSI2SD/src/time.c
software/SCSI2SD/src/time.h
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
software/include/scsi2sd.h
software/scsi2sd-util/ConfigUtil.cc
software/scsi2sd-util/SCSI2SD_HID.cc
software/scsi2sd-util/scsi2sd-util.cc

index 41398d9..cf022b5 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,9 @@
+201501??               4.1.1
+       - Fix MODE SENSE bug when the allocation length is less than the
+       page size.
+       - Add WRITE BUFFER and WRITE AND VERIFY support.
+       - Fix rare case of very slow performance
+
 20150201               4.1
        - Rewrite of the SD card interface to fix compatibility problems.
                This fixes write issues with Samsung SD cards.
index 50b5f86..1c22fde 100644 (file)
@@ -82,6 +82,11 @@ Compatibility
         Alpha 21264 CPU, 667MHz, with a QLogic SCSI controller in a PCI slot 
     SCSI-based Macintosh Powerbooks (2.5" SCSI2SD)
         Also reported to work on Thinkpad 860 running Win NT 4.0 PowerPC. 
+       Data General MV/2500DC running AOS/VS
+               Vendor: MICROoP
+               Product: 1578-15       UP
+               Revision: DG02
+               Device-type modifier: 0x4c
 
 Samplers
 
@@ -105,3 +110,6 @@ Other
 
     HP 16601A, 16700A logic analyzers
     Fluke 9100 series 
+       Reftek RT-72A Seismic datalogger.
+               http://www.iris.iris.edu/passcal/Reftek/72A-R-005-00.1.pdf
+               http://www.iris.iris.edu/passcal/Manual/rtfm.s3a.13.html
index ab83ba0..ec8eea7 100755 (executable)
@@ -14,6 +14,9 @@
 //\r
 //     You should have received a copy of the GNU General Public License\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
+#pragma GCC push_options\r
+#pragma GCC optimize("-flto")\r
+\r
 #include "bits.h"\r
 \r
 const uint8 Lookup_OddParity[] =\r
@@ -45,3 +48,5 @@ uint8 countBits(uint8 value)
        }\r
        return i;\r
 }\r
+\r
+#pragma GCC pop_options\r
index 44d03a3..18ed321 100755 (executable)
@@ -14,6 +14,8 @@
 //
 //     You should have received a copy of the GNU General Public License
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "device.h"
 #include "scsi.h"
@@ -327,3 +329,5 @@ int scsiCDRomCommand()
 
        return commandHandled;
 }
+
+#pragma GCC pop_options
index 74c554e..6178b9f 100755 (executable)
@@ -14,6 +14,8 @@
 //\r
 //     You should have received a copy of the GNU General Public License\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
+#pragma GCC push_options\r
+#pragma GCC optimize("-flto")\r
 \r
 #include "device.h"\r
 #include "config.h"\r
@@ -30,7 +32,7 @@
 \r
 #include <string.h>\r
 \r
-static const uint16_t FIRMWARE_VERSION = 0x0410;\r
+static const uint16_t FIRMWARE_VERSION = 0x0411;\r
 \r
 enum USB_ENDPOINTS\r
 {\r
@@ -274,7 +276,7 @@ void debugPoll()
                hidBuffer[26] = blockDev.state;\r
                hidBuffer[27] = scsiDev.lastSenseASC >> 8;\r
                hidBuffer[28] = scsiDev.lastSenseASC;\r
-\r
+               hidBuffer[29] = scsiReadDBxPins();\r
 \r
                hidBuffer[58] = sdDev.capacity >> 24;\r
                hidBuffer[59] = sdDev.capacity >> 16;\r
@@ -323,6 +325,11 @@ void debugResume()
        Debug_Timer_Start();\r
 }\r
 \r
+int isDebugEnabled()\r
+{\r
+       return usbReady;\r
+}\r
+\r
 // Public method for storing MODE SELECT results.\r
 void configSave(int scsiId, uint16_t bytesPerSector)\r
 {\r
@@ -377,4 +384,4 @@ const TargetConfig* getConfigById(int scsiId)
 \r
 }\r
 \r
-\r
+#pragma GCC pop_options\r
index cece6bc..683c75b 100755 (executable)
@@ -20,6 +20,7 @@
 void debugInit(void);
 void debugPause(void);
 void debugResume(void);
+int isDebugEnabled(void);
 
 #endif
 
index c518d75..709836c 100755 (executable)
@@ -14,6 +14,8 @@
 //\r
 //     You should have received a copy of the GNU General Public License\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
+#pragma GCC push_options\r
+#pragma GCC optimize("-flto")\r
 \r
 #include "device.h"\r
 #include "scsi.h"\r
@@ -162,4 +164,54 @@ void scsiReadBuffer()
                        (allocLength > MAX_SECTOR_SIZE) ? MAX_SECTOR_SIZE : allocLength;\r
                scsiDev.phase = DATA_IN;\r
        }\r
+       else\r
+       {\r
+               // error.\r
+               scsiDev.status = CHECK_CONDITION;\r
+               scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
+               scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
+               scsiDev.phase = STATUS;\r
+       }\r
+}\r
+\r
+// Callback after the DATA OUT phase is complete.\r
+static void doWriteBuffer(void)\r
+{\r
+       if (scsiDev.status == GOOD) // skip if we've already encountered an error\r
+       {\r
+               // scsiDev.dataLen bytes are in scsiDev.data\r
+               // Don't shift it down 4 bytes ... this space is taken by\r
+               // the read buffer header anyway\r
+               scsiDev.phase = STATUS;\r
+       }\r
 }\r
+\r
+void scsiWriteBuffer()\r
+{\r
+       // WRITE BUFFER\r
+       // Used for testing the speed of the SCSI interface.\r
+       uint8 mode = scsiDev.data[1] & 7;\r
+\r
+       int allocLength =\r
+               (((uint32) scsiDev.cdb[6]) << 16) +\r
+               (((uint32) scsiDev.cdb[7]) << 8) +\r
+               scsiDev.cdb[8];\r
+\r
+       if (mode == 0 && allocLength <= sizeof(scsiDev.data))\r
+       {\r
+               scsiDev.dataLen = allocLength;\r
+               scsiDev.phase = DATA_OUT;\r
+               scsiDev.postDataOutHook = doWriteBuffer;\r
+       }\r
+       else\r
+       {\r
+               // error.\r
+               scsiDev.status = CHECK_CONDITION;\r
+               scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
+               scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
+               scsiDev.phase = STATUS;\r
+       }\r
+}\r
+\r
+\r
+#pragma GCC pop_options\r
index 4cba50c..98e90d2 100755 (executable)
@@ -19,6 +19,7 @@
 
 void scsiSendDiagnostic(void);
 void scsiReceiveDiagnostic(void);
+void scsiWriteBuffer(void);
 void scsiReadBuffer(void);
 
 #endif
index 003f5f3..af1c50a 100755 (executable)
@@ -15,6 +15,8 @@
 //\r
 //     You should have received a copy of the GNU General Public License\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
+#pragma GCC push_options\r
+#pragma GCC optimize("-flto")\r
 \r
 #include "device.h"\r
 #include "scsi.h"\r
@@ -38,7 +40,7 @@ static int doSdInit()
        if (blockDev.state & DISK_PRESENT)\r
        {\r
                result = sdInit();\r
-       \r
+\r
                if (result)\r
                {\r
                        blockDev.state = blockDev.state | DISK_INITIALISED;\r
@@ -167,8 +169,8 @@ static void doReadCapacity()
 \r
 static void doWrite(uint32 lba, uint32 blocks)\r
 {\r
-       if ((blockDev.state & DISK_WP) ||\r
-               (scsiDev.target->cfg->deviceType == CONFIG_OPTICAL))\r
+       if (unlikely(blockDev.state & DISK_WP) ||\r
+               unlikely(scsiDev.target->cfg->deviceType == CONFIG_OPTICAL))\r
 \r
        {\r
                scsiDev.status = CHECK_CONDITION;\r
@@ -176,12 +178,13 @@ static void doWrite(uint32 lba, uint32 blocks)
                scsiDev.target->sense.asc = WRITE_PROTECTED;\r
                scsiDev.phase = STATUS;\r
        }\r
-       else if (((uint64) lba) + blocks >\r
+       else if (unlikely(((uint64) lba) + blocks >\r
                getScsiCapacity(\r
                        scsiDev.target->cfg->sdSectorStart,\r
                        scsiDev.target->liveCfg.bytesPerSector,\r
                        scsiDev.target->cfg->scsiSectors\r
-                       ))\r
+                       )\r
+               ))\r
        {\r
                scsiDev.status = CHECK_CONDITION;\r
                scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
@@ -201,7 +204,7 @@ static void doWrite(uint32 lba, uint32 blocks)
                // No need for single-block writes atm.  Overhead of the\r
                // multi-block write is minimal.\r
                transfer.multiBlock = 1;\r
-               \r
+\r
                sdWriteMultiSectorPrep();\r
        }\r
 }\r
@@ -213,7 +216,7 @@ static void doRead(uint32 lba, uint32 blocks)
                scsiDev.target->cfg->sdSectorStart,\r
                scsiDev.target->liveCfg.bytesPerSector,\r
                scsiDev.target->cfg->scsiSectors);\r
-       if (((uint64) lba) + blocks > capacity)\r
+       if (unlikely(((uint64) lba) + blocks > capacity))\r
        {\r
                scsiDev.status = CHECK_CONDITION;\r
                scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
@@ -230,7 +233,7 @@ static void doRead(uint32 lba, uint32 blocks)
                scsiDev.dataLen = 0; // No data yet\r
 \r
                if ((blocks == 1) ||\r
-                       (((uint64) lba) + blocks == capacity)\r
+                       unlikely(((uint64) lba) + blocks == capacity)\r
                        )\r
                {\r
                        // We get errors on reading the last sector using a multi-sector\r
@@ -264,7 +267,11 @@ static void doSeek(uint32 lba)
 static int doTestUnitReady()\r
 {\r
        int ready = 1;\r
-       if (!(blockDev.state & DISK_STARTED))\r
+       if (likely(blockDev.state == (DISK_STARTED | DISK_PRESENT | DISK_INITIALISED)))\r
+       {\r
+               // nothing to do.\r
+       }\r
+       else if (unlikely(!(blockDev.state & DISK_STARTED)))\r
        {\r
                ready = 0;\r
                scsiDev.status = CHECK_CONDITION;\r
@@ -272,7 +279,7 @@ static int doTestUnitReady()
                scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED;\r
                scsiDev.phase = STATUS;\r
        }\r
-       else if (!(blockDev.state & DISK_PRESENT))\r
+       else if (unlikely(!(blockDev.state & DISK_PRESENT)))\r
        {\r
                ready = 0;\r
                scsiDev.status = CHECK_CONDITION;\r
@@ -280,7 +287,7 @@ static int doTestUnitReady()
                scsiDev.target->sense.asc = MEDIUM_NOT_PRESENT;\r
                scsiDev.phase = STATUS;\r
        }\r
-       else if (!(blockDev.state & DISK_INITIALISED))\r
+       else if (unlikely(!(blockDev.state & DISK_INITIALISED)))\r
        {\r
                ready = 0;\r
                scsiDev.status = CHECK_CONDITION;\r
@@ -297,7 +304,7 @@ int scsiDiskCommand()
        int commandHandled = 1;\r
 \r
        uint8 command = scsiDev.cdb[0];\r
-       if (command == 0x1B)\r
+       if (unlikely(command == 0x1B))\r
        {\r
                // START STOP UNIT\r
                // Enable or disable media access operations.\r
@@ -318,36 +325,16 @@ int scsiDiskCommand()
                        blockDev.state &= ~DISK_STARTED;\r
                }\r
        }\r
-       else if (command == 0x00)\r
+       else if (unlikely(command == 0x00))\r
        {\r
                // TEST UNIT READY\r
                doTestUnitReady();\r
        }\r
-       else if (!doTestUnitReady())\r
+       else if (unlikely(!doTestUnitReady()))\r
        {\r
                // Status and sense codes already set by doTestUnitReady\r
        }\r
-       else if (command == 0x04)\r
-       {\r
-               // FORMAT UNIT\r
-               // We don't really do any formatting, but we need to read the correct\r
-               // number of bytes in the DATA_OUT phase to make the SCSI host happy.\r
-\r
-               int fmtData = (scsiDev.cdb[1] & 0x10) ? 1 : 0;\r
-               if (fmtData)\r
-               {\r
-                       // We need to read the parameter list, but we don't know how\r
-                       // big it is yet. Start with the header.\r
-                       scsiDev.dataLen = 4;\r
-                       scsiDev.phase = DATA_OUT;\r
-                       scsiDev.postDataOutHook = doFormatUnitHeader;\r
-               }\r
-               else\r
-               {\r
-                       // No data to read, we're already finished!\r
-               }\r
-       }\r
-       else if (command == 0x08)\r
+       else if (likely(command == 0x08))\r
        {\r
                // READ(6)\r
                uint32 lba =\r
@@ -355,11 +342,10 @@ int scsiDiskCommand()
                        (((uint32) scsiDev.cdb[2]) << 8) +\r
                        scsiDev.cdb[3];\r
                uint32 blocks = scsiDev.cdb[4];\r
-               if (blocks == 0) blocks = 256;\r
+               if (unlikely(blocks == 0)) blocks = 256;\r
                doRead(lba, blocks);\r
        }\r
-\r
-       else if (command == 0x28)\r
+       else if (likely(command == 0x28))\r
        {\r
                // READ(10)\r
                // Ignore all cache control bits - we don't support a memory cache.\r
@@ -375,90 +361,110 @@ int scsiDiskCommand()
 \r
                doRead(lba, blocks);\r
        }\r
-\r
-       else if (command == 0x25)\r
+       else if (likely(command == 0x0A))\r
        {\r
-               // READ CAPACITY\r
-               doReadCapacity();\r
-       }\r
-\r
-       else if (command == 0x0B)\r
-       {\r
-               // SEEK(6)\r
+               // WRITE(6)\r
                uint32 lba =\r
                        (((uint32) scsiDev.cdb[1] & 0x1F) << 16) +\r
                        (((uint32) scsiDev.cdb[2]) << 8) +\r
                        scsiDev.cdb[3];\r
-\r
-               doSeek(lba);\r
+               uint32 blocks = scsiDev.cdb[4];\r
+               if (unlikely(blocks == 0)) blocks = 256;\r
+               doWrite(lba, blocks);\r
        }\r
-\r
-       else if (command == 0x2B)\r
+       else if (likely(command == 0x2A) || // WRITE(10)\r
+               unlikely(command == 0x2E)) // WRITE AND VERIFY\r
        {\r
-               // SEEK(10)\r
+               // Ignore all cache control bits - we don't support a memory cache.\r
+               // Don't bother verifying either. The SD card likely stores ECC\r
+               // along with each flash row.\r
+\r
                uint32 lba =\r
                        (((uint32) scsiDev.cdb[2]) << 24) +\r
                        (((uint32) scsiDev.cdb[3]) << 16) +\r
                        (((uint32) scsiDev.cdb[4]) << 8) +\r
                        scsiDev.cdb[5];\r
+               uint32 blocks =\r
+                       (((uint32) scsiDev.cdb[7]) << 8) +\r
+                       scsiDev.cdb[8];\r
 \r
-               doSeek(lba);\r
+               doWrite(lba, blocks);\r
        }\r
-       else if (command == 0x0A)\r
+\r
+       else if (unlikely(command == 0x04))\r
        {\r
-               // WRITE(6)\r
+               // FORMAT UNIT\r
+               // We don't really do any formatting, but we need to read the correct\r
+               // number of bytes in the DATA_OUT phase to make the SCSI host happy.\r
+\r
+               int fmtData = (scsiDev.cdb[1] & 0x10) ? 1 : 0;\r
+               if (fmtData)\r
+               {\r
+                       // We need to read the parameter list, but we don't know how\r
+                       // big it is yet. Start with the header.\r
+                       scsiDev.dataLen = 4;\r
+                       scsiDev.phase = DATA_OUT;\r
+                       scsiDev.postDataOutHook = doFormatUnitHeader;\r
+               }\r
+               else\r
+               {\r
+                       // No data to read, we're already finished!\r
+               }\r
+       }\r
+       else if (unlikely(command == 0x25))\r
+       {\r
+               // READ CAPACITY\r
+               doReadCapacity();\r
+       }\r
+       else if (unlikely(command == 0x0B))\r
+       {\r
+               // SEEK(6)\r
                uint32 lba =\r
                        (((uint32) scsiDev.cdb[1] & 0x1F) << 16) +\r
                        (((uint32) scsiDev.cdb[2]) << 8) +\r
                        scsiDev.cdb[3];\r
-               uint32 blocks = scsiDev.cdb[4];\r
-               if (blocks == 0) blocks = 256;\r
-               doWrite(lba, blocks);\r
+\r
+               doSeek(lba);\r
        }\r
 \r
-       else if (command == 0x2A)\r
+       else if (unlikely(command == 0x2B))\r
        {\r
-               // WRITE(10)\r
-               // Ignore all cache control bits - we don't support a memory cache.\r
-\r
+               // SEEK(10)\r
                uint32 lba =\r
                        (((uint32) scsiDev.cdb[2]) << 24) +\r
                        (((uint32) scsiDev.cdb[3]) << 16) +\r
                        (((uint32) scsiDev.cdb[4]) << 8) +\r
                        scsiDev.cdb[5];\r
-               uint32 blocks =\r
-                       (((uint32) scsiDev.cdb[7]) << 8) +\r
-                       scsiDev.cdb[8];\r
 \r
-               doWrite(lba, blocks);\r
+               doSeek(lba);\r
        }\r
-       else if (command == 0x36)\r
+       else if (unlikely(command == 0x36))\r
        {\r
                // LOCK UNLOCK CACHE\r
                // We don't have a cache to lock data into. do nothing.\r
        }\r
-       else if (command == 0x34)\r
+       else if (unlikely(command == 0x34))\r
        {\r
                // PRE-FETCH.\r
                // We don't have a cache to pre-fetch into. do nothing.\r
        }\r
-       else if (command == 0x1E)\r
+       else if (unlikely(command == 0x1E))\r
        {\r
                // PREVENT ALLOW MEDIUM REMOVAL\r
                // Not much we can do to prevent the user removing the SD card.\r
                // do nothing.\r
        }\r
-       else if (command == 0x01)\r
+       else if (unlikely(command == 0x01))\r
        {\r
                // REZERO UNIT\r
                // Set the lun to a vendor-specific state. Ignore.\r
        }\r
-       else if (command == 0x35)\r
+       else if (unlikely(command == 0x35))\r
        {\r
                // SYNCHRONIZE CACHE\r
                // We don't have a cache. do nothing.\r
        }\r
-       else if (command == 0x2F)\r
+       else if (unlikely(command == 0x2F))\r
        {\r
                // VERIFY\r
                // TODO: When they supply data to verify, we should read the data and\r
@@ -512,15 +518,27 @@ void scsiDiskPoll()
                int scsiActive = 0;\r
                int sdActive = 0;\r
                while ((i < totalSDSectors) &&\r
-                       (scsiDev.phase == DATA_IN) &&\r
-                       !scsiDev.resetFlag)\r
+                       likely(scsiDev.phase == DATA_IN) &&\r
+                       likely(!scsiDev.resetFlag))\r
                {\r
-                       if ((sdActive == 1) && sdReadSectorDMAPoll())\r
+                       // Wait for the next DMA interrupt. It's beneficial to halt the\r
+                       // processor to give the DMA controller more memory bandwidth to\r
+                       // work with.\r
+                       // We're optimistically assuming a race condition won't occur\r
+                       // between these checks and the interrupt handers. The 1ms\r
+                       // systick timer interrupt saves us on the event of a race.\r
+                       int scsiBusy = scsiDMABusy();\r
+                       int sdBusy = sdDMABusy();\r
+                       if (scsiBusy && sdBusy) __WFI();\r
+\r
+                       if (sdActive && !sdBusy && sdReadSectorDMAPoll())\r
                        {\r
                                sdActive = 0;\r
                                prep++;\r
                        }\r
-                       else if ((sdActive == 0) && (prep - i < buffers) && (prep < totalSDSectors))\r
+                       else if (!sdActive &&\r
+                               (prep - i < buffers) &&\r
+                               (prep < totalSDSectors))\r
                        {\r
                                // Start an SD transfer if we have space.\r
                                if (transfer.multiBlock)\r
@@ -534,12 +552,12 @@ void scsiDiskPoll()
                                sdActive = 1;\r
                        }\r
 \r
-                       if ((scsiActive == 1) && scsiWriteDMAPoll())\r
+                       if (scsiActive && !scsiBusy && scsiWriteDMAPoll())\r
                        {\r
                                scsiActive = 0;\r
                                ++i;\r
                        }\r
-                       else if ((scsiActive == 0) && ((prep - i) > 0))\r
+                       else if (!scsiActive && ((prep - i) > 0))\r
                        {\r
                                int dmaBytes = SD_SECTOR_SIZE;\r
                                if ((i % sdPerScsi) == (sdPerScsi - 1))\r
@@ -575,16 +593,26 @@ void scsiDiskPoll()
                int sdActive = 0;\r
 \r
                while ((i < totalSDSectors) &&\r
-                       ((scsiDev.phase == DATA_OUT) || // scsiDisconnect keeps our phase.\r
+                       (likely(scsiDev.phase == DATA_OUT) || // scsiDisconnect keeps our phase.\r
                                scsiComplete) &&\r
-                       !scsiDev.resetFlag)\r
+                       likely(!scsiDev.resetFlag))\r
                {\r
-                       if ((sdActive == 1) && sdWriteSectorDMAPoll(i == (totalSDSectors - 1)))\r
+                       // Wait for the next DMA interrupt. It's beneficial to halt the\r
+                       // processor to give the DMA controller more memory bandwidth to\r
+                       // work with.\r
+                       // We're optimistically assuming a race condition won't occur\r
+                       // between these checks and the interrupt handers. The 1ms\r
+                       // systick timer interrupt saves us on the event of a race.\r
+                       int scsiBusy = scsiDMABusy();\r
+                       int sdBusy = sdDMABusy();\r
+                       if (scsiBusy && sdBusy) __WFI();\r
+\r
+                       if (sdActive && !sdBusy && sdWriteSectorDMAPoll(i == (totalSDSectors - 1)))\r
                        {\r
                                sdActive = 0;\r
                                i++;\r
                        }\r
-                       else if ((sdActive == 0) && ((prep - i) > 0))\r
+                       else if (!sdActive && ((prep - i) > 0))\r
                        {\r
                                // Start an SD transfer if we have space.\r
                                sdWriteMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (i % buffers)]);\r
@@ -593,16 +621,16 @@ void scsiDiskPoll()
 \r
                        uint32_t now = getTime_ms();\r
 \r
-                       if ((scsiActive == 1) && scsiReadDMAPoll())\r
+                       if (scsiActive && !scsiBusy && scsiReadDMAPoll())\r
                        {\r
                                scsiActive = 0;\r
                                ++prep;\r
                                lastActivityTime = now;\r
                        }\r
-                       else if ((scsiActive == 0) &&\r
+                       else if (!scsiActive &&\r
                                ((prep - i) < buffers) &&\r
                                (prep < totalSDSectors) &&\r
-                               !scsiDisconnected)\r
+                               likely(!scsiDisconnected))\r
                        {\r
                                int dmaBytes = SD_SECTOR_SIZE;\r
                                if ((prep % sdPerScsi) == (sdPerScsi - 1))\r
@@ -615,10 +643,10 @@ void scsiDiskPoll()
                        }\r
                        else if (\r
                                (scsiActive == 0) &&\r
-                               !scsiDisconnected &&\r
-                               scsiDev.discPriv &&\r
-                               (diffTime_ms(lastActivityTime, now) >= 20) &&\r
-                               (scsiDev.phase == DATA_OUT))\r
+                               likely(!scsiDisconnected) &&\r
+                               unlikely(scsiDev.discPriv) &&\r
+                               unlikely(diffTime_ms(lastActivityTime, now) >= 20) &&\r
+                               likely(scsiDev.phase == DATA_OUT))\r
                        {\r
                                // We're transferring over the SCSI bus faster than the SD card\r
                                // can write.  There is no more buffer space once we've finished\r
@@ -631,12 +659,12 @@ void scsiDiskPoll()
                                scsiDisconnected = 1;\r
                                lastActivityTime = getTime_ms();\r
                        }\r
-                       else if (scsiDisconnected &&\r
+                       else if (unlikely(scsiDisconnected) &&\r
                                (\r
                                        (prep == i) || // Buffers empty.\r
                                        // Send some messages every 100ms so we don't timeout.\r
                                        // At a minimum, a reselection involves an IDENTIFY message.\r
-                                       (diffTime_ms(lastActivityTime, now) >= 100)\r
+                                       unlikely(diffTime_ms(lastActivityTime, now) >= 100)\r
                                ))\r
                        {\r
                                int reconnected = scsiReconnect();\r
@@ -652,13 +680,13 @@ void scsiDiskPoll()
                                }\r
                        }\r
                        else if (\r
-                               !scsiComplete &&\r
+                               likely(!scsiComplete) &&\r
                                (sdActive == 1) &&\r
                                (prep == totalSDSectors) && // All scsi data read and buffered\r
-                               !scsiDev.discPriv && // Prefer disconnect where possible.\r
-                               (diffTime_ms(lastActivityTime, now) >= 150) &&\r
+                               likely(!scsiDev.discPriv) && // Prefer disconnect where possible.\r
+                               unlikely(diffTime_ms(lastActivityTime, now) >= 150) &&\r
 \r
-                               (scsiDev.phase == DATA_OUT) &&\r
+                               likely(scsiDev.phase == DATA_OUT) &&\r
                                !(scsiDev.cdb[scsiDev.cdbLen - 1] & 0x01) // Not linked command\r
                                )\r
                        {\r
@@ -685,8 +713,8 @@ void scsiDiskPoll()
                }\r
                while (\r
                        !scsiDev.resetFlag &&\r
-                       scsiDisconnected &&\r
-                       (diffTime_ms(lastActivityTime, getTime_ms()) <= 10000))\r
+                       unlikely(scsiDisconnected) &&\r
+                       (elapsedTime_ms(lastActivityTime) <= 10000))\r
                {\r
                        scsiDisconnected = !scsiReconnect();\r
                }\r
@@ -723,7 +751,7 @@ void scsiDiskReset()
        transfer.currentBlock = 0;\r
 \r
        // Cancel long running commands!\r
-       if (transfer.inProgress == 1)\r
+       if (unlikely(transfer.inProgress == 1))\r
        {\r
                if (transfer.dir == TRANSFER_WRITE)\r
                {\r
@@ -736,8 +764,6 @@ void scsiDiskReset()
        }\r
        transfer.inProgress = 0;\r
        transfer.multiBlock = 0;\r
-               //              SD_CS_Write(1);\r
-\r
 }\r
 \r
 void scsiDiskInit()\r
@@ -757,3 +783,4 @@ void scsiDiskInit()
        #endif\r
 }\r
 \r
+#pragma GCC pop_options\r
index 5420beb..51dd319 100755 (executable)
@@ -14,6 +14,8 @@
 //\r
 //     You should have received a copy of the GNU General Public License\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
+#pragma GCC push_options\r
+#pragma GCC optimize("-flto")\r
 \r
 #include "device.h"\r
 #include "scsi.h"\r
@@ -25,7 +27,7 @@
 static uint8 StandardResponse[] =\r
 {\r
 0x00, // "Direct-access device". AKA standard hard disk\r
-0x00, // device type qualifier\r
+0x00, // device type modifier\r
 0x02, // Complies with ANSI SCSI-2.\r
 0x01, // Response format is compatible with the old CCS format.\r
 0x1f, // standard length.\r
@@ -112,6 +114,7 @@ void scsiInquiry()
                {\r
                        const TargetConfig* config = scsiDev.target->cfg;\r
                        memcpy(scsiDev.data, StandardResponse, sizeof(StandardResponse));\r
+                       scsiDev.data[1] = scsiDev.target->cfg->deviceTypeModifier;\r
                        memcpy(&scsiDev.data[8], config->vendor, sizeof(config->vendor));\r
                        memcpy(&scsiDev.data[16], config->prodId, sizeof(config->prodId));\r
                        memcpy(&scsiDev.data[32], config->revision, sizeof(config->revision));\r
@@ -203,3 +206,4 @@ void scsiInquiry()
        }\r
 }\r
 \r
+#pragma GCC pop_options\r
index 8ad6dad..47cc093 100755 (executable)
@@ -14,6 +14,8 @@
 //
 //     You should have received a copy of the GNU General Public License
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "led.h"
 
@@ -75,3 +77,4 @@ void ledOff()
 #endif
 }
 
+#pragma GCC pop_options
index 00f9f83..58e4ca8 100755 (executable)
@@ -14,6 +14,8 @@
 //\r
 //     You should have received a copy of the GNU General Public License\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
+#pragma GCC push_options\r
+#pragma GCC optimize("-flto")\r
 \r
 #include "device.h"\r
 #include "scsi.h"\r
@@ -59,13 +61,21 @@ int main()
                scsiDiskPoll();\r
                configPoll();\r
 \r
-               uint32_t now = getTime_ms();\r
-               if (diffTime_ms(lastSDPoll, now) > 200)\r
+               if (unlikely(scsiDev.phase == BUS_FREE))\r
                {\r
-                       lastSDPoll = now;\r
-                       sdPoll();\r
+                       if (unlikely(elapsedTime_ms(lastSDPoll) > 200))\r
+                       {\r
+                               lastSDPoll = getTime_ms();\r
+                               sdPoll();\r
+                       }\r
+                       else\r
+                       {\r
+                               // Wait for our 1ms timer to save some power.\r
+                               __WFI();\r
+                       }\r
                }\r
        }\r
        return 0;\r
 }\r
 \r
+#pragma GCC pop_options\r
index e748b1b..c66608a 100755 (executable)
@@ -15,6 +15,8 @@
 //\r
 //     You should have received a copy of the GNU General Public License\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
+#pragma GCC push_options\r
+#pragma GCC optimize("-flto")\r
 \r
 #include "device.h"\r
 #include "scsi.h"\r
@@ -152,8 +154,6 @@ static void doModeSense(
        }\r
        else\r
        {\r
-               int pageFound = 1;\r
-\r
                ////////////// Mode Parameter Header\r
                ////////////////////////////////////\r
 \r
@@ -243,22 +243,25 @@ static void doModeSense(
                        scsiDev.data[idx++] = bytesPerSector & 0xFF;\r
                }\r
 \r
-               switch (pageCode)\r
-               {\r
-               case 0x3F:\r
-                       // EVERYTHING\r
+               int pageFound = 0;\r
 \r
-               case 0x01:\r
+               if (pageCode == 0x01 || pageCode == 0x3F)\r
+               {\r
+                       pageFound = 1;\r
                        pageIn(pc, idx, ReadWriteErrorRecoveryPage, sizeof(ReadWriteErrorRecoveryPage));\r
                        idx += sizeof(ReadWriteErrorRecoveryPage);\r
-                       if (pageCode != 0x3f) break;\r
+               }\r
 \r
-               case 0x02:\r
+               if (pageCode == 0x02 || pageCode == 0x3F)\r
+               {\r
+                       pageFound = 1;\r
                        pageIn(pc, idx, DisconnectReconnectPage, sizeof(DisconnectReconnectPage));\r
                        idx += sizeof(DisconnectReconnectPage);\r
-                       if (pageCode != 0x3f) break;\r
+               }\r
 \r
-               case 0x03:\r
+               if (pageCode == 0x03 || pageCode == 0x3F)\r
+               {\r
+                       pageFound = 1;\r
                        pageIn(pc, idx, FormatDevicePage, sizeof(FormatDevicePage));\r
                        if (pc != 0x01)\r
                        {\r
@@ -275,10 +278,11 @@ static void doModeSense(
                        }\r
 \r
                        idx += sizeof(FormatDevicePage);\r
-                       if (pageCode != 0x3f) break;\r
+               }\r
 \r
-               case 0x04:\r
+               if (pageCode == 0x04 || pageCode == 0x3F)\r
                {\r
+                       pageFound = 1;\r
                        pageIn(pc, idx, RigidDiskDriveGeometry, sizeof(RigidDiskDriveGeometry));\r
 \r
                        if (pc != 0x01)\r
@@ -305,25 +309,40 @@ static void doModeSense(
                        }\r
 \r
                        idx += sizeof(RigidDiskDriveGeometry);\r
-                       if (pageCode != 0x3f) break;\r
                }\r
 \r
-               case 0x08:\r
+               // DON'T output the following pages for SCSI1 hosts. They get upset when\r
+               // we have more data to send than the allocation length provided.\r
+               // (ie. Try not to output any more pages below this comment)\r
+\r
+\r
+               if (!scsiDev.compatMode && (pageCode == 0x08 || pageCode == 0x3F))\r
+               {\r
+                       pageFound = 1;\r
                        pageIn(pc, idx, CachingPage, sizeof(CachingPage));\r
                        idx += sizeof(CachingPage);\r
-                       if (pageCode != 0x3f) break;\r
+               }\r
 \r
-               case 0x0A:\r
+               if (!scsiDev.compatMode && (pageCode == 0x0A || pageCode == 0x3F))\r
+               {\r
+                       pageFound = 1;\r
                        pageIn(pc, idx, ControlModePage, sizeof(ControlModePage));\r
                        idx += sizeof(ControlModePage);\r
-                       if (pageCode != 0x3f) break;\r
+               }\r
 \r
-               case 0x30:\r
+               if ((\r
+                               (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_APPLE) ||\r
+                               (idx + sizeof(AppleVendorPage) <= allocLength)\r
+                       ) &&\r
+                       (pageCode == 0x30 || pageCode == 0x3F))\r
+               {\r
+                       pageFound = 1;\r
                        pageIn(pc, idx, AppleVendorPage, sizeof(AppleVendorPage));\r
                        idx += sizeof(AppleVendorPage);\r
-                       break;\r
+               }\r
 \r
-               default:\r
+               if (!pageFound)\r
+               {\r
                        // Unknown Page Code\r
                        pageFound = 0;\r
                        scsiDev.status = CHECK_CONDITION;\r
@@ -331,15 +350,7 @@ static void doModeSense(
                        scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
                        scsiDev.phase = STATUS;\r
                }\r
-\r
-\r
-               if (idx > allocLength)\r
-               {\r
-                       // Chop the reply off early if shorter length is requested\r
-                       idx = allocLength;\r
-               }\r
-\r
-               if (pageFound)\r
+               else\r
                {\r
                        // Go back and fill out the mode data length\r
                        if (sixByteCmd)\r
@@ -353,17 +364,9 @@ static void doModeSense(
                                scsiDev.data[1] = (idx - 2);\r
                        }\r
 \r
-                       scsiDev.dataLen = idx;\r
+                       scsiDev.dataLen = idx > allocLength ? allocLength : idx;\r
                        scsiDev.phase = DATA_IN;\r
                }\r
-               else\r
-               {\r
-                       // Page not found\r
-                       scsiDev.status = CHECK_CONDITION;\r
-                       scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
-                       scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
-                       scsiDev.phase = STATUS;\r
-               }\r
        }\r
 }\r
 \r
@@ -538,4 +541,4 @@ int scsiModeCommand()
        return commandHandled;\r
 }\r
 \r
-\r
+#pragma GCC pop_options\r
index 63739e0..15622d5 100755 (executable)
@@ -14,6 +14,8 @@
 //\r
 //     You should have received a copy of the GNU General Public License\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
+#pragma GCC push_options\r
+#pragma GCC optimize("-flto")\r
 \r
 #include "device.h"\r
 #include "scsi.h"\r
@@ -28,6 +30,7 @@
 #include "disk.h"\r
 #include "time.h"\r
 #include "cdrom.h"\r
+#include "debug.h"\r
 \r
 #include <string.h>\r
 \r
@@ -50,7 +53,16 @@ static void enter_BusFree()
 {\r
        // This delay probably isn't needed for most SCSI hosts, but it won't\r
        // hurt either. It's possible some of the samplers needed this delay.\r
-       CyDelayUs(2);\r
+       if (scsiDev.compatMode)\r
+       {\r
+               CyDelayUs(2);\r
+       }\r
+\r
+       if (scsiDev.status != GOOD && isDebugEnabled())\r
+       {\r
+               // We want to capture debug information for failure cases.\r
+               CyDelay(64);\r
+       }\r
 \r
        SCSI_ClearPin(SCSI_Out_BSY);\r
        // We now have a Bus Clear Delay of 800ns to release remaining signals.\r
@@ -75,7 +87,7 @@ void process_MessageIn()
        scsiEnterPhase(MESSAGE_IN);\r
        scsiWriteByte(scsiDev.msgIn);\r
 \r
-       if (scsiDev.atnFlag)\r
+       if (unlikely(scsiDev.atnFlag))\r
        {\r
                // If there was a parity error, we go\r
                // back to MESSAGE_OUT first, get out parity error message, then come\r
@@ -253,7 +265,7 @@ static void process_Command()
 \r
        scsiDev.cmdCount++;\r
 \r
-       if (scsiDev.resetFlag)\r
+       if (unlikely(scsiDev.resetFlag))\r
        {\r
                // Don't log bogus commands\r
                scsiDev.cmdCount--;\r
@@ -340,6 +352,12 @@ static void process_Command()
        {\r
                enter_Status(CONFLICT);\r
        }\r
+       else if (scsiDiskCommand())\r
+       {\r
+               // Already handled.\r
+               // check for the performance-critical read/write\r
+               // commands ASAP.\r
+       }\r
        else if (command == 0x1C)\r
        {\r
                scsiReceiveDiagnostic();\r
@@ -348,14 +366,17 @@ static void process_Command()
        {\r
                scsiSendDiagnostic();\r
        }\r
+       else if (command == 0x3B)\r
+       {\r
+               scsiWriteBuffer();\r
+       }\r
        else if (command == 0x3C)\r
        {\r
                scsiReadBuffer();\r
        }\r
        else if (\r
-               !scsiModeCommand() &&\r
-               !scsiDiskCommand() &&\r
-               !scsiCDRomCommand())\r
+               !scsiCDRomCommand() &&\r
+               !scsiModeCommand())\r
        {\r
                scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
                scsiDev.target->sense.asc = INVALID_COMMAND_OPERATION_CODE;\r
@@ -515,7 +536,7 @@ static void process_SelectionPhase()
        if (!bsy && sel &&\r
                target &&\r
                (goodParity || !(target->cfg->flags & CONFIG_ENABLE_PARITY) || !atnFlag) &&\r
-               (maskBitCount <= 2))\r
+               likely(maskBitCount <= 2))\r
        {\r
                scsiDev.target = target;\r
 \r
@@ -546,7 +567,7 @@ static void process_SelectionPhase()
                scsiDev.selCount++;\r
 \r
                // Wait until the end of the selection phase.\r
-               while (!scsiDev.resetFlag)\r
+               while (likely(!scsiDev.resetFlag))\r
                {\r
                        if (!SCSI_ReadFilt(SCSI_Filt_SEL))\r
                        {\r
@@ -686,20 +707,32 @@ static void process_MessageOut()
                // Extended message.\r
                int msgLen = scsiReadByte();\r
                if (msgLen == 0) msgLen = 256;\r
+               uint8_t extmsg[256];\r
                for (i = 0; i < msgLen && !scsiDev.resetFlag; ++i)\r
                {\r
                        // Discard bytes.\r
-                       scsiReadByte();\r
+                       extmsg[i] = scsiReadByte();\r
+               }\r
+               \r
+               if (extmsg[0] == 3 && msgLen == 2) // Wide Data Request\r
+               {\r
+                       // Negotiate down to 8bit\r
+                       scsiEnterPhase(MESSAGE_IN);\r
+                       static const uint8_t WDTR[] = {0x01, 0x02, 0x03, 0x00};\r
+                       scsiWrite(WDTR, sizeof(WDTR));\r
+               }\r
+               else if (extmsg[0] == 1 && msgLen == 5) // Synchronous data request\r
+               {\r
+                       // Negotiate back to async\r
+                       scsiEnterPhase(MESSAGE_IN);\r
+                       static const uint8_t SDTR[] = {0x01, 0x03, 0x01, 0x00, 0x00};\r
+                       scsiWrite(SDTR, sizeof(SDTR));\r
+               }\r
+               else\r
+               {\r
+                       // Not supported\r
+                       messageReject();\r
                }\r
-\r
-               // We don't support ANY extended messages.\r
-               // Modify Data Pointer:  We don't support reselection.\r
-               // Wide Data Transfer Request: No. 8bit only.\r
-               // Synchronous data transfer request. No, we can't do that.\r
-               // We don't support any 2-byte messages either.\r
-               // And we don't support any optional 1-byte messages.\r
-               // In each case, the correct response is MESSAGE REJECT.\r
-               messageReject();\r
        }\r
        else\r
        {\r
@@ -712,7 +745,7 @@ static void process_MessageOut()
 \r
 void scsiPoll(void)\r
 {\r
-       if (scsiDev.resetFlag)\r
+       if (unlikely(scsiDev.resetFlag))\r
        {\r
                scsiReset();\r
                if ((scsiDev.resetFlag = SCSI_ReadFilt(SCSI_Filt_RST)))\r
@@ -932,7 +965,7 @@ int scsiReconnect()
                        while (\r
                                !bsy &&\r
                                !scsiDev.resetFlag &&\r
-                               (diffTime_ms(waitStart_ms, getTime_ms()) < 250))\r
+                               (elapsedTime_ms(waitStart_ms) < 250))\r
                        {\r
                                bsy = SCSI_ReadFilt(SCSI_Filt_BSY);\r
                        }\r
@@ -967,3 +1000,4 @@ int scsiReconnect()
        return reconnected;\r
 }\r
 \r
+#pragma GCC pop_options\r
index d7e2404..2a48af3 100755 (executable)
@@ -147,4 +147,10 @@ void scsiPoll(void);
 void scsiDisconnect(void);
 int scsiReconnect(void);
 
+
+// Utility macros, consistent with the Linux Kernel code.
+#define likely(x)       __builtin_expect(!!(x), 1)
+#define unlikely(x)     __builtin_expect(!!(x), 0)
+//#define likely(x)       (x)
+//#define unlikely(x)     (x)
 #endif
index b6c4e64..5952b85 100755 (executable)
@@ -14,6 +14,8 @@
 //\r
 //     You should have received a copy of the GNU General Public License\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
+#pragma GCC push_options\r
+#pragma GCC optimize("-flto")\r
 \r
 #include "device.h"\r
 #include "scsi.h"\r
@@ -42,19 +44,19 @@ static uint8 scsiDmaTxTd[1] = { CY_DMA_INVALID_TD };
 // Source of dummy bytes for DMA reads\r
 static uint8 dummyBuffer = 0xFF;\r
 \r
-volatile static uint8 rxDMAComplete;\r
-volatile static uint8 txDMAComplete;\r
+volatile uint8_t scsiRxDMAComplete;\r
+volatile uint8_t scsiTxDMAComplete;\r
 \r
 CY_ISR_PROTO(scsiRxCompleteISR);\r
 CY_ISR(scsiRxCompleteISR)\r
 {\r
-       rxDMAComplete = 1;\r
+       scsiRxDMAComplete = 1;\r
 }\r
 \r
 CY_ISR_PROTO(scsiTxCompleteISR);\r
 CY_ISR(scsiTxCompleteISR)\r
 {\r
-       txDMAComplete = 1;\r
+       scsiTxDMAComplete = 1;\r
 }\r
 \r
 CY_ISR_PROTO(scsiResetISR);\r
@@ -80,14 +82,14 @@ scsiReadDBxPins()
 uint8_t\r
 scsiReadByte(void)\r
 {\r
-       while (scsiPhyTxFifoFull() && !scsiDev.resetFlag) {}\r
+       while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}\r
        scsiPhyTx(0);\r
 \r
-       while (scsiPhyRxFifoEmpty() && !scsiDev.resetFlag) {}\r
+       while (scsiPhyRxFifoEmpty() && likely(!scsiDev.resetFlag)) {}\r
        uint8_t val = scsiPhyRx();\r
        scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
 \r
-       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
+       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
 \r
        return val;\r
 }\r
@@ -98,7 +100,7 @@ scsiReadPIO(uint8* data, uint32 count)
        int prep = 0;\r
        int i = 0;\r
 \r
-       while (i < count && !scsiDev.resetFlag)\r
+       while (i < count && likely(!scsiDev.resetFlag))\r
        {\r
                uint8_t status = scsiPhyStatus();\r
 \r
@@ -114,7 +116,7 @@ scsiReadPIO(uint8* data, uint32 count)
                }\r
        }\r
        scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
-       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
+       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
 }\r
 \r
 static void\r
@@ -136,7 +138,7 @@ doRxSingleDMA(uint8* data, uint32 count)
                TD_INC_DST_ADR |\r
                        SCSI_RX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete\r
                );\r
-       \r
+\r
        CyDmaTdSetAddress(\r
                scsiDmaTxTd[0],\r
                LO16((uint32)&dummyBuffer),\r
@@ -146,18 +148,18 @@ doRxSingleDMA(uint8* data, uint32 count)
                LO16((uint32)scsiTarget_datapath__F1_REG),\r
                LO16((uint32)data)\r
                );\r
-       \r
+\r
        CyDmaChSetInitialTd(scsiDmaTxChan, scsiDmaTxTd[0]);\r
        CyDmaChSetInitialTd(scsiDmaRxChan, scsiDmaRxTd[0]);\r
-       \r
+\r
        // The DMA controller is a bit trigger-happy. It will retain\r
        // a drq request that was triggered while the channel was\r
        // disabled.\r
        CyDmaClearPendingDrq(scsiDmaTxChan);\r
        CyDmaClearPendingDrq(scsiDmaRxChan);\r
 \r
-       txDMAComplete = 0;\r
-       rxDMAComplete = 0;\r
+       scsiTxDMAComplete = 0;\r
+       scsiRxDMAComplete = 0;\r
 \r
        CyDmaChEnable(scsiDmaRxChan, 1);\r
        CyDmaChEnable(scsiDmaTxChan, 1);\r
@@ -178,9 +180,13 @@ scsiReadDMA(uint8* data, uint32 count)
 int\r
 scsiReadDMAPoll()\r
 {\r
-       if (txDMAComplete && rxDMAComplete && (scsiPhyStatus() & SCSI_PHY_TX_COMPLETE))\r
+       if (scsiTxDMAComplete && scsiRxDMAComplete)\r
        {\r
-               if (dmaSentCount == dmaTotalCount)\r
+               // Wait until our scsi signals are consistent. This should only be\r
+               // a few cycles.\r
+               while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}\r
+\r
+               if (likely(dmaSentCount == dmaTotalCount))\r
                {\r
                        dmaInProgress = 0;\r
                        scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
@@ -191,7 +197,7 @@ scsiReadDMAPoll()
                        // Transfer was too large for a single DMA transfer. Continue\r
                        // to send remaining bytes.\r
                        uint32_t count = dmaTotalCount - dmaSentCount;\r
-                       if (count > MAX_DMA_BYTES) count = MAX_DMA_BYTES;\r
+                       if (unlikely(count > MAX_DMA_BYTES)) count = MAX_DMA_BYTES;\r
                        doRxSingleDMA(dmaBuffer + dmaSentCount, count);\r
                        dmaSentCount += count;\r
                        return 0;\r
@@ -213,26 +219,32 @@ scsiRead(uint8_t* data, uint32_t count)
        else\r
        {\r
                scsiReadDMA(data, count);\r
-               while (!scsiReadDMAPoll() && !scsiDev.resetFlag) {};\r
+               \r
+               // Wait for the next DMA interrupt (or the 1ms systick)\r
+               // It's beneficial to halt the processor to\r
+               // give the DMA controller more memory bandwidth to work with.\r
+               __WFI();\r
+               \r
+               while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) {};\r
        }\r
 }\r
 \r
 void\r
 scsiWriteByte(uint8 value)\r
 {\r
-       while (scsiPhyTxFifoFull() && !scsiDev.resetFlag) {}\r
+       while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}\r
        scsiPhyTx(value);\r
 \r
-       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
+       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
        scsiPhyRxFifoClear();\r
 }\r
 \r
 static void\r
-scsiWritePIO(uint8_t* data, uint32_t count)\r
+scsiWritePIO(const uint8_t* data, uint32_t count)\r
 {\r
        int i = 0;\r
 \r
-       while (i < count && !scsiDev.resetFlag)\r
+       while (i < count && likely(!scsiDev.resetFlag))\r
        {\r
                if (!scsiPhyTxFifoFull())\r
                {\r
@@ -241,12 +253,12 @@ scsiWritePIO(uint8_t* data, uint32_t count)
                }\r
        }\r
 \r
-       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
+       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
        scsiPhyRxFifoClear();\r
 }\r
 \r
 static void\r
-doTxSingleDMA(uint8* data, uint32 count)\r
+doTxSingleDMA(const uint8* data, uint32 count)\r
 {\r
        // Prepare DMA transfer\r
        dmaInProgress = 1;\r
@@ -269,14 +281,14 @@ doTxSingleDMA(uint8* data, uint32 count)
        // disabled.\r
        CyDmaClearPendingDrq(scsiDmaTxChan);\r
 \r
-       txDMAComplete = 0;\r
-       rxDMAComplete = 1;\r
+       scsiTxDMAComplete = 0;\r
+       scsiRxDMAComplete = 1;\r
 \r
        CyDmaChEnable(scsiDmaTxChan, 1);\r
 }\r
 \r
 void\r
-scsiWriteDMA(uint8* data, uint32 count)\r
+scsiWriteDMA(const uint8* data, uint32 count)\r
 {\r
        dmaSentCount = 0;\r
        dmaTotalCount = count;\r
@@ -290,9 +302,13 @@ scsiWriteDMA(uint8* data, uint32 count)
 int\r
 scsiWriteDMAPoll()\r
 {\r
-       if (txDMAComplete && (scsiPhyStatus() & SCSI_PHY_TX_COMPLETE))\r
+       if (scsiTxDMAComplete)\r
        {\r
-               if (dmaSentCount == dmaTotalCount)\r
+               // Wait until our scsi signals are consistent. This should only be\r
+               // a few cycles.\r
+               while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}\r
+\r
+               if (likely(dmaSentCount == dmaTotalCount))\r
                {\r
                        scsiPhyRxFifoClear();\r
                        dmaInProgress = 0;\r
@@ -303,7 +319,7 @@ scsiWriteDMAPoll()
                        // Transfer was too large for a single DMA transfer. Continue\r
                        // to send remaining bytes.\r
                        uint32_t count = dmaTotalCount - dmaSentCount;\r
-                       if (count > MAX_DMA_BYTES) count = MAX_DMA_BYTES;\r
+                       if (unlikely(count > MAX_DMA_BYTES)) count = MAX_DMA_BYTES;\r
                        doTxSingleDMA(dmaBuffer + dmaSentCount, count);\r
                        dmaSentCount += count;\r
                        return 0;\r
@@ -316,7 +332,7 @@ scsiWriteDMAPoll()
 }\r
 \r
 void\r
-scsiWrite(uint8_t* data, uint32_t count)\r
+scsiWrite(const uint8_t* data, uint32_t count)\r
 {\r
        if (count < 8)\r
        {\r
@@ -325,11 +341,17 @@ scsiWrite(uint8_t* data, uint32_t count)
        else\r
        {\r
                scsiWriteDMA(data, count);\r
-               while (!scsiWriteDMAPoll() && !scsiDev.resetFlag) {};\r
+               \r
+               // Wait for the next DMA interrupt (or the 1ms systick)\r
+               // It's beneficial to halt the processor to\r
+               // give the DMA controller more memory bandwidth to work with.\r
+               __WFI();\r
+\r
+               while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) {};\r
        }\r
 }\r
 \r
-static void busSettleDelay(void)\r
+static inline void busSettleDelay(void)\r
 {\r
        // Data Release time (switching IO) = 400ns\r
        // + Bus Settle time (switching phase) = 400ns.\r
@@ -356,7 +378,7 @@ void scsiPhyReset()
                dmaTotalCount = 0;\r
                CyDmaChSetRequest(scsiDmaTxChan, CY_DMA_CPU_TERM_CHAIN);\r
                CyDmaChSetRequest(scsiDmaRxChan, CY_DMA_CPU_TERM_CHAIN);\r
-               while (!(txDMAComplete && rxDMAComplete)) {}\r
+               while (!(scsiTxDMAComplete && scsiRxDMAComplete)) {}\r
 \r
                CyDmaChDisable(scsiDmaTxChan);\r
                CyDmaChDisable(scsiDmaRxChan);\r
@@ -406,7 +428,7 @@ static void scsiPhyInitDMA()
                                HI16(CYDEV_SRAM_BASE),\r
                                HI16(CYDEV_PERIPH_BASE)\r
                                );\r
-\r
+               \r
                CyDmaChDisable(scsiDmaRxChan);\r
                CyDmaChDisable(scsiDmaTxChan);\r
 \r
@@ -425,3 +447,4 @@ void scsiPhyInit()
 \r
        SCSI_RST_ISR_StartEx(scsiResetISR);\r
 }\r
+#pragma GCC pop_options\r
index bee2987..b4c0f79 100755 (executable)
@@ -67,6 +67,10 @@ enum FilteredInputs
 // Contains the odd-parity flag for a given 8-bit value.
 extern const uint8_t Lookup_OddParity[256];
 
+extern volatile uint8_t scsiRxDMAComplete;
+extern volatile uint8_t scsiTxDMAComplete;
+#define scsiDMABusy() (!(scsiRxDMAComplete && scsiTxDMAComplete))
+
 void scsiPhyReset(void);
 void scsiPhyInit(void);
 
@@ -76,8 +80,8 @@ void scsiReadDMA(uint8_t* data, uint32_t count);
 int scsiReadDMAPoll();
 
 void scsiWriteByte(uint8_t value);
-void scsiWrite(uint8_t* data, uint32_t count);
-void scsiWriteDMA(uint8_t* data, uint32_t count);
+void scsiWrite(const uint8_t* data, uint32_t count);
+void scsiWriteDMA(const uint8_t* data, uint32_t count);
 int scsiWriteDMAPoll();
 
 uint8_t scsiReadDBxPins(void);
index e0649bd..00163f3 100755 (executable)
@@ -14,6 +14,8 @@
 //\r
 //     You should have received a copy of the GNU General Public License\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
+#pragma GCC push_options\r
+#pragma GCC optimize("-flto")\r
 \r
 #include "device.h"\r
 #include "scsi.h"\r
@@ -37,10 +39,6 @@ static int sdIOState = SD_IDLE;
 static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL;\r
 static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL;\r
 \r
-// DMA descriptors\r
-static uint8 sdDMARxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };\r
-static uint8 sdDMATxTd[3] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };\r
-\r
 // Dummy location for DMA to send unchecked CRC bytes to\r
 static uint8 discardBuffer;\r
 \r
@@ -53,18 +51,18 @@ static uint8_t writeStartToken = 0xFC;
 // Source of dummy SPI bytes for DMA\r
 static uint8 dummyBuffer = 0xFF;\r
 \r
-volatile static uint8 rxDMAComplete;\r
-volatile static uint8 txDMAComplete;\r
+volatile uint8_t sdRxDMAComplete;\r
+volatile uint8_t sdTxDMAComplete;\r
 \r
 CY_ISR_PROTO(sdRxISR);\r
 CY_ISR(sdRxISR)\r
 {\r
-       rxDMAComplete = 1;\r
+       sdRxDMAComplete = 1;\r
 }\r
 CY_ISR_PROTO(sdTxISR);\r
 CY_ISR(sdTxISR)\r
 {\r
-       txDMAComplete = 1;\r
+       sdTxDMAComplete = 1;\r
 }\r
 \r
 static uint8 sdCrc7(uint8* chr, uint8 cnt, uint8 crc)\r
@@ -98,14 +96,23 @@ static uint16_t sdDoCommand(
        int useCRC,\r
        int use2byteResponse)\r
 {\r
-       uint8_t send[7];\r
+       int waitWhileBusy = (cmd != SD_GO_IDLE_STATE) && (cmd != SD_STOP_TRANSMISSION);\r
+\r
+       // "busy" probe. We'll examine the results later.\r
+       if (waitWhileBusy)\r
+       {\r
+               SDCard_WriteTxData(0xFF);\r
+       }\r
 \r
+       // send is static as the address must remain consistent for the static\r
+       // DMA descriptors to work.\r
+       static uint8_t send[7];\r
        send[0] = cmd | 0x40;\r
        send[1] = param >> 24;\r
        send[2] = param >> 16;\r
        send[3] = param >> 8;\r
        send[4] = param;\r
-       if (useCRC)\r
+       if (unlikely(useCRC))\r
        {\r
                send[5] = (sdCrc7(send, 5, 0) << 1) | 1;\r
        }\r
@@ -115,31 +122,52 @@ static uint16_t sdDoCommand(
        }\r
        send[6] = 0xFF; // Result code or stuff byte.\r
 \r
-       CyDmaTdSetConfiguration(sdDMATxTd[0], sizeof(send), CY_DMA_DISABLE_TD, TD_INC_SRC_ADR|SD_TX_DMA__TD_TERMOUT_EN);\r
-       CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&send), LO16((uint32)SDCard_TXDATA_PTR));\r
-       CyDmaTdSetConfiguration(sdDMARxTd[0], sizeof(send), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);\r
-       CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
+       static uint8_t dmaRxTd = CY_DMA_INVALID_TD;\r
+       static uint8_t dmaTxTd = CY_DMA_INVALID_TD;\r
+       if (unlikely(dmaRxTd == CY_DMA_INVALID_TD))\r
+       {\r
+               dmaRxTd = CyDmaTdAllocate();\r
+               dmaTxTd = CyDmaTdAllocate();\r
+               CyDmaTdSetConfiguration(dmaTxTd, sizeof(send), CY_DMA_DISABLE_TD, TD_INC_SRC_ADR|SD_TX_DMA__TD_TERMOUT_EN);\r
+               CyDmaTdSetAddress(dmaTxTd, LO16((uint32)&send), LO16((uint32)SDCard_TXDATA_PTR));\r
+               CyDmaTdSetConfiguration(dmaRxTd, sizeof(send), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);\r
+               CyDmaTdSetAddress(dmaRxTd, LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
+       }\r
+\r
+       sdTxDMAComplete = 0;\r
+       sdRxDMAComplete = 0;\r
+\r
+       CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd);\r
+       CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd);\r
+\r
+       // Some Samsung cards enter a busy-state after single-sector reads.\r
+       // But we also need to wait for R1B to complete from the multi-sector\r
+       // reads.\r
+       if (waitWhileBusy)\r
+       {\r
+               while (!(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)) {}\r
+               int busy = SDCard_ReadRxData() != 0xFF;\r
+               if (unlikely(busy))\r
+               {\r
+                       while (sdSpiByte(0xFF) != 0xFF) {}\r
+               }\r
+       }\r
+\r
        // The DMA controller is a bit trigger-happy. It will retain\r
        // a drq request that was triggered while the channel was\r
        // disabled.\r
        CyDmaClearPendingDrq(sdDMATxChan);\r
        CyDmaClearPendingDrq(sdDMARxChan);\r
 \r
-       txDMAComplete = 0;\r
-       rxDMAComplete = 0;\r
-\r
-       CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);\r
-       CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);\r
-\r
        // There is no flow control, so we must ensure we can read the bytes\r
        // before we start transmitting\r
        CyDmaChEnable(sdDMARxChan, 1);\r
        CyDmaChEnable(sdDMATxChan, 1);\r
 \r
-       while (!(txDMAComplete && rxDMAComplete)) {}\r
+       while (!(sdTxDMAComplete && sdRxDMAComplete)) { __WFI(); }\r
 \r
        uint16_t response = discardBuffer;\r
-       if (cmd == SD_STOP_TRANSMISSION)\r
+       if (unlikely(cmd == SD_STOP_TRANSMISSION))\r
        {\r
                // Stuff byte is required for this command only.\r
                // Part 1 Simplified standard 3.01\r
@@ -149,11 +177,11 @@ static uint16_t sdDoCommand(
        }\r
 \r
        uint32_t start = getTime_ms();\r
-       while ((response & 0x80) && (diffTime_ms(start, getTime_ms()) <= 200))\r
+       while ((response & 0x80) && likely(elapsedTime_ms(start) <= 200))\r
        {\r
                response = sdSpiByte(0xFF);\r
        }\r
-       if (use2byteResponse)\r
+       if (unlikely(use2byteResponse))\r
        {\r
                response = (response << 8) | sdSpiByte(0xFF);\r
        }\r
@@ -161,21 +189,13 @@ static uint16_t sdDoCommand(
 }\r
 \r
 \r
-static uint16_t sdCommandAndResponse(uint8_t cmd, uint32_t param)\r
+static inline uint16_t sdCommandAndResponse(uint8_t cmd, uint32_t param)\r
 {\r
-       // Some Samsung cards enter a busy-state after single-sector reads.\r
-       // But we also need to wait for R1B to complete from the multi-sector\r
-       // reads.\r
-       while (sdSpiByte(0xFF) == 0x00) {}\r
        return sdDoCommand(cmd, param, 0, 0);\r
 }\r
 \r
-static uint16_t sdCRCCommandAndResponse(uint8_t cmd, uint32_t param)\r
+static inline uint16_t sdCRCCommandAndResponse(uint8_t cmd, uint32_t param)\r
 {\r
-       // Some Samsung cards enter a busy-state after single-sector reads.\r
-       // But we also need to wait for R1B to complete from the multi-sector\r
-       // reads.\r
-       while (sdSpiByte(0xFF) == 0x00) {}\r
        return sdDoCommand(cmd, param, 1, 0);\r
 }\r
 \r
@@ -203,14 +223,14 @@ sdReadMultiSectorPrep()
                sdLBA = sdLBA * SD_SECTOR_SIZE;\r
        }\r
        v = sdCommandAndResponse(SD_READ_MULTIPLE_BLOCK, sdLBA);\r
-       if (v)\r
+       if (unlikely(v))\r
        {\r
                scsiDiskReset();\r
                sdClearStatus();\r
 \r
                scsiDev.status = CHECK_CONDITION;\r
                scsiDev.target->sense.code = HARDWARE_ERROR;\r
-               scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE;\r
+               scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
                scsiDev.phase = STATUS;\r
        }\r
        else\r
@@ -226,16 +246,16 @@ dmaReadSector(uint8_t* outputBuffer)
        // Don't wait more than 200ms.  The standard recommends 100ms.\r
        uint32_t start = getTime_ms();\r
        uint8_t token = sdSpiByte(0xFF);\r
-       while (token != 0xFE && (diffTime_ms(start, getTime_ms()) <= 200))\r
+       while (token != 0xFE && likely(elapsedTime_ms(start) <= 200))\r
        {\r
-               if (token && ((token & 0xE0) == 0))\r
+               if (unlikely(token && ((token & 0xE0) == 0)))\r
                {\r
                        // Error token!\r
                        break;\r
                }\r
                token = sdSpiByte(0xFF);\r
        }\r
-       if (token != 0xFE)\r
+       if (unlikely(token != 0xFE))\r
        {\r
                if (transfer.multiBlock)\r
                {\r
@@ -245,31 +265,41 @@ dmaReadSector(uint8_t* outputBuffer)
                {\r
                        scsiDev.status = CHECK_CONDITION;\r
                        scsiDev.target->sense.code = HARDWARE_ERROR;\r
-                       scsiDev.target->sense.asc = 0x4400 | token;\r
+                       scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;\r
                        scsiDev.phase = STATUS;\r
                }\r
                sdClearStatus();\r
                return;\r
        }\r
 \r
-       // Receive 512 bytes of data and then 2 bytes CRC.\r
-       CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE, sdDMARxTd[1], TD_INC_DST_ADR);\r
-       CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)outputBuffer));\r
-       CyDmaTdSetConfiguration(sdDMARxTd[1], 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);\r
-       CyDmaTdSetAddress(sdDMARxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
+       static uint8_t dmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD};\r
+       static uint8_t dmaTxTd = CY_DMA_INVALID_TD;\r
+       if (unlikely(dmaRxTd[0] == CY_DMA_INVALID_TD))\r
+       {\r
+               dmaRxTd[0] = CyDmaTdAllocate();\r
+               dmaRxTd[1] = CyDmaTdAllocate();\r
+               dmaTxTd = CyDmaTdAllocate();\r
+               \r
+               // Receive 512 bytes of data and then 2 bytes CRC.\r
+               CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE, dmaRxTd[1], TD_INC_DST_ADR);\r
+               CyDmaTdSetConfiguration(dmaRxTd[1], 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);\r
+               CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
+       \r
+               CyDmaTdSetConfiguration(dmaTxTd, SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
+               CyDmaTdSetAddress(dmaTxTd, LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
 \r
-       CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
-       CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
+       }\r
+       CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)outputBuffer));\r
 \r
        sdIOState = SD_DMA;\r
-       txDMAComplete = 0;\r
-       rxDMAComplete = 0;\r
+       sdTxDMAComplete = 0;\r
+       sdRxDMAComplete = 0;\r
 \r
        // Re-loading the initial TD's here is very important, or else\r
        // we'll be re-using the last-used TD, which would be the last\r
        // in the chain (ie. CRC TD)\r
-       CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);\r
-       CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);\r
+       CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd[0]);\r
+       CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd);\r
 \r
        // The DMA controller is a bit trigger-happy. It will retain\r
        // a drq request that was triggered while the channel was\r
@@ -286,7 +316,7 @@ dmaReadSector(uint8_t* outputBuffer)
 int\r
 sdReadSectorDMAPoll()\r
 {\r
-       if (rxDMAComplete && txDMAComplete)\r
+       if (sdRxDMAComplete && sdTxDMAComplete)\r
        {\r
                // DMA transfer is complete\r
                sdIOState = SD_IDLE;\r
@@ -306,14 +336,14 @@ void sdReadSingleSectorDMA(uint32_t lba, uint8_t* outputBuffer)
                lba = lba * SD_SECTOR_SIZE;\r
        }\r
        v = sdCommandAndResponse(SD_READ_SINGLE_BLOCK, lba);\r
-       if (v)\r
+       if (unlikely(v))\r
        {\r
                scsiDiskReset();\r
                sdClearStatus();\r
 \r
                scsiDev.status = CHECK_CONDITION;\r
                scsiDev.target->sense.code = HARDWARE_ERROR;\r
-               scsiDev.target->sense.asc = LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION;\r
+               scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
                scsiDev.phase = STATUS;\r
        }\r
        else\r
@@ -332,29 +362,26 @@ sdReadMultiSectorDMA(uint8_t* outputBuffer)
 \r
 void sdCompleteRead()\r
 {\r
-       if (sdIOState != SD_IDLE)\r
+       if (unlikely(sdIOState != SD_IDLE))\r
        {\r
                // Not much choice but to wait until we've completed the transfer.\r
                // Cancelling the transfer can't be done as we have no way to reset\r
                // the SD card.\r
                while (!sdReadSectorDMAPoll()) { /* spin */ }\r
        }\r
-       transfer.inProgress = 0;\r
-\r
-       // We cannot send even a single "padding" byte, as we normally would when\r
-       // sending a command.  If we've just finished reading the very last block\r
-       // on the card, then reading an additional dummy byte will just trigger\r
-       // an error condition as we're trying to read past-the-end of the storage\r
-       // device.\r
-       // ie. do not use sdCommandAndResponse here.\r
-       uint8 r1b = sdDoCommand(SD_STOP_TRANSMISSION, 0, 0, 0);\r
-\r
-       if (r1b)\r
+       \r
+       if (transfer.inProgress)\r
        {\r
-               scsiDev.status = CHECK_CONDITION;\r
-               scsiDev.target->sense.code = HARDWARE_ERROR;\r
-               scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR | r1b;\r
-               scsiDev.phase = STATUS;\r
+               transfer.inProgress = 0;\r
+               uint8 r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0);\r
+\r
+               if (unlikely(r1b))\r
+               {\r
+                       scsiDev.status = CHECK_CONDITION;\r
+                       scsiDev.target->sense.code = HARDWARE_ERROR;\r
+                       scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;\r
+                       scsiDev.phase = STATUS;\r
+               }\r
        }\r
 \r
        // R1b has an optional trailing "busy" signal, but we defer waiting on this.\r
@@ -374,22 +401,34 @@ static void sdWaitWriteBusy()
 void\r
 sdWriteMultiSectorDMA(uint8_t* outputBuffer)\r
 {\r
-       // Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte\r
-       // We need to do this without stopping the clock\r
-       CyDmaTdSetConfiguration(sdDMATxTd[0], 1, sdDMATxTd[1], TD_INC_SRC_ADR);\r
-       CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR));\r
+       static uint8_t dmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD};\r
+       static uint8_t dmaTxTd[3] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD, CY_DMA_INVALID_TD};\r
+       if (unlikely(dmaRxTd[0] == CY_DMA_INVALID_TD))\r
+       {\r
+               dmaRxTd[0] = CyDmaTdAllocate();\r
+               dmaRxTd[1] = CyDmaTdAllocate();\r
+               dmaTxTd[0] = CyDmaTdAllocate();\r
+               dmaTxTd[1] = CyDmaTdAllocate();\r
+               dmaTxTd[2] = CyDmaTdAllocate();\r
+               \r
+               // Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte\r
+               // We need to do this without stopping the clock\r
+               CyDmaTdSetConfiguration(dmaTxTd[0], 1, dmaTxTd[1], TD_INC_SRC_ADR);\r
+               CyDmaTdSetAddress(dmaTxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR));\r
 \r
-       CyDmaTdSetConfiguration(sdDMATxTd[1], SD_SECTOR_SIZE, sdDMATxTd[2], TD_INC_SRC_ADR);\r
-       CyDmaTdSetAddress(sdDMATxTd[1], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
+               CyDmaTdSetConfiguration(dmaTxTd[1], SD_SECTOR_SIZE, dmaTxTd[2], TD_INC_SRC_ADR);\r
+\r
+               CyDmaTdSetConfiguration(dmaTxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
+               CyDmaTdSetAddress(dmaTxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
+\r
+               CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 3, dmaRxTd[1], 0);\r
+               CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
+               CyDmaTdSetConfiguration(dmaRxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR);\r
+               CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer));\r
+       }\r
+       CyDmaTdSetAddress(dmaTxTd[1], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
 \r
-       CyDmaTdSetConfiguration(sdDMATxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
-       CyDmaTdSetAddress(sdDMATxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
 \r
-       CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE + 3, sdDMARxTd[1], 0);\r
-       CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
-       CyDmaTdSetConfiguration(sdDMARxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR);\r
-       CyDmaTdSetAddress(sdDMARxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer));\r
-       \r
        sdIOState = SD_DMA;\r
        // The DMA controller is a bit trigger-happy. It will retain\r
        // a drq request that was triggered while the channel was\r
@@ -397,14 +436,14 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer)
        CyDmaClearPendingDrq(sdDMATxChan);\r
        CyDmaClearPendingDrq(sdDMARxChan);\r
 \r
-       txDMAComplete = 0;\r
-       rxDMAComplete = 0;\r
+       sdTxDMAComplete = 0;\r
+       sdRxDMAComplete = 0;\r
 \r
        // Re-loading the initial TD's here is very important, or else\r
        // we'll be re-using the last-used TD, which would be the last\r
        // in the chain (ie. CRC TD)\r
-       CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);\r
-       CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);\r
+       CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd[0]);\r
+       CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd[0]);\r
 \r
        // There is no flow control, so we must ensure we can read the bytes\r
        // before we start transmitting\r
@@ -415,7 +454,7 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer)
 int\r
 sdWriteSectorDMAPoll(int sendStopToken)\r
 {\r
-       if (rxDMAComplete && txDMAComplete)\r
+       if (sdRxDMAComplete && sdTxDMAComplete)\r
        {\r
                if (sdIOState == SD_DMA)\r
                {\r
@@ -431,7 +470,7 @@ sdWriteSectorDMAPoll(int sendStopToken)
 \r
                        // At this point we should either have an accepted token, or we'll\r
                        // timeout and proceed into the error case below.\r
-                       if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted.\r
+                       if (unlikely(((dataToken & 0x1F) >> 1) != 0x2)) // Accepted.\r
                        {\r
                                sdIOState = SD_IDLE;\r
 \r
@@ -445,7 +484,7 @@ sdWriteSectorDMAPoll(int sendStopToken)
 \r
                                scsiDev.status = CHECK_CONDITION;\r
                                scsiDev.target->sense.code = HARDWARE_ERROR;\r
-                               scsiDev.target->sense.asc = 0x6900 | dataToken;\r
+                               scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
                                scsiDev.phase = STATUS;\r
                        }\r
                        else\r
@@ -492,7 +531,7 @@ sdWriteSectorDMAPoll(int sendStopToken)
 \r
 void sdCompleteWrite()\r
 {\r
-       if (sdIOState != SD_IDLE)\r
+       if (unlikely(sdIOState != SD_IDLE))\r
        {\r
                // Not much choice but to wait until we've completed the transfer.\r
                // Cancelling the transfer can't be done as we have no way to reset\r
@@ -500,13 +539,10 @@ void sdCompleteWrite()
                while (!sdWriteSectorDMAPoll(1)) { /* spin */ }\r
        }\r
 \r
-       transfer.inProgress = 0;\r
-\r
-       if (scsiDev.phase == DATA_OUT)\r
+       if (transfer.inProgress && likely(scsiDev.phase == DATA_OUT))\r
        {\r
-               sdSpiByte(0xFF);\r
                uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 0, 1);\r
-               if (r2)\r
+               if (unlikely(r2))\r
                {\r
                        sdClearStatus();\r
                        scsiDev.status = CHECK_CONDITION;\r
@@ -515,6 +551,7 @@ void sdCompleteWrite()
                        scsiDev.phase = STATUS;\r
                }\r
        }\r
+       transfer.inProgress = 0;\r
 }\r
 \r
 \r
@@ -569,7 +606,7 @@ static int sdOpCond()
                sdClearStatus();\r
 \r
        // Spec says to poll for 1 second.\r
-       } while ((status != 0) && (diffTime_ms(start, getTime_ms()) < 1000));\r
+       } while ((status != 0) && (elapsedTime_ms(start) < 1000));\r
 \r
        return status == 0;\r
 }\r
@@ -598,7 +635,7 @@ static int sdReadOCR()
 \r
        } while (!status &&\r
                !complete &&\r
-               (diffTime_ms(start, getTime_ms()) < 1000));\r
+               (elapsedTime_ms(start) < 1000));\r
 \r
        return (status == 0) && complete;\r
 }\r
@@ -702,12 +739,6 @@ static void sdInitDMA()
                CyDmaChDisable(sdDMATxChan);\r
                CyDmaChDisable(sdDMARxChan);\r
 \r
-               sdDMARxTd[0] = CyDmaTdAllocate();\r
-               sdDMARxTd[1] = CyDmaTdAllocate();\r
-               sdDMATxTd[0] = CyDmaTdAllocate();\r
-               sdDMATxTd[1] = CyDmaTdAllocate();\r
-               sdDMATxTd[2] = CyDmaTdAllocate();\r
-\r
                SD_RX_DMA_COMPLETE_StartEx(sdRxISR);\r
                SD_TX_DMA_COMPLETE_StartEx(sdTxISR);\r
        }\r
@@ -791,6 +822,7 @@ int sdInit()
        goto out;\r
 \r
 bad:\r
+       SD_Data_Clk_SetDivider(clkDiv25MHz); // Restore the clock for our next retry\r
        sdDev.capacity = 0;\r
 \r
 out:\r
@@ -826,13 +858,13 @@ void sdWriteMultiSectorPrep()
                sdLBA = sdLBA * SD_SECTOR_SIZE;\r
        }\r
        v = sdCommandAndResponse(SD_WRITE_MULTIPLE_BLOCK, sdLBA);\r
-       if (v)\r
+       if (unlikely(v))\r
        {\r
                scsiDiskReset();\r
                sdClearStatus();\r
                scsiDev.status = CHECK_CONDITION;\r
                scsiDev.target->sense.code = HARDWARE_ERROR;\r
-               scsiDev.target->sense.asc = 0x8800 | v;\r
+               scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
                scsiDev.phase = STATUS;\r
        }\r
        else\r
@@ -854,7 +886,7 @@ void sdPoll()
                // overpower the SD pullup resistor.\r
                SD_CS_Write(0);\r
                SD_CS_SetDriveMode(SD_CS_DM_DIG_HIZ);\r
-               \r
+\r
                CyDelayCycles(64);\r
                uint8_t cs = SD_CS_Read();\r
                SD_CS_SetDriveMode(SD_CS_DM_STRONG)     ;\r
@@ -862,14 +894,14 @@ void sdPoll()
                if (cs && !(blockDev.state & DISK_PRESENT))\r
                {\r
                        static int firstInit = 1;\r
-               \r
+\r
                        // Debounce\r
                        CyDelay(250);\r
-                       \r
+\r
                        if (sdInit())\r
                        {\r
                                blockDev.state |= DISK_PRESENT | DISK_INITIALISED;\r
-                               \r
+\r
                                if (!firstInit)\r
                                {\r
                                        int i;\r
@@ -894,3 +926,5 @@ void sdPoll()
                }\r
        }\r
 }\r
+\r
+#pragma GCC pop_options\r
index abb4507..3b4a11d 100755 (executable)
@@ -61,9 +61,13 @@ typedef struct
 } SdDevice;
 
 extern SdDevice sdDev;
+extern volatile uint8_t sdRxDMAComplete;
+extern volatile uint8_t sdTxDMAComplete;
 
 int sdInit(void);
 
+#define sdDMABusy() (!(sdRxDMAComplete && sdTxDMAComplete))
+
 void sdWriteMultiSectorPrep(void);
 void sdWriteMultiSectorDMA(uint8_t* outputBuffer);
 int sdWriteSectorDMAPoll(int sendStopToken);
index 3880a9d..3d6b3fe 100755 (executable)
@@ -14,6 +14,8 @@
 //
 //     You should have received a copy of the GNU General Public License
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "time.h"
 #include "limits.h"
@@ -54,3 +56,18 @@ uint32_t diffTime_ms(uint32_t start, uint32_t end)
                return (UINT_MAX - start) + end;
        }
 }
+
+uint32_t elapsedTime_ms(uint32_t since)
+{
+       uint32_t now = counter;
+       if (now >= since)
+       {
+               return now - since;
+       }
+       else
+       {
+               return (UINT_MAX - since) + now;
+       }
+}
+
+#pragma GCC pop_options
index 69b88eb..ca1ebe0 100755 (executable)
@@ -22,5 +22,6 @@
 void timeInit(void);
 uint32_t getTime_ms(void); // Returns milliseconds since init
 uint32_t diffTime_ms(uint32_t start, uint32_t end);
+uint32_t elapsedTime_ms(uint32_t since);
 
 #endif
index a110bfa..0db6988 100644 (file)
 #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
 \r
 /* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
 #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
 #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
 #define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
 #define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
 #define SDCard_BSPIM_TxStsReg__0__POS 0\r
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
 #define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
 #define SDCard_BSPIM_TxStsReg__2__POS 2\r
 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_TxStsReg__4__POS 4\r
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST\r
 \r
 /* SD_SCK */\r
 #define SD_SCK__0__MASK 0x04u\r
 /* SCSI_Out_Ctl */\r
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
 #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
 \r
 /* SCSI_Out_DBx */\r
 #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
 #define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
 #define SD_RX_DMA__DRQ_NUMBER 2u\r
 #define SD_RX_DMA__NUMBEROF_TDS 0u\r
-#define SD_RX_DMA__PRIORITY 2u\r
+#define SD_RX_DMA__PRIORITY 0u\r
 #define SD_RX_DMA__TERMIN_EN 0u\r
 #define SD_RX_DMA__TERMIN_SEL 0u\r
 #define SD_RX_DMA__TERMOUT0_EN 1u\r
 #define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
 #define SD_TX_DMA__DRQ_NUMBER 3u\r
 #define SD_TX_DMA__NUMBEROF_TDS 0u\r
-#define SD_TX_DMA__PRIORITY 2u\r
+#define SD_TX_DMA__PRIORITY 1u\r
 #define SD_TX_DMA__TERMIN_EN 0u\r
 #define SD_TX_DMA__TERMIN_SEL 0u\r
 #define SD_TX_DMA__TERMOUT0_EN 1u\r
 #define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW\r
 \r
 /* scsiTarget */\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB05_06_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB05_06_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB05_06_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB05_06_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB05_06_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB05_06_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB05_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB05_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB05_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB05_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB05_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB05_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB05_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB05_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB05_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB05_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB05_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB05_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB05_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB05_MSK\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB00_01_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB00_01_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB00_01_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB00_01_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB00_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB00_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB00_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB00_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB00_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB00_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB00_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB00_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB00_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB00_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB00_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB00_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB00_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB00_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB00_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB00_MSK\r
 #define scsiTarget_StatusReg__0__MASK 0x01u\r
 #define scsiTarget_StatusReg__0__POS 0\r
 #define scsiTarget_StatusReg__1__MASK 0x02u\r
 #define scsiTarget_StatusReg__1__POS 1\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
 #define scsiTarget_StatusReg__2__MASK 0x04u\r
 #define scsiTarget_StatusReg__2__POS 2\r
 #define scsiTarget_StatusReg__3__MASK 0x08u\r
 #define scsiTarget_StatusReg__4__MASK 0x10u\r
 #define scsiTarget_StatusReg__4__POS 4\r
 #define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK\r
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
 \r
 /* Debug_Timer_Interrupt */\r
 #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define SCSI_Filtered_sts_sts_reg__0__POS 0\r
 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
 #define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST\r
 #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
 #define SCSI_Filtered_sts_sts_reg__2__POS 2\r
 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
 #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
 #define SCSI_Filtered_sts_sts_reg__4__POS 4\r
 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK\r
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST\r
 \r
 /* SCSI_CTL_PHASE */\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
 \r
 /* SCSI_Parity_Error */\r
 #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
 #define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
 #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST\r
 \r
 /* Miscellaneous */\r
 #define BCLK__BUS_CLK__HZ 50000000U\r
index f8cc0b1..7b14d7c 100644 (file)
@@ -380,43 +380,43 @@ void cyfitter_cfg(void)
                static const uint32 CYCODE cy_cfg_addr_table[] = {\r
                        0x40004501u, /* Base address: 0x40004500 Count: 1 */\r
                        0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
-                       0x4000520Bu, /* Base address: 0x40005200 Count: 11 */\r
+                       0x4000520Cu, /* Base address: 0x40005200 Count: 12 */\r
                        0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
                        0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
-                       0x4001004Eu, /* Base address: 0x40010000 Count: 78 */\r
+                       0x4001003Eu, /* Base address: 0x40010000 Count: 62 */\r
                        0x40010137u, /* Base address: 0x40010100 Count: 55 */\r
-                       0x4001024Du, /* Base address: 0x40010200 Count: 77 */\r
-                       0x40010353u, /* Base address: 0x40010300 Count: 83 */\r
-                       0x40010439u, /* Base address: 0x40010400 Count: 57 */\r
-                       0x4001054Cu, /* Base address: 0x40010500 Count: 76 */\r
-                       0x40010621u, /* Base address: 0x40010600 Count: 33 */\r
-                       0x40010754u, /* Base address: 0x40010700 Count: 84 */\r
-                       0x40010918u, /* Base address: 0x40010900 Count: 24 */\r
-                       0x40010A42u, /* Base address: 0x40010A00 Count: 66 */\r
+                       0x40010246u, /* Base address: 0x40010200 Count: 70 */\r
+                       0x40010350u, /* Base address: 0x40010300 Count: 80 */\r
+                       0x4001044Eu, /* Base address: 0x40010400 Count: 78 */\r
+                       0x4001054Eu, /* Base address: 0x40010500 Count: 78 */\r
+                       0x40010654u, /* Base address: 0x40010600 Count: 84 */\r
+                       0x40010750u, /* Base address: 0x40010700 Count: 80 */\r
+                       0x40010851u, /* Base address: 0x40010800 Count: 81 */\r
+                       0x40010958u, /* Base address: 0x40010900 Count: 88 */\r
+                       0x40010A46u, /* Base address: 0x40010A00 Count: 70 */\r
                        0x40010B4Eu, /* Base address: 0x40010B00 Count: 78 */\r
-                       0x40010C43u, /* Base address: 0x40010C00 Count: 67 */\r
-                       0x40010D53u, /* Base address: 0x40010D00 Count: 83 */\r
-                       0x40010E55u, /* Base address: 0x40010E00 Count: 85 */\r
-                       0x40010F35u, /* Base address: 0x40010F00 Count: 53 */\r
-                       0x40011451u, /* Base address: 0x40011400 Count: 81 */\r
-                       0x4001154Bu, /* Base address: 0x40011500 Count: 75 */\r
-                       0x4001164Cu, /* Base address: 0x40011600 Count: 76 */\r
+                       0x40010C46u, /* Base address: 0x40010C00 Count: 70 */\r
+                       0x40010D4Au, /* Base address: 0x40010D00 Count: 74 */\r
+                       0x40010F06u, /* Base address: 0x40010F00 Count: 6 */\r
+                       0x4001145Fu, /* Base address: 0x40011400 Count: 95 */\r
+                       0x40011558u, /* Base address: 0x40011500 Count: 88 */\r
+                       0x4001164Eu, /* Base address: 0x40011600 Count: 78 */\r
                        0x40011750u, /* Base address: 0x40011700 Count: 80 */\r
                        0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
-                       0x40011910u, /* Base address: 0x40011900 Count: 16 */\r
-                       0x40011B07u, /* Base address: 0x40011B00 Count: 7 */\r
-                       0x40014016u, /* Base address: 0x40014000 Count: 22 */\r
-                       0x4001411Cu, /* Base address: 0x40014100 Count: 28 */\r
-                       0x4001420Cu, /* Base address: 0x40014200 Count: 12 */\r
-                       0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
-                       0x40014411u, /* Base address: 0x40014400 Count: 17 */\r
-                       0x4001451Au, /* Base address: 0x40014500 Count: 26 */\r
-                       0x4001460Eu, /* Base address: 0x40014600 Count: 14 */\r
-                       0x4001470Bu, /* Base address: 0x40014700 Count: 11 */\r
-                       0x4001480Bu, /* Base address: 0x40014800 Count: 11 */\r
-                       0x4001490Cu, /* Base address: 0x40014900 Count: 12 */\r
-                       0x40014C05u, /* Base address: 0x40014C00 Count: 5 */\r
-                       0x40014D03u, /* Base address: 0x40014D00 Count: 3 */\r
+                       0x40011913u, /* Base address: 0x40011900 Count: 19 */\r
+                       0x40011B0Cu, /* Base address: 0x40011B00 Count: 12 */\r
+                       0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
+                       0x4001411Eu, /* Base address: 0x40014100 Count: 30 */\r
+                       0x4001420Bu, /* Base address: 0x40014200 Count: 11 */\r
+                       0x4001430Cu, /* Base address: 0x40014300 Count: 12 */\r
+                       0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
+                       0x40014518u, /* Base address: 0x40014500 Count: 24 */\r
+                       0x40014611u, /* Base address: 0x40014600 Count: 17 */\r
+                       0x40014711u, /* Base address: 0x40014700 Count: 17 */\r
+                       0x4001480Cu, /* Base address: 0x40014800 Count: 12 */\r
+                       0x4001490Fu, /* Base address: 0x40014900 Count: 15 */\r
+                       0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
+                       0x40014D06u, /* Base address: 0x40014D00 Count: 6 */\r
                        0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
                        0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
                };\r
@@ -425,790 +425,681 @@ void cyfitter_cfg(void)
                        {0x7Eu, 0x02u},\r
                        {0x01u, 0x20u},\r
                        {0x0Au, 0x36u},\r
-                       {0x00u, 0x12u},\r
-                       {0x01u, 0x04u},\r
+                       {0x00u, 0x04u},\r
+                       {0x01u, 0x11u},\r
+                       {0x18u, 0x0Cu},\r
                        {0x19u, 0x04u},\r
                        {0x1Cu, 0x71u},\r
-                       {0x20u, 0x58u},\r
-                       {0x21u, 0x98u},\r
+                       {0x20u, 0x60u},\r
+                       {0x21u, 0xC0u},\r
                        {0x2Cu, 0x0Eu},\r
-                       {0x30u, 0x0Au},\r
+                       {0x30u, 0x05u},\r
                        {0x31u, 0x0Cu},\r
                        {0x34u, 0x80u},\r
                        {0x7Cu, 0x40u},\r
-                       {0x25u, 0x02u},\r
-                       {0x87u, 0x0Fu},\r
-                       {0x01u, 0x30u},\r
-                       {0x02u, 0x08u},\r
-                       {0x03u, 0xC0u},\r
-                       {0x05u, 0x06u},\r
-                       {0x07u, 0x09u},\r
-                       {0x09u, 0x0Fu},\r
-                       {0x0Bu, 0xF0u},\r
-                       {0x11u, 0x05u},\r
-                       {0x12u, 0x80u},\r
-                       {0x13u, 0x0Au},\r
-                       {0x16u, 0x17u},\r
-                       {0x19u, 0x03u},\r
-                       {0x1Au, 0x40u},\r
-                       {0x1Bu, 0x0Cu},\r
-                       {0x1Eu, 0x20u},\r
-                       {0x20u, 0x0Au},\r
-                       {0x22u, 0x05u},\r
-                       {0x24u, 0x50u},\r
-                       {0x25u, 0x50u},\r
-                       {0x26u, 0xA0u},\r
-                       {0x27u, 0xA0u},\r
-                       {0x28u, 0x09u},\r
-                       {0x2Au, 0x02u},\r
-                       {0x2Cu, 0x04u},\r
-                       {0x2Du, 0x60u},\r
-                       {0x2Eu, 0x08u},\r
-                       {0x2Fu, 0x90u},\r
-                       {0x32u, 0x0Fu},\r
-                       {0x34u, 0xC0u},\r
-                       {0x36u, 0x30u},\r
-                       {0x37u, 0xFFu},\r
-                       {0x3Eu, 0x50u},\r
-                       {0x3Fu, 0x40u},\r
-                       {0x56u, 0x08u},\r
+                       {0x20u, 0x02u},\r
+                       {0x86u, 0x0Fu},\r
+                       {0x02u, 0x07u},\r
+                       {0x06u, 0x70u},\r
+                       {0x08u, 0xAAu},\r
+                       {0x0Au, 0x55u},\r
+                       {0x0Eu, 0x08u},\r
+                       {0x11u, 0x01u},\r
+                       {0x15u, 0x08u},\r
+                       {0x20u, 0x44u},\r
+                       {0x22u, 0x88u},\r
+                       {0x26u, 0x80u},\r
+                       {0x28u, 0x99u},\r
+                       {0x29u, 0x02u},\r
+                       {0x2Au, 0x22u},\r
+                       {0x2Du, 0x04u},\r
+                       {0x30u, 0x0Fu},\r
+                       {0x31u, 0x04u},\r
+                       {0x33u, 0x02u},\r
+                       {0x34u, 0xF0u},\r
+                       {0x35u, 0x08u},\r
+                       {0x37u, 0x01u},\r
+                       {0x3Fu, 0x55u},\r
+                       {0x40u, 0x56u},\r
+                       {0x41u, 0x02u},\r
+                       {0x42u, 0x30u},\r
+                       {0x45u, 0xF2u},\r
+                       {0x46u, 0xCDu},\r
+                       {0x47u, 0x0Eu},\r
+                       {0x48u, 0x1Fu},\r
+                       {0x49u, 0xFFu},\r
+                       {0x4Au, 0xFFu},\r
+                       {0x4Bu, 0xFFu},\r
+                       {0x4Fu, 0x2Cu},\r
+                       {0x56u, 0x01u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
+                       {0x5Au, 0x04u},\r
                        {0x5Bu, 0x04u},\r
                        {0x5Cu, 0x01u},\r
-                       {0x5Du, 0x90u},\r
+                       {0x5Du, 0x01u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x81u, 0x0Fu},\r
-                       {0x82u, 0x70u},\r
-                       {0x83u, 0xF0u},\r
-                       {0x84u, 0x90u},\r
-                       {0x86u, 0x2Fu},\r
-                       {0x87u, 0xFFu},\r
-                       {0x8Bu, 0xFFu},\r
-                       {0x8Cu, 0xC0u},\r
-                       {0x8Du, 0x55u},\r
-                       {0x8Eu, 0x1Fu},\r
-                       {0x8Fu, 0xAAu},\r
-                       {0x91u, 0xFFu},\r
-                       {0x92u, 0x80u},\r
-                       {0x94u, 0x06u},\r
-                       {0x95u, 0xFFu},\r
-                       {0x96u, 0x09u},\r
-                       {0x9Cu, 0x05u},\r
-                       {0x9Eu, 0x0Au},\r
-                       {0x9Fu, 0xFFu},\r
-                       {0xA0u, 0xA0u},\r
-                       {0xA2u, 0x4Fu},\r
-                       {0xA6u, 0x80u},\r
-                       {0xA8u, 0x0Fu},\r
-                       {0xA9u, 0x69u},\r
-                       {0xABu, 0x96u},\r
-                       {0xACu, 0x03u},\r
-                       {0xADu, 0x33u},\r
-                       {0xAEu, 0x0Cu},\r
-                       {0xAFu, 0xCCu},\r
-                       {0xB0u, 0x7Fu},\r
-                       {0xB1u, 0xFFu},\r
-                       {0xB2u, 0x80u},\r
-                       {0xBBu, 0x02u},\r
-                       {0xBEu, 0x04u},\r
-                       {0xD8u, 0x04u},\r
+                       {0x62u, 0xC0u},\r
+                       {0x66u, 0x80u},\r
+                       {0x68u, 0x40u},\r
+                       {0x69u, 0x40u},\r
+                       {0x6Eu, 0x08u},\r
+                       {0x85u, 0x08u},\r
+                       {0x8Bu, 0x3Fu},\r
+                       {0x8Du, 0x40u},\r
+                       {0x91u, 0x01u},\r
+                       {0x93u, 0x14u},\r
+                       {0x95u, 0x19u},\r
+                       {0x97u, 0x22u},\r
+                       {0x99u, 0x26u},\r
+                       {0x9Bu, 0x19u},\r
+                       {0xABu, 0x02u},\r
+                       {0xB1u, 0x07u},\r
+                       {0xB3u, 0x40u},\r
+                       {0xB5u, 0x38u},\r
+                       {0xBFu, 0x04u},\r
                        {0xD9u, 0x04u},\r
-                       {0xDCu, 0x11u},\r
+                       {0xDCu, 0x10u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x02u},\r
-                       {0x05u, 0x41u},\r
-                       {0x07u, 0x20u},\r
-                       {0x08u, 0x02u},\r
-                       {0x09u, 0x40u},\r
-                       {0x0Au, 0x24u},\r
-                       {0x0Bu, 0x05u},\r
-                       {0x0Du, 0x04u},\r
-                       {0x0Eu, 0x01u},\r
-                       {0x0Fu, 0x80u},\r
-                       {0x10u, 0x01u},\r
-                       {0x11u, 0x28u},\r
-                       {0x13u, 0x02u},\r
+                       {0x00u, 0x80u},\r
+                       {0x01u, 0x22u},\r
+                       {0x03u, 0x20u},\r
+                       {0x11u, 0x22u},\r
+                       {0x13u, 0x04u},\r
+                       {0x19u, 0x02u},\r
+                       {0x1Bu, 0x20u},\r
+                       {0x20u, 0x04u},\r
+                       {0x21u, 0x80u},\r
+                       {0x22u, 0x05u},\r
+                       {0x25u, 0x31u},\r
+                       {0x26u, 0x01u},\r
+                       {0x27u, 0x58u},\r
+                       {0x28u, 0x02u},\r
+                       {0x2Au, 0x08u},\r
+                       {0x2Bu, 0x24u},\r
+                       {0x2Fu, 0x04u},\r
+                       {0x31u, 0x06u},\r
+                       {0x35u, 0x20u},\r
+                       {0x36u, 0x01u},\r
+                       {0x37u, 0x08u},\r
+                       {0x3Du, 0x04u},\r
+                       {0x3Eu, 0x90u},\r
+                       {0x41u, 0x30u},\r
+                       {0x43u, 0x08u},\r
+                       {0x49u, 0x10u},\r
+                       {0x4Au, 0x01u},\r
+                       {0x4Bu, 0x0Au},\r
+                       {0x50u, 0x08u},\r
+                       {0x52u, 0x90u},\r
+                       {0x5Au, 0x8Au},\r
+                       {0x5Bu, 0x10u},\r
+                       {0x60u, 0x54u},\r
+                       {0x61u, 0x80u},\r
+                       {0x68u, 0x40u},\r
+                       {0x69u, 0x50u},\r
+                       {0x6Au, 0x04u},\r
+                       {0x70u, 0x02u},\r
+                       {0x72u, 0x20u},\r
+                       {0x73u, 0x06u},\r
+                       {0x83u, 0x01u},\r
+                       {0x85u, 0x10u},\r
+                       {0x8Cu, 0x08u},\r
+                       {0xC0u, 0x0Fu},\r
+                       {0xC4u, 0x0Eu},\r
+                       {0xCAu, 0x2Cu},\r
+                       {0xCCu, 0xE3u},\r
+                       {0xCEu, 0x70u},\r
+                       {0xD0u, 0x06u},\r
+                       {0xD2u, 0x0Cu},\r
+                       {0xD6u, 0x0Fu},\r
+                       {0xD8u, 0x0Fu},\r
+                       {0xE2u, 0x01u},\r
+                       {0xE4u, 0x0Cu},\r
+                       {0xE6u, 0x10u},\r
+                       {0x00u, 0x08u},\r
+                       {0x01u, 0x47u},\r
+                       {0x02u, 0x04u},\r
+                       {0x03u, 0x88u},\r
+                       {0x07u, 0x80u},\r
+                       {0x09u, 0x95u},\r
+                       {0x0Bu, 0x2Au},\r
+                       {0x11u, 0x03u},\r
+                       {0x13u, 0x0Cu},\r
+                       {0x14u, 0x04u},\r
                        {0x16u, 0x08u},\r
-                       {0x17u, 0x4Au},\r
+                       {0x17u, 0x70u},\r
                        {0x18u, 0x08u},\r
-                       {0x1Au, 0x22u},\r
-                       {0x1Du, 0x01u},\r
-                       {0x1Eu, 0x50u},\r
-                       {0x21u, 0x80u},\r
+                       {0x19u, 0xA6u},\r
+                       {0x1Au, 0x14u},\r
+                       {0x1Bu, 0x59u},\r
+                       {0x1Cu, 0x08u},\r
+                       {0x1Eu, 0x05u},\r
+                       {0x23u, 0x03u},\r
                        {0x25u, 0x01u},\r
-                       {0x27u, 0x40u},\r
-                       {0x28u, 0x02u},\r
-                       {0x2Bu, 0x10u},\r
-                       {0x2Du, 0x20u},\r
-                       {0x2Eu, 0x80u},\r
-                       {0x32u, 0x12u},\r
-                       {0x35u, 0x40u},\r
-                       {0x37u, 0x0Au},\r
-                       {0x38u, 0x20u},\r
-                       {0x3Bu, 0x05u},\r
-                       {0x3Du, 0x22u},\r
-                       {0x3Fu, 0x48u},\r
-                       {0x58u, 0x04u},\r
-                       {0x59u, 0x10u},\r
-                       {0x5Au, 0x80u},\r
-                       {0x61u, 0x08u},\r
-                       {0x62u, 0x50u},\r
-                       {0x81u, 0x90u},\r
-                       {0x85u, 0x40u},\r
-                       {0x86u, 0x40u},\r
-                       {0x88u, 0x10u},\r
-                       {0x8Eu, 0x40u},\r
-                       {0xC0u, 0xB8u},\r
-                       {0xC2u, 0xBFu},\r
-                       {0xC4u, 0xFFu},\r
-                       {0xCAu, 0x3Au},\r
-                       {0xCCu, 0xD5u},\r
-                       {0xCEu, 0xF7u},\r
-                       {0xD6u, 0x0Eu},\r
-                       {0xD8u, 0x0Eu},\r
-                       {0xE0u, 0x08u},\r
-                       {0xE2u, 0x02u},\r
-                       {0xE4u, 0x01u},\r
-                       {0xE6u, 0xC4u},\r
-                       {0x01u, 0x02u},\r
-                       {0x02u, 0x07u},\r
-                       {0x07u, 0x20u},\r
-                       {0x09u, 0x57u},\r
-                       {0x0Bu, 0xA0u},\r
-                       {0x0Cu, 0x06u},\r
-                       {0x0Du, 0x03u},\r
-                       {0x0Eu, 0x01u},\r
-                       {0x11u, 0x6Fu},\r
-                       {0x13u, 0x90u},\r
-                       {0x15u, 0x08u},\r
-                       {0x17u, 0x03u},\r
-                       {0x19u, 0x30u},\r
-                       {0x1Au, 0x02u},\r
-                       {0x1Bu, 0xC0u},\r
-                       {0x1Cu, 0x01u},\r
-                       {0x1Du, 0x70u},\r
-                       {0x1Eu, 0x04u},\r
-                       {0x1Fu, 0x8Cu},\r
-                       {0x20u, 0x10u},\r
-                       {0x23u, 0x3Fu},\r
-                       {0x24u, 0x08u},\r
-                       {0x25u, 0x10u},\r
-                       {0x27u, 0x01u},\r
-                       {0x28u, 0x01u},\r
-                       {0x2Au, 0x02u},\r
-                       {0x30u, 0x10u},\r
-                       {0x32u, 0x08u},\r
-                       {0x33u, 0xF0u},\r
-                       {0x36u, 0x07u},\r
-                       {0x37u, 0x0Fu},\r
-                       {0x3Bu, 0x08u},\r
-                       {0x3Eu, 0x05u},\r
+                       {0x2Bu, 0x02u},\r
+                       {0x2Cu, 0x08u},\r
+                       {0x2Eu, 0x06u},\r
+                       {0x30u, 0x01u},\r
+                       {0x31u, 0x0Fu},\r
+                       {0x32u, 0x0Cu},\r
+                       {0x34u, 0x02u},\r
+                       {0x35u, 0xF0u},\r
+                       {0x36u, 0x10u},\r
+                       {0x3Au, 0x08u},\r
+                       {0x3Bu, 0x02u},\r
                        {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x11u},\r
+                       {0x5Cu, 0x19u},\r
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x01u},\r
-                       {0x81u, 0x02u},\r
-                       {0x82u, 0x02u},\r
-                       {0x83u, 0x01u},\r
-                       {0x85u, 0x02u},\r
-                       {0x87u, 0x01u},\r
-                       {0x89u, 0x02u},\r
-                       {0x8Bu, 0x05u},\r
-                       {0x90u, 0x02u},\r
-                       {0x92u, 0x01u},\r
-                       {0x94u, 0x02u},\r
-                       {0x96u, 0x09u},\r
-                       {0x97u, 0x08u},\r
-                       {0x98u, 0x02u},\r
-                       {0x99u, 0x01u},\r
-                       {0x9Au, 0x01u},\r
-                       {0x9Bu, 0x02u},\r
-                       {0x9Cu, 0x02u},\r
-                       {0x9Eu, 0x05u},\r
-                       {0xA1u, 0x02u},\r
-                       {0xA3u, 0x11u},\r
-                       {0xB0u, 0x03u},\r
-                       {0xB1u, 0x04u},\r
-                       {0xB3u, 0x10u},\r
-                       {0xB4u, 0x04u},\r
-                       {0xB5u, 0x03u},\r
-                       {0xB6u, 0x08u},\r
-                       {0xB7u, 0x08u},\r
-                       {0xBAu, 0x02u},\r
-                       {0xBBu, 0x20u},\r
+                       {0x80u, 0x02u},\r
+                       {0x84u, 0x03u},\r
+                       {0x88u, 0x10u},\r
+                       {0x8Au, 0x60u},\r
+                       {0x8Cu, 0x18u},\r
+                       {0x8Eu, 0x03u},\r
+                       {0x90u, 0x20u},\r
+                       {0x92u, 0x5Cu},\r
+                       {0x96u, 0x1Fu},\r
+                       {0x98u, 0x3Fu},\r
+                       {0x9Au, 0x40u},\r
+                       {0xA0u, 0x80u},\r
+                       {0xA5u, 0x01u},\r
+                       {0xA6u, 0x01u},\r
+                       {0xA8u, 0x27u},\r
+                       {0xA9u, 0x02u},\r
+                       {0xAAu, 0x50u},\r
+                       {0xB0u, 0x80u},\r
+                       {0xB1u, 0x02u},\r
+                       {0xB2u, 0x70u},\r
+                       {0xB3u, 0x01u},\r
+                       {0xB4u, 0x0Fu},\r
+                       {0xBAu, 0x08u},\r
+                       {0xBEu, 0x01u},\r
+                       {0xBFu, 0x05u},\r
                        {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x99u},\r
+                       {0xDCu, 0x01u},\r
                        {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x02u},\r
-                       {0x04u, 0x02u},\r
-                       {0x07u, 0x02u},\r
-                       {0x09u, 0x08u},\r
-                       {0x0Au, 0x8Au},\r
-                       {0x0Du, 0x80u},\r
-                       {0x0Fu, 0x08u},\r
-                       {0x16u, 0x50u},\r
-                       {0x17u, 0x20u},\r
-                       {0x19u, 0x02u},\r
-                       {0x1Au, 0x0Au},\r
-                       {0x1Du, 0xC4u},\r
-                       {0x1Fu, 0x01u},\r
-                       {0x21u, 0x01u},\r
-                       {0x22u, 0x70u},\r
-                       {0x23u, 0x18u},\r
-                       {0x27u, 0x12u},\r
-                       {0x28u, 0x40u},\r
-                       {0x2Eu, 0x08u},\r
-                       {0x2Fu, 0x80u},\r
-                       {0x32u, 0x14u},\r
-                       {0x35u, 0x40u},\r
-                       {0x37u, 0x1Au},\r
-                       {0x38u, 0x08u},\r
-                       {0x39u, 0x02u},\r
-                       {0x3Bu, 0x10u},\r
-                       {0x3Du, 0x21u},\r
-                       {0x3Fu, 0x88u},\r
-                       {0x44u, 0x01u},\r
-                       {0x45u, 0x80u},\r
-                       {0x58u, 0x24u},\r
-                       {0x5Au, 0x01u},\r
-                       {0x5Bu, 0x80u},\r
-                       {0x5Du, 0x80u},\r
-                       {0x5Eu, 0x20u},\r
-                       {0x60u, 0x08u},\r
-                       {0x62u, 0x89u},\r
-                       {0x63u, 0x40u},\r
-                       {0x65u, 0x20u},\r
+                       {0x01u, 0x81u},\r
+                       {0x02u, 0x90u},\r
+                       {0x03u, 0x18u},\r
+                       {0x05u, 0x01u},\r
+                       {0x09u, 0x01u},\r
+                       {0x0Au, 0x18u},\r
+                       {0x0Eu, 0x2Au},\r
+                       {0x11u, 0x24u},\r
+                       {0x12u, 0x40u},\r
+                       {0x16u, 0x02u},\r
+                       {0x19u, 0x30u},\r
+                       {0x1Au, 0x88u},\r
+                       {0x1Bu, 0x08u},\r
+                       {0x1Du, 0x01u},\r
+                       {0x1Eu, 0x3Au},\r
+                       {0x20u, 0x50u},\r
+                       {0x26u, 0x02u},\r
+                       {0x27u, 0x04u},\r
+                       {0x28u, 0x28u},\r
+                       {0x2Du, 0x04u},\r
+                       {0x2Fu, 0x84u},\r
+                       {0x35u, 0x20u},\r
+                       {0x36u, 0x02u},\r
+                       {0x37u, 0x04u},\r
+                       {0x3Du, 0x22u},\r
+                       {0x3Eu, 0x04u},\r
+                       {0x45u, 0x04u},\r
+                       {0x47u, 0x04u},\r
+                       {0x58u, 0x90u},\r
+                       {0x5Au, 0x02u},\r
+                       {0x5Bu, 0x08u},\r
+                       {0x5Fu, 0x80u},\r
+                       {0x60u, 0x02u},\r
+                       {0x61u, 0x06u},\r
+                       {0x62u, 0x05u},\r
+                       {0x63u, 0x08u},\r
                        {0x66u, 0x80u},\r
-                       {0x80u, 0x04u},\r
-                       {0x82u, 0x10u},\r
-                       {0x84u, 0x04u},\r
-                       {0x86u, 0x19u},\r
-                       {0x89u, 0x02u},\r
-                       {0x8Au, 0x08u},\r
-                       {0x8Cu, 0x08u},\r
-                       {0x8Fu, 0x98u},\r
-                       {0x90u, 0x02u},\r
-                       {0x92u, 0x50u},\r
-                       {0x95u, 0x08u},\r
-                       {0x96u, 0x04u},\r
-                       {0x97u, 0x40u},\r
-                       {0x9Au, 0x50u},\r
-                       {0x9Cu, 0x03u},\r
-                       {0x9Du, 0x60u},\r
-                       {0x9Eu, 0x88u},\r
-                       {0x9Fu, 0x2Au},\r
-                       {0xA1u, 0x08u},\r
-                       {0xA3u, 0x80u},\r
-                       {0xA4u, 0x11u},\r
-                       {0xA5u, 0x10u},\r
-                       {0xA6u, 0x02u},\r
-                       {0xA7u, 0x50u},\r
-                       {0xA8u, 0x15u},\r
-                       {0xA9u, 0x04u},\r
-                       {0xABu, 0x84u},\r
-                       {0xAEu, 0x01u},\r
-                       {0xB0u, 0x04u},\r
-                       {0xB2u, 0x11u},\r
-                       {0xC0u, 0x98u},\r
-                       {0xC2u, 0xCFu},\r
-                       {0xC4u, 0x70u},\r
-                       {0xCAu, 0xC1u},\r
-                       {0xCCu, 0xF6u},\r
-                       {0xCEu, 0xF7u},\r
-                       {0xD6u, 0x3Fu},\r
-                       {0xD8u, 0x3Fu},\r
-                       {0xE2u, 0x38u},\r
-                       {0xE4u, 0x04u},\r
-                       {0xE6u, 0x4Bu},\r
-                       {0xEAu, 0x2Cu},\r
-                       {0xEEu, 0x04u},\r
-                       {0x00u, 0x02u},\r
-                       {0x01u, 0x02u},\r
-                       {0x03u, 0x0Du},\r
-                       {0x05u, 0x0Du},\r
-                       {0x0Bu, 0x10u},\r
-                       {0x0Du, 0x0Du},\r
-                       {0x11u, 0x02u},\r
-                       {0x13u, 0x54u},\r
-                       {0x15u, 0x0Du},\r
-                       {0x19u, 0x01u},\r
-                       {0x1Bu, 0x32u},\r
-                       {0x1Du, 0x0Du},\r
-                       {0x21u, 0x0Du},\r
-                       {0x25u, 0x62u},\r
-                       {0x27u, 0x08u},\r
-                       {0x28u, 0x01u},\r
-                       {0x29u, 0x80u},\r
-                       {0x30u, 0x01u},\r
-                       {0x33u, 0x70u},\r
+                       {0x6Du, 0x14u},\r
+                       {0x6Fu, 0x22u},\r
+                       {0x83u, 0x08u},\r
+                       {0x84u, 0x90u},\r
+                       {0x86u, 0x10u},\r
+                       {0x87u, 0x80u},\r
+                       {0x88u, 0x10u},\r
+                       {0x89u, 0x10u},\r
+                       {0x8Au, 0x02u},\r
+                       {0x8Du, 0x40u},\r
+                       {0x8Fu, 0x02u},\r
+                       {0x91u, 0x60u},\r
+                       {0x92u, 0x04u},\r
+                       {0x93u, 0x08u},\r
+                       {0x94u, 0x50u},\r
+                       {0x95u, 0x04u},\r
+                       {0x96u, 0x90u},\r
+                       {0x99u, 0x02u},\r
+                       {0x9Au, 0x38u},\r
+                       {0x9Bu, 0x42u},\r
+                       {0x9Cu, 0x02u},\r
+                       {0x9Du, 0x34u},\r
+                       {0x9Eu, 0x80u},\r
+                       {0xA0u, 0x02u},\r
+                       {0xA1u, 0x11u},\r
+                       {0xA2u, 0x80u},\r
+                       {0xA5u, 0x02u},\r
+                       {0xA7u, 0x0Cu},\r
+                       {0xA9u, 0x10u},\r
+                       {0xB6u, 0x01u},\r
+                       {0xC0u, 0x1Fu},\r
+                       {0xC2u, 0xEEu},\r
+                       {0xC4u, 0x8Eu},\r
+                       {0xCAu, 0xE6u},\r
+                       {0xCCu, 0xE0u},\r
+                       {0xCEu, 0xE0u},\r
+                       {0xD6u, 0x1Fu},\r
+                       {0xD8u, 0x1Fu},\r
+                       {0xE2u, 0xC4u},\r
+                       {0xE4u, 0x08u},\r
+                       {0xE6u, 0xE2u},\r
+                       {0xE8u, 0x01u},\r
+                       {0xEEu, 0x02u},\r
+                       {0x02u, 0xFFu},\r
+                       {0x04u, 0x0Fu},\r
+                       {0x05u, 0x0Fu},\r
+                       {0x06u, 0xF0u},\r
+                       {0x08u, 0x69u},\r
+                       {0x09u, 0x90u},\r
+                       {0x0Au, 0x96u},\r
+                       {0x0Bu, 0x2Fu},\r
+                       {0x0Cu, 0xFFu},\r
+                       {0x10u, 0x33u},\r
+                       {0x12u, 0xCCu},\r
+                       {0x13u, 0x70u},\r
+                       {0x15u, 0x03u},\r
+                       {0x16u, 0xFFu},\r
+                       {0x17u, 0x0Cu},\r
+                       {0x18u, 0xFFu},\r
+                       {0x1Bu, 0x80u},\r
+                       {0x1Du, 0xC0u},\r
+                       {0x1Fu, 0x1Fu},\r
+                       {0x21u, 0x06u},\r
+                       {0x23u, 0x09u},\r
+                       {0x25u, 0x05u},\r
+                       {0x27u, 0x0Au},\r
+                       {0x29u, 0xA0u},\r
+                       {0x2Au, 0xFFu},\r
+                       {0x2Bu, 0x4Fu},\r
+                       {0x2Cu, 0x55u},\r
+                       {0x2Eu, 0xAAu},\r
+                       {0x2Fu, 0x80u},\r
+                       {0x31u, 0x7Fu},\r
+                       {0x32u, 0xFFu},\r
                        {0x35u, 0x80u},\r
-                       {0x36u, 0x02u},\r
-                       {0x37u, 0x0Fu},\r
-                       {0x3Bu, 0x80u},\r
-                       {0x3Eu, 0x41u},\r
+                       {0x3Au, 0x08u},\r
                        {0x3Fu, 0x10u},\r
+                       {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
+                       {0x5Bu, 0x04u},\r
+                       {0x5Cu, 0x11u},\r
+                       {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x02u},\r
-                       {0x88u, 0x04u},\r
-                       {0xACu, 0x01u},\r
-                       {0xB0u, 0x02u},\r
-                       {0xB2u, 0x01u},\r
-                       {0xB4u, 0x04u},\r
-                       {0xBEu, 0x15u},\r
-                       {0xC0u, 0x14u},\r
-                       {0xC1u, 0x02u},\r
-                       {0xC2u, 0x30u},\r
-                       {0xC5u, 0xD2u},\r
-                       {0xC6u, 0xECu},\r
-                       {0xC7u, 0x0Fu},\r
-                       {0xC8u, 0x1Fu},\r
-                       {0xC9u, 0xFFu},\r
-                       {0xCAu, 0xFFu},\r
-                       {0xCBu, 0xFFu},\r
-                       {0xCFu, 0x2Cu},\r
-                       {0xD6u, 0x01u},\r
+                       {0x83u, 0x7Cu},\r
+                       {0x84u, 0x40u},\r
+                       {0x85u, 0x48u},\r
+                       {0x86u, 0x80u},\r
+                       {0x87u, 0x03u},\r
+                       {0x88u, 0x20u},\r
+                       {0x8Au, 0x18u},\r
+                       {0x92u, 0x01u},\r
+                       {0x93u, 0x01u},\r
+                       {0x94u, 0x18u},\r
+                       {0x95u, 0x70u},\r
+                       {0x96u, 0x25u},\r
+                       {0x98u, 0x2Eu},\r
+                       {0x99u, 0x04u},\r
+                       {0x9Au, 0x10u},\r
+                       {0x9Bu, 0x23u},\r
+                       {0x9Du, 0x11u},\r
+                       {0x9Fu, 0x02u},\r
+                       {0xA0u, 0x08u},\r
+                       {0xA2u, 0x33u},\r
+                       {0xA6u, 0x80u},\r
+                       {0xAAu, 0x40u},\r
+                       {0xAFu, 0x02u},\r
+                       {0xB0u, 0x07u},\r
+                       {0xB1u, 0x0Fu},\r
+                       {0xB2u, 0xC0u},\r
+                       {0xB3u, 0x70u},\r
+                       {0xB4u, 0x38u},\r
+                       {0xBAu, 0x20u},\r
+                       {0xBEu, 0x04u},\r
+                       {0xBFu, 0x04u},\r
+                       {0xD4u, 0x01u},\r
                        {0xD8u, 0x04u},\r
-                       {0xDAu, 0x04u},\r
+                       {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDDu, 0x01u},\r
+                       {0xDDu, 0x10u},\r
                        {0xDFu, 0x01u},\r
-                       {0xE2u, 0xC0u},\r
-                       {0xE6u, 0x80u},\r
-                       {0xE8u, 0x40u},\r
-                       {0xE9u, 0x40u},\r
-                       {0xEEu, 0x08u},\r
-                       {0x02u, 0x80u},\r
-                       {0x05u, 0x20u},\r
-                       {0x06u, 0x80u},\r
+                       {0x01u, 0x88u},\r
+                       {0x02u, 0x04u},\r
+                       {0x03u, 0x40u},\r
+                       {0x04u, 0x08u},\r
+                       {0x05u, 0x10u},\r
+                       {0x08u, 0x02u},\r
+                       {0x0Au, 0x18u},\r
+                       {0x0Eu, 0x64u},\r
+                       {0x11u, 0x20u},\r
+                       {0x12u, 0x01u},\r
+                       {0x14u, 0x50u},\r
+                       {0x15u, 0x02u},\r
+                       {0x16u, 0x08u},\r
+                       {0x19u, 0x08u},\r
+                       {0x1Cu, 0x20u},\r
+                       {0x1Du, 0x10u},\r
+                       {0x1Eu, 0x40u},\r
+                       {0x1Fu, 0x10u},\r
+                       {0x20u, 0x08u},\r
+                       {0x21u, 0x02u},\r
+                       {0x23u, 0x80u},\r
+                       {0x25u, 0x09u},\r
+                       {0x29u, 0xA8u},\r
+                       {0x2Bu, 0x40u},\r
+                       {0x2Fu, 0x01u},\r
+                       {0x31u, 0x02u},\r
+                       {0x32u, 0x08u},\r
+                       {0x33u, 0x50u},\r
+                       {0x34u, 0x40u},\r
+                       {0x35u, 0x01u},\r
+                       {0x36u, 0x10u},\r
+                       {0x37u, 0x04u},\r
+                       {0x39u, 0x24u},\r
+                       {0x3Du, 0x02u},\r
+                       {0x3Eu, 0x04u},\r
+                       {0x4Cu, 0x0Cu},\r
+                       {0x58u, 0x80u},\r
+                       {0x59u, 0x04u},\r
+                       {0x5Bu, 0x20u},\r
+                       {0x5Fu, 0x80u},\r
+                       {0x60u, 0x38u},\r
+                       {0x62u, 0x40u},\r
+                       {0x63u, 0x02u},\r
+                       {0x80u, 0x10u},\r
+                       {0x88u, 0x04u},\r
+                       {0x8Eu, 0x0Au},\r
+                       {0x8Fu, 0x40u},\r
+                       {0x91u, 0xE4u},\r
+                       {0x92u, 0x18u},\r
+                       {0x98u, 0x02u},\r
+                       {0x99u, 0x22u},\r
+                       {0x9Au, 0xADu},\r
+                       {0x9Bu, 0x52u},\r
+                       {0x9Cu, 0x28u},\r
+                       {0x9Du, 0x80u},\r
+                       {0x9Eu, 0x42u},\r
+                       {0xA0u, 0x02u},\r
+                       {0xA1u, 0x14u},\r
+                       {0xA3u, 0x24u},\r
+                       {0xA4u, 0x10u},\r
+                       {0xABu, 0x80u},\r
+                       {0xADu, 0x01u},\r
+                       {0xAEu, 0x11u},\r
+                       {0xAFu, 0x20u},\r
+                       {0xB1u, 0x20u},\r
+                       {0xC0u, 0x6Fu},\r
+                       {0xC2u, 0x7Eu},\r
+                       {0xC4u, 0x73u},\r
+                       {0xCAu, 0x1Fu},\r
+                       {0xCCu, 0xFFu},\r
+                       {0xCEu, 0xC6u},\r
+                       {0xD6u, 0x1Eu},\r
+                       {0xD8u, 0x0Eu},\r
+                       {0xE4u, 0x01u},\r
+                       {0xE6u, 0x10u},\r
+                       {0xE8u, 0x0Au},\r
+                       {0xEAu, 0x01u},\r
+                       {0xEEu, 0x02u},\r
+                       {0x00u, 0x04u},\r
+                       {0x01u, 0x33u},\r
+                       {0x02u, 0x20u},\r
+                       {0x03u, 0xCCu},\r
+                       {0x04u, 0x42u},\r
+                       {0x05u, 0x69u},\r
+                       {0x07u, 0x96u},\r
+                       {0x08u, 0x01u},\r
+                       {0x0Au, 0x5Eu},\r
+                       {0x0Bu, 0xFFu},\r
+                       {0x10u, 0x77u},\r
                        {0x12u, 0x08u},\r
-                       {0x16u, 0x01u},\r
-                       {0x19u, 0x01u},\r
-                       {0x1Au, 0x01u},\r
-                       {0x1Cu, 0x40u},\r
-                       {0x1Eu, 0x28u},\r
-                       {0x20u, 0x11u},\r
-                       {0x23u, 0x04u},\r
-                       {0x28u, 0x28u},\r
-                       {0x2Au, 0x02u},\r
+                       {0x14u, 0x39u},\r
+                       {0x15u, 0xFFu},\r
+                       {0x16u, 0x06u},\r
+                       {0x19u, 0x0Fu},\r
+                       {0x1Bu, 0xF0u},\r
+                       {0x1Cu, 0x46u},\r
+                       {0x1Fu, 0xFFu},\r
+                       {0x20u, 0x46u},\r
+                       {0x25u, 0xFFu},\r
+                       {0x26u, 0x46u},\r
+                       {0x28u, 0x42u},\r
+                       {0x2Au, 0x04u},\r
+                       {0x2Bu, 0xFFu},\r
+                       {0x2Cu, 0x46u},\r
+                       {0x2Du, 0x55u},\r
+                       {0x2Fu, 0xAAu},\r
                        {0x30u, 0x08u},\r
-                       {0x31u, 0x10u},\r
-                       {0x32u, 0x01u},\r
-                       {0x33u, 0x40u},\r
-                       {0x38u, 0x11u},\r
-                       {0x39u, 0x44u},\r
-                       {0x44u, 0x41u},\r
-                       {0x45u, 0x90u},\r
-                       {0x47u, 0x26u},\r
-                       {0x4Du, 0x01u},\r
-                       {0x4Fu, 0x08u},\r
-                       {0x54u, 0x10u},\r
-                       {0x57u, 0x68u},\r
-                       {0x5Cu, 0x40u},\r
-                       {0x5Eu, 0x29u},\r
-                       {0x65u, 0x05u},\r
-                       {0x67u, 0x06u},\r
-                       {0x6Cu, 0x24u},\r
-                       {0x6Eu, 0x02u},\r
-                       {0x6Fu, 0x01u},\r
-                       {0x74u, 0x01u},\r
-                       {0x75u, 0x80u},\r
-                       {0x76u, 0x08u},\r
-                       {0x77u, 0x10u},\r
-                       {0x84u, 0x02u},\r
-                       {0x89u, 0x04u},\r
-                       {0x8Fu, 0x10u},\r
-                       {0x92u, 0x50u},\r
-                       {0x93u, 0x02u},\r
-                       {0x95u, 0x09u},\r
-                       {0x96u, 0x04u},\r
-                       {0x98u, 0x08u},\r
-                       {0x99u, 0x24u},\r
-                       {0x9Au, 0x81u},\r
-                       {0x9Bu, 0x02u},\r
-                       {0x9Cu, 0x02u},\r
-                       {0x9Fu, 0x20u},\r
-                       {0xA0u, 0x04u},\r
-                       {0xA1u, 0x80u},\r
-                       {0xA2u, 0xA8u},\r
-                       {0xA3u, 0x80u},\r
-                       {0xA4u, 0x11u},\r
-                       {0xA5u, 0x10u},\r
-                       {0xA6u, 0x02u},\r
-                       {0xA7u, 0x5Cu},\r
-                       {0xA9u, 0x80u},\r
-                       {0xAAu, 0x80u},\r
-                       {0xACu, 0x44u},\r
-                       {0xB0u, 0x20u},\r
-                       {0xB3u, 0x02u},\r
-                       {0xB5u, 0x80u},\r
-                       {0xC0u, 0x58u},\r
-                       {0xC4u, 0x82u},\r
-                       {0xCAu, 0x07u},\r
-                       {0xCCu, 0x0Fu},\r
-                       {0xCEu, 0x0Fu},\r
-                       {0xD0u, 0xF0u},\r
-                       {0xD6u, 0xF0u},\r
-                       {0xD8u, 0xF0u},\r
-                       {0xE6u, 0x02u},\r
-                       {0xEAu, 0x19u},\r
-                       {0xECu, 0x05u},\r
-                       {0xEEu, 0x08u},\r
-                       {0x02u, 0x70u},\r
-                       {0x05u, 0x01u},\r
-                       {0x09u, 0x13u},\r
-                       {0x0Bu, 0x2Cu},\r
-                       {0x0Cu, 0xAAu},\r
-                       {0x0Eu, 0x55u},\r
-                       {0x10u, 0x44u},\r
-                       {0x11u, 0x1Cu},\r
-                       {0x12u, 0x88u},\r
-                       {0x13u, 0x23u},\r
-                       {0x15u, 0x08u},\r
-                       {0x16u, 0x07u},\r
-                       {0x17u, 0x30u},\r
-                       {0x19u, 0x08u},\r
-                       {0x1Eu, 0x80u},\r
-                       {0x22u, 0x08u},\r
-                       {0x23u, 0x0Fu},\r
-                       {0x28u, 0x99u},\r
-                       {0x2Au, 0x22u},\r
-                       {0x2Du, 0x10u},\r
-                       {0x2Fu, 0x2Au},\r
-                       {0x30u, 0xF0u},\r
                        {0x32u, 0x0Fu},\r
-                       {0x33u, 0x07u},\r
-                       {0x35u, 0x38u},\r
-                       {0x3Bu, 0x20u},\r
-                       {0x54u, 0x01u},\r
+                       {0x33u, 0xFFu},\r
+                       {0x34u, 0x70u},\r
+                       {0x38u, 0x08u},\r
+                       {0x3Au, 0x30u},\r
+                       {0x3Bu, 0x08u},\r
+                       {0x3Eu, 0x01u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
-                       {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x11u},\r
-                       {0x5Du, 0x10u},\r
+                       {0x5Cu, 0x10u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x00u, 0x05u},\r
-                       {0x05u, 0x01u},\r
-                       {0x07u, 0x02u},\r
-                       {0x0Bu, 0x09u},\r
-                       {0x0Cu, 0x01u},\r
-                       {0x0Eu, 0x12u},\r
-                       {0x13u, 0x08u},\r
-                       {0x17u, 0x21u},\r
-                       {0x1Au, 0x08u},\r
-                       {0x1Bu, 0x28u},\r
-                       {0x1Du, 0x01u},\r
-                       {0x1Eu, 0x10u},\r
-                       {0x20u, 0x04u},\r
-                       {0x24u, 0x30u},\r
-                       {0x26u, 0x08u},\r
-                       {0x27u, 0x24u},\r
-                       {0x29u, 0x20u},\r
-                       {0x2Au, 0x02u},\r
-                       {0x2Bu, 0x01u},\r
-                       {0x2Cu, 0x01u},\r
-                       {0x2Fu, 0x80u},\r
-                       {0x30u, 0x08u},\r
-                       {0x32u, 0x01u},\r
-                       {0x33u, 0x60u},\r
-                       {0x36u, 0x20u},\r
-                       {0x37u, 0x06u},\r
-                       {0x39u, 0x46u},\r
-                       {0x3Bu, 0x10u},\r
-                       {0x3Cu, 0x18u},\r
-                       {0x40u, 0x28u},\r
-                       {0x41u, 0x08u},\r
-                       {0x43u, 0x02u},\r
-                       {0x49u, 0x38u},\r
-                       {0x4Au, 0x80u},\r
-                       {0x4Bu, 0x40u},\r
-                       {0x50u, 0x02u},\r
-                       {0x51u, 0x21u},\r
-                       {0x52u, 0x44u},\r
-                       {0x5Eu, 0x40u},\r
-                       {0x60u, 0x80u},\r
-                       {0x61u, 0x20u},\r
-                       {0x62u, 0x40u},\r
-                       {0x63u, 0x20u},\r
-                       {0x83u, 0x01u},\r
-                       {0x8Du, 0x01u},\r
-                       {0x8Eu, 0x10u},\r
-                       {0x90u, 0x08u},\r
-                       {0x92u, 0x40u},\r
-                       {0x95u, 0x44u},\r
-                       {0x96u, 0x06u},\r
-                       {0x98u, 0x41u},\r
-                       {0x99u, 0x80u},\r
-                       {0x9Au, 0x08u},\r
-                       {0x9Bu, 0x13u},\r
-                       {0x9Cu, 0x20u},\r
-                       {0x9Du, 0x10u},\r
-                       {0x9Eu, 0x02u},\r
-                       {0x9Fu, 0x64u},\r
-                       {0xA0u, 0x24u},\r
-                       {0xA2u, 0x21u},\r
-                       {0xA3u, 0x80u},\r
-                       {0xA4u, 0x08u},\r
-                       {0xA6u, 0x02u},\r
-                       {0xABu, 0x40u},\r
-                       {0xB1u, 0x01u},\r
-                       {0xB3u, 0x08u},\r
-                       {0xB4u, 0x10u},\r
-                       {0xB6u, 0x10u},\r
-                       {0xB7u, 0x20u},\r
-                       {0xC0u, 0x9Cu},\r
-                       {0xC2u, 0xB3u},\r
-                       {0xC4u, 0x54u},\r
-                       {0xCAu, 0x9Du},\r
-                       {0xCCu, 0xEFu},\r
-                       {0xCEu, 0x6Fu},\r
-                       {0xD0u, 0x07u},\r
-                       {0xD2u, 0x0Cu},\r
-                       {0xD6u, 0x10u},\r
-                       {0xD8u, 0x0Fu},\r
-                       {0xE2u, 0x01u},\r
-                       {0xE6u, 0x02u},\r
-                       {0xE8u, 0x04u},\r
-                       {0xEAu, 0x19u},\r
-                       {0xEEu, 0x08u},\r
-                       {0x82u, 0x10u},\r
-                       {0x8Du, 0x10u},\r
-                       {0x8Fu, 0x40u},\r
-                       {0x92u, 0x50u},\r
-                       {0x95u, 0x10u},\r
-                       {0x96u, 0x08u},\r
-                       {0x99u, 0x04u},\r
-                       {0x9Au, 0x02u},\r
-                       {0x9Fu, 0x14u},\r
-                       {0xA1u, 0x04u},\r
-                       {0xA5u, 0x10u},\r
-                       {0xA6u, 0x0Au},\r
-                       {0xA7u, 0x40u},\r
-                       {0xA8u, 0x05u},\r
-                       {0xB1u, 0x20u},\r
-                       {0xB2u, 0x01u},\r
-                       {0xB5u, 0x40u},\r
-                       {0xB7u, 0x01u},\r
-                       {0xE4u, 0x50u},\r
-                       {0xE6u, 0x02u},\r
-                       {0xE8u, 0x60u},\r
-                       {0xEAu, 0x08u},\r
-                       {0xECu, 0x90u},\r
-                       {0xEEu, 0x08u},\r
-                       {0x01u, 0xFFu},\r
-                       {0x05u, 0x06u},\r
-                       {0x06u, 0xFFu},\r
-                       {0x07u, 0x09u},\r
-                       {0x08u, 0x03u},\r
-                       {0x0Au, 0x0Cu},\r
-                       {0x0Bu, 0xFFu},\r
-                       {0x10u, 0x0Fu},\r
-                       {0x11u, 0x60u},\r
-                       {0x12u, 0xF0u},\r
-                       {0x13u, 0x90u},\r
-                       {0x14u, 0x50u},\r
-                       {0x15u, 0x05u},\r
-                       {0x16u, 0xA0u},\r
-                       {0x17u, 0x0Au},\r
-                       {0x18u, 0x05u},\r
-                       {0x19u, 0x50u},\r
-                       {0x1Au, 0x0Au},\r
-                       {0x1Bu, 0xA0u},\r
-                       {0x1Du, 0x0Fu},\r
-                       {0x1Eu, 0xFFu},\r
-                       {0x1Fu, 0xF0u},\r
-                       {0x21u, 0x03u},\r
-                       {0x22u, 0xFFu},\r
-                       {0x23u, 0x0Cu},\r
-                       {0x24u, 0x30u},\r
-                       {0x25u, 0x30u},\r
-                       {0x26u, 0xC0u},\r
-                       {0x27u, 0xC0u},\r
-                       {0x28u, 0x09u},\r
-                       {0x2Au, 0x06u},\r
-                       {0x2Cu, 0x90u},\r
-                       {0x2Eu, 0x60u},\r
-                       {0x2Fu, 0xFFu},\r
-                       {0x31u, 0xFFu},\r
-                       {0x32u, 0xFFu},\r
-                       {0x3Eu, 0x04u},\r
-                       {0x3Fu, 0x01u},\r
-                       {0x56u, 0x08u},\r
-                       {0x58u, 0x04u},\r
-                       {0x59u, 0x04u},\r
-                       {0x5Bu, 0x04u},\r
-                       {0x5Du, 0x90u},\r
-                       {0x5Fu, 0x01u},\r
-                       {0x82u, 0xFFu},\r
-                       {0x84u, 0x55u},\r
-                       {0x86u, 0xAAu},\r
-                       {0x8Au, 0xFFu},\r
-                       {0x8Cu, 0x0Fu},\r
-                       {0x8Eu, 0xF0u},\r
-                       {0x90u, 0xFFu},\r
-                       {0x91u, 0x01u},\r
-                       {0x96u, 0xFFu},\r
-                       {0xA4u, 0x96u},\r
-                       {0xA6u, 0x69u},\r
-                       {0xA8u, 0xFFu},\r
-                       {0xACu, 0x33u},\r
-                       {0xAEu, 0xCCu},\r
+                       {0x80u, 0xFFu},\r
+                       {0x86u, 0xFFu},\r
+                       {0x87u, 0xFFu},\r
+                       {0x88u, 0x50u},\r
+                       {0x8Au, 0xA0u},\r
+                       {0x8Bu, 0xFFu},\r
+                       {0x8Cu, 0x09u},\r
+                       {0x8Du, 0x05u},\r
+                       {0x8Eu, 0x06u},\r
+                       {0x8Fu, 0x0Au},\r
+                       {0x90u, 0x05u},\r
+                       {0x92u, 0x0Au},\r
+                       {0x94u, 0x90u},\r
+                       {0x95u, 0x0Fu},\r
+                       {0x96u, 0x60u},\r
+                       {0x97u, 0xF0u},\r
+                       {0x9Bu, 0xFFu},\r
+                       {0x9Cu, 0x03u},\r
+                       {0x9Du, 0x30u},\r
+                       {0x9Eu, 0x0Cu},\r
+                       {0x9Fu, 0xC0u},\r
+                       {0xA0u, 0x30u},\r
+                       {0xA1u, 0x03u},\r
+                       {0xA2u, 0xC0u},\r
+                       {0xA3u, 0x0Cu},\r
+                       {0xA4u, 0xFFu},\r
+                       {0xA5u, 0x50u},\r
+                       {0xA7u, 0xA0u},\r
+                       {0xA8u, 0x0Fu},\r
+                       {0xA9u, 0x90u},\r
+                       {0xAAu, 0xF0u},\r
+                       {0xABu, 0x60u},\r
+                       {0xADu, 0x09u},\r
+                       {0xAFu, 0x06u},\r
                        {0xB0u, 0xFFu},\r
-                       {0xB7u, 0x01u},\r
-                       {0xBAu, 0x02u},\r
+                       {0xB1u, 0xFFu},\r
+                       {0xBEu, 0x01u},\r
+                       {0xBFu, 0x01u},\r
+                       {0xD4u, 0x40u},\r
+                       {0xD6u, 0x04u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x91u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x04u},\r
-                       {0x02u, 0x18u},\r
-                       {0x04u, 0x40u},\r
-                       {0x05u, 0x02u},\r
-                       {0x07u, 0x24u},\r
-                       {0x09u, 0x80u},\r
-                       {0x0Au, 0xF8u},\r
-                       {0x0Bu, 0x02u},\r
-                       {0x0Fu, 0x60u},\r
-                       {0x10u, 0x11u},\r
-                       {0x11u, 0xAAu},\r
-                       {0x12u, 0x44u},\r
-                       {0x14u, 0x0Au},\r
-                       {0x15u, 0x08u},\r
-                       {0x1Bu, 0x08u},\r
-                       {0x1Cu, 0x40u},\r
-                       {0x1Fu, 0x02u},\r
-                       {0x22u, 0x01u},\r
-                       {0x24u, 0x01u},\r
-                       {0x28u, 0x10u},\r
-                       {0x29u, 0x01u},\r
-                       {0x2Au, 0x40u},\r
-                       {0x30u, 0x01u},\r
-                       {0x32u, 0x54u},\r
-                       {0x35u, 0x02u},\r
-                       {0x3Au, 0x14u},\r
-                       {0x3Bu, 0x02u},\r
-                       {0x58u, 0x40u},\r
-                       {0x5Cu, 0x04u},\r
-                       {0x5Du, 0x60u},\r
-                       {0x5Eu, 0x01u},\r
+                       {0x01u, 0x01u},\r
+                       {0x03u, 0x2Au},\r
+                       {0x04u, 0x04u},\r
+                       {0x05u, 0x10u},\r
+                       {0x06u, 0x40u},\r
+                       {0x08u, 0x44u},\r
+                       {0x0Bu, 0x80u},\r
+                       {0x0Du, 0x03u},\r
+                       {0x0Eu, 0x21u},\r
+                       {0x10u, 0x88u},\r
+                       {0x11u, 0x04u},\r
+                       {0x16u, 0x02u},\r
+                       {0x17u, 0x15u},\r
+                       {0x18u, 0x80u},\r
+                       {0x1Du, 0x10u},\r
+                       {0x1Eu, 0x64u},\r
+                       {0x1Fu, 0x04u},\r
+                       {0x23u, 0x80u},\r
+                       {0x26u, 0x08u},\r
+                       {0x27u, 0x20u},\r
+                       {0x28u, 0x44u},\r
+                       {0x29u, 0x04u},\r
+                       {0x2Bu, 0x42u},\r
+                       {0x2Du, 0x08u},\r
+                       {0x2Eu, 0x90u},\r
+                       {0x30u, 0x88u},\r
+                       {0x33u, 0x20u},\r
+                       {0x37u, 0x68u},\r
+                       {0x39u, 0x84u},\r
+                       {0x3Bu, 0x90u},\r
+                       {0x3Du, 0x20u},\r
+                       {0x3Fu, 0x0Au},\r
+                       {0x59u, 0x08u},\r
+                       {0x5Au, 0x08u},\r
                        {0x60u, 0x02u},\r
-                       {0x67u, 0x01u},\r
-                       {0x6Du, 0x89u},\r
-                       {0x6Eu, 0x10u},\r
-                       {0x75u, 0x04u},\r
-                       {0x76u, 0x8Au},\r
-                       {0x86u, 0x08u},\r
-                       {0x88u, 0x40u},\r
-                       {0x8Bu, 0x02u},\r
-                       {0x8Du, 0x05u},\r
-                       {0x8Eu, 0x08u},\r
-                       {0x91u, 0x0Cu},\r
-                       {0x92u, 0x40u},\r
-                       {0x93u, 0x40u},\r
-                       {0x95u, 0x11u},\r
-                       {0x96u, 0x12u},\r
-                       {0x98u, 0x08u},\r
+                       {0x61u, 0x28u},\r
+                       {0x62u, 0x01u},\r
+                       {0x80u, 0x40u},\r
+                       {0x81u, 0x04u},\r
+                       {0x83u, 0x40u},\r
+                       {0x89u, 0x04u},\r
+                       {0x8Bu, 0x80u},\r
+                       {0x8Cu, 0x80u},\r
+                       {0x8Du, 0x10u},\r
+                       {0x91u, 0xE0u},\r
+                       {0x92u, 0x18u},\r
+                       {0x93u, 0x20u},\r
+                       {0x95u, 0x02u},\r
+                       {0x96u, 0x04u},\r
+                       {0x97u, 0x02u},\r
+                       {0x98u, 0x04u},\r
                        {0x99u, 0x02u},\r
-                       {0x9Bu, 0x20u},\r
-                       {0x9Cu, 0x11u},\r
+                       {0x9Au, 0xA0u},\r
+                       {0x9Bu, 0x4Au},\r
                        {0x9Du, 0x01u},\r
-                       {0x9Eu, 0x86u},\r
-                       {0x9Fu, 0x10u},\r
-                       {0xA1u, 0x81u},\r
-                       {0xA3u, 0x10u},\r
-                       {0xA5u, 0x40u},\r
-                       {0xA6u, 0x02u},\r
-                       {0xA7u, 0x48u},\r
-                       {0xA8u, 0x28u},\r
-                       {0xAAu, 0x08u},\r
-                       {0xABu, 0x10u},\r
-                       {0xADu, 0x20u},\r
-                       {0xAFu, 0x04u},\r
-                       {0xB3u, 0x40u},\r
-                       {0xC0u, 0xF6u},\r
-                       {0xC2u, 0x3Fu},\r
-                       {0xC4u, 0xEFu},\r
-                       {0xCAu, 0x0Bu},\r
-                       {0xCCu, 0x8Fu},\r
-                       {0xCEu, 0x07u},\r
-                       {0xD6u, 0xF8u},\r
-                       {0xD8u, 0x18u},\r
-                       {0xE2u, 0x10u},\r
-                       {0xE6u, 0x80u},\r
-                       {0xE8u, 0x20u},\r
-                       {0xEAu, 0x98u},\r
-                       {0xEEu, 0x42u},\r
-                       {0x07u, 0xFFu},\r
-                       {0x09u, 0x0Fu},\r
-                       {0x0Bu, 0xF0u},\r
-                       {0x0Du, 0xFFu},\r
-                       {0x10u, 0x08u},\r
-                       {0x12u, 0x05u},\r
-                       {0x13u, 0xFFu},\r
-                       {0x15u, 0xFFu},\r
-                       {0x19u, 0x33u},\r
-                       {0x1Bu, 0xCCu},\r
-                       {0x1Cu, 0x0Du},\r
-                       {0x1Eu, 0x32u},\r
-                       {0x20u, 0x20u},\r
-                       {0x22u, 0x12u},\r
-                       {0x23u, 0xFFu},\r
-                       {0x25u, 0x69u},\r
-                       {0x26u, 0x40u},\r
-                       {0x27u, 0x96u},\r
-                       {0x28u, 0x04u},\r
-                       {0x2Au, 0x08u},\r
-                       {0x2Cu, 0x10u},\r
-                       {0x2Du, 0x55u},\r
-                       {0x2Eu, 0x20u},\r
-                       {0x2Fu, 0xAAu},\r
-                       {0x32u, 0x40u},\r
-                       {0x34u, 0x03u},\r
-                       {0x35u, 0xFFu},\r
-                       {0x36u, 0x3Cu},\r
-                       {0x3Bu, 0x20u},\r
-                       {0x3Eu, 0x50u},\r
+                       {0xA0u, 0x02u},\r
+                       {0xA1u, 0x14u},\r
+                       {0xA3u, 0x25u},\r
+                       {0xA4u, 0x08u},\r
+                       {0xA6u, 0x18u},\r
+                       {0xA9u, 0x80u},\r
+                       {0xABu, 0x28u},\r
+                       {0xACu, 0x80u},\r
+                       {0xB0u, 0x14u},\r
+                       {0xB1u, 0x08u},\r
+                       {0xB4u, 0x08u},\r
+                       {0xB5u, 0x04u},\r
+                       {0xB6u, 0x40u},\r
+                       {0xB7u, 0x04u},\r
+                       {0xC0u, 0x7Fu},\r
+                       {0xC2u, 0xBDu},\r
+                       {0xC4u, 0xFEu},\r
+                       {0xCAu, 0x7Fu},\r
+                       {0xCCu, 0x7Eu},\r
+                       {0xCEu, 0xEEu},\r
+                       {0xD8u, 0x0Fu},\r
+                       {0xE0u, 0x05u},\r
+                       {0xE2u, 0x0Au},\r
+                       {0xEAu, 0x05u},\r
+                       {0xEEu, 0x62u},\r
+                       {0x00u, 0x0Fu},\r
+                       {0x02u, 0xF0u},\r
+                       {0x03u, 0xFFu},\r
+                       {0x04u, 0x50u},\r
+                       {0x05u, 0x30u},\r
+                       {0x06u, 0xA0u},\r
+                       {0x07u, 0xC0u},\r
+                       {0x0Du, 0x06u},\r
+                       {0x0Eu, 0xFFu},\r
+                       {0x0Fu, 0x09u},\r
+                       {0x10u, 0x06u},\r
+                       {0x12u, 0x09u},\r
+                       {0x14u, 0x05u},\r
+                       {0x15u, 0x03u},\r
+                       {0x16u, 0x0Au},\r
+                       {0x17u, 0x0Cu},\r
+                       {0x18u, 0x30u},\r
+                       {0x19u, 0x05u},\r
+                       {0x1Au, 0xC0u},\r
+                       {0x1Bu, 0x0Au},\r
+                       {0x1Cu, 0x60u},\r
+                       {0x1Eu, 0x90u},\r
+                       {0x1Fu, 0xFFu},\r
+                       {0x20u, 0xFFu},\r
+                       {0x21u, 0x60u},\r
+                       {0x23u, 0x90u},\r
+                       {0x24u, 0x03u},\r
+                       {0x25u, 0x50u},\r
+                       {0x26u, 0x0Cu},\r
+                       {0x27u, 0xA0u},\r
+                       {0x29u, 0xFFu},\r
+                       {0x2Au, 0xFFu},\r
+                       {0x2Du, 0x0Fu},\r
+                       {0x2Fu, 0xF0u},\r
+                       {0x32u, 0xFFu},\r
+                       {0x33u, 0xFFu},\r
+                       {0x3Eu, 0x04u},\r
+                       {0x3Fu, 0x04u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x19u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x01u},\r
-                       {0x82u, 0x02u},\r
+                       {0x82u, 0x20u},\r
+                       {0x83u, 0x02u},\r
+                       {0x84u, 0x08u},\r
+                       {0x86u, 0x04u},\r
+                       {0x88u, 0x04u},\r
                        {0x89u, 0x04u},\r
-                       {0x8Bu, 0x08u},\r
-                       {0x92u, 0x04u},\r
-                       {0x95u, 0x08u},\r
-                       {0x97u, 0x04u},\r
-                       {0x99u, 0x08u},\r
-                       {0x9Bu, 0x05u},\r
-                       {0x9Du, 0x08u},\r
-                       {0x9Eu, 0x02u},\r
-                       {0x9Fu, 0x04u},\r
-                       {0xA2u, 0x08u},\r
-                       {0xAAu, 0x01u},\r
-                       {0xABu, 0x02u},\r
-                       {0xADu, 0x08u},\r
-                       {0xAFu, 0x04u},\r
-                       {0xB0u, 0x03u},\r
-                       {0xB2u, 0x08u},\r
+                       {0x8Au, 0x08u},\r
+                       {0x8Cu, 0x08u},\r
+                       {0x8Eu, 0x04u},\r
+                       {0x91u, 0x04u},\r
+                       {0x94u, 0x08u},\r
+                       {0x95u, 0x01u},\r
+                       {0x96u, 0x14u},\r
+                       {0x99u, 0x04u},\r
+                       {0x9Cu, 0x08u},\r
+                       {0x9Eu, 0x04u},\r
+                       {0xA5u, 0x04u},\r
+                       {0xA6u, 0x01u},\r
+                       {0xAAu, 0x02u},\r
+                       {0xACu, 0x01u},\r
+                       {0xAEu, 0x02u},\r
+                       {0xB0u, 0x10u},\r
+                       {0xB1u, 0x01u},\r
+                       {0xB2u, 0x0Cu},\r
                        {0xB3u, 0x02u},\r
-                       {0xB4u, 0x04u},\r
-                       {0xB5u, 0x0Cu},\r
-                       {0xB7u, 0x01u},\r
-                       {0xBBu, 0x20u},\r
-                       {0xBEu, 0x01u},\r
+                       {0xB4u, 0x20u},\r
+                       {0xB5u, 0x04u},\r
+                       {0xB6u, 0x03u},\r
+                       {0xB9u, 0x20u},\r
+                       {0xBAu, 0x08u},\r
+                       {0xBEu, 0x40u},\r
+                       {0xBFu, 0x10u},\r
                        {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
@@ -1216,740 +1107,953 @@ void cyfitter_cfg(void)
                        {0xDCu, 0x99u},\r
                        {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x02u},\r
-                       {0x08u, 0x02u},\r
-                       {0x09u, 0x40u},\r
-                       {0x0Du, 0x40u},\r
-                       {0x0Fu, 0x80u},\r
-                       {0x12u, 0x84u},\r
-                       {0x15u, 0x01u},\r
-                       {0x16u, 0x12u},\r
-                       {0x17u, 0x10u},\r
-                       {0x18u, 0x80u},\r
-                       {0x19u, 0x14u},\r
-                       {0x1Du, 0x80u},\r
-                       {0x1Eu, 0x05u},\r
-                       {0x1Fu, 0x04u},\r
-                       {0x21u, 0x18u},\r
-                       {0x22u, 0x80u},\r
-                       {0x23u, 0x08u},\r
-                       {0x25u, 0x30u},\r
-                       {0x28u, 0x02u},\r
-                       {0x2Bu, 0x04u},\r
-                       {0x2Du, 0x8Au},\r
-                       {0x31u, 0x14u},\r
-                       {0x32u, 0x80u},\r
-                       {0x34u, 0x28u},\r
-                       {0x36u, 0x02u},\r
+                       {0x00u, 0x41u},\r
+                       {0x03u, 0x28u},\r
+                       {0x04u, 0x0Au},\r
+                       {0x06u, 0x02u},\r
+                       {0x07u, 0x20u},\r
+                       {0x09u, 0x08u},\r
+                       {0x0Bu, 0x01u},\r
+                       {0x0Eu, 0x21u},\r
+                       {0x0Fu, 0x88u},\r
+                       {0x10u, 0x10u},\r
+                       {0x11u, 0x80u},\r
+                       {0x13u, 0x20u},\r
+                       {0x14u, 0x40u},\r
+                       {0x15u, 0x10u},\r
+                       {0x17u, 0x08u},\r
+                       {0x18u, 0x40u},\r
+                       {0x19u, 0x40u},\r
+                       {0x1Au, 0x84u},\r
+                       {0x1Bu, 0x08u},\r
+                       {0x1Du, 0x04u},\r
+                       {0x21u, 0x28u},\r
+                       {0x22u, 0x01u},\r
+                       {0x27u, 0x10u},\r
+                       {0x29u, 0x04u},\r
+                       {0x2Du, 0x30u},\r
+                       {0x2Eu, 0x09u},\r
+                       {0x2Fu, 0x42u},\r
+                       {0x32u, 0x06u},\r
+                       {0x33u, 0x10u},\r
+                       {0x34u, 0x50u},\r
+                       {0x35u, 0x80u},\r
+                       {0x36u, 0x18u},\r
+                       {0x37u, 0x08u},\r
                        {0x39u, 0x20u},\r
-                       {0x3Du, 0x20u},\r
-                       {0x3Eu, 0x08u},\r
-                       {0x3Fu, 0x40u},\r
-                       {0x59u, 0x20u},\r
-                       {0x5Au, 0x80u},\r
-                       {0x5Du, 0x42u},\r
-                       {0x5Eu, 0x20u},\r
-                       {0x5Fu, 0x08u},\r
-                       {0x60u, 0x02u},\r
-                       {0x62u, 0x30u},\r
-                       {0x67u, 0x02u},\r
-                       {0x68u, 0x01u},\r
-                       {0x69u, 0x80u},\r
-                       {0x6Au, 0x40u},\r
-                       {0x6Cu, 0x08u},\r
-                       {0x6Du, 0x04u},\r
-                       {0x6Eu, 0x80u},\r
-                       {0x80u, 0x08u},\r
-                       {0x82u, 0x20u},\r
-                       {0x83u, 0x01u},\r
-                       {0x85u, 0x04u},\r
-                       {0x89u, 0x04u},\r
-                       {0x8Au, 0x54u},\r
-                       {0x8Du, 0x08u},\r
-                       {0x8Eu, 0x40u},\r
-                       {0x91u, 0x40u},\r
-                       {0x94u, 0x80u},\r
-                       {0x95u, 0x14u},\r
-                       {0x96u, 0x53u},\r
-                       {0x99u, 0x82u},\r
-                       {0x9Bu, 0x20u},\r
-                       {0x9Cu, 0x11u},\r
-                       {0x9Du, 0x01u},\r
-                       {0x9Eu, 0x84u},\r
-                       {0xA1u, 0x01u},\r
-                       {0xA3u, 0x04u},\r
-                       {0xA5u, 0x28u},\r
-                       {0xA7u, 0x08u},\r
-                       {0xA9u, 0x02u},\r
+                       {0x3Bu, 0x01u},\r
+                       {0x3Du, 0x08u},\r
+                       {0x3Eu, 0x02u},\r
+                       {0x3Fu, 0x88u},\r
+                       {0x58u, 0x20u},\r
+                       {0x5Bu, 0x40u},\r
+                       {0x62u, 0x10u},\r
+                       {0x63u, 0x01u},\r
+                       {0x6Cu, 0x01u},\r
+                       {0x6Du, 0x80u},\r
+                       {0x6Fu, 0x02u},\r
+                       {0x81u, 0x01u},\r
+                       {0x82u, 0x0Au},\r
+                       {0x83u, 0x40u},\r
+                       {0x85u, 0x20u},\r
+                       {0x88u, 0x04u},\r
+                       {0x89u, 0x30u},\r
+                       {0x8Cu, 0x10u},\r
+                       {0x8Du, 0x0Cu},\r
+                       {0x90u, 0x29u},\r
+                       {0x92u, 0x08u},\r
+                       {0x93u, 0x80u},\r
+                       {0x94u, 0x02u},\r
+                       {0x96u, 0x86u},\r
+                       {0x9Cu, 0x0Cu},\r
+                       {0x9Du, 0x49u},\r
+                       {0x9Eu, 0x10u},\r
+                       {0x9Fu, 0x04u},\r
+                       {0xA0u, 0x45u},\r
+                       {0xA2u, 0x10u},\r
+                       {0xA3u, 0xA0u},\r
+                       {0xA6u, 0x04u},\r
+                       {0xA7u, 0x4Au},\r
                        {0xAAu, 0x40u},\r
-                       {0xADu, 0x20u},\r
-                       {0xB0u, 0x20u},\r
-                       {0xB3u, 0x20u},\r
-                       {0xC0u, 0x08u},\r
-                       {0xC2u, 0x99u},\r
-                       {0xC4u, 0xFAu},\r
-                       {0xCAu, 0xDCu},\r
-                       {0xCCu, 0xEEu},\r
-                       {0xCEu, 0x74u},\r
-                       {0xD6u, 0xFCu},\r
-                       {0xD8u, 0x1Cu},\r
-                       {0xE0u, 0xC0u},\r
-                       {0xE2u, 0x28u},\r
-                       {0xE4u, 0x80u},\r
-                       {0xE6u, 0x18u},\r
-                       {0xECu, 0x20u},\r
-                       {0xEEu, 0x80u},\r
-                       {0x00u, 0x01u},\r
-                       {0x02u, 0x02u},\r
-                       {0x04u, 0x02u},\r
-                       {0x05u, 0x02u},\r
-                       {0x06u, 0x01u},\r
-                       {0x09u, 0x02u},\r
-                       {0x0Du, 0x08u},\r
-                       {0x0Fu, 0x05u},\r
-                       {0x11u, 0x02u},\r
-                       {0x12u, 0x08u},\r
+                       {0xB0u, 0x22u},\r
+                       {0xB2u, 0x08u},\r
+                       {0xB3u, 0x40u},\r
+                       {0xB5u, 0x02u},\r
+                       {0xB6u, 0x02u},\r
+                       {0xC0u, 0xBFu},\r
+                       {0xC2u, 0xF5u},\r
+                       {0xC4u, 0x77u},\r
+                       {0xCAu, 0xF2u},\r
+                       {0xCCu, 0x77u},\r
+                       {0xCEu, 0xD5u},\r
+                       {0xD6u, 0x0Cu},\r
+                       {0xD8u, 0x0Cu},\r
+                       {0xE0u, 0x40u},\r
+                       {0xE2u, 0x22u},\r
+                       {0xE4u, 0x20u},\r
+                       {0xE6u, 0x41u},\r
+                       {0xE8u, 0x40u},\r
+                       {0xEAu, 0x31u},\r
+                       {0xEEu, 0x92u},\r
+                       {0x00u, 0x02u},\r
+                       {0x02u, 0x01u},\r
+                       {0x0Cu, 0x01u},\r
+                       {0x0Eu, 0x02u},\r
+                       {0x11u, 0x06u},\r
+                       {0x12u, 0x10u},\r
                        {0x14u, 0x02u},\r
-                       {0x15u, 0x02u},\r
-                       {0x16u, 0x01u},\r
+                       {0x15u, 0x01u},\r
+                       {0x16u, 0x05u},\r
+                       {0x17u, 0x02u},\r
                        {0x18u, 0x02u},\r
-                       {0x19u, 0x08u},\r
-                       {0x1Au, 0x05u},\r
-                       {0x1Bu, 0x04u},\r
-                       {0x1Du, 0x04u},\r
-                       {0x1Fu, 0x08u},\r
-                       {0x21u, 0x08u},\r
-                       {0x23u, 0x14u},\r
-                       {0x24u, 0x02u},\r
-                       {0x26u, 0x11u},\r
-                       {0x2Du, 0x08u},\r
-                       {0x2Fu, 0x04u},\r
+                       {0x1Au, 0x01u},\r
+                       {0x25u, 0x02u},\r
+                       {0x27u, 0x01u},\r
+                       {0x28u, 0x02u},\r
+                       {0x29u, 0x01u},\r
+                       {0x2Au, 0x09u},\r
+                       {0x2Bu, 0x04u},\r
                        {0x30u, 0x03u},\r
-                       {0x31u, 0x10u},\r
-                       {0x32u, 0x04u},\r
-                       {0x33u, 0x02u},\r
+                       {0x31u, 0x07u},\r
+                       {0x32u, 0x08u},\r
                        {0x34u, 0x10u},\r
-                       {0x35u, 0x01u},\r
-                       {0x36u, 0x08u},\r
-                       {0x37u, 0x0Cu},\r
-                       {0x39u, 0x08u},\r
+                       {0x36u, 0x04u},\r
+                       {0x39u, 0x02u},\r
                        {0x3Au, 0x02u},\r
-                       {0x3Bu, 0x80u},\r
-                       {0x3Fu, 0x04u},\r
                        {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x99u},\r
+                       {0x5Cu, 0x09u},\r
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x03u},\r
-                       {0x81u, 0xFFu},\r
-                       {0x82u, 0x0Cu},\r
-                       {0x84u, 0xFFu},\r
-                       {0x87u, 0xFFu},\r
-                       {0x88u, 0x06u},\r
-                       {0x89u, 0x05u},\r
-                       {0x8Au, 0x09u},\r
-                       {0x8Bu, 0x0Au},\r
-                       {0x8Du, 0x0Fu},\r
-                       {0x8Fu, 0xF0u},\r
-                       {0x90u, 0x0Fu},\r
-                       {0x91u, 0x90u},\r
-                       {0x92u, 0xF0u},\r
-                       {0x93u, 0x60u},\r
-                       {0x94u, 0x50u},\r
-                       {0x96u, 0xA0u},\r
-                       {0x98u, 0x30u},\r
-                       {0x99u, 0x30u},\r
-                       {0x9Au, 0xC0u},\r
-                       {0x9Bu, 0xC0u},\r
-                       {0x9Du, 0x03u},\r
-                       {0x9Eu, 0xFFu},\r
-                       {0x9Fu, 0x0Cu},\r
-                       {0xA1u, 0xFFu},\r
-                       {0xA5u, 0x09u},\r
-                       {0xA6u, 0xFFu},\r
-                       {0xA7u, 0x06u},\r
-                       {0xA8u, 0x05u},\r
-                       {0xA9u, 0x50u},\r
-                       {0xAAu, 0x0Au},\r
-                       {0xABu, 0xA0u},\r
-                       {0xACu, 0x60u},\r
-                       {0xAEu, 0x90u},\r
-                       {0xB2u, 0xFFu},\r
+                       {0x80u, 0x0Fu},\r
+                       {0x82u, 0xF0u},\r
+                       {0x84u, 0x06u},\r
+                       {0x85u, 0xFFu},\r
+                       {0x86u, 0x09u},\r
+                       {0x88u, 0x60u},\r
+                       {0x89u, 0x55u},\r
+                       {0x8Au, 0x90u},\r
+                       {0x8Bu, 0xAAu},\r
+                       {0x94u, 0x05u},\r
+                       {0x95u, 0x0Fu},\r
+                       {0x96u, 0x0Au},\r
+                       {0x97u, 0xF0u},\r
+                       {0x98u, 0x03u},\r
+                       {0x9Au, 0x0Cu},\r
+                       {0x9Bu, 0xFFu},\r
+                       {0x9Du, 0x33u},\r
+                       {0x9Fu, 0xCCu},\r
+                       {0xA1u, 0x96u},\r
+                       {0xA3u, 0x69u},\r
+                       {0xA7u, 0xFFu},\r
+                       {0xA8u, 0x50u},\r
+                       {0xAAu, 0xA0u},\r
+                       {0xABu, 0xFFu},\r
+                       {0xACu, 0x30u},\r
+                       {0xADu, 0xFFu},\r
+                       {0xAEu, 0xC0u},\r
                        {0xB3u, 0xFFu},\r
-                       {0xBEu, 0x04u},\r
-                       {0xBFu, 0x04u},\r
+                       {0xB4u, 0xFFu},\r
+                       {0xBBu, 0x08u},\r
+                       {0xBEu, 0x10u},\r
+                       {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
+                       {0xDBu, 0x04u},\r
+                       {0xDCu, 0x10u},\r
+                       {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x0Au},\r
-                       {0x04u, 0x08u},\r
-                       {0x05u, 0x01u},\r
-                       {0x06u, 0x0Cu},\r
-                       {0x07u, 0x40u},\r
-                       {0x08u, 0x02u},\r
-                       {0x09u, 0x08u},\r
-                       {0x0Au, 0x04u},\r
-                       {0x0Cu, 0x10u},\r
-                       {0x0Eu, 0x51u},\r
-                       {0x12u, 0x10u},\r
-                       {0x14u, 0x01u},\r
-                       {0x15u, 0x14u},\r
-                       {0x19u, 0x0Au},\r
-                       {0x1Au, 0x04u},\r
-                       {0x1Bu, 0x84u},\r
-                       {0x1Fu, 0x04u},\r
-                       {0x21u, 0x40u},\r
-                       {0x22u, 0x58u},\r
-                       {0x23u, 0x40u},\r
-                       {0x24u, 0x20u},\r
-                       {0x28u, 0x02u},\r
-                       {0x2Bu, 0x80u},\r
-                       {0x2Eu, 0x19u},\r
-                       {0x32u, 0x51u},\r
-                       {0x33u, 0x08u},\r
-                       {0x34u, 0x11u},\r
-                       {0x37u, 0x40u},\r
-                       {0x38u, 0x20u},\r
-                       {0x3Bu, 0x48u},\r
-                       {0x3Du, 0x16u},\r
-                       {0x3Eu, 0x40u},\r
-                       {0x58u, 0xA0u},\r
-                       {0x60u, 0x02u},\r
-                       {0x62u, 0x10u},\r
-                       {0x79u, 0xC0u},\r
-                       {0x80u, 0x44u},\r
-                       {0x81u, 0x01u},\r
-                       {0x84u, 0x80u},\r
-                       {0x85u, 0x80u},\r
-                       {0x86u, 0x80u},\r
-                       {0x8Eu, 0x08u},\r
-                       {0xC0u, 0x7Cu},\r
-                       {0xC2u, 0xFEu},\r
-                       {0xC4u, 0xE4u},\r
-                       {0xCAu, 0xE9u},\r
-                       {0xCCu, 0xBFu},\r
-                       {0xCEu, 0xFEu},\r
-                       {0xD6u, 0x0Cu},\r
-                       {0xD8u, 0x0Cu},\r
-                       {0xE0u, 0x01u},\r
-                       {0xE2u, 0x10u},\r
-                       {0xE6u, 0x46u},\r
-                       {0x00u, 0x0Cu},\r
-                       {0x02u, 0x10u},\r
-                       {0x04u, 0x11u},\r
-                       {0x06u, 0x62u},\r
-                       {0x08u, 0xC0u},\r
-                       {0x0Cu, 0x1Cu},\r
-                       {0x0Du, 0x04u},\r
-                       {0x0Fu, 0x03u},\r
-                       {0x10u, 0x24u},\r
-                       {0x11u, 0x23u},\r
-                       {0x12u, 0x10u},\r
-                       {0x13u, 0x04u},\r
-                       {0x14u, 0x70u},\r
-                       {0x15u, 0x25u},\r
-                       {0x16u, 0x0Fu},\r
-                       {0x17u, 0x02u},\r
-                       {0x1Bu, 0x08u},\r
-                       {0x1Cu, 0x1Cu},\r
-                       {0x20u, 0x08u},\r
-                       {0x21u, 0x08u},\r
-                       {0x23u, 0x10u},\r
-                       {0x24u, 0x14u},\r
+                       {0x00u, 0x41u},\r
+                       {0x04u, 0x02u},\r
+                       {0x05u, 0x04u},\r
+                       {0x06u, 0x08u},\r
+                       {0x0Au, 0xA4u},\r
+                       {0x0Cu, 0x04u},\r
+                       {0x0Eu, 0x08u},\r
+                       {0x12u, 0x04u},\r
+                       {0x17u, 0x50u},\r
+                       {0x18u, 0x41u},\r
+                       {0x1Au, 0x60u},\r
+                       {0x1Bu, 0x20u},\r
+                       {0x1Cu, 0x08u},\r
+                       {0x21u, 0x02u},\r
                        {0x26u, 0x08u},\r
-                       {0x28u, 0x10u},\r
-                       {0x29u, 0x21u},\r
-                       {0x2Au, 0x0Cu},\r
-                       {0x2Bu, 0x06u},\r
-                       {0x2Cu, 0x21u},\r
-                       {0x2Eu, 0x9Eu},\r
-                       {0x2Fu, 0x10u},\r
-                       {0x30u, 0x30u},\r
-                       {0x31u, 0x07u},\r
-                       {0x32u, 0xC1u},\r
-                       {0x34u, 0x0Fu},\r
-                       {0x35u, 0x18u},\r
-                       {0x37u, 0x20u},\r
-                       {0x38u, 0x08u},\r
-                       {0x3Au, 0x02u},\r
-                       {0x3Bu, 0x02u},\r
-                       {0x3Fu, 0x50u},\r
-                       {0x54u, 0x09u},\r
-                       {0x56u, 0x04u},\r
+                       {0x28u, 0x08u},\r
+                       {0x29u, 0x08u},\r
+                       {0x2Cu, 0x20u},\r
+                       {0x2Du, 0x10u},\r
+                       {0x2Eu, 0x42u},\r
+                       {0x31u, 0x02u},\r
+                       {0x33u, 0x04u},\r
+                       {0x35u, 0x20u},\r
+                       {0x36u, 0x88u},\r
+                       {0x38u, 0x40u},\r
+                       {0x3Au, 0x40u},\r
+                       {0x3Du, 0x04u},\r
+                       {0x3Fu, 0x20u},\r
+                       {0x58u, 0x60u},\r
+                       {0x5Bu, 0x08u},\r
+                       {0x5Eu, 0x80u},\r
+                       {0x62u, 0x84u},\r
+                       {0x63u, 0x08u},\r
+                       {0x67u, 0x02u},\r
+                       {0x6Cu, 0x16u},\r
+                       {0x6Fu, 0x80u},\r
+                       {0x74u, 0x41u},\r
+                       {0x76u, 0x08u},\r
+                       {0x77u, 0x50u},\r
+                       {0x83u, 0x10u},\r
+                       {0x85u, 0x40u},\r
+                       {0x87u, 0x08u},\r
+                       {0x88u, 0x02u},\r
+                       {0x8Du, 0x04u},\r
+                       {0x8Eu, 0x08u},\r
+                       {0x8Fu, 0x01u},\r
+                       {0x91u, 0x14u},\r
+                       {0x92u, 0x08u},\r
+                       {0x94u, 0x20u},\r
+                       {0x96u, 0x02u},\r
+                       {0x98u, 0x40u},\r
+                       {0x99u, 0x20u},\r
+                       {0x9Cu, 0x06u},\r
+                       {0x9Du, 0x01u},\r
+                       {0x9Eu, 0x50u},\r
+                       {0x9Fu, 0x10u},\r
+                       {0xA0u, 0x20u},\r
+                       {0xA2u, 0x50u},\r
+                       {0xA4u, 0x02u},\r
+                       {0xA7u, 0x4Eu},\r
+                       {0xAEu, 0x05u},\r
+                       {0xB0u, 0x40u},\r
+                       {0xB1u, 0x04u},\r
+                       {0xC0u, 0x79u},\r
+                       {0xC2u, 0x6Eu},\r
+                       {0xC4u, 0xC2u},\r
+                       {0xCAu, 0xF6u},\r
+                       {0xCCu, 0x73u},\r
+                       {0xCEu, 0x60u},\r
+                       {0xD6u, 0x1Eu},\r
+                       {0xD8u, 0x1Eu},\r
+                       {0xE0u, 0x30u},\r
+                       {0xE2u, 0x48u},\r
+                       {0xE4u, 0x08u},\r
+                       {0xE6u, 0x50u},\r
+                       {0xE8u, 0x20u},\r
+                       {0xEAu, 0x01u},\r
+                       {0xEEu, 0x02u},\r
+                       {0x02u, 0x01u},\r
+                       {0x05u, 0x0Au},\r
+                       {0x07u, 0x05u},\r
+                       {0x0Au, 0x02u},\r
+                       {0x0Bu, 0x07u},\r
+                       {0x17u, 0x10u},\r
+                       {0x1Bu, 0x20u},\r
+                       {0x1Cu, 0x01u},\r
+                       {0x1Eu, 0x02u},\r
+                       {0x23u, 0x08u},\r
+                       {0x25u, 0x09u},\r
+                       {0x27u, 0x02u},\r
+                       {0x29u, 0x04u},\r
+                       {0x2Bu, 0x08u},\r
+                       {0x2Du, 0x10u},\r
+                       {0x2Eu, 0x04u},\r
+                       {0x2Fu, 0x20u},\r
+                       {0x31u, 0x30u},\r
+                       {0x32u, 0x03u},\r
+                       {0x35u, 0x0Fu},\r
+                       {0x36u, 0x04u},\r
+                       {0x3Eu, 0x04u},\r
+                       {0x3Fu, 0x01u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
+                       {0x5Cu, 0x19u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x83u, 0x17u},\r
-                       {0x87u, 0x40u},\r
-                       {0x88u, 0x21u},\r
-                       {0x8Au, 0x02u},\r
-                       {0x91u, 0x04u},\r
-                       {0x92u, 0x01u},\r
+                       {0x80u, 0x01u},\r
+                       {0x82u, 0x02u},\r
+                       {0x83u, 0x10u},\r
+                       {0x85u, 0x01u},\r
+                       {0x87u, 0x02u},\r
+                       {0x8Cu, 0x02u},\r
+                       {0x8Du, 0x02u},\r
+                       {0x8Eu, 0x01u},\r
+                       {0x8Fu, 0x01u},\r
+                       {0x92u, 0x08u},\r
                        {0x93u, 0x08u},\r
-                       {0x94u, 0x88u},\r
-                       {0x95u, 0x09u},\r
-                       {0x96u, 0x03u},\r
-                       {0x97u, 0x02u},\r
-                       {0x9Au, 0xECu},\r
+                       {0x94u, 0x02u},\r
+                       {0x96u, 0x01u},\r
+                       {0x99u, 0x02u},\r
+                       {0x9Bu, 0x01u},\r
+                       {0x9Du, 0x02u},\r
+                       {0x9Fu, 0x01u},\r
+                       {0xA3u, 0x04u},\r
+                       {0xA4u, 0x02u},\r
+                       {0xA6u, 0x11u},\r
+                       {0xA8u, 0x02u},\r
+                       {0xA9u, 0x02u},\r
+                       {0xAAu, 0x05u},\r
+                       {0xABu, 0x21u},\r
+                       {0xADu, 0x04u},\r
+                       {0xAFu, 0x08u},\r
+                       {0xB0u, 0x03u},\r
+                       {0xB1u, 0x0Cu},\r
+                       {0xB2u, 0x04u},\r
+                       {0xB3u, 0x10u},\r
+                       {0xB4u, 0x08u},\r
+                       {0xB5u, 0x03u},\r
+                       {0xB6u, 0x10u},\r
+                       {0xB7u, 0x20u},\r
+                       {0xBAu, 0x02u},\r
+                       {0xBBu, 0x20u},\r
+                       {0xBFu, 0x01u},\r
+                       {0xD8u, 0x04u},\r
+                       {0xD9u, 0x04u},\r
+                       {0xDBu, 0x04u},\r
+                       {0xDCu, 0x99u},\r
+                       {0xDFu, 0x01u},\r
+                       {0x01u, 0x82u},\r
+                       {0x04u, 0x20u},\r
+                       {0x05u, 0x01u},\r
+                       {0x0Au, 0x10u},\r
+                       {0x0Bu, 0x80u},\r
+                       {0x0Fu, 0x02u},\r
+                       {0x12u, 0x18u},\r
+                       {0x15u, 0x80u},\r
+                       {0x18u, 0x02u},\r
+                       {0x19u, 0x92u},\r
+                       {0x1Au, 0x10u},\r
+                       {0x1Du, 0x04u},\r
+                       {0x1Fu, 0x40u},\r
+                       {0x20u, 0x80u},\r
+                       {0x21u, 0x40u},\r
+                       {0x22u, 0x58u},\r
+                       {0x23u, 0x04u},\r
+                       {0x24u, 0x80u},\r
+                       {0x25u, 0x10u},\r
+                       {0x26u, 0x10u},\r
+                       {0x2Bu, 0x47u},\r
+                       {0x2Cu, 0x20u},\r
+                       {0x2Du, 0x20u},\r
+                       {0x2Fu, 0x82u},\r
+                       {0x30u, 0x02u},\r
+                       {0x31u, 0x10u},\r
+                       {0x32u, 0x40u},\r
+                       {0x34u, 0x04u},\r
+                       {0x37u, 0x10u},\r
+                       {0x38u, 0x02u},\r
+                       {0x3Bu, 0x84u},\r
+                       {0x3Du, 0x24u},\r
+                       {0x58u, 0x09u},\r
+                       {0x5Au, 0x20u},\r
+                       {0x5Bu, 0x40u},\r
+                       {0x5Cu, 0x20u},\r
+                       {0x5Eu, 0x05u},\r
+                       {0x5Fu, 0x80u},\r
+                       {0x62u, 0x40u},\r
+                       {0x64u, 0x02u},\r
+                       {0x78u, 0x01u},\r
+                       {0x7Au, 0x80u},\r
+                       {0x80u, 0x08u},\r
+                       {0x81u, 0x02u},\r
+                       {0x83u, 0x48u},\r
+                       {0x85u, 0x10u},\r
+                       {0x86u, 0x84u},\r
+                       {0x88u, 0x40u},\r
+                       {0x8Du, 0x10u},\r
+                       {0x94u, 0x80u},\r
+                       {0x96u, 0x02u},\r
+                       {0x98u, 0x20u},\r
+                       {0x99u, 0x20u},\r
+                       {0x9Bu, 0x80u},\r
+                       {0x9Du, 0x04u},\r
+                       {0xA0u, 0x20u},\r
+                       {0xA2u, 0x40u},\r
+                       {0xA3u, 0x80u},\r
+                       {0xA8u, 0x20u},\r
+                       {0xA9u, 0x04u},\r
+                       {0xAEu, 0x01u},\r
+                       {0xB5u, 0x20u},\r
+                       {0xC0u, 0x59u},\r
+                       {0xC2u, 0x8Cu},\r
+                       {0xC4u, 0x86u},\r
+                       {0xCAu, 0xFDu},\r
+                       {0xCCu, 0x6Du},\r
+                       {0xCEu, 0x6Bu},\r
+                       {0xD6u, 0xFFu},\r
+                       {0xD8u, 0x18u},\r
+                       {0xE2u, 0x64u},\r
+                       {0xE6u, 0x92u},\r
+                       {0xE8u, 0x10u},\r
+                       {0xECu, 0x01u},\r
+                       {0x80u, 0x60u},\r
+                       {0x86u, 0x40u},\r
+                       {0x87u, 0x80u},\r
+                       {0x8Fu, 0x80u},\r
+                       {0xE4u, 0x10u},\r
+                       {0xE6u, 0x02u},\r
+                       {0x09u, 0x04u},\r
+                       {0x0Bu, 0x88u},\r
+                       {0x15u, 0x53u},\r
+                       {0x16u, 0x01u},\r
+                       {0x17u, 0xACu},\r
+                       {0x1Eu, 0x02u},\r
+                       {0x21u, 0x02u},\r
+                       {0x23u, 0x11u},\r
+                       {0x25u, 0x01u},\r
+                       {0x27u, 0x42u},\r
+                       {0x28u, 0x01u},\r
+                       {0x29u, 0x08u},\r
+                       {0x2Au, 0x02u},\r
+                       {0x2Bu, 0x24u},\r
+                       {0x30u, 0x03u},\r
+                       {0x31u, 0xC0u},\r
+                       {0x33u, 0x0Fu},\r
+                       {0x35u, 0x30u},\r
+                       {0x3Eu, 0x01u},\r
+                       {0x3Fu, 0x15u},\r
+                       {0x40u, 0x36u},\r
+                       {0x41u, 0x04u},\r
+                       {0x42u, 0x50u},\r
+                       {0x44u, 0x01u},\r
+                       {0x45u, 0xBEu},\r
+                       {0x46u, 0xFCu},\r
+                       {0x47u, 0x0Du},\r
+                       {0x48u, 0x1Fu},\r
+                       {0x49u, 0xFFu},\r
+                       {0x4Au, 0xFFu},\r
+                       {0x4Bu, 0xFFu},\r
+                       {0x4Cu, 0x22u},\r
+                       {0x4Eu, 0xF0u},\r
+                       {0x4Fu, 0x08u},\r
+                       {0x50u, 0x04u},\r
+                       {0x58u, 0x04u},\r
+                       {0x59u, 0x04u},\r
+                       {0x5Au, 0x04u},\r
+                       {0x5Fu, 0x01u},\r
+                       {0x62u, 0xC0u},\r
+                       {0x64u, 0x40u},\r
+                       {0x65u, 0x01u},\r
+                       {0x66u, 0x10u},\r
+                       {0x67u, 0x11u},\r
+                       {0x68u, 0xC0u},\r
+                       {0x69u, 0x01u},\r
+                       {0x6Bu, 0x11u},\r
+                       {0x6Cu, 0x40u},\r
+                       {0x6Du, 0x01u},\r
+                       {0x6Eu, 0x40u},\r
+                       {0x6Fu, 0x01u},\r
+                       {0x80u, 0x40u},\r
+                       {0x81u, 0x0Du},\r
+                       {0x84u, 0x01u},\r
+                       {0x88u, 0x22u},\r
+                       {0x89u, 0x0Du},\r
+                       {0x8Au, 0x08u},\r
+                       {0x8Cu, 0x01u},\r
+                       {0x90u, 0x07u},\r
+                       {0x91u, 0x0Du},\r
+                       {0x92u, 0x18u},\r
+                       {0x94u, 0x08u},\r
+                       {0x95u, 0x0Du},\r
+                       {0x96u, 0x21u},\r
+                       {0x98u, 0x04u},\r
+                       {0x99u, 0x12u},\r
                        {0x9Bu, 0x08u},\r
-                       {0x9Du, 0x0Au},\r
-                       {0x9Fu, 0x05u},\r
-                       {0xA1u, 0x50u},\r
-                       {0xA2u, 0x12u},\r
-                       {0xA3u, 0xA0u},\r
-                       {0xA4u, 0xE0u},\r
-                       {0xA7u, 0x20u},\r
-                       {0xACu, 0x04u},\r
-                       {0xAEu, 0x43u},\r
-                       {0xAFu, 0x80u},\r
-                       {0xB0u, 0x10u},\r
+                       {0x9Cu, 0x10u},\r
+                       {0x9Du, 0x02u},\r
+                       {0x9Eu, 0x80u},\r
+                       {0x9Fu, 0x0Du},\r
+                       {0xA0u, 0x01u},\r
+                       {0xA1u, 0x0Du},\r
+                       {0xA4u, 0x40u},\r
+                       {0xA8u, 0x01u},\r
+                       {0xA9u, 0x12u},\r
+                       {0xABu, 0x04u},\r
+                       {0xACu, 0x01u},\r
+                       {0xADu, 0x11u},\r
+                       {0xAFu, 0x02u},\r
+                       {0xB0u, 0x80u},\r
                        {0xB1u, 0x0Fu},\r
-                       {0xB4u, 0x0Fu},\r
-                       {0xB5u, 0xC0u},\r
-                       {0xB6u, 0xE0u},\r
-                       {0xB7u, 0x30u},\r
+                       {0xB4u, 0x40u},\r
+                       {0xB6u, 0x3Fu},\r
+                       {0xB7u, 0x10u},\r
+                       {0xB8u, 0xA0u},\r
+                       {0xBBu, 0x02u},\r
                        {0xBEu, 0x40u},\r
-                       {0xBFu, 0x50u},\r
+                       {0xBFu, 0x40u},\r
+                       {0xD4u, 0x09u},\r
+                       {0xD6u, 0x04u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
-                       {0xDCu, 0x10u},\r
+                       {0xDBu, 0x04u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x82u},\r
-                       {0x03u, 0x2Cu},\r
-                       {0x05u, 0x20u},\r
-                       {0x09u, 0x08u},\r
-                       {0x0Au, 0x41u},\r
-                       {0x0Du, 0x0Au},\r
-                       {0x0Eu, 0x08u},\r
+                       {0x04u, 0x05u},\r
+                       {0x05u, 0x10u},\r
+                       {0x07u, 0x01u},\r
+                       {0x08u, 0x40u},\r
+                       {0x0Au, 0x20u},\r
+                       {0x0Du, 0x06u},\r
+                       {0x0Eu, 0x24u},\r
+                       {0x0Fu, 0x01u},\r
                        {0x10u, 0x08u},\r
-                       {0x11u, 0x04u},\r
-                       {0x12u, 0x80u},\r
-                       {0x13u, 0x80u},\r
-                       {0x15u, 0x02u},\r
-                       {0x17u, 0x84u},\r
-                       {0x19u, 0x20u},\r
-                       {0x1Au, 0x40u},\r
-                       {0x1Bu, 0x29u},\r
-                       {0x1Du, 0x02u},\r
-                       {0x1Eu, 0x0Au},\r
-                       {0x20u, 0x48u},\r
-                       {0x21u, 0x80u},\r
-                       {0x24u, 0x02u},\r
-                       {0x25u, 0x11u},\r
-                       {0x26u, 0x02u},\r
-                       {0x29u, 0x20u},\r
-                       {0x2Au, 0x03u},\r
-                       {0x2Bu, 0x02u},\r
-                       {0x2Eu, 0x0Au},\r
-                       {0x2Fu, 0x01u},\r
-                       {0x31u, 0x08u},\r
-                       {0x32u, 0x21u},\r
-                       {0x34u, 0x41u},\r
-                       {0x36u, 0x08u},\r
-                       {0x37u, 0x10u},\r
-                       {0x38u, 0x40u},\r
-                       {0x3Du, 0x0Au},\r
-                       {0x59u, 0x1Au},\r
-                       {0x5Au, 0x80u},\r
-                       {0x61u, 0x80u},\r
-                       {0x63u, 0x80u},\r
-                       {0x82u, 0x08u},\r
-                       {0x83u, 0x40u},\r
-                       {0x8Du, 0x10u},\r
-                       {0x8Eu, 0x81u},\r
-                       {0x8Fu, 0x02u},\r
-                       {0x91u, 0x06u},\r
-                       {0x92u, 0x83u},\r
-                       {0x93u, 0x02u},\r
-                       {0x94u, 0x42u},\r
-                       {0x96u, 0x40u},\r
-                       {0x98u, 0x41u},\r
-                       {0x99u, 0x0Au},\r
-                       {0x9Au, 0x01u},\r
-                       {0x9Bu, 0x90u},\r
-                       {0x9Du, 0x20u},\r
-                       {0xA0u, 0x49u},\r
-                       {0xA1u, 0x0Cu},\r
-                       {0xA2u, 0xA8u},\r
-                       {0xA4u, 0x04u},\r
-                       {0xA5u, 0x10u},\r
-                       {0xA6u, 0x02u},\r
+                       {0x15u, 0x01u},\r
+                       {0x16u, 0x02u},\r
+                       {0x17u, 0x18u},\r
+                       {0x1Bu, 0x01u},\r
+                       {0x1Cu, 0x01u},\r
+                       {0x1Du, 0x01u},\r
+                       {0x1Eu, 0x04u},\r
+                       {0x1Fu, 0x20u},\r
+                       {0x20u, 0x08u},\r
+                       {0x22u, 0x02u},\r
+                       {0x23u, 0x10u},\r
+                       {0x27u, 0x42u},\r
+                       {0x28u, 0x08u},\r
+                       {0x29u, 0x0Au},\r
+                       {0x2Du, 0x01u},\r
+                       {0x2Fu, 0x06u},\r
+                       {0x30u, 0x08u},\r
+                       {0x35u, 0x10u},\r
+                       {0x36u, 0x04u},\r
+                       {0x37u, 0x41u},\r
+                       {0x3Au, 0x10u},\r
+                       {0x3Eu, 0x12u},\r
+                       {0x41u, 0x06u},\r
+                       {0x42u, 0x01u},\r
+                       {0x43u, 0x02u},\r
+                       {0x48u, 0x01u},\r
+                       {0x49u, 0x10u},\r
+                       {0x4Bu, 0x07u},\r
+                       {0x50u, 0x44u},\r
+                       {0x51u, 0x20u},\r
+                       {0x52u, 0x40u},\r
+                       {0x58u, 0x02u},\r
+                       {0x5Bu, 0x02u},\r
+                       {0x5Eu, 0x42u},\r
+                       {0x5Fu, 0x24u},\r
+                       {0x64u, 0x02u},\r
+                       {0x66u, 0x01u},\r
+                       {0x80u, 0x40u},\r
+                       {0x82u, 0x01u},\r
+                       {0x83u, 0x20u},\r
+                       {0x84u, 0x04u},\r
+                       {0x86u, 0x01u},\r
+                       {0x88u, 0x08u},\r
+                       {0x8Au, 0x10u},\r
+                       {0x8Eu, 0x02u},\r
+                       {0x90u, 0x04u},\r
+                       {0x91u, 0x01u},\r
+                       {0x92u, 0x70u},\r
+                       {0x93u, 0x08u},\r
+                       {0x94u, 0x08u},\r
+                       {0x97u, 0x12u},\r
+                       {0x98u, 0x40u},\r
+                       {0x99u, 0x1Au},\r
+                       {0x9Au, 0x02u},\r
+                       {0x9Bu, 0x19u},\r
+                       {0x9Du, 0x01u},\r
+                       {0x9Eu, 0x40u},\r
+                       {0xA0u, 0x09u},\r
+                       {0xA1u, 0x02u},\r
+                       {0xA2u, 0x15u},\r
+                       {0xA5u, 0x20u},\r
                        {0xA7u, 0x21u},\r
-                       {0xA9u, 0x04u},\r
-                       {0xAFu, 0x08u},\r
-                       {0xB4u, 0x08u},\r
-                       {0xC0u, 0x4Fu},\r
-                       {0xC2u, 0x7Du},\r
-                       {0xC4u, 0xBFu},\r
-                       {0xCAu, 0xDDu},\r
-                       {0xCCu, 0xF7u},\r
-                       {0xCEu, 0xC8u},\r
-                       {0xD6u, 0x0Fu},\r
-                       {0xD8u, 0x09u},\r
-                       {0xE2u, 0x10u},\r
-                       {0xE6u, 0x01u},\r
-                       {0xE8u, 0x4Cu},\r
-                       {0x06u, 0x08u},\r
-                       {0x07u, 0x07u},\r
-                       {0x08u, 0x99u},\r
-                       {0x0Au, 0x22u},\r
-                       {0x11u, 0x44u},\r
-                       {0x13u, 0x88u},\r
-                       {0x16u, 0x07u},\r
-                       {0x17u, 0x70u},\r
-                       {0x19u, 0x99u},\r
-                       {0x1Au, 0x70u},\r
-                       {0x1Bu, 0x22u},\r
-                       {0x1Du, 0xAAu},\r
-                       {0x1Fu, 0x55u},\r
-                       {0x20u, 0xAAu},\r
-                       {0x22u, 0x55u},\r
-                       {0x27u, 0x80u},\r
-                       {0x2Au, 0x80u},\r
-                       {0x2Cu, 0x44u},\r
-                       {0x2Eu, 0x88u},\r
-                       {0x2Fu, 0x08u},\r
-                       {0x32u, 0x0Fu},\r
-                       {0x33u, 0x0Fu},\r
-                       {0x34u, 0xF0u},\r
-                       {0x35u, 0xF0u},\r
+                       {0xAAu, 0x10u},\r
+                       {0xB0u, 0x40u},\r
+                       {0xB4u, 0x02u},\r
+                       {0xB5u, 0x04u},\r
+                       {0xC0u, 0xF0u},\r
+                       {0xC2u, 0xF5u},\r
+                       {0xC4u, 0xF2u},\r
+                       {0xCAu, 0xB7u},\r
+                       {0xCCu, 0xF2u},\r
+                       {0xCEu, 0xA4u},\r
+                       {0xD0u, 0x0Bu},\r
+                       {0xD2u, 0x0Cu},\r
+                       {0xD6u, 0xF0u},\r
+                       {0xD8u, 0x90u},\r
+                       {0xE4u, 0x02u},\r
+                       {0xE6u, 0x10u},\r
+                       {0xECu, 0x04u},\r
+                       {0x00u, 0x10u},\r
+                       {0x01u, 0xC0u},\r
+                       {0x03u, 0x02u},\r
+                       {0x05u, 0x80u},\r
+                       {0x06u, 0x01u},\r
+                       {0x08u, 0xC0u},\r
+                       {0x09u, 0xC0u},\r
+                       {0x0Au, 0x1Eu},\r
+                       {0x0Bu, 0x08u},\r
+                       {0x0Cu, 0x18u},\r
+                       {0x0Du, 0x1Fu},\r
+                       {0x0Eu, 0x61u},\r
+                       {0x0Fu, 0x20u},\r
+                       {0x10u, 0x42u},\r
+                       {0x11u, 0x90u},\r
+                       {0x12u, 0x84u},\r
+                       {0x13u, 0x40u},\r
+                       {0x14u, 0x82u},\r
+                       {0x15u, 0xC0u},\r
+                       {0x16u, 0x5Cu},\r
+                       {0x17u, 0x04u},\r
+                       {0x18u, 0x88u},\r
+&n