Performance fixes, scsi2sd-util crash fixes, scsi2 config option.
authorMichael McMaster <michael@codesrc.com>
Tue, 21 Jul 2015 00:55:08 +0000 (10:55 +1000)
committerMichael McMaster <michael@codesrc.com>
Tue, 21 Jul 2015 00:55:08 +0000 (10:55 +1000)
43 files changed:
CHANGELOG
readme.txt
software/SCSI2SD/src/disk.c
software/SCSI2SD/src/inquiry.c
software/SCSI2SD/src/mode.c
software/SCSI2SD/src/scsi.c
software/SCSI2SD/src/scsiPhy.c
software/SCSI2SD/src/sd.c
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c [new file with mode: 0644]
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h [new file with mode: 0644]
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c [new file with mode: 0644]
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h [new file with mode: 0644]
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
software/include/scsi2sd.h
software/scsi2sd-util/ConfigUtil.cc
software/scsi2sd-util/TargetPanel.cc
software/scsi2sd-util/TargetPanel.hh
software/scsi2sd-util/scsi2sd-util.cc

index 5620134..f0e0e7f 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,18 @@
+201507XX               4.4
+       - Added configuration option to allow SCSI2 mode. This option is OFF by
+       default, and should only be enabled when using the SCSI2SD with a SCSI2 host
+       controller. Extra timing delays are added in the default SCSI1/SASI mode to
+       work with slow hardware.
+       - Modified hot-swap card detection to work with longer (60cm) microSD to SD
+       cables.
+       - Fixed off-by-one error in scsi2sd-util "Auto" sector start feature.
+       - Fixed crashes and stalls of scsi2sd-util after saving/loading options
+       to/from the device
+       - Fixed synchronous transfer request negotiation.
+       SCSI2SD now negotiates back to async transfers instead of simply
+       rejecting the message.
+       - Fixed INQUIRY response to commands lacking an allocation length.
+
 20150614        4.3
        - Added configurable disk geometry.
        - Added configuration import/export function to scsi2sd-util
index 4664ced..fe3254d 100644 (file)
@@ -78,7 +78,7 @@ Compatibility
     Atari TT030 System V
     Atari MEGA STE
         needs J3 TERMPWR jumper
-        1GB limit (--blocks=2048000) 
+        1GB limit (--blocks=2048000). The OS will fail to read the boot sector if the disk is >= 1GB.
     Sharp X68000
         SASI models supported. See gamesx.com for information on building a custom cable.
         needs J3 TERMPWR jumper
@@ -118,7 +118,7 @@ Samplers
     EMU E6400 w/ EOS2.80f
     EMU Emax2
     Ensoniq ASR-X, ASR-10 (from v3.4, 2GB size limit)
-        ASR-20 Requires TERMPWR jumper.
+        ASR-10 Requires TERMPWR jumper (applies to pre. 5.0 SCSI2SD boards only)
         ASR-X resets when writing to devices > 2Gb. 
     Kurzweil K2000R
         See kurzweil.com for size limits which a dependant on the OS version. Older OS versions have a 1GB limit.
index a2f5cc6..a4251d5 100755 (executable)
@@ -527,14 +527,24 @@ void scsiDiskPoll()
                        // systick timer interrupt saves us on the event of a race.\r
                        int scsiBusy = scsiDMABusy();\r
                        int sdBusy = sdDMABusy();\r
-                       if (scsiBusy && sdBusy) __WFI();\r
+                       while (scsiBusy && sdBusy)\r
+                       {\r
+                               __WFI();\r
+                               scsiBusy = scsiDMABusy();\r
+                               sdBusy = sdDMABusy();\r
+                       }\r
 \r
                        if (sdActive && !sdBusy && sdReadSectorDMAPoll())\r
                        {\r
                                sdActive = 0;\r
                                prep++;\r
                        }\r
-                       else if (!sdActive &&\r
+\r
+                       // Usually SD is slower than the SCSI interface.\r
+                       // Prioritise starting the read of the next sector over starting a\r
+                       // SCSI transfer for the last sector\r
+                       // ie. NO "else" HERE.\r
+                       if (!sdActive &&\r
                                (prep - i < buffers) &&\r
                                (prep < totalSDSectors))\r
                        {\r
@@ -555,7 +565,7 @@ void scsiDiskPoll()
                                scsiActive = 0;\r
                                ++i;\r
                        }\r
-                       else if (!scsiActive && ((prep - i) > 0))\r
+                       if (!scsiActive && ((prep - i) > 0))\r
                        {\r
                                int dmaBytes = SD_SECTOR_SIZE;\r
                                if ((i % sdPerScsi) == (sdPerScsi - 1))\r
@@ -603,14 +613,19 @@ void scsiDiskPoll()
                        // systick timer interrupt saves us on the event of a race.\r
                        int scsiBusy = scsiDMABusy();\r
                        int sdBusy = sdDMABusy();\r
-                       if (scsiBusy && sdBusy) __WFI();\r
+                       while (scsiBusy && sdBusy)\r
+                       {\r
+                               __WFI();\r
+                               scsiBusy = scsiDMABusy();\r
+                               sdBusy = sdDMABusy();\r
+                       }\r
 \r
                        if (sdActive && !sdBusy && sdWriteSectorDMAPoll(i == (totalSDSectors - 1)))\r
                        {\r
                                sdActive = 0;\r
                                i++;\r
                        }\r
-                       else if (!sdActive && ((prep - i) > 0))\r
+                       if (!sdActive && ((prep - i) > 0))\r
                        {\r
                                // Start an SD transfer if we have space.\r
                                sdWriteMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (i % buffers)]);\r
@@ -625,7 +640,7 @@ void scsiDiskPoll()
                                ++prep;\r
                                lastActivityTime = now;\r
                        }\r
-                       else if (!scsiActive &&\r
+                       if (!scsiActive &&\r
                                ((prep - i) < buffers) &&\r
                                (prep < totalSDSectors) &&\r
                                likely(!scsiDisconnected))\r
index 51dd319..cf9bab7 100755 (executable)
@@ -98,8 +98,10 @@ void scsiInquiry()
        uint8 evpd = scsiDev.cdb[1] & 1; // enable vital product data.\r
        uint8 pageCode = scsiDev.cdb[2];\r
        uint32 allocationLength = scsiDev.cdb[4];\r
+\r
+       // SASI standard, X3T9.3_185_RevE  states that 0 == 256 bytes\r
        if (allocationLength == 0) allocationLength = 256;\r
-       \r
+\r
        if (!evpd)\r
        {\r
                if (pageCode)\r
@@ -171,6 +173,7 @@ void scsiInquiry()
                // with zeroes. This only seems to happen for Inquiry responses, and not\r
                // other commands that also supply an allocation length such as Mode Sense or\r
                // Request Sense.\r
+               // (See below for exception to this rule when 0 allocation length)\r
                if (scsiDev.dataLen < allocationLength)\r
                {\r
                        memset(\r
@@ -178,9 +181,20 @@ void scsiInquiry()
                                0,\r
                                allocationLength - scsiDev.dataLen);\r
                }\r
-               // Spec 8.2.5 requires us to simply truncate the response if it's too big.\r
-               scsiDev.dataLen = allocationLength;\r
-               \r
+               if (scsiDev.cdb[4] == 0 && scsiDev.dataLen < allocationLength)\r
+               {\r
+                       // Only send back the minimum number of bytes.\r
+                       // Don't forcably send back 256 bytes, as that may cause problems\r
+                       // with some machines (SGI Iris Indigo running IRIX)\r
+                       // scsiDev.dataLen is already the correct value.\r
+               }\r
+               else\r
+               {\r
+                       // Spec 8.2.5 requires us to simply truncate the response if it's\r
+                       // too big.\r
+                       scsiDev.dataLen = allocationLength;\r
+               }\r
+\r
                // Set the device type as needed.\r
                switch (scsiDev.target->cfg->deviceType)\r
                {\r
index 17ead1c..2eb3c50 100755 (executable)
@@ -551,7 +551,10 @@ int scsiModeCommand()
                int pc = scsiDev.cdb[2] >> 6; // Page Control\r
                int pageCode = scsiDev.cdb[2] & 0x3F;\r
                int allocLength = scsiDev.cdb[4];\r
-               if (allocLength == 0) allocLength = 256;\r
+\r
+               // SCSI1 standard: (CCS X3T9.2/86-52)\r
+               // "An Allocation Length of zero indicates that no MODE SENSE data shall\r
+               // be transferred. This condition shall not be considered as an error."\r
                doModeSense(1, dbd, pc, pageCode, allocLength);\r
        }\r
        else if (command == 0x5A)\r
index e8aa0aa..d8f5d7c 100755 (executable)
@@ -560,6 +560,10 @@ static void process_SelectionPhase()
                        target->unitAttention = 0;\r
                        scsiDev.compatMode = COMPAT_SCSI1;\r
                }\r
+               else if (!(target->cfg->flags & CONFIG_ENABLE_SCSI2))\r
+               {\r
+                       scsiDev.compatMode = COMPAT_SCSI1;\r
+               }\r
                else if (scsiDev.compatMode == COMPAT_UNKNOWN)\r
                {\r
                        scsiDev.compatMode = COMPAT_SCSI2;\r
@@ -723,7 +727,7 @@ static void process_MessageOut()
                        // Discard bytes.\r
                        extmsg[i] = scsiReadByte();\r
                }\r
-               \r
+\r
                if (extmsg[0] == 3 && msgLen == 2) // Wide Data Request\r
                {\r
                        // Negotiate down to 8bit\r
@@ -731,7 +735,7 @@ static void process_MessageOut()
                        static const uint8_t WDTR[] = {0x01, 0x02, 0x03, 0x00};\r
                        scsiWrite(WDTR, sizeof(WDTR));\r
                }\r
-               else if (extmsg[0] == 1 && msgLen == 5) // Synchronous data request\r
+               else if (extmsg[0] == 1 && msgLen == 3) // Synchronous data request\r
                {\r
                        // Negotiate back to async\r
                        scsiEnterPhase(MESSAGE_IN);\r
index dd3a579..08e774c 100755 (executable)
@@ -25,8 +25,9 @@
 \r
 #define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG)\r
 \r
-// DMA controller can't handle any more bytes.\r
-#define MAX_DMA_BYTES 4095\r
+// DMA controller can't handle any more than 4095 bytes,\r
+// but we round down to nearest multiple of 4 bytes..\r
+#define MAX_DMA_BYTES 4088\r
 \r
 // Private DMA variables.\r
 static int dmaInProgress = 0;\r
@@ -235,7 +236,8 @@ scsiRead(uint8_t* data, uint32_t count)
        }\r
        else\r
        {\r
-               scsiReadDMA(data, count);\r
+               uint32_t alignedCount = count & 0xFFFFFFF8;\r
+               scsiReadDMA(data, alignedCount);\r
 \r
                // Wait for the next DMA interrupt (or the 1ms systick)\r
                // It's beneficial to halt the processor to\r
@@ -243,7 +245,15 @@ scsiRead(uint8_t* data, uint32_t count)
                __WFI();\r
 \r
                trace(trace_spinReadDMAPoll);\r
-               while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) {};\r
+               while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag))\r
+               {\r
+                       __WFI();\r
+               };\r
+\r
+               if (count > alignedCount)\r
+               {\r
+                       scsiReadPIO(data + alignedCount, count - alignedCount);\r
+               }\r
        }\r
 }\r
 \r
@@ -363,7 +373,8 @@ scsiWrite(const uint8_t* data, uint32_t count)
        }\r
        else\r
        {\r
-               scsiWriteDMA(data, count);\r
+               uint32_t alignedCount = count & 0xFFFFFFF8;\r
+               scsiWriteDMA(data, alignedCount);\r
 \r
                // Wait for the next DMA interrupt (or the 1ms systick)\r
                // It's beneficial to halt the processor to\r
@@ -371,7 +382,15 @@ scsiWrite(const uint8_t* data, uint32_t count)
                __WFI();\r
 \r
                trace(trace_spinWriteDMAPoll);\r
-               while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) {};\r
+               while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag))\r
+               {\r
+                       __WFI();\r
+               };\r
+               \r
+               if (count > alignedCount)\r
+               {\r
+                       scsiWritePIO(data + alignedCount, count - alignedCount);\r
+               }\r
        }\r
 }\r
 \r
@@ -452,7 +471,7 @@ static void scsiPhyInitDMA()
        {\r
                scsiDmaRxChan =\r
                        SCSI_RX_DMA_DmaInitialize(\r
-                               1, // Bytes per burst\r
+                               4, // Bytes per burst\r
                                1, // request per burst\r
                                HI16(CYDEV_PERIPH_BASE),\r
                                HI16(CYDEV_SRAM_BASE)\r
@@ -460,7 +479,7 @@ static void scsiPhyInitDMA()
 \r
                scsiDmaTxChan =\r
                        SCSI_TX_DMA_DmaInitialize(\r
-                               1, // Bytes per burst\r
+                               4, // Bytes per burst\r
                                1, // request per burst\r
                                HI16(CYDEV_SRAM_BASE),\r
                                HI16(CYDEV_PERIPH_BASE)\r
@@ -486,6 +505,13 @@ void scsiPhyInit()
 \r
        SCSI_SEL_ISR_StartEx(scsiSelectionISR);\r
 \r
+/*\r
+       // Disable the glitch filter for ACK to improve performance.\r
+       // TODO NEED SOME CONFIG\r
+       SCSI_Glitch_Ctl_Write(1);\r
+       CY_SET_REG8(scsiTarget_datapath__D0_REG, 0);\r
+*/\r
+\r
 }\r
 \r
 // 1 = DBx error\r
index fdc2b7d..e11e8b6 100755 (executable)
@@ -41,16 +41,18 @@ static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL;
 static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL;\r
 \r
 // Dummy location for DMA to send unchecked CRC bytes to\r
-static uint8 discardBuffer;\r
+static uint8 discardBuffer __attribute__((aligned(4)));\r
 \r
 // 2 bytes CRC, response, 8bits to close the clock..\r
 // "NCR" time is up to 8 bytes.\r
-static uint8_t writeResponseBuffer[8];\r
+static uint8_t writeResponseBuffer[8]  __attribute__((aligned(4)));\r
 \r
-static uint8_t writeStartToken = 0xFC;\r
+// Padded with a dummy byte just to allow the tx DMA channel to\r
+// use 2-byte bursts for performance.\r
+static uint8_t writeStartToken[2]  __attribute__((aligned(4))) = {0xFF, 0xFC};\r
 \r
 // Source of dummy SPI bytes for DMA\r
-static uint8 dummyBuffer = 0xFF;\r
+static uint8_t dummyBuffer[2]  __attribute__((aligned(4))) = {0xFF, 0xFF};\r
 \r
 volatile uint8_t sdRxDMAComplete;\r
 volatile uint8_t sdTxDMAComplete;\r
@@ -109,7 +111,8 @@ static uint16_t sdDoCommand(
 \r
        // send is static as the address must remain consistent for the static\r
        // DMA descriptors to work.\r
-       static uint8_t send[7];\r
+       // Size must be divisible by 2 to suit 2-byte-burst TX DMA channel.\r
+       static uint8_t send[6] __attribute__((aligned(4)));\r
        send[0] = cmd | 0x40;\r
        send[1] = param >> 24;\r
        send[2] = param >> 16;\r
@@ -123,7 +126,6 @@ static uint16_t sdDoCommand(
        {\r
                send[5] = 1; // stop bit\r
        }\r
-       send[6] = 0xFF; // Result code or stuff byte.\r
 \r
        static uint8_t dmaRxTd = CY_DMA_INVALID_TD;\r
        static uint8_t dmaTxTd = CY_DMA_INVALID_TD;\r
@@ -161,7 +163,7 @@ static uint16_t sdDoCommand(
        // The DMA controller is a bit trigger-happy. It will retain\r
        // a drq request that was triggered while the channel was\r
        // disabled.\r
-       CyDmaClearPendingDrq(sdDMATxChan);\r
+       CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ);\r
        CyDmaClearPendingDrq(sdDMARxChan);\r
 \r
        // There is no flow control, so we must ensure we can read the bytes\r
@@ -172,7 +174,7 @@ static uint16_t sdDoCommand(
        trace(trace_spinSDDMA);\r
        while (!(sdTxDMAComplete && sdRxDMAComplete)) { __WFI(); }\r
 \r
-       uint16_t response = discardBuffer;\r
+       uint16_t response = sdSpiByte(0xFF); // Result code or stuff byte\r
        if (unlikely(cmd == SD_STOP_TRANSMISSION))\r
        {\r
                // Stuff byte is required for this command only.\r
@@ -313,7 +315,7 @@ dmaReadSector(uint8_t* outputBuffer)
        // The DMA controller is a bit trigger-happy. It will retain\r
        // a drq request that was triggered while the channel was\r
        // disabled.\r
-       CyDmaClearPendingDrq(sdDMATxChan);\r
+       CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ);\r
        CyDmaClearPendingDrq(sdDMARxChan);\r
 \r
        // There is no flow control, so we must ensure we can read the bytes\r
@@ -423,7 +425,7 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer)
                \r
                // Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte\r
                // We need to do this without stopping the clock\r
-               CyDmaTdSetConfiguration(dmaTxTd[0], 1, dmaTxTd[1], TD_INC_SRC_ADR);\r
+               CyDmaTdSetConfiguration(dmaTxTd[0], 2, dmaTxTd[1], TD_INC_SRC_ADR);\r
                CyDmaTdSetAddress(dmaTxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR));\r
 \r
                CyDmaTdSetConfiguration(dmaTxTd[1], SD_SECTOR_SIZE, dmaTxTd[2], TD_INC_SRC_ADR);\r
@@ -431,7 +433,7 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer)
                CyDmaTdSetConfiguration(dmaTxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
                CyDmaTdSetAddress(dmaTxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
 \r
-               CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 3, dmaRxTd[1], 0);\r
+               CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 4, dmaRxTd[1], 0);\r
                CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
                CyDmaTdSetConfiguration(dmaRxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR);\r
                CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer));\r
@@ -443,7 +445,7 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer)
        // The DMA controller is a bit trigger-happy. It will retain\r
        // a drq request that was triggered while the channel was\r
        // disabled.\r
-       CyDmaClearPendingDrq(sdDMATxChan);\r
+       CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ);\r
        CyDmaClearPendingDrq(sdDMARxChan);\r
 \r
        sdTxDMAComplete = 0;\r
@@ -733,7 +735,7 @@ static void sdInitDMA()
        {\r
                sdDMATxChan =\r
                        SD_TX_DMA_DmaInitialize(\r
-                               1, // Bytes per burst\r
+                               2, // Bytes per burst\r
                                1, // request per burst\r
                                HI16(CYDEV_SRAM_BASE),\r
                                HI16(CYDEV_PERIPH_BASE)\r
@@ -898,7 +900,8 @@ void sdPoll()
                SD_CS_Write(0);\r
                SD_CS_SetDriveMode(SD_CS_DM_DIG_HIZ);\r
 \r
-               CyDelayCycles(64);\r
+               // Delay extended to work with 60cm cables running cards at 2.85V\r
+               CyDelayCycles(128);\r
                uint8_t cs = SD_CS_Read();\r
                SD_CS_SetDriveMode(SD_CS_DM_STRONG)     ;\r
 \r
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c
new file mode 100644 (file)
index 0000000..8c80437
--- /dev/null
@@ -0,0 +1,63 @@
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl.c  
+* Version 1.70
+*
+* Description:
+*  This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Glitch_Ctl.h"
+
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Write
+********************************************************************************
+*
+* Summary:
+*  Write a byte to the Control Register.
+*
+* Parameters:
+*  control:  The value to be assigned to the Control Register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Write(uint8 control) 
+{
+    SCSI_Glitch_Ctl_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Control Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_Glitch_Ctl_Read(void) 
+{
+    return SCSI_Glitch_Ctl_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h
new file mode 100644 (file)
index 0000000..bcd7650
--- /dev/null
@@ -0,0 +1,42 @@
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl.h  
+* Version 1.70
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
+#define CY_CONTROL_REG_SCSI_Glitch_Ctl_H
+
+#include "cytypes.h"
+
+
+/***************************************
+*         Function Prototypes 
+***************************************/
+
+void    SCSI_Glitch_Ctl_Write(uint8 control) ;
+uint8   SCSI_Glitch_Ctl_Read(void) ;
+
+
+/***************************************
+*            Registers        
+***************************************/
+
+/* Control Register */
+#define SCSI_Glitch_Ctl_Control        (* (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_Glitch_Ctl_Control_PTR    (  (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
+
+
+/* [] END OF FILE */
index 124adc7..adee8b3 100644 (file)
@@ -146,8 +146,8 @@ extern uint8 SDCard_initVar;
 ***************************************/\r
 \r
 #define SDCard_INT_ON_SPI_DONE    ((uint8) (0u   << SDCard_STS_SPI_DONE_SHIFT))\r
-#define SDCard_INT_ON_TX_EMPTY    ((uint8) (0u   << SDCard_STS_TX_FIFO_EMPTY_SHIFT))\r
-#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (1u << \\r
+#define SDCard_INT_ON_TX_EMPTY    ((uint8) (1u   << SDCard_STS_TX_FIFO_EMPTY_SHIFT))\r
+#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \\r
                                                                            SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))\r
 #define SDCard_INT_ON_BYTE_COMP   ((uint8) (0u  << SDCard_STS_BYTE_COMPLETE_SHIFT))\r
 #define SDCard_INT_ON_SPI_IDLE    ((uint8) (0u   << SDCard_STS_SPI_IDLE_SHIFT))\r
index bda3f9f..ebd35c1 100644 (file)
 #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
 \r
 /* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_RxStsReg__4__POS 4\r
 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
 #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
 #define SDCard_BSPIM_RxStsReg__6__POS 6\r
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
 #define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
 #define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
 #define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
 #define SDCard_BSPIM_TxStsReg__0__POS 0\r
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL\r
 #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK\r
 \r
 /* SCSI_Out_Ctl */\r
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
 #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
 \r
 /* SCSI_Out_DBx */\r
 #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
 #define scsiTarget_StatusReg__0__POS 0\r
 #define scsiTarget_StatusReg__1__MASK 0x02u\r
 #define scsiTarget_StatusReg__1__POS 1\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
 #define scsiTarget_StatusReg__2__MASK 0x04u\r
 #define scsiTarget_StatusReg__2__POS 2\r
 #define scsiTarget_StatusReg__3__MASK 0x08u\r
 #define scsiTarget_StatusReg__4__MASK 0x10u\r
 #define scsiTarget_StatusReg__4__POS 4\r
 #define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST\r
 \r
 /* Debug_Timer_Interrupt */\r
 #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define SCSI_Filtered_sts_sts_reg__0__POS 0\r
 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
 #define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
 #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
 #define SCSI_Filtered_sts_sts_reg__2__POS 2\r
 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
 #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
 #define SCSI_Filtered_sts_sts_reg__4__POS 4\r
 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK\r
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST\r
 \r
 /* SCSI_CTL_PHASE */\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
+\r
+/* SCSI_Glitch_Ctl */\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
 \r
 /* SCSI_Parity_Error */\r
 #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
 #define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
 #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST\r
 \r
 /* Miscellaneous */\r
 #define BCLK__BUS_CLK__HZ 50000000U\r
index 8829a4f..77d7a0e 100644 (file)
@@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode)
 }\r
 #endif\r
 \r
-#define CY_CFG_BASE_ADDR_COUNT 40u\r
+#define CY_CFG_BASE_ADDR_COUNT 42u\r
 CYPACKED typedef struct\r
 {\r
        uint8 offset;\r
@@ -383,92 +383,96 @@ void cyfitter_cfg(void)
                        0x4000520Cu, /* Base address: 0x40005200 Count: 12 */\r
                        0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
                        0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
-                       0x40010036u, /* Base address: 0x40010000 Count: 54 */\r
-                       0x4001013Du, /* Base address: 0x40010100 Count: 61 */\r
+                       0x40010039u, /* Base address: 0x40010000 Count: 57 */\r
+                       0x40010135u, /* Base address: 0x40010100 Count: 53 */\r
                        0x40010243u, /* Base address: 0x40010200 Count: 67 */\r
-                       0x40010358u, /* Base address: 0x40010300 Count: 88 */\r
-                       0x40010448u, /* Base address: 0x40010400 Count: 72 */\r
-                       0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
-                       0x4001064Cu, /* Base address: 0x40010600 Count: 76 */\r
-                       0x40010746u, /* Base address: 0x40010700 Count: 70 */\r
-                       0x4001083Fu, /* Base address: 0x40010800 Count: 63 */\r
-                       0x40010948u, /* Base address: 0x40010900 Count: 72 */\r
-                       0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */\r
-                       0x40010B4Au, /* Base address: 0x40010B00 Count: 74 */\r
-                       0x40010C42u, /* Base address: 0x40010C00 Count: 66 */\r
-                       0x40010D4Cu, /* Base address: 0x40010D00 Count: 76 */\r
-                       0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */\r
-                       0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */\r
-                       0x4001142Cu, /* Base address: 0x40011400 Count: 44 */\r
-                       0x40011550u, /* Base address: 0x40011500 Count: 80 */\r
-                       0x4001163Eu, /* Base address: 0x40011600 Count: 62 */\r
-                       0x4001173Fu, /* Base address: 0x40011700 Count: 63 */\r
-                       0x40011904u, /* Base address: 0x40011900 Count: 4 */\r
-                       0x40011B02u, /* Base address: 0x40011B00 Count: 2 */\r
+                       0x40010354u, /* Base address: 0x40010300 Count: 84 */\r
+                       0x4001043Fu, /* Base address: 0x40010400 Count: 63 */\r
+                       0x40010551u, /* Base address: 0x40010500 Count: 81 */\r
+                       0x4001064Au, /* Base address: 0x40010600 Count: 74 */\r
+                       0x4001074Du, /* Base address: 0x40010700 Count: 77 */\r
+                       0x40010804u, /* Base address: 0x40010800 Count: 4 */\r
+                       0x4001091Eu, /* Base address: 0x40010900 Count: 30 */\r
+                       0x40010A54u, /* Base address: 0x40010A00 Count: 84 */\r
+                       0x40010B53u, /* Base address: 0x40010B00 Count: 83 */\r
+                       0x40010C4Eu, /* Base address: 0x40010C00 Count: 78 */\r
+                       0x40010D52u, /* Base address: 0x40010D00 Count: 82 */\r
+                       0x40010E42u, /* Base address: 0x40010E00 Count: 66 */\r
+                       0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */\r
+                       0x4001145Du, /* Base address: 0x40011400 Count: 93 */\r
+                       0x40011552u, /* Base address: 0x40011500 Count: 82 */\r
+                       0x40011653u, /* Base address: 0x40011600 Count: 83 */\r
+                       0x40011744u, /* Base address: 0x40011700 Count: 68 */\r
+                       0x40011912u, /* Base address: 0x40011900 Count: 18 */\r
+                       0x40011A4Au, /* Base address: 0x40011A00 Count: 74 */\r
+                       0x40011B47u, /* Base address: 0x40011B00 Count: 71 */\r
                        0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
-                       0x4001411Bu, /* Base address: 0x40014100 Count: 27 */\r
+                       0x4001411Du, /* Base address: 0x40014100 Count: 29 */\r
                        0x40014211u, /* Base address: 0x40014200 Count: 17 */\r
-                       0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
-                       0x40014411u, /* Base address: 0x40014400 Count: 17 */\r
+                       0x4001430Eu, /* Base address: 0x40014300 Count: 14 */\r
+                       0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
                        0x40014517u, /* Base address: 0x40014500 Count: 23 */\r
-                       0x40014608u, /* Base address: 0x40014600 Count: 8 */\r
-                       0x4001470Du, /* Base address: 0x40014700 Count: 13 */\r
-                       0x40014806u, /* Base address: 0x40014800 Count: 6 */\r
-                       0x40014908u, /* Base address: 0x40014900 Count: 8 */\r
+                       0x4001460Fu, /* Base address: 0x40014600 Count: 15 */\r
+                       0x4001470Bu, /* Base address: 0x40014700 Count: 11 */\r
+                       0x4001480Eu, /* Base address: 0x40014800 Count: 14 */\r
+                       0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
+                       0x40014C03u, /* Base address: 0x40014C00 Count: 3 */\r
                        0x40014D04u, /* Base address: 0x40014D00 Count: 4 */\r
-                       0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
+                       0x40015005u, /* Base address: 0x40015000 Count: 5 */\r
                        0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
                };\r
 \r
                static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
                        {0x7Eu, 0x02u},\r
                        {0x01u, 0x20u},\r
-                       {0x0Au, 0x4Bu},\r
-                       {0x00u, 0x11u},\r
-                       {0x01u, 0x02u},\r
+                       {0x0Au, 0x1Bu},\r
+                       {0x00u, 0x14u},\r
+                       {0x01u, 0x11u},\r
                        {0x18u, 0x08u},\r
                        {0x19u, 0x04u},\r
                        {0x1Cu, 0x71u},\r
-                       {0x20u, 0xA0u},\r
-                       {0x21u, 0x68u},\r
+                       {0x20u, 0x60u},\r
+                       {0x21u, 0xA0u},\r
                        {0x2Cu, 0x0Eu},\r
-                       {0x30u, 0x0Au},\r
-                       {0x31u, 0x0Cu},\r
+                       {0x30u, 0x06u},\r
+                       {0x31u, 0x03u},\r
                        {0x34u, 0x80u},\r
                        {0x7Cu, 0x40u},\r
                        {0x20u, 0x02u},\r
-                       {0x84u, 0x0Fu},\r
-                       {0x00u, 0x80u},\r
-                       {0x04u, 0x10u},\r
-                       {0x0Cu, 0x02u},\r
-                       {0x0Du, 0x02u},\r
-                       {0x0Eu, 0x28u},\r
-                       {0x10u, 0x01u},\r
-                       {0x14u, 0x32u},\r
-                       {0x15u, 0x04u},\r
-                       {0x16u, 0x44u},\r
-                       {0x1Au, 0x04u},\r
-                       {0x1Du, 0x08u},\r
-                       {0x24u, 0x4Cu},\r
-                       {0x26u, 0x32u},\r
-                       {0x29u, 0x01u},\r
-                       {0x2Eu, 0x7Eu},\r
-                       {0x30u, 0x0Eu},\r
-                       {0x31u, 0x08u},\r
-                       {0x32u, 0x70u},\r
-                       {0x33u, 0x04u},\r
-                       {0x34u, 0x01u},\r
-                       {0x35u, 0x01u},\r
-                       {0x36u, 0x80u},\r
-                       {0x37u, 0x02u},\r
+                       {0x85u, 0x0Fu},\r
+                       {0x00u, 0x01u},\r
+                       {0x02u, 0x02u},\r
+                       {0x04u, 0x04u},\r
+                       {0x05u, 0x04u},\r
+                       {0x14u, 0x02u},\r
+                       {0x15u, 0x08u},\r
+                       {0x16u, 0x01u},\r
+                       {0x18u, 0x02u},\r
+                       {0x1Au, 0x01u},\r
+                       {0x1Cu, 0x10u},\r
+                       {0x21u, 0x01u},\r
+                       {0x24u, 0x02u},\r
+                       {0x26u, 0x01u},\r
+                       {0x2Bu, 0x02u},\r
+                       {0x2Cu, 0x02u},\r
+                       {0x2Eu, 0x09u},\r
+                       {0x30u, 0x03u},\r
+                       {0x31u, 0x04u},\r
+                       {0x32u, 0x08u},\r
+                       {0x33u, 0x08u},\r
+                       {0x34u, 0x04u},\r
+                       {0x35u, 0x02u},\r
+                       {0x36u, 0x10u},\r
+                       {0x37u, 0x01u},\r
+                       {0x3Au, 0x02u},\r
                        {0x3Eu, 0x50u},\r
-                       {0x3Fu, 0x55u},\r
-                       {0x40u, 0x42u},\r
-                       {0x41u, 0x03u},\r
+                       {0x3Fu, 0x45u},\r
+                       {0x40u, 0x34u},\r
+                       {0x41u, 0x06u},\r
                        {0x42u, 0x50u},\r
-                       {0x45u, 0xF2u},\r
-                       {0x46u, 0xCDu},\r
-                       {0x47u, 0x0Eu},\r
+                       {0x45u, 0xCDu},\r
+                       {0x46u, 0xE2u},\r
+                       {0x47u, 0x0Fu},\r
                        {0x48u, 0x1Fu},\r
                        {0x49u, 0xFFu},\r
                        {0x4Au, 0xFFu},\r
@@ -479,7 +483,7 @@ void cyfitter_cfg(void)
                        {0x59u, 0x04u},\r
                        {0x5Au, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x01u},\r
+                       {0x5Cu, 0x99u},\r
                        {0x5Du, 0x01u},\r
                        {0x5Fu, 0x01u},\r
                        {0x62u, 0xC0u},\r
@@ -487,132 +491,125 @@ void cyfitter_cfg(void)
                        {0x68u, 0x40u},\r
                        {0x69u, 0x40u},\r
                        {0x6Eu, 0x08u},\r
-                       {0x88u, 0x01u},\r
-                       {0xB6u, 0x01u},\r
-                       {0xBEu, 0x40u},\r
-                       {0xD8u, 0x04u},\r
+                       {0xADu, 0x01u},\r
+                       {0xB3u, 0x01u},\r
+                       {0xBFu, 0x04u},\r
+                       {0xD9u, 0x04u},\r
+                       {0xDBu, 0x04u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x41u},\r
-                       {0x03u, 0x10u},\r
-                       {0x05u, 0x10u},\r
-                       {0x0Au, 0x10u},\r
-                       {0x0Bu, 0x44u},\r
+                       {0x01u, 0x02u},\r
+                       {0x02u, 0x10u},\r
+                       {0x09u, 0x80u},\r
+                       {0x0Au, 0x18u},\r
                        {0x11u, 0x40u},\r
                        {0x12u, 0x20u},\r
-                       {0x18u, 0x40u},\r
-                       {0x19u, 0x48u},\r
-                       {0x1Au, 0x10u},\r
-                       {0x1Bu, 0x12u},\r
-                       {0x1Du, 0x80u},\r
-                       {0x20u, 0x04u},\r
+                       {0x19u, 0x12u},\r
+                       {0x1Au, 0x12u},\r
+                       {0x1Bu, 0x04u},\r
                        {0x21u, 0x02u},\r
-                       {0x23u, 0x22u},\r
-                       {0x2Bu, 0x04u},\r
-                       {0x31u, 0x04u},\r
-                       {0x32u, 0x80u},\r
-                       {0x3Au, 0x40u},\r
-                       {0x41u, 0x10u},\r
-                       {0x42u, 0x10u},\r
-                       {0x43u, 0x02u},\r
-                       {0x48u, 0x01u},\r
-                       {0x49u, 0x02u},\r
-                       {0x4Bu, 0x04u},\r
-                       {0x50u, 0x10u},\r
-                       {0x52u, 0x04u},\r
-                       {0x53u, 0x80u},\r
-                       {0x59u, 0x40u},\r
-                       {0x5Au, 0x08u},\r
-                       {0x5Bu, 0x22u},\r
-                       {0x60u, 0x04u},\r
-                       {0x61u, 0x82u},\r
-                       {0x63u, 0x20u},\r
-                       {0x68u, 0x90u},\r
-                       {0x69u, 0x10u},\r
-                       {0x6Au, 0x80u},\r
-                       {0x70u, 0x60u},\r
-                       {0x72u, 0x40u},\r
-                       {0x73u, 0x10u},\r
-                       {0x81u, 0x02u},\r
-                       {0x83u, 0x10u},\r
-                       {0x85u, 0x40u},\r
-                       {0x88u, 0x40u},\r
-                       {0x89u, 0x08u},\r
-                       {0x8Cu, 0x40u},\r
-                       {0x8Eu, 0x10u},\r
-                       {0xC0u, 0x4Du},\r
-                       {0xC2u, 0x0Eu},\r
+                       {0x22u, 0xA8u},\r
+                       {0x27u, 0x10u},\r
+                       {0x2Bu, 0x44u},\r
+                       {0x2Fu, 0x01u},\r
+                       {0x31u, 0x08u},\r
+                       {0x3Au, 0x04u},\r
+                       {0x41u, 0x04u},\r
+                       {0x43u, 0x01u},\r
+                       {0x48u, 0xD4u},\r
+                       {0x49u, 0x04u},\r
+                       {0x4Au, 0x01u},\r
+                       {0x50u, 0x40u},\r
+                       {0x53u, 0xA4u},\r
+                       {0x5Au, 0x46u},\r
+                       {0x5Bu, 0x10u},\r
+                       {0x61u, 0x12u},\r
+                       {0x62u, 0x88u},\r
+                       {0x69u, 0x86u},\r
+                       {0x6Bu, 0x08u},\r
+                       {0x6Cu, 0x30u},\r
+                       {0x6Eu, 0x08u},\r
+                       {0x6Fu, 0x0Au},\r
+                       {0x72u, 0x02u},\r
+                       {0x73u, 0x64u},\r
+                       {0x82u, 0x04u},\r
+                       {0x83u, 0x08u},\r
+                       {0x85u, 0x02u},\r
+                       {0x87u, 0x02u},\r
+                       {0x89u, 0x01u},\r
+                       {0x8Du, 0x40u},\r
+                       {0x8Fu, 0x20u},\r
+                       {0xC0u, 0x0Cu},\r
+                       {0xC2u, 0x07u},\r
                        {0xC4u, 0x05u},\r
-                       {0xCAu, 0x04u},\r
-                       {0xCCu, 0x0Au},\r
-                       {0xCEu, 0x08u},\r
-                       {0xD0u, 0x07u},\r
-                       {0xD2u, 0x08u},\r
+                       {0xCAu, 0x15u},\r
+                       {0xCCu, 0x02u},\r
+                       {0xCEu, 0x02u},\r
+                       {0xD0u, 0x03u},\r
+                       {0xD2u, 0x0Cu},\r
                        {0xD6u, 0x0Fu},\r
                        {0xD8u, 0x0Fu},\r
-                       {0xE0u, 0x06u},\r
-                       {0xE2u, 0x10u},\r
-                       {0xE4u, 0x04u},\r
-                       {0xE6u, 0x20u},\r
-                       {0x09u, 0x05u},\r
-                       {0x0Bu, 0x0Au},\r
-                       {0x0Du, 0x0Fu},\r
-                       {0x0Eu, 0x01u},\r
-                       {0x0Fu, 0xF0u},\r
-                       {0x10u, 0x01u},\r
-                       {0x12u, 0x02u},\r
-                       {0x15u, 0x60u},\r
-                       {0x17u, 0x90u},\r
-                       {0x19u, 0x30u},\r
-                       {0x1Bu, 0xC0u},\r
-                       {0x1Du, 0x06u},\r
-                       {0x1Fu, 0x09u},\r
-                       {0x21u, 0x03u},\r
-                       {0x23u, 0x0Cu},\r
-                       {0x25u, 0x50u},\r
-                       {0x26u, 0x02u},\r
-                       {0x27u, 0xA0u},\r
-                       {0x30u, 0x03u},\r
-                       {0x37u, 0xFFu},\r
-                       {0x3Eu, 0x01u},\r
-                       {0x3Fu, 0x40u},\r
+                       {0xE4u, 0x0Cu},\r
+                       {0xE6u, 0x02u},\r
+                       {0x04u, 0x09u},\r
+                       {0x05u, 0x0Cu},\r
+                       {0x06u, 0x02u},\r
+                       {0x07u, 0x30u},\r
+                       {0x09u, 0x13u},\r
+                       {0x0Bu, 0x44u},\r
+                       {0x0Cu, 0x0Au},\r
+                       {0x0Du, 0x08u},\r
+                       {0x0Eu, 0x05u},\r
+                       {0x13u, 0x7Fu},\r
+                       {0x14u, 0x04u},\r
+                       {0x16u, 0x08u},\r
+                       {0x17u, 0x02u},\r
+                       {0x1Au, 0x07u},\r
+                       {0x1Du, 0x6Cu},\r
+                       {0x1Fu, 0x13u},\r
+                       {0x23u, 0x20u},\r
+                       {0x25u, 0x03u},\r
+                       {0x26u, 0x08u},\r
+                       {0x29u, 0x71u},\r
+                       {0x34u, 0x0Fu},\r
+                       {0x37u, 0x7Fu},\r
                        {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
+                       {0x5Cu, 0x11u},\r
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x83u, 0x1Fu},\r
-                       {0x85u, 0x3Fu},\r
-                       {0x86u, 0x70u},\r
-                       {0x87u, 0x40u},\r
-                       {0x89u, 0x03u},\r
-                       {0x8Cu, 0x44u},\r
-                       {0x8Du, 0x20u},\r
-                       {0x8Eu, 0x88u},\r
-                       {0x8Fu, 0x5Cu},\r
-                       {0x94u, 0x99u},\r
-                       {0x95u, 0x18u},\r
-                       {0x96u, 0x22u},\r
-                       {0x97u, 0x03u},\r
-                       {0x98u, 0xAAu},\r
-                       {0x9Au, 0x55u},\r
-                       {0x9Bu, 0x01u},\r
-                       {0x9Du, 0x10u},\r
-                       {0x9Eu, 0x07u},\r
-                       {0x9Fu, 0x60u},\r
-                       {0xA1u, 0x02u},\r
-                       {0xA5u, 0x27u},\r
+                       {0x83u, 0x08u},\r
+                       {0x84u, 0x09u},\r
+                       {0x85u, 0x44u},\r
+                       {0x86u, 0x02u},\r
+                       {0x87u, 0x88u},\r
+                       {0x8Au, 0x07u},\r
+                       {0x8Bu, 0x07u},\r
+                       {0x8Cu, 0x40u},\r
+                       {0x8Eu, 0x80u},\r
+                       {0x8Fu, 0x80u},\r
+                       {0x90u, 0x20u},\r
+                       {0x94u, 0x10u},\r
+                       {0x97u, 0x70u},\r
+                       {0x99u, 0x99u},\r
+                       {0x9Au, 0x40u},\r
+                       {0x9Bu, 0x22u},\r
+                       {0x9Du, 0xAAu},\r
+                       {0x9Fu, 0x55u},\r
+                       {0xA0u, 0x0Au},\r
+                       {0xA2u, 0x05u},\r
                        {0xA6u, 0x08u},\r
-                       {0xA7u, 0x50u},\r
-                       {0xA9u, 0x80u},\r
-                       {0xAAu, 0x80u},\r
-                       {0xB3u, 0x80u},\r
-                       {0xB4u, 0xF0u},\r
+                       {0xA8u, 0x04u},\r
+                       {0xAAu, 0x08u},\r
+                       {0xAEu, 0x80u},\r
+                       {0xB0u, 0x20u},\r
+                       {0xB2u, 0x0Fu},\r
+                       {0xB3u, 0xF0u},\r
+                       {0xB4u, 0x10u},\r
                        {0xB5u, 0x0Fu},\r
-                       {0xB6u, 0x0Fu},\r
-                       {0xB7u, 0x70u},\r
-                       {0xBBu, 0x80u},\r
-                       {0xBFu, 0x04u},\r
+                       {0xB6u, 0xC0u},\r
+                       {0xBEu, 0x51u},\r
                        {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
@@ -620,1384 +617,1551 @@ void cyfitter_cfg(void)
                        {0xDCu, 0x11u},\r
                        {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x40u},\r
-                       {0x03u, 0x20u},\r
-                       {0x05u, 0x40u},\r
+                       {0x00u, 0x04u},\r
+                       {0x03u, 0x0Au},\r
+                       {0x04u, 0x04u},\r
+                       {0x07u, 0x01u},\r
+                       {0x08u, 0x0Au},\r
                        {0x09u, 0x20u},\r
-                       {0x0Au, 0x12u},\r
-                       {0x0Cu, 0x02u},\r
-                       {0x0Fu, 0x80u},\r
-                       {0x10u, 0x20u},\r
-                       {0x13u, 0x10u},\r
-                       {0x17u, 0x04u},\r
+                       {0x0Cu, 0x10u},\r
+                       {0x0Eu, 0x08u},\r
+                       {0x0Fu, 0x10u},\r
+                       {0x12u, 0x82u},\r
+                       {0x13u, 0x14u},\r
+                       {0x17u, 0x08u},\r
                        {0x19u, 0x40u},\r
-                       {0x1Au, 0x02u},\r
-                       {0x1Bu, 0x30u},\r
-                       {0x1Cu, 0x80u},\r
-                       {0x20u, 0x06u},\r
-                       {0x21u, 0xB0u},\r
-                       {0x22u, 0x24u},\r
-                       {0x23u, 0x08u},\r
-                       {0x25u, 0x40u},\r
-                       {0x28u, 0x08u},\r
-                       {0x29u, 0x08u},\r
-                       {0x2Bu, 0x80u},\r
-                       {0x2Du, 0x01u},\r
-                       {0x2Eu, 0x04u},\r
-                       {0x31u, 0x80u},\r
-                       {0x32u, 0x08u},\r
-                       {0x33u, 0x10u},\r
-                       {0x34u, 0x10u},\r
-                       {0x35u, 0x40u},\r
-                       {0x37u, 0x04u},\r
-                       {0x38u, 0x64u},\r
+                       {0x1Au, 0x44u},\r
+                       {0x1Bu, 0x08u},\r
+                       {0x1Eu, 0x08u},\r
+                       {0x21u, 0x30u},\r
+                       {0x22u, 0x08u},\r
+                       {0x26u, 0x80u},\r
+                       {0x27u, 0x01u},\r
+                       {0x2Cu, 0x20u},\r
+                       {0x2Eu, 0x20u},\r
+                       {0x2Fu, 0x80u},\r
+                       {0x32u, 0x98u},\r
+                       {0x35u, 0x06u},\r
+                       {0x36u, 0x80u},\r
+                       {0x39u, 0xA8u},\r
                        {0x3Au, 0x02u},\r
-                       {0x3Fu, 0xA0u},\r
-                       {0x58u, 0x66u},\r
-                       {0x5Du, 0x80u},\r
-                       {0x5Fu, 0x20u},\r
-                       {0x61u, 0x04u},\r
-                       {0x62u, 0x80u},\r
-                       {0x63u, 0x48u},\r
-                       {0x65u, 0x30u},\r
-                       {0x66u, 0x40u},\r
-                       {0x67u, 0x02u},\r
-                       {0x6Du, 0x28u},\r
-                       {0x6Eu, 0x80u},\r
-                       {0x6Fu, 0x10u},\r
-                       {0x80u, 0x30u},\r
-                       {0x85u, 0x80u},\r
-                       {0x86u, 0x40u},\r
-                       {0x87u, 0xA0u},\r
-                       {0x88u, 0x42u},\r
-                       {0x8Au, 0x0Au},\r
-                       {0x8Du, 0x04u},\r
-                       {0x90u, 0x60u},\r
-                       {0x91u, 0x10u},\r
-                       {0x92u, 0xF0u},\r
-                       {0x93u, 0x14u},\r
-                       {0x94u, 0x01u},\r
-                       {0x95u, 0x60u},\r
-                       {0x96u, 0x08u},\r
-                       {0x97u, 0x40u},\r
-                       {0x99u, 0x08u},\r
-                       {0x9Du, 0x14u},\r
-                       {0x9Eu, 0x40u},\r
-                       {0x9Fu, 0x10u},\r
-                       {0xA0u, 0xA0u},\r
-                       {0xA3u, 0x82u},\r
-                       {0xA4u, 0x45u},\r
-                       {0xA5u, 0x40u},\r
-                       {0xA6u, 0xA0u},\r
-                       {0xA7u, 0x04u},\r
-                       {0xAAu, 0x04u},\r
-                       {0xACu, 0x14u},\r
-                       {0xADu, 0x10u},\r
-                       {0xB7u, 0x02u},\r
-                       {0xC0u, 0x85u},\r
-                       {0xC2u, 0x17u},\r
-                       {0xC4u, 0x26u},\r
-                       {0xCAu, 0xC7u},\r
-                       {0xCCu, 0x7Eu},\r
-                       {0xCEu, 0x3Fu},\r
-                       {0xD6u, 0x3Fu},\r
-                       {0xD8u, 0x3Fu},\r
-                       {0xE0u, 0x04u},\r
-                       {0xE2u, 0x0Au},\r
-                       {0xE4u, 0x08u},\r
-                       {0xE6u, 0x24u},\r
-                       {0xE8u, 0x0Bu},\r
-                       {0xEEu, 0x01u},\r
-                       {0x02u, 0x07u},\r
-                       {0x07u, 0x10u},\r
-                       {0x09u, 0x0Au},\r
-                       {0x0Bu, 0x05u},\r
-                       {0x0Cu, 0x44u},\r
-                       {0x0Du, 0x04u},\r
-                       {0x0Eu, 0x88u},\r
-                       {0x0Fu, 0x08u},\r
-                       {0x11u, 0x10u},\r
-                       {0x13u, 0x20u},\r
-                       {0x14u, 0x99u},\r
-                       {0x16u, 0x22u},\r
-                       {0x17u, 0x07u},\r
-                       {0x1Eu, 0x70u},\r
-                       {0x1Fu, 0x08u},\r
-                       {0x22u, 0x80u},\r
-                       {0x23u, 0x20u},\r
-                       {0x24u, 0xAAu},\r
-                       {0x25u, 0x09u},\r
-                       {0x26u, 0x55u},\r
-                       {0x27u, 0x02u},\r
-                       {0x2Au, 0x08u},\r
-                       {0x30u, 0x0Fu},\r
-                       {0x33u, 0x0Fu},\r
-                       {0x35u, 0x30u},\r
-                       {0x36u, 0xF0u},\r
+                       {0x3Cu, 0x88u},\r
                        {0x3Fu, 0x10u},\r
+                       {0x5Au, 0x80u},\r
+                       {0x5Bu, 0x26u},\r
+                       {0x5Fu, 0x80u},\r
+                       {0x61u, 0x80u},\r
+                       {0x62u, 0x14u},\r
+                       {0x63u, 0xA0u},\r
+                       {0x64u, 0x01u},\r
+                       {0x67u, 0x02u},\r
+                       {0x83u, 0x30u},\r
+                       {0x85u, 0x40u},\r
+                       {0x87u, 0x03u},\r
+                       {0x88u, 0x10u},\r
+                       {0x8Au, 0x10u},\r
+                       {0x8Bu, 0x02u},\r
+                       {0x90u, 0xA0u},\r
+                       {0x91u, 0x84u},\r
+                       {0x93u, 0x44u},\r
+                       {0x95u, 0x08u},\r
+                       {0x96u, 0x4Cu},\r
+                       {0x97u, 0x02u},\r
+                       {0x99u, 0x26u},\r
+                       {0x9Au, 0x02u},\r
+                       {0x9Bu, 0x08u},\r
+                       {0x9Eu, 0x14u},\r
+                       {0x9Fu, 0x01u},\r
+                       {0xA0u, 0x60u},\r
+                       {0xA2u, 0x20u},\r
+                       {0xA3u, 0x80u},\r
+                       {0xA4u, 0x04u},\r
+                       {0xA5u, 0x88u},\r
+                       {0xA6u, 0x01u},\r
+                       {0xA7u, 0x40u},\r
+                       {0xABu, 0xC0u},\r
+                       {0xACu, 0x10u},\r
+                       {0xADu, 0x20u},\r
+                       {0xAFu, 0x04u},\r
+                       {0xB0u, 0x80u},\r
+                       {0xB1u, 0x80u},\r
+                       {0xB7u, 0x20u},\r
+                       {0xC0u, 0xA7u},\r
+                       {0xC2u, 0x6Eu},\r
+                       {0xC4u, 0x2Fu},\r
+                       {0xCAu, 0xE0u},\r
+                       {0xCCu, 0xDEu},\r
+                       {0xCEu, 0x7Fu},\r
+                       {0xD6u, 0x1Fu},\r
+                       {0xD8u, 0x1Fu},\r
+                       {0xE0u, 0x02u},\r
+                       {0xE2u, 0x01u},\r
+                       {0xE4u, 0x01u},\r
+                       {0xE6u, 0x02u},\r
+                       {0xE8u, 0x0Cu},\r
+                       {0xECu, 0x0Cu},\r
+                       {0xEEu, 0x82u},\r
+                       {0x04u, 0x02u},\r
+                       {0x05u, 0x0Bu},\r
+                       {0x07u, 0x90u},\r
+                       {0x09u, 0x20u},\r
+                       {0x0Au, 0x04u},\r
+                       {0x0Bu, 0x03u},\r
+                       {0x0Cu, 0x02u},\r
+                       {0x0Fu, 0x04u},\r
+                       {0x12u, 0x20u},\r
+                       {0x15u, 0x08u},\r
+                       {0x16u, 0x08u},\r
+                       {0x19u, 0x21u},\r
+                       {0x1Au, 0x10u},\r
+                       {0x1Bu, 0x44u},\r
+                       {0x1Cu, 0x02u},\r
+                       {0x1Du, 0x14u},\r
+                       {0x1Fu, 0xABu},\r
+                       {0x20u, 0x02u},\r
+                       {0x21u, 0x40u},\r
+                       {0x23u, 0xBFu},\r
+                       {0x26u, 0x01u},\r
+                       {0x28u, 0x14u},\r
+                       {0x2Au, 0x28u},\r
+                       {0x2Bu, 0x0Eu},\r
+                       {0x30u, 0x02u},\r
+                       {0x32u, 0x0Cu},\r
+                       {0x33u, 0x1Fu},\r
+                       {0x34u, 0x01u},\r
+                       {0x35u, 0xE0u},\r
+                       {0x36u, 0x30u},\r
+                       {0x38u, 0x02u},\r
+                       {0x3Bu, 0x20u},\r
+                       {0x3Eu, 0x45u},\r
                        {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x11u},\r
+                       {0x5Cu, 0x19u},\r
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x84u, 0x10u},\r
-                       {0x85u, 0x69u},\r
-                       {0x86u, 0x20u},\r
-                       {0x87u, 0x96u},\r
-                       {0x88u, 0x06u},\r
-                       {0x8Au, 0x09u},\r
-                       {0x8Bu, 0xFFu},\r
-                       {0x8Cu, 0x07u},\r
-                       {0x8Eu, 0x08u},\r
-                       {0x8Fu, 0xFFu},\r
-                       {0x90u, 0x03u},\r
-                       {0x91u, 0x0Fu},\r
-                       {0x92u, 0x0Cu},\r
-                       {0x93u, 0xF0u},\r
-                       {0x94u, 0x05u},\r
-                       {0x95u, 0xFFu},\r
-                       {0x96u, 0x0Au},\r
-                       {0x99u, 0xFFu},\r
-                       {0x9Au, 0x02u},\r
-                       {0xA2u, 0x10u},\r
-                       {0xA3u, 0xFFu},\r
-                       {0xA6u, 0x20u},\r
-                       {0xA8u, 0x01u},\r
-                       {0xA9u, 0x55u},\r
-                       {0xABu, 0xAAu},\r
-                       {0xADu, 0x33u},\r
-                       {0xAEu, 0x03u},\r
-                       {0xAFu, 0xCCu},\r
-                       {0xB0u, 0x0Fu},\r
-                       {0xB4u, 0x30u},\r
-                       {0xB7u, 0xFFu},\r
-                       {0xBAu, 0x02u},\r
-                       {0xBBu, 0x80u},\r
+                       {0x80u, 0x01u},\r
+                       {0x85u, 0x01u},\r
+                       {0x87u, 0x02u},\r
+                       {0x88u, 0x02u},\r
+                       {0x89u, 0x04u},\r
+                       {0x8Bu, 0x03u},\r
+                       {0x95u, 0x08u},\r
+                       {0x97u, 0x03u},\r
+                       {0x9Bu, 0x01u},\r
+                       {0x9Cu, 0x0Eu},\r
+                       {0x9Fu, 0x0Cu},\r
+                       {0xA4u, 0x08u},\r
+                       {0xAAu, 0x04u},\r
+                       {0xABu, 0x02u},\r
+                       {0xAEu, 0x0Eu},\r
+                       {0xB0u, 0x01u},\r
+                       {0xB1u, 0x0Fu},\r
+                       {0xB4u, 0x0Eu},\r
                        {0xBEu, 0x10u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
-                       {0xDCu, 0x11u},\r
+                       {0xDCu, 0x09u},\r
                        {0xDFu, 0x01u},\r
                        {0x00u, 0x40u},\r
-                       {0x01u, 0x02u},\r
-                       {0x04u, 0x40u},\r
-                       {0x06u, 0x20u},\r
-                       {0x07u, 0x08u},\r
-                       {0x0Au, 0x12u},\r
-                       {0x0Eu, 0x90u},\r
-                       {0x0Fu, 0x04u},\r
+                       {0x02u, 0x10u},\r
+                       {0x03u, 0x08u},\r
+                       {0x05u, 0x02u},\r
+                       {0x06u, 0x08u},\r
+                       {0x08u, 0x10u},\r
+                       {0x09u, 0x02u},\r
+                       {0x0Au, 0x11u},\r
+                       {0x0Du, 0x40u},\r
                        {0x10u, 0x80u},\r
-                       {0x11u, 0x10u},\r
-                       {0x13u, 0x08u},\r
-                       {0x14u, 0x10u},\r
-                       {0x15u, 0x01u},\r
-                       {0x16u, 0x12u},\r
-                       {0x17u, 0x10u},\r
-                       {0x19u, 0x02u},\r
-                       {0x1Au, 0x02u},\r
-                       {0x1Du, 0x20u},\r
-                       {0x1Eu, 0x80u},\r
-                       {0x20u, 0x08u},\r
-                       {0x21u, 0x08u},\r
-                       {0x27u, 0x01u},\r
-                       {0x29u, 0x08u},\r
-                       {0x2Bu, 0x40u},\r
-                       {0x2Du, 0x20u},\r
-                       {0x2Eu, 0x02u},\r
-                       {0x2Fu, 0x01u},\r
-                       {0x30u, 0x02u},\r
-                       {0x31u, 0x08u},\r
-                       {0x32u, 0x40u},\r
-                       {0x36u, 0x28u},\r
-                       {0x37u, 0x01u},\r
-                       {0x38u, 0x48u},\r
-                       {0x39u, 0x20u},\r
-                       {0x3Cu, 0x40u},\r
-                       {0x3Eu, 0x10u},\r
-                       {0x3Fu, 0x08u},\r
-                       {0x5Bu, 0xA0u},\r
-                       {0x60u, 0x09u},\r
-                       {0x68u, 0x02u},\r
-                       {0x80u, 0x01u},\r
-                       {0x83u, 0x10u},\r
-                       {0x85u, 0x02u},\r
-                       {0x89u, 0x10u},\r
-                       {0x8Au, 0x40u},\r
-                       {0x8Cu, 0x24u},\r
-                       {0x8Du, 0x10u},\r
-                       {0x8Eu, 0x02u},\r
-                       {0x90u, 0x40u},\r
-                       {0x91u, 0x30u},\r
-                       {0x92u, 0xF0u},\r
-                       {0x93u, 0x46u},\r
-                       {0x94u, 0x01u},\r
-                       {0x95u, 0x01u},\r
-                       {0x99u, 0x28u},\r
-                       {0x9Bu, 0x98u},\r
-                       {0x9Cu, 0x18u},\r
-                       {0x9Fu, 0x04u},\r
-                       {0xA0u, 0x80u},\r
-                       {0xA1u, 0x04u},\r
-                       {0xA2u, 0xA8u},\r
-                       {0xA3u, 0x06u},\r
-                       {0xA4u, 0x06u},\r
+                       {0x12u, 0x24u},\r
+                       {0x17u, 0x98u},\r
+                       {0x19u, 0x08u},\r
+                       {0x1Au, 0x88u},\r
+                       {0x1Bu, 0x40u},\r
+                       {0x1Du, 0x10u},\r
+                       {0x1Eu, 0x40u},\r
+                       {0x20u, 0x0Cu},\r
+                       {0x21u, 0x14u},\r
+                       {0x22u, 0x10u},\r
+                       {0x23u, 0x10u},\r
+                       {0x27u, 0x80u},\r
+                       {0x29u, 0x02u},\r
+                       {0x2Au, 0x20u},\r
+                       {0x2Cu, 0x08u},\r
+                       {0x31u, 0x04u},\r
+                       {0x32u, 0x90u},\r
+                       {0x36u, 0x10u},\r
+                       {0x37u, 0x88u},\r
+                       {0x38u, 0xA0u},\r
+                       {0x39u, 0x18u},\r
+                       {0x3Cu, 0x20u},\r
+                       {0x3Eu, 0x0Cu},\r
+                       {0x44u, 0x02u},\r
+                       {0x45u, 0x40u},\r
+                       {0x58u, 0x80u},\r
+                       {0x5Bu, 0x24u},\r
+                       {0x60u, 0x0Au},\r
+                       {0x61u, 0x08u},\r
+                       {0x82u, 0x40u},\r
+                       {0x83u, 0x04u},\r
+                       {0x86u, 0x02u},\r
+                       {0x88u, 0x04u},\r
+                       {0x89u, 0x14u},\r
+                       {0x8Du, 0x08u},\r
+                       {0x8Fu, 0x40u},\r
+                       {0x90u, 0xA0u},\r
+                       {0x91u, 0x04u},\r
+                       {0x93u, 0x40u},\r
+                       {0x94u, 0x04u},\r
+                       {0x95u, 0x08u},\r
+                       {0x96u, 0x28u},\r
+                       {0x97u, 0x10u},\r
+                       {0x98u, 0x11u},\r
+                       {0x99u, 0x26u},\r
+                       {0x9Cu, 0x0Au},\r
+                       {0x9Eu, 0x20u},\r
+                       {0xA1u, 0x20u},\r
+                       {0xA2u, 0xA0u},\r
+                       {0xA3u, 0x08u},\r
+                       {0xA4u, 0x04u},\r
+                       {0xA5u, 0x08u},\r
                        {0xA6u, 0x02u},\r
-                       {0xABu, 0xB0u},\r
-                       {0xACu, 0x04u},\r
-                       {0xB2u, 0x04u},\r
-                       {0xB3u, 0x08u},\r
-                       {0xB5u, 0x50u},\r
-                       {0xB6u, 0x02u},\r
-                       {0xC0u, 0xE9u},\r
-                       {0xC2u, 0x75u},\r
-                       {0xC4u, 0xFEu},\r
-                       {0xCAu, 0xB3u},\r
-                       {0xCCu, 0xEBu},\r
-                       {0xCEu, 0x7Eu},\r
-                       {0xD6u, 0x0Cu},\r
-                       {0xD8u, 0x0Cu},\r
-                       {0xE0u, 0x05u},\r
-                       {0xE2u, 0x20u},\r
-                       {0xE4u, 0x08u},\r
-                       {0xE6u, 0x80u},\r
-                       {0xEAu, 0x09u},\r
-                       {0xECu, 0x04u},\r
-                       {0xEEu, 0x10u},\r
+                       {0xAAu, 0x01u},\r
+                       {0xABu, 0x04u},\r
+                       {0xAEu, 0x08u},\r
+                       {0xAFu, 0x80u},\r
+                       {0xB6u, 0x40u},\r
+                       {0xC0u, 0x57u},\r
+                       {0xC2u, 0x8Fu},\r
+                       {0xC4u, 0xEEu},\r
+                       {0xCAu, 0x25u},\r
+                       {0xCCu, 0x7Eu},\r
+                       {0xCEu, 0x6Eu},\r
+                       {0xD6u, 0x0Eu},\r
+                       {0xD8u, 0x0Eu},\r
+                       {0xE0u, 0x02u},\r
+                       {0xE2u, 0x41u},\r
+                       {0xE8u, 0x08u},\r
+                       {0xEAu, 0x07u},\r
+                       {0xEEu, 0x41u},\r
                        {0x00u, 0x0Du},\r
-                       {0x04u, 0x01u},\r
-                       {0x05u, 0x0Fu},\r
-                       {0x06u, 0x32u},\r
-                       {0x08u, 0x62u},\r
-                       {0x09u, 0x03u},\r
-                       {0x0Au, 0x08u},\r
-                       {0x0Bu, 0x0Cu},\r
+                       {0x04u, 0x0Du},\r
+                       {0x07u, 0xFFu},\r
+                       {0x08u, 0x0Du},\r
+                       {0x0Bu, 0xFFu},\r
+                       {0x0Du, 0x33u},\r
+                       {0x0Fu, 0xCCu},\r
                        {0x10u, 0x02u},\r
-                       {0x11u, 0x05u},\r
+                       {0x11u, 0x55u},\r
                        {0x12u, 0x0Du},\r
-                       {0x13u, 0x0Au},\r
-                       {0x14u, 0x0Du},\r
-                       {0x15u, 0x20u},\r
-                       {0x17u, 0x4Fu},\r
-                       {0x1Au, 0x10u},\r
-                       {0x1Cu, 0x02u},\r
-                       {0x1Eu, 0x54u},\r
-                       {0x1Fu, 0x70u},\r
+                       {0x13u, 0xAAu},\r
+                       {0x15u, 0x69u},\r
+                       {0x16u, 0x80u},\r
+                       {0x17u, 0x96u},\r
+                       {0x18u, 0x01u},\r
+                       {0x19u, 0x0Fu},\r
+                       {0x1Au, 0x32u},\r
+                       {0x1Bu, 0xF0u},\r
+                       {0x1Du, 0xFFu},\r
+                       {0x1Eu, 0x10u},\r
                        {0x20u, 0x0Du},\r
-                       {0x24u, 0x0Du},\r
-                       {0x25u, 0x06u},\r
-                       {0x27u, 0x09u},\r
-                       {0x29u, 0x10u},\r
-                       {0x2Bu, 0x2Fu},\r
+                       {0x23u, 0xFFu},\r
+                       {0x24u, 0x62u},\r
+                       {0x26u, 0x08u},\r
+                       {0x28u, 0x02u},\r
+                       {0x29u, 0xFFu},\r
+                       {0x2Au, 0x54u},\r
                        {0x2Cu, 0x0Du},\r
-                       {0x2Du, 0x40u},\r
-                       {0x2Fu, 0x1Fu},\r
                        {0x30u, 0x0Fu},\r
-                       {0x31u, 0x7Fu},\r
-                       {0x34u, 0x70u},\r
+                       {0x32u, 0x80u},\r
+                       {0x35u, 0xFFu},\r
+                       {0x36u, 0x70u},\r
                        {0x3Au, 0x02u},\r
-                       {0x54u, 0x01u},\r
+                       {0x3Bu, 0x20u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
-                       {0x5Bu, 0x04u},\r
                        {0x5Cu, 0x10u},\r
-                       {0x5Du, 0x10u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x96u},\r
-                       {0x82u, 0x69u},\r
-                       {0x85u, 0x02u},\r
-                       {0x87u, 0x11u},\r
+                       {0x80u, 0xFFu},\r
+                       {0x84u, 0x30u},\r
+                       {0x86u, 0xC0u},\r
+                       {0x87u, 0x80u},\r
                        {0x88u, 0x0Fu},\r
+                       {0x89u, 0x44u},\r
                        {0x8Au, 0xF0u},\r
-                       {0x8Du, 0x01u},\r
-                       {0x8Eu, 0xFFu},\r
-                       {0x8Fu, 0x02u},\r
-                       {0x90u, 0x55u},\r
-                       {0x92u, 0xAAu},\r
-                       {0x95u, 0x02u},\r
-                       {0x96u, 0xFFu},\r
-                       {0x97u, 0x05u},\r
-                       {0x99u, 0x02u},\r
-                       {0x9Au, 0xFFu},\r
-                       {0x9Bu, 0x09u},\r
-                       {0x9Cu, 0x33u},\r
-                       {0x9Du, 0x02u},\r
-                       {0x9Eu, 0xCCu},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA4u, 0xFFu},\r
-                       {0xA8u, 0xFFu},\r
-                       {0xB1u, 0x03u},\r
-                       {0xB3u, 0x08u},\r
-                       {0xB4u, 0xFFu},\r
-                       {0xB5u, 0x10u},\r
-                       {0xB7u, 0x04u},\r
-                       {0xBAu, 0x20u},\r
-                       {0xBBu, 0x02u},\r
-                       {0xD6u, 0x08u},\r
+                       {0x8Bu, 0x88u},\r
+                       {0x8Cu, 0xFFu},\r
+                       {0x8Fu, 0x08u},\r
+                       {0x90u, 0x50u},\r
+                       {0x92u, 0xA0u},\r
+                       {0x93u, 0x07u},\r
+                       {0x94u, 0x09u},\r
+                       {0x96u, 0x06u},\r
+                       {0x97u, 0x70u},\r
+                       {0x98u, 0x05u},\r
+                       {0x99u, 0x99u},\r
+                       {0x9Au, 0x0Au},\r
+                       {0x9Bu, 0x22u},\r
+                       {0x9Du, 0xAAu},\r
+                       {0x9Fu, 0x55u},\r
+                       {0xA4u, 0x03u},\r
+                       {0xA6u, 0x0Cu},\r
+                       {0xAAu, 0xFFu},\r
+                       {0xACu, 0x90u},\r
+                       {0xAEu, 0x60u},\r
+                       {0xB0u, 0xFFu},\r
+                       {0xB1u, 0x0Fu},\r
+                       {0xB3u, 0xF0u},\r
+                       {0xBEu, 0x01u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x91u},\r
-                       {0xDDu, 0x90u},\r
+                       {0xDCu, 0x10u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x20u},\r
-                       {0x02u, 0x80u},\r
-                       {0x03u, 0x02u},\r
-                       {0x04u, 0x08u},\r
-                       {0x05u, 0x10u},\r
-                       {0x07u, 0x40u},\r
-                       {0x08u, 0x20u},\r
-                       {0x0Au, 0x10u},\r
-                       {0x0Bu, 0x41u},\r
-                       {0x0Cu, 0x08u},\r
-                       {0x0Eu, 0x8Au},\r
-                       {0x12u, 0x08u},\r
-                       {0x13u, 0x08u},\r
-                       {0x15u, 0x06u},\r
-                       {0x16u, 0x02u},\r
-                       {0x19u, 0x20u},\r
-                       {0x1Bu, 0x20u},\r
-                       {0x1Eu, 0x88u},\r
-                       {0x20u, 0x40u},\r
-                       {0x21u, 0x28u},\r
-                       {0x22u, 0x40u},\r
-                       {0x27u, 0x80u},\r
-                       {0x2Eu, 0x10u},\r
-                       {0x2Fu, 0x22u},\r
-                       {0x31u, 0x28u},\r
-                       {0x32u, 0x40u},\r
-                       {0x37u, 0x89u},\r
-                       {0x38u, 0x44u},\r
-                       {0x39u, 0x80u},\r
-                       {0x3Du, 0x28u},\r
+                       {0x00u, 0x04u},\r
+                       {0x01u, 0x80u},\r
+                       {0x02u, 0x44u},\r
+                       {0x03u, 0x08u},\r
+                       {0x04u, 0x28u},\r
+                       {0x07u, 0x40u},\r
+                       {0x08u, 0x14u},\r
+                       {0x09u, 0x02u},\r
+                       {0x0Cu, 0x08u},\r
+                       {0x0Eu, 0x46u},\r
+                       {0x10u, 0x20u},\r
+                       {0x11u, 0x10u},\r
+                       {0x12u, 0x01u},\r
+                       {0x15u, 0x41u},\r
+                       {0x17u, 0x18u},\r
+                       {0x18u, 0x40u},\r
+                       {0x1Eu, 0x62u},\r
+                       {0x21u, 0x08u},\r
+                       {0x22u, 0x01u},\r
+                       {0x26u, 0x20u},\r
+                       {0x2Du, 0x02u},\r
+                       {0x2Eu, 0x20u},\r
+                       {0x31u, 0x08u},\r
+                       {0x32u, 0x91u},\r
+                       {0x34u, 0x09u},\r
+                       {0x36u, 0xA0u},\r
+                       {0x39u, 0x04u},\r
+                       {0x3Bu, 0x50u},\r
+                       {0x3Cu, 0x08u},\r
+                       {0x3Du, 0x80u},\r
+                       {0x3Fu, 0x10u},\r
                        {0x58u, 0x80u},\r
-                       {0x5Au, 0x20u},\r
-                       {0x5Fu, 0x80u},\r
-                       {0x60u, 0x04u},\r
-                       {0x63u, 0x01u},\r
-                       {0x83u, 0x40u},\r
-                       {0x8Au, 0x11u},\r
-                       {0x8Fu, 0x04u},\r
-                       {0x92u, 0x72u},\r
-                       {0x93u, 0x40u},\r
-                       {0x95u, 0x01u},\r
-                       {0x98u, 0xA0u},\r
-                       {0x99u, 0x08u},\r
-                       {0x9Bu, 0x09u},\r
-                       {0x9Eu, 0x10u},\r
-                       {0x9Fu, 0x04u},\r
-                       {0xA1u, 0x14u},\r
-                       {0xA2u, 0x88u},\r
-                       {0xA3u, 0x02u},\r
-                       {0xA6u, 0x02u},\r
-                       {0xA7u, 0x40u},\r
-                       {0xA8u, 0x02u},\r
-                       {0xAAu, 0x20u},\r
+                       {0x59u, 0x22u},\r
+                       {0x5Au, 0x08u},\r
+                       {0x63u, 0x02u},\r
+                       {0x80u, 0x80u},\r
+                       {0x85u, 0x10u},\r
+                       {0x88u, 0x20u},\r
+                       {0x89u, 0x08u},\r
+                       {0x8Au, 0x01u},\r
+                       {0x8Bu, 0x01u},\r
+                       {0x8Eu, 0x01u},\r
+                       {0x91u, 0x14u},\r
+                       {0x92u, 0x20u},\r
+                       {0x93u, 0x50u},\r
+                       {0x94u, 0x40u},\r
+                       {0x95u, 0x80u},\r
+                       {0x96u, 0x15u},\r
+                       {0x98u, 0x19u},\r
+                       {0x99u, 0x32u},\r
+                       {0x9Au, 0x20u},\r
+                       {0x9Eu, 0x14u},\r
+                       {0x9Fu, 0x18u},\r
+                       {0xA0u, 0x04u},\r
+                       {0xA1u, 0x40u},\r
+                       {0xA2u, 0x80u},\r
+                       {0xA4u, 0x98u},\r
+                       {0xA5u, 0x02u},\r
+                       {0xA6u, 0x12u},\r
+                       {0xAAu, 0x60u},\r
                        {0xABu, 0x20u},\r
                        {0xACu, 0x80u},\r
-                       {0xB1u, 0x28u},\r
-                       {0xB4u, 0x08u},\r
-                       {0xC0u, 0x7Bu},\r
-                       {0xC2u, 0xFFu},\r
-                       {0xC4u, 0xB6u},\r
-                       {0xCAu, 0x70u},\r
-                       {0xCCu, 0xDEu},\r
-                       {0xCEu, 0x6Au},\r
-                       {0xD6u, 0x1Cu},\r
-                       {0xD8u, 0x0Cu},\r
-                       {0xE2u, 0x44u},\r
-                       {0xE6u, 0xCAu},\r
-                       {0xE8u, 0x04u},\r
-                       {0xEAu, 0x01u},\r
-                       {0xEEu, 0x86u},\r
-                       {0x00u, 0x01u},\r
-                       {0x01u, 0x02u},\r
-                       {0x02u, 0x02u},\r
-                       {0x03u, 0x01u},\r
-                       {0x08u, 0x02u},\r
-                       {0x0Au, 0x01u},\r
-                       {0x0Cu, 0x04u},\r
-                       {0x0Eu, 0x08u},\r
-                       {0x15u, 0x02u},\r
-                       {0x16u, 0x20u},\r
-                       {0x17u, 0x01u},\r
-                       {0x19u, 0x02u},\r
-                       {0x1Au, 0x10u},\r
-                       {0x1Bu, 0x01u},\r
-                       {0x1Du, 0x01u},\r
-                       {0x1Eu, 0x40u},\r
-                       {0x1Fu, 0x02u},\r
-                       {0x20u, 0x08u},\r
-                       {0x22u, 0x04u},\r
-                       {0x28u, 0x03u},\r
-                       {0x2Au, 0x0Cu},\r
-                       {0x2Du, 0x02u},\r
-                       {0x2Fu, 0x01u},\r
-                       {0x30u, 0x10u},\r
-                       {0x32u, 0x40u},\r
-                       {0x34u, 0x20u},\r
-                       {0x36u, 0x0Fu},\r
-                       {0x37u, 0x03u},\r
-                       {0x3Bu, 0x80u},\r
-                       {0x3Eu, 0x40u},\r
-                       {0x58u, 0x04u},\r
+                       {0xB1u, 0x08u},\r
+                       {0xB5u, 0x20u},\r
+                       {0xB7u, 0x08u},\r
+                       {0xC0u, 0x7Fu},\r
+                       {0xC2u, 0xFEu},\r
+                       {0xC4u, 0xF7u},\r
+                       {0xCAu, 0xA0u},\r
+                       {0xCCu, 0xFFu},\r
+                       {0xCEu, 0x7Eu},\r
+                       {0xD6u, 0x0Fu},\r
+                       {0xD8u, 0x08u},\r
+                       {0xE2u, 0x58u},\r
+                       {0xE6u, 0x01u},\r
+                       {0xEAu, 0x05u},\r
+                       {0xEEu, 0x02u},\r
+                       {0x39u, 0x80u},\r
+                       {0x3Fu, 0x40u},\r
                        {0x59u, 0x04u},\r
-                       {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x99u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x87u, 0x10u},\r
-                       {0x89u, 0x02u},\r
-                       {0x8Bu, 0x01u},\r
-                       {0x8Du, 0x02u},\r
-                       {0x8Fu, 0x01u},\r
-                       {0x91u, 0x01u},\r
-                       {0x93u, 0x02u},\r
-                       {0x95u, 0x10u},\r
-                       {0x97u, 0x20u},\r
-                       {0x9Du, 0x04u},\r
-                       {0xA3u, 0x20u},\r
-                       {0xA5u, 0x08u},\r
-                       {0xA9u, 0x02u},\r
-                       {0xABu, 0x01u},\r
-                       {0xADu, 0x02u},\r
-                       {0xAFu, 0x01u},\r
-                       {0xB1u, 0x03u},\r
-                       {0xB3u, 0x08u},\r
-                       {0xB5u, 0x04u},\r
-                       {0xB7u, 0x30u},\r
-                       {0xBBu, 0x02u},\r
-                       {0xBFu, 0x40u},\r
-                       {0xD6u, 0x08u},\r
-                       {0xD9u, 0x04u},\r
-                       {0xDBu, 0x04u},\r
-                       {0xDCu, 0x90u},\r
-                       {0xDDu, 0x90u},\r
-                       {0xDFu, 0x01u},\r
-                       {0x05u, 0x01u},\r
-                       {0x06u, 0x09u},\r
-                       {0x0Eu, 0x28u},\r
-                       {0x0Fu, 0x02u},\r
-                       {0x14u, 0x04u},\r
-                       {0x15u, 0x01u},\r
-                       {0x1Du, 0x40u},\r
-                       {0x1Eu, 0x28u},\r
-                       {0x1Fu, 0x01u},\r
-                       {0x21u, 0x42u},\r
-                       {0x22u, 0x04u},\r
-                       {0x23u, 0x48u},\r
-                       {0x25u, 0x80u},\r
-                       {0x26u, 0x80u},\r
-                       {0x28u, 0x02u},\r
-                       {0x29u, 0x10u},\r
-                       {0x2Bu, 0xA0u},\r
-                       {0x2Fu, 0x01u},\r
-                       {0x30u, 0x04u},\r
-                       {0x31u, 0x82u},\r
-                       {0x32u, 0x08u},\r
-                       {0x36u, 0x94u},\r
-                       {0x38u, 0x90u},\r
-                       {0x3Au, 0x08u},\r
-                       {0x3Fu, 0x02u},\r
-                       {0x58u, 0x80u},\r
-                       {0x5Du, 0x06u},\r
-                       {0x5Fu, 0x60u},\r
-                       {0x63u, 0x02u},\r
-                       {0x65u, 0x80u},\r
-                       {0x6Cu, 0x16u},\r
-                       {0x6Du, 0x41u},\r
-                       {0x6Fu, 0x80u},\r
-                       {0x74u, 0x80u},\r
-                       {0x76u, 0x95u},\r
-                       {0x80u, 0x80u},\r
-                       {0x86u, 0x04u},\r
-                       {0x8Au, 0x88u},\r
-                       {0x8Bu, 0x08u},\r
-                       {0x8Eu, 0x04u},\r
-                       {0x90u, 0x90u},\r
-                       {0x94u, 0x28u},\r
-                       {0x95u, 0xC0u},\r
-                       {0x98u, 0x02u},\r
-                       {0x99u, 0x91u},\r
-                       {0x9Du, 0x40u},\r
-                       {0x9Eu, 0x10u},\r
-                       {0xA2u, 0x08u},\r
-                       {0xA3u, 0x20u},\r
-                       {0xA4u, 0x02u},\r
-                       {0xA8u, 0x80u},\r
-                       {0xAAu, 0x08u},\r
-                       {0xABu, 0x01u},\r
-                       {0xB0u, 0x40u},\r
-                       {0xB1u, 0x10u},\r
-                       {0xB2u, 0x80u},\r
-                       {0xB7u, 0x80u},\r
-                       {0xC0u, 0xD0u},\r
-                       {0xC2u, 0xE0u},\r
-                       {0xC4u, 0x50u},\r
-                       {0xCAu, 0x1Fu},\r
-                       {0xCCu, 0x7Bu},\r
-                       {0xCEu, 0x8Eu},\r
-                       {0xD6u, 0xF8u},\r
-                       {0xD8u, 0x18u},\r
-                       {0xE0u, 0x20u},\r
-                       {0xE2u, 0x40u},\r
-                       {0xE6u, 0xF2u},\r
-                       {0xE8u, 0x40u},\r
+                       {0x24u, 0x02u},\r
+                       {0x7Au, 0x30u},\r
+                       {0x80u, 0x14u},\r
+                       {0x88u, 0x20u},\r
+                       {0x89u, 0x10u},\r
+                       {0x8Au, 0x08u},\r
+                       {0x8Cu, 0x01u},\r
+                       {0x90u, 0x10u},\r
+                       {0x91u, 0x02u},\r
+                       {0x94u, 0x08u},\r
+                       {0x95u, 0x01u},\r
+                       {0x97u, 0x01u},\r
+                       {0x98u, 0x28u},\r
+                       {0x9Au, 0x22u},\r
+                       {0x9Bu, 0x10u},\r
+                       {0x9Du, 0x0Bu},\r
+                       {0x9Eu, 0x18u},\r
+                       {0xA2u, 0x62u},\r
+                       {0xA4u, 0x80u},\r
+                       {0xABu, 0x02u},\r
+                       {0xB2u, 0x04u},\r
+                       {0xB6u, 0x01u},\r
+                       {0xB7u, 0x10u},\r
+                       {0xE0u, 0x24u},\r
+                       {0xE2u, 0xC8u},\r
+                       {0xE4u, 0x20u},\r
+                       {0xE8u, 0x10u},\r
                        {0xEAu, 0x01u},\r
-                       {0xECu, 0x20u},\r
+                       {0xECu, 0x60u},\r
                        {0xEEu, 0x02u},\r
-                       {0x03u, 0xFFu},\r
-                       {0x05u, 0x50u},\r
-                       {0x07u, 0xA0u},\r
-                       {0x09u, 0x30u},\r
-                       {0x0Bu, 0xC0u},\r
-                       {0x0Du, 0x06u},\r
+                       {0x00u, 0x04u},\r
+                       {0x02u, 0x08u},\r
+                       {0x04u, 0x02u},\r
+                       {0x06u, 0x01u},\r
+                       {0x07u, 0x20u},\r
+                       {0x08u, 0x01u},\r
+                       {0x09u, 0x04u},\r
+                       {0x0Au, 0x02u},\r
+                       {0x0Bu, 0x08u},\r
+                       {0x0Cu, 0x02u},\r
+                       {0x0Du, 0x03u},\r
                        {0x0Eu, 0x01u},\r
-                       {0x0Fu, 0x09u},\r
-                       {0x11u, 0x60u},\r
-                       {0x12u, 0x04u},\r
-                       {0x13u, 0x90u},\r
-                       {0x17u, 0xFFu},\r
-                       {0x19u, 0x03u},\r
-                       {0x1Au, 0x08u},\r
-                       {0x1Bu, 0x0Cu},\r
-                       {0x1Du, 0x0Fu},\r
-                       {0x1Eu, 0x10u},\r
-                       {0x1Fu, 0xF0u},\r
-                       {0x20u, 0x01u},\r
-                       {0x21u, 0x05u},\r
-                       {0x22u, 0x02u},\r
-                       {0x23u, 0x0Au},\r
-                       {0x2Du, 0xFFu},\r
-                       {0x2Eu, 0x02u},\r
-                       {0x30u, 0x10u},\r
-                       {0x32u, 0x08u},\r
-                       {0x34u, 0x04u},\r
-                       {0x35u, 0xFFu},\r
-                       {0x36u, 0x03u},\r
-                       {0x3Eu, 0x40u},\r
+                       {0x0Fu, 0x0Cu},\r
+                       {0x11u, 0x02u},\r
+                       {0x12u, 0x20u},\r
+                       {0x13u, 0x01u},\r
+                       {0x14u, 0x02u},\r
+                       {0x16u, 0x01u},\r
+                       {0x1Au, 0x10u},\r
+                       {0x1Du, 0x08u},\r
+                       {0x1Fu, 0x04u},\r
+                       {0x21u, 0x01u},\r
+                       {0x22u, 0x08u},\r
+                       {0x23u, 0x02u},\r
+                       {0x24u, 0x02u},\r
+                       {0x26u, 0x01u},\r
+                       {0x27u, 0x10u},\r
+                       {0x2Au, 0x04u},\r
+                       {0x2Cu, 0x10u},\r
+                       {0x2Eu, 0x20u},\r
+                       {0x30u, 0x30u},\r
+                       {0x31u, 0x20u},\r
+                       {0x32u, 0x03u},\r
+                       {0x33u, 0x10u},\r
+                       {0x34u, 0x0Cu},\r
+                       {0x35u, 0x0Fu},\r
+                       {0x3Au, 0x08u},\r
+                       {0x3Eu, 0x11u},\r
                        {0x3Fu, 0x10u},\r
                        {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x09u},\r
+                       {0x5Cu, 0x99u},\r
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x84u, 0x50u},\r
-                       {0x85u, 0xFFu},\r
-                       {0x86u, 0xA0u},\r
-                       {0x88u, 0x30u},\r
-                       {0x89u, 0x33u},\r
-                       {0x8Au, 0xC0u},\r
-                       {0x8Bu, 0xCCu},\r
-                       {0x8Cu, 0xFFu},\r
-                       {0x8Fu, 0xFFu},\r
-                       {0x90u, 0x90u},\r
-                       {0x91u, 0x0Fu},\r
-                       {0x92u, 0x60u},\r
-                       {0x93u, 0xF0u},\r
-                       {0x94u, 0x05u},\r
-                       {0x96u, 0x0Au},\r
-                       {0x97u, 0xFFu},\r
-                       {0x99u, 0x55u},\r
-                       {0x9Bu, 0xAAu},\r
-                       {0x9Cu, 0x0Fu},\r
-                       {0x9Du, 0xFFu},\r
-                       {0x9Eu, 0xF0u},\r
-                       {0xA0u, 0x09u},\r
-                       {0xA1u, 0x69u},\r
-                       {0xA2u, 0x06u},\r
-                       {0xA3u, 0x96u},\r
-                       {0xA4u, 0x03u},\r
-                       {0xA6u, 0x0Cu},\r
-                       {0xA7u, 0xFFu},\r
-                       {0xA8u, 0xFFu},\r
-                       {0xAEu, 0xFFu},\r
-                       {0xB1u, 0xFFu},\r
-                       {0xB6u, 0xFFu},\r
-                       {0xB8u, 0x02u},\r
-                       {0xBBu, 0x02u},\r
-                       {0xBEu, 0x41u},\r
+                       {0x81u, 0x60u},\r
+                       {0x83u, 0x90u},\r
+                       {0x84u, 0x03u},\r
+                       {0x85u, 0x03u},\r
+                       {0x86u, 0x0Cu},\r
+                       {0x87u, 0x0Cu},\r
+                       {0x88u, 0x06u},\r
+                       {0x89u, 0x06u},\r
+                       {0x8Au, 0x09u},\r
+                       {0x8Bu, 0x09u},\r
+                       {0x8Cu, 0x0Fu},\r
+                       {0x92u, 0x70u},\r
+                       {0x95u, 0x05u},\r
+                       {0x97u, 0x0Au},\r
+                       {0x98u, 0x20u},\r
+                       {0x99u, 0x50u},\r
+                       {0x9Au, 0x4Fu},\r
+                       {0x9Bu, 0xA0u},\r
+                       {0x9Cu, 0x05u},\r
+                       {0x9Du, 0x0Fu},\r
+                       {0x9Eu, 0x0Au},\r
+                       {0x9Fu, 0xF0u},\r
+                       {0xA1u, 0x30u},\r
+                       {0xA3u, 0xC0u},\r
+                       {0xA8u, 0x40u},\r
+                       {0xAAu, 0x1Fu},\r
+                       {0xACu, 0x10u},\r
+                       {0xAEu, 0x2Fu},\r
+                       {0xB0u, 0x7Fu},\r
+                       {0xB3u, 0xFFu},\r
+                       {0xBFu, 0x04u},\r
+                       {0xD4u, 0x01u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
-                       {0xDCu, 0x10u},\r
+                       {0xDBu, 0x04u},\r
+                       {0xDCu, 0x01u},\r
+                       {0xDDu, 0x10u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x80u},\r
-                       {0x04u, 0x28u},\r
-                       {0x05u, 0x41u},\r
-                       {0x07u, 0x40u},\r
-                       {0x09u, 0x80u},\r
-                       {0x0Au, 0x44u},\r
-                       {0x0Cu, 0x82u},\r
-                       {0x0Eu, 0x20u},\r
-                       {0x10u, 0x80u},\r
-                       {0x11u, 0x40u},\r
-                       {0x14u, 0x14u},\r
-                       {0x16u, 0x81u},\r
-                       {0x18u, 0x92u},\r
-                       {0x19u, 0x10u},\r
-                       {0x1Au, 0x44u},\r
-                       {0x1Fu, 0x41u},\r
-                       {0x22u, 0x20u},\r
-                       {0x26u, 0x02u},\r
-                       {0x29u, 0x40u},\r
-                       {0x2Au, 0x02u},\r
-                       {0x2Fu, 0xA0u},\r
-                       {0x30u, 0x9Eu},\r
-                       {0x31u, 0x20u},\r
-                       {0x34u, 0x08u},\r
-                       {0x35u, 0xA0u},\r
-                       {0x36u, 0x02u},\r
-                       {0x38u, 0x28u},\r
-                       {0x3Au, 0x81u},\r
-                       {0x3Du, 0x20u},\r
-                       {0x3Fu, 0x84u},\r
+                       {0x00u, 0x10u},\r
+                       {0x01u, 0x08u},\r
+                       {0x02u, 0x42u},\r
+                       {0x03u, 0x80u},\r
+                       {0x04u, 0x08u},\r
+                       {0x06u, 0x02u},\r
+                       {0x07u, 0x08u},\r
+                       {0x08u, 0x22u},\r
+                       {0x09u, 0x28u},\r
+                       {0x0Cu, 0x20u},\r
+                       {0x0Eu, 0x42u},\r
+                       {0x10u, 0x08u},\r
+                       {0x11u, 0x41u},\r
+                       {0x13u, 0x04u},\r
+                       {0x14u, 0x05u},\r
+                       {0x18u, 0x90u},\r
+                       {0x1Au, 0x08u},\r
+                       {0x1Bu, 0x02u},\r
+                       {0x1Eu, 0x40u},\r
+                       {0x21u, 0x08u},\r
+                       {0x22u, 0x22u},\r
+                       {0x27u, 0x10u},\r
+                       {0x29u, 0x18u},\r
+                       {0x2Au, 0x11u},\r
+                       {0x2Cu, 0x08u},\r
+                       {0x2Du, 0x02u},\r
+                       {0x2Eu, 0x20u},\r
+                       {0x30u, 0x80u},\r
+                       {0x32u, 0x01u},\r
+                       {0x35u, 0x10u},\r
+                       {0x36u, 0x40u},\r
+                       {0x37u, 0x04u},\r
+                       {0x39u, 0x20u},\r
+                       {0x3Au, 0x40u},\r
+                       {0x3Bu, 0x04u},\r
+                       {0x3Eu, 0x08u},\r
+                       {0x3Fu, 0x21u},\r
                        {0x58u, 0x80u},\r
+                       {0x5Bu, 0x20u},\r
+                       {0x5Eu, 0x40u},\r
                        {0x60u, 0x02u},\r
-                       {0x61u, 0x80u},\r
-                       {0x81u, 0x10u},\r
-                       {0x82u, 0x01u},\r
-                       {0x84u, 0x80u},\r
-                       {0x86u, 0x12u},\r
-                       {0x8Bu, 0x04u},\r
-                       {0x8Cu, 0x40u},\r
-                       {0x8Eu, 0x02u},\r
-                       {0x8Fu, 0x60u},\r
-                       {0x90u, 0x40u},\r
-                       {0x94u, 0x2Au},\r
-                       {0x95u, 0xE0u},\r
-                       {0x97u, 0x80u},\r
-                       {0x98u, 0x08u},\r
-                       {0x99u, 0xA0u},\r
-                       {0x9Bu, 0x40u},\r
-                       {0x9Du, 0x40u},\r
+                       {0x62u, 0x80u},\r
+                       {0x63u, 0x04u},\r
+                       {0x69u, 0x40u},\r
+                       {0x7Au, 0x40u},\r
+                       {0x7Bu, 0x80u},\r
+                       {0x85u, 0x10u},\r
+                       {0x88u, 0x05u},\r
+                       {0x8Bu, 0x40u},\r
+                       {0x91u, 0x02u},\r
+                       {0x92u, 0x02u},\r
+                       {0x94u, 0x80u},\r
+                       {0x96u, 0x0Cu},\r
+                       {0x97u, 0x40u},\r
+                       {0x98u, 0x88u},\r
+                       {0x9Au, 0x22u},\r
+                       {0x9Bu, 0x2Cu},\r
+                       {0x9Cu, 0x06u},\r
+                       {0x9Du, 0x01u},\r
                        {0x9Eu, 0x10u},\r
-                       {0xA0u, 0x08u},\r
+                       {0xA0u, 0x20u},\r
                        {0xA1u, 0x20u},\r
-                       {0xA3u, 0x40u},\r
+                       {0xA2u, 0x41u},\r
                        {0xA4u, 0x80u},\r
-                       {0xA6u, 0x30u},\r
-                       {0xABu, 0x04u},\r
-                       {0xB2u, 0x10u},\r
-                       {0xB3u, 0x02u},\r
-                       {0xB4u, 0x40u},\r
-                       {0xB6u, 0x80u},\r
-                       {0xC0u, 0xE1u},\r
-                       {0xC2u, 0xBBu},\r
-                       {0xC4u, 0xF9u},\r
-                       {0xCAu, 0xC9u},\r
-                       {0xCCu, 0xFFu},\r
-                       {0xCEu, 0x7Fu},\r
-                       {0xD6u, 0x08u},\r
-                       {0xD8u, 0x08u},\r
-                       {0xE2u, 0x50u},\r
-                       {0xE4u, 0x20u},\r
-                       {0xE6u, 0x92u},\r
-                       {0xEAu, 0x49u},\r
-                       {0xECu, 0x80u},\r
-                       {0xEEu, 0x20u},\r
-                       {0x02u, 0x02u},\r
-                       {0x06u, 0x08u},\r
-                       {0x0Bu, 0x08u},\r
-                       {0x0Du, 0x04u},\r
-                       {0x0Fu, 0x08u},\r
-                       {0x15u, 0x09u},\r
-                       {0x17u, 0x02u},\r
-                       {0x1Au, 0x04u},\r
-                       {0x1Eu, 0x01u},\r
-                       {0x1Fu, 0x07u},\r
-                       {0x20u, 0x04u},\r
-                       {0x22u, 0x08u},\r
-                       {0x2Du, 0x0Au},\r
-                       {0x2Fu, 0x05u},\r
-                       {0x30u, 0x01u},\r
-                       {0x31u, 0x0Fu},\r
-                       {0x32u, 0x0Cu},\r
-                       {0x34u, 0x02u},\r
-                       {0x3Eu, 0x04u},\r
+                       {0xA6u, 0x80u},\r
+                       {0xA7u, 0x02u},\r
+                       {0xAAu, 0x40u},\r
+                       {0xACu, 0x80u},\r
+                       {0xAEu, 0x20u},\r
+                       {0xB6u, 0x40u},\r
+                       {0xC0u, 0xEFu},\r
+                       {0xC2u, 0xDEu},\r
+                       {0xC4u, 0xCFu},\r
+                       {0xCAu, 0x83u},\r
+                       {0xCCu, 0x79u},\r
+                       {0xCEu, 0xEEu},\r
+                       {0xD6u, 0x1Cu},\r
+                       {0xD8u, 0x0Cu},\r
+                       {0xE0u, 0x20u},\r
+                       {0xE2u, 0x01u},\r
+                       {0xE4u, 0xE0u},\r
+                       {0xEAu, 0x17u},\r
+                       {0xEEu, 0x42u},\r
+                       {0x00u, 0x08u},\r
+                       {0x01u, 0x33u},\r
+                       {0x02u, 0x16u},\r
+                       {0x03u, 0xCCu},\r
+                       {0x05u, 0xFFu},\r
+                       {0x06u, 0x40u},\r
+                       {0x09u, 0x0Fu},\r
+                       {0x0Au, 0x04u},\r
+                       {0x0Bu, 0xF0u},\r
+                       {0x0Eu, 0x07u},\r
+                       {0x0Fu, 0xFFu},\r
+                       {0x10u, 0x07u},\r
+                       {0x12u, 0x18u},\r
+                       {0x15u, 0x96u},\r
+                       {0x16u, 0x07u},\r
+                       {0x17u, 0x69u},\r
+                       {0x18u, 0x0Cu},\r
+                       {0x1Au, 0x13u},\r
+                       {0x1Bu, 0xFFu},\r
+                       {0x1Cu, 0x20u},\r
+                       {0x1Eu, 0x40u},\r
+                       {0x20u, 0x01u},\r
+                       {0x25u, 0x55u},\r
+                       {0x26u, 0x20u},\r
+                       {0x27u, 0xAAu},\r
+                       {0x28u, 0x0Fu},\r
+                       {0x2Au, 0x10u},\r
+                       {0x2Bu, 0xFFu},\r
+                       {0x2Cu, 0x01u},\r
+                       {0x2Du, 0xFFu},\r
+                       {0x2Eu, 0x02u},\r
+                       {0x30u, 0x1Fu},\r
+                       {0x34u, 0x60u},\r
+                       {0x35u, 0xFFu},\r
+                       {0x3Au, 0x02u},\r
+                       {0x3Bu, 0x20u},\r
+                       {0x3Eu, 0x10u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x19u},\r
+                       {0x5Cu, 0x11u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x01u},\r
-                       {0x82u, 0x02u},\r
-                       {0x84u, 0x08u},\r
-                       {0x86u, 0x04u},\r
-                       {0x8Bu, 0x02u},\r
-                       {0x8Cu, 0x08u},\r
-                       {0x8Eu, 0x04u},\r
-                       {0x90u, 0x02u},\r
-                       {0x92u, 0x01u},\r
-                       {0x94u, 0x02u},\r
-                       {0x96u, 0x01u},\r
-                       {0x97u, 0x08u},\r
-                       {0x9Bu, 0x01u},\r
-                       {0x9Cu, 0x04u},\r
-                       {0x9Du, 0x01u},\r
-                       {0x9Eu, 0x08u},\r
-                       {0x9Fu, 0x02u},\r
-                       {0xA0u, 0x08u},\r
-                       {0xA2u, 0x04u},\r
-                       {0xA4u, 0x02u},\r
-                       {0xA6u, 0x01u},\r
-                       {0xA7u, 0x10u},\r
-                       {0xA8u, 0x02u},\r
-                       {0xAAu, 0x01u},\r
-                       {0xABu, 0x04u},\r
-                       {0xACu, 0x08u},\r
-                       {0xAEu, 0x04u},\r
-                       {0xB0u, 0x03u},\r
-                       {0xB1u, 0x04u},\r
-                       {0xB3u, 0x10u},\r
-                       {0xB5u, 0x08u},\r
-                       {0xB6u, 0x0Cu},\r
-                       {0xB7u, 0x03u},\r
-                       {0xBAu, 0x82u},\r
-                       {0xBFu, 0x40u},\r
+                       {0x82u, 0x10u},\r
+                       {0x85u, 0x02u},\r
+                       {0x87u, 0x01u},\r
+                       {0x8Cu, 0x10u},\r
+                       {0x90u, 0x10u},\r
+                       {0x92u, 0x60u},\r
+                       {0x93u, 0x04u},\r
+                       {0x98u, 0x3Au},\r
+                       {0x99u, 0x01u},\r
+                       {0x9Au, 0x45u},\r
+                       {0x9Bu, 0x02u},\r
+                       {0x9Du, 0x02u},\r
+                       {0x9Eu, 0x07u},\r
+                       {0x9Fu, 0x01u},\r
+                       {0xA1u, 0x02u},\r
+                       {0xA3u, 0x01u},\r
+                       {0xA6u, 0x08u},\r
+                       {0xA8u, 0x24u},\r
+                       {0xAAu, 0x58u},\r
+                       {0xACu, 0x29u},\r
+                       {0xADu, 0x02u},\r
+                       {0xAEu, 0x52u},\r
+                       {0xAFu, 0x01u},\r
+                       {0xB0u, 0x70u},\r
+                       {0xB3u, 0x04u},\r
+                       {0xB5u, 0x03u},\r
+                       {0xB6u, 0x0Fu},\r
+                       {0xBAu, 0x02u},\r
+                       {0xBBu, 0x20u},\r
                        {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x99u},\r
+                       {0xDCu, 0x91u},\r
                        {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x88u},\r
-                       {0x02u, 0x80u},\r
-                       {0x05u, 0x01u},\r
-                       {0x06u, 0x10u},\r
-                       {0x08u, 0x02u},\r
-                       {0x0Au, 0x22u},\r
-                       {0x0Fu, 0x0Au},\r
-                       {0x12u, 0x4Au},\r
-                       {0x13u, 0x04u},\r
-                       {0x14u, 0x40u},\r
-                       {0x18u, 0x40u},\r
-                       {0x19u, 0x80u},\r
-                       {0x1Au, 0x03u},\r
-                       {0x1Cu, 0x88u},\r
-                       {0x1Du, 0x15u},\r
-                       {0x22u, 0x0Au},\r
-                       {0x23u, 0x06u},\r
-                       {0x27u, 0x40u},\r
-                       {0x28u, 0x10u},\r
-                       {0x29u, 0x10u},\r
+                       {0x00u, 0x02u},\r
+                       {0x03u, 0x02u},\r
+                       {0x04u, 0x80u},\r
+                       {0x05u, 0x10u},\r
+                       {0x06u, 0x90u},\r
+                       {0x0Au, 0x82u},\r
+                       {0x0Bu, 0x06u},\r
+                       {0x0Eu, 0x61u},\r
+                       {0x0Fu, 0x04u},\r
+                       {0x10u, 0x04u},\r
+                       {0x11u, 0x04u},\r
+                       {0x13u, 0x40u},\r
+                       {0x14u, 0x14u},\r
+                       {0x15u, 0x01u},\r
+                       {0x16u, 0x02u},\r
+                       {0x17u, 0x04u},\r
+                       {0x1Au, 0x82u},\r
+                       {0x1Eu, 0x40u},\r
+                       {0x1Fu, 0x10u},\r
+                       {0x21u, 0x28u},\r
+                       {0x25u, 0x10u},\r
+                       {0x27u, 0x08u},\r
+                       {0x29u, 0x82u},\r
+                       {0x2Cu, 0x04u},\r
+                       {0x2Eu, 0x04u},\r
                        {0x2Fu, 0x02u},\r
-                       {0x30u, 0xC0u},\r
-                       {0x31u, 0x20u},\r
-                       {0x32u, 0x08u},\r
-                       {0x34u, 0x08u},\r
-                       {0x37u, 0x40u},\r
-                       {0x38u, 0x20u},\r
-                       {0x3Eu, 0x10u},\r
-                       {0x3Fu, 0x80u},\r
-                       {0x58u, 0x10u},\r
-                       {0x5Au, 0x60u},\r
-                       {0x5Cu, 0x24u},\r
-                       {0x5Du, 0x02u},\r
-                       {0x5Fu, 0x80u},\r
-                       {0x62u, 0x40u},\r
-                       {0x63u, 0x02u},\r
-                       {0x64u, 0x01u},\r
-                       {0x80u, 0x04u},\r
-                       {0x81u, 0x40u},\r
-                       {0x85u, 0x02u},\r
+                       {0x31u, 0x21u},\r
+                       {0x32u, 0x80u},\r
+                       {0x35u, 0x04u},\r
+                       {0x36u, 0x10u},\r
+                       {0x38u, 0x08u},\r
+                       {0x3Du, 0x20u},\r
+                       {0x3Eu, 0x80u},\r
+                       {0x3Fu, 0x45u},\r
+                       {0x59u, 0x40u},\r
+                       {0x63u, 0x01u},\r
+                       {0x6Cu, 0x02u},\r
+                       {0x6Eu, 0x80u},\r
+                       {0x81u, 0x04u},\r
+                       {0x84u, 0x20u},\r
+                       {0x86u, 0x04u},\r
+                       {0x87u, 0x04u},\r
+                       {0x88u, 0x0Au},\r
+                       {0x89u, 0x41u},\r
                        {0x8Au, 0x01u},\r
-                       {0x8Cu, 0x01u},\r
-                       {0x8Du, 0x20u},\r
-                       {0x92u, 0x70u},\r
-                       {0x94u, 0x2Cu},\r
-                       {0x95u, 0x60u},\r
-                       {0x97u, 0x80u},\r
-                       {0x98u, 0x2Bu},\r
-                       {0x9Bu, 0x80u},\r
-                       {0x9Du, 0xC4u},\r
-                       {0x9Fu, 0x02u},\r
-                       {0xA0u, 0x08u},\r
-                       {0xA1u, 0x20u},\r
-                       {0xA3u, 0x40u},\r
-                       {0xA4u, 0x80u},\r
-                       {0xA6u, 0x30u},\r
-                       {0xA8u, 0x10u},\r
-                       {0xAAu, 0x40u},\r
-                       {0xABu, 0x80u},\r
-                       {0xACu, 0x20u},\r
-                       {0xADu, 0x01u},\r
-                       {0xB6u, 0x60u},\r
-                       {0xB7u, 0x40u},\r
-                       {0xC0u, 0x3Du},\r
-                       {0xC2u, 0xCDu},\r
-                       {0xC4u, 0x1Fu},\r
-                       {0xCAu, 0x16u},\r
-                       {0xCCu, 0x5Eu},\r
-                       {0xCEu, 0x34u},\r
-                       {0xD6u, 0xF8u},\r
-                       {0xD8u, 0x18u},\r
-                       {0xE0u, 0x11u},\r
-                       {0xE2u, 0xAAu},\r
-                       {0xE6u, 0x84u},\r
-                       {0xEAu, 0x04u},\r
-                       {0xECu, 0x40u},\r
-                       {0x07u, 0x02u},\r
-                       {0x08u, 0x30u},\r
-                       {0x0Au, 0xC0u},\r
-                       {0x0Cu, 0x60u},\r
-                       {0x0Eu, 0x90u},\r
-                       {0x10u, 0xFFu},\r
-                       {0x14u, 0x05u},\r
-                       {0x16u, 0x0Au},\r
+                       {0x8Fu, 0x20u},\r
+                       {0x90u, 0x08u},\r
+                       {0x91u, 0x05u},\r
+                       {0x94u, 0x80u},\r
+                       {0x97u, 0x62u},\r
+                       {0x98u, 0x18u},\r
+                       {0x99u, 0x92u},\r
+                       {0x9Au, 0x02u},\r
+                       {0x9Cu, 0x06u},\r
+                       {0x9Du, 0x01u},\r
+                       {0xA0u, 0x01u},\r
+                       {0xA2u, 0x11u},\r
+                       {0xA4u, 0xAAu},\r
+                       {0xA5u, 0x08u},\r
+                       {0xA9u, 0x10u},\r
+                       {0xABu, 0x50u},\r
+                       {0xADu, 0x11u},\r
+                       {0xAEu, 0x01u},\r
+                       {0xB2u, 0x08u},\r
+                       {0xB3u, 0x08u},\r
+                       {0xB5u, 0x40u},\r
+                       {0xB6u, 0x40u},\r
+                       {0xC0u, 0xF9u},\r
+                       {0xC2u, 0xFBu},\r
+                       {0xC4u, 0xF7u},\r
+                       {0xCAu, 0x79u},\r
+                       {0xCCu, 0x6Du},\r
+                       {0xCEu, 0xF2u},\r
+                       {0xD6u, 0x08u},\r
+                       {0xD8u, 0x08u},\r
+                       {0xE0u, 0x20u},\r
+                       {0xE2u, 0x01u},\r
+                       {0xE4u, 0x28u},\r
+                       {0xE6u, 0x82u},\r
+                       {0xE8u, 0x60u},\r
+                       {0xECu, 0x80u},\r
+                       {0xEEu, 0x01u},\r
+                       {0x02u, 0x02u},\r
+                       {0x03u, 0x04u},\r
+                       {0x09u, 0x02u},\r
+                       {0x0Bu, 0x01u},\r
+                       {0x0Du, 0x01u},\r
+                       {0x0Fu, 0x02u},\r
+                       {0x11u, 0x04u},\r
+                       {0x12u, 0x01u},\r
+                       {0x13u, 0x08u},\r
+                       {0x15u, 0x02u},\r
+                       {0x16u, 0x04u},\r
                        {0x17u, 0x01u},\r
-                       {0x18u, 0x03u},\r
-                       {0x1Au, 0x0Cu},\r
-                       {0x1Du, 0x01u},\r
-                       {0x1Eu, 0xFFu},\r
-                       {0x1Fu, 0x02u},\r
-                       {0x20u, 0x0Fu},\r
-                       {0x22u, 0xF0u},\r
-                       {0x24u, 0x50u},\r
-                       {0x26u, 0xA0u},\r
-                       {0x28u, 0x06u},\r
-                       {0x2Au, 0x09u},\r
-                       {0x2Eu, 0xFFu},\r
-                       {0x2Fu, 0x04u},\r
-                       {0x30u, 0xFFu},\r
-                       {0x33u, 0x03u},\r
-                       {0x35u, 0x04u},\r
-                       {0x3Eu, 0x01u},\r
-                       {0x3Fu, 0x04u},\r
+                       {0x1Au, 0x08u},\r
+                       {0x1Fu, 0x08u},\r
+                       {0x21u, 0x02u},\r
+                       {0x23u, 0x01u},\r
+                       {0x29u, 0x02u},\r
+                       {0x2Bu, 0x01u},\r
+                       {0x30u, 0x08u},\r
+                       {0x31u, 0x03u},\r
+                       {0x32u, 0x04u},\r
+                       {0x34u, 0x01u},\r
+                       {0x36u, 0x02u},\r
+                       {0x37u, 0x0Cu},\r
+                       {0x3Bu, 0x02u},\r
+                       {0x3Fu, 0x40u},\r
                        {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x90u},\r
+                       {0x5Cu, 0x99u},\r
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x83u, 0x10u},\r
-                       {0x84u, 0x50u},\r
-                       {0x86u, 0xA0u},\r
-                       {0x87u, 0x20u},\r
-                       {0x88u, 0x30u},\r
-                       {0x8Au, 0xC0u},\r
-                       {0x8Bu, 0x0Eu},\r
-                       {0x8Du, 0x01u},\r
-                       {0x8Eu, 0xFFu},\r
-                       {0x94u, 0x05u},\r
-                       {0x95u, 0x32u},\r
-                       {0x96u, 0x0Au},\r
-                       {0x97u, 0x04u},\r
-                       {0x98u, 0x03u},\r
-                       {0x99u, 0x01u},\r
-                       {0x9Au, 0x0Cu},\r
+                       {0x84u, 0x55u},\r
+                       {0x86u, 0xAAu},\r
+                       {0x88u, 0x33u},\r
+                       {0x8Au, 0xCCu},\r
+                       {0x8Bu, 0x08u},\r
+                       {0x8Cu, 0xFFu},\r
+                       {0x8Du, 0x19u},\r
+                       {0x8Fu, 0x02u},\r
+                       {0x92u, 0xFFu},\r
+                       {0x93u, 0x10u},\r
+                       {0x94u, 0x69u},\r
+                       {0x96u, 0x96u},\r
+                       {0x97u, 0x10u},\r
+                       {0x98u, 0xFFu},\r
+                       {0x9Bu, 0x07u},\r
                        {0x9Cu, 0x0Fu},\r
-                       {0x9Du, 0x01u},\r
                        {0x9Eu, 0xF0u},\r
-                       {0xA1u, 0x01u},\r
-                       {0xA2u, 0xFFu},\r
-                       {0xA5u, 0x34u},\r
+                       {0xA5u, 0x1Au},\r
                        {0xA6u, 0xFFu},\r
-                       {0xA7u, 0x0Au},\r
-                       {0xA8u, 0x09u},\r
-                       {0xA9u, 0x28u},\r
-                       {0xAAu, 0x06u},\r
-                       {0xABu, 0x10u},\r
-                       {0xACu, 0x90u},\r
-                       {0xAEu, 0x60u},\r
-                       {0xAFu, 0x20u},\r
-                       {0xB0u, 0xFFu},\r
-                       {0xB3u, 0x01u},\r
-                       {0xB5u, 0x1Eu},\r
-                       {0xB7u, 0x20u},\r
-                       {0xB9u, 0x08u},\r
-                       {0xBEu, 0x01u},\r
-                       {0xBFu, 0x44u},\r
+                       {0xA7u, 0x05u},\r
+                       {0xA9u, 0x14u},\r
+                       {0xAAu, 0xFFu},\r
+                       {0xABu, 0x08u},\r
+                       {0xB1u, 0x10u},\r
+                       {0xB3u, 0x0Fu},\r
+                       {0xB6u, 0xFFu},\r
+                       {0xBAu, 0x80u},\r
+                       {0xBFu, 0x01u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
-                       {0xDCu, 0x10u},\r
+                       {0xDBu, 0x04u},\r
+                       {0xDCu, 0x11u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x40u},\r
-                       {0x02u, 0x04u},\r
-                       {0x04u, 0x28u},\r
-                       {0x05u, 0x40u},\r
-                       {0x06u, 0x14u},\r
-                       {0x09u, 0x1Au},\r
-                       {0x0Bu, 0x02u},\r
-                       {0x0Cu, 0x80u},\r
-                       {0x0Du, 0x28u},\r
-                       {0x0Eu, 0x20u},\r
-                       {0x10u, 0x86u},\r
-                       {0x12u, 0x10u},\r
-                       {0x14u, 0x04u},\r
-                       {0x15u, 0x60u},\r
-                       {0x17u, 0x09u},\r
-                       {0x18u, 0x40u},\r
-                       {0x1Eu, 0x80u},\r
-                       {0x22u, 0x10u},\r
-                       {0x23u, 0x20u},\r
-                       {0x24u, 0x10u},\r
-                       {0x25u, 0x30u},\r
-                       {0x26u, 0x80u},\r
-                       {0x28u, 0x02u},\r
-                       {0x2Cu, 0x20u},\r
-                       {0x2Du, 0x80u},\r
-                       {0x2Eu, 0x20u},\r
-                       {0x2Fu, 0x40u},\r
-                       {0x30u, 0x80u},\r
+                       {0x01u, 0x02u},\r
+                       {0x04u, 0x80u},\r
+                       {0x06u, 0x08u},\r
+                       {0x07u, 0x11u},\r
+                       {0x08u, 0x02u},\r
+                       {0x09u, 0x08u},\r
+                       {0x0Au, 0x04u},\r
+                       {0x0Cu, 0x28u},\r
+                       {0x0Eu, 0x02u},\r
+                       {0x0Fu, 0x40u},\r
+                       {0x14u, 0x24u},\r
+                       {0x18u, 0x08u},\r
+                       {0x19u, 0x82u},\r
+                       {0x1Au, 0x04u},\r
+                       {0x1Bu, 0x04u},\r
+                       {0x1Eu, 0x02u},\r
+                       {0x20u, 0x40u},\r
+                       {0x22u, 0x41u},\r
+                       {0x25u, 0x01u},\r
+                       {0x27u, 0x20u},\r
+                       {0x29u, 0x01u},\r
+                       {0x2Bu, 0x04u},\r
+                       {0x2Cu, 0x24u},\r
+                       {0x30u, 0x82u},\r
                        {0x31u, 0x08u},\r
-                       {0x34u, 0x08u},\r
-                       {0x36u, 0x60u},\r
-                       {0x38u, 0x08u},\r
-                       {0x3Cu, 0x44u},\r
-                       {0x3Du, 0x21u},\r
-                       {0x5Au, 0x80u},\r
-                       {0x60u, 0x02u},\r
-                       {0x65u, 0x40u},\r
-                       {0x67u, 0x02u},\r
-                       {0x78u, 0x01u},\r
-                       {0x7Au, 0x80u},\r
-                       {0x80u, 0x22u},\r
-                       {0x83u, 0x2Au},\r
-                       {0x84u, 0x08u},\r
-                       {0x85u, 0x02u},\r
-                       {0x87u, 0x01u},\r
-                       {0x88u, 0x08u},\r
-                       {0x8Du, 0x04u},\r
-                       {0x8Eu, 0x10u},\r
-                       {0xC0u, 0xE3u},\r
-                       {0xC2u, 0xEFu},\r
-                       {0xC4u, 0xFFu},\r
-                       {0xCAu, 0xF8u},\r
-                       {0xCCu, 0x7Au},\r
-                       {0xCEu, 0xF2u},\r
-                       {0xD6u, 0x08u},\r
-                       {0xD8u, 0x08u},\r
-                       {0xE0u, 0x81u},\r
-                       {0xE2u, 0x50u},\r
-                       {0xE4u, 0x11u},\r
-                       {0x81u, 0x5Cu},\r
-                       {0x84u, 0x14u},\r
-                       {0x85u, 0x24u},\r
+                       {0x34u, 0x10u},\r
+                       {0x37u, 0x29u},\r
+                       {0x38u, 0x40u},\r
+                       {0x3Au, 0x10u},\r
+                       {0x3Bu, 0x02u},\r
+                       {0x3Eu, 0x10u},\r
+                       {0x3Fu, 0x40u},\r
+                       {0x45u, 0x01u},\r
+                       {0x46u, 0x40u},\r
+                       {0x59u, 0x20u},\r
+                       {0x5Bu, 0x40u},\r
+                       {0x5Du, 0x51u},\r
+                       {0x5Fu, 0x08u},\r
+                       {0x60u, 0x08u},\r
+                       {0x62u, 0x90u},\r
+                       {0x66u, 0x40u},\r
+                       {0x81u, 0x20u},\r
+                       {0x82u, 0x02u},\r
+                       {0x84u, 0x21u},\r
+                       {0x86u, 0x10u},\r
                        {0x87u, 0x10u},\r
-                       {0x88u, 0x3Fu},\r
-                       {0x89u, 0x50u},\r
-                       {0x8Au, 0x40u},\r
-                       {0x8Bu, 0x0Cu},\r
-                       {0x8Cu, 0x34u},\r
-                       {0x90u, 0x34u},\r
-                       {0x91u, 0x21u},\r
-                       {0x93u, 0x1Eu},\r
-                       {0x94u, 0x20u},\r
-                       {0x95u, 0x11u},\r
-                       {0x96u, 0x02u},\r
-                       {0x97u, 0x22u},\r
-                       {0x98u, 0x08u},\r
-                       {0x99u, 0x30u},\r
-                       {0x9Au, 0x75u},\r
-                       {0x9Bu, 0x0Fu},\r
-                       {0x9Cu, 0x4Bu},\r
-                       {0x9Eu, 0x30u},\r
-                       {0xA0u, 0x34u},\r
-                       {0xA1u, 0x5Cu},\r
-                       {0xA5u, 0x54u},\r
-                       {0xA6u, 0x34u},\r
-                       {0xA7u, 0x08u},\r
-                       {0xA8u, 0x14u},\r
-                       {0xA9u, 0x08u},\r
-                       {0xAAu, 0x20u},\r
-                       {0xADu, 0x0Cu},\r
-                       {0xAFu, 0x50u},\r
-                       {0xB3u, 0x30u},\r
-                       {0xB4u, 0x07u},\r
-                       {0xB5u, 0x0Fu},\r
-                       {0xB6u, 0x78u},\r
-                       {0xB7u, 0x40u},\r
+                       {0x89u, 0x04u},\r
+                       {0x8Eu, 0x90u},\r
+                       {0xC0u, 0xE8u},\r
+                       {0xC2u, 0xFEu},\r
+                       {0xC4u, 0x60u},\r
+                       {0xCAu, 0x65u},\r
+                       {0xCCu, 0xEBu},\r
+                       {0xCEu, 0x3Du},\r
+                       {0xD6u, 0xFCu},\r
+                       {0xD8u, 0x1Cu},\r
+                       {0xE0u, 0x20u},\r
+                       {0xE2u, 0x40u},\r
+                       {0xE4u, 0x10u},\r
+                       {0xE6u, 0x01u},\r
+                       {0x02u, 0x02u},\r
+                       {0x08u, 0x01u},\r
+                       {0x09u, 0x01u},\r
+                       {0x0Au, 0x02u},\r
+                       {0x1Eu, 0x01u},\r
+                       {0x32u, 0x03u},\r
+                       {0x35u, 0x01u},\r
+                       {0x3Eu, 0x04u},\r
+                       {0x40u, 0x36u},\r
+                       {0x41u, 0x02u},\r
+                       {0x42u, 0x10u},\r
+                       {0x44u, 0x05u},\r
+                       {0x45u, 0xDEu},\r
+                       {0x46u, 0xF0u},\r
+                       {0x47u, 0xCBu},\r
+                       {0x48u, 0x3Bu},\r
+                       {0x49u, 0xFFu},\r
+                       {0x4Au, 0xFFu},\r
+                       {0x4Bu, 0xFFu},\r
+                       {0x4Cu, 0x22u},\r
+                       {0x4Eu, 0xF0u},\r
+                       {0x4Fu, 0x08u},\r
+                       {0x50u, 0x04u},\r
+                       {0x54u, 0x40u},\r
+                       {0x56u, 0x04u},\r
+                       {0x58u, 0x04u},\r
+                       {0x59u, 0x04u},\r
+                       {0x5Au, 0x04u},\r
+                       {0x5Bu, 0x04u},\r
+                       {0x5Cu, 0x90u},\r
+                       {0x5Fu, 0x01u},\r
+                       {0x62u, 0xC0u},\r
+                       {0x64u, 0x40u},\r
+                       {0x65u, 0x01u},\r
+                       {0x66u, 0x10u},\r
+                       {0x67u, 0x11u},\r
+                       {0x68u, 0xC0u},\r
+                       {0x69u, 0x01u},\r
+                       {0x6Bu, 0x11u},\r
+                       {0x6Cu, 0x40u},\r
+                       {0x6Du, 0x01u},\r
+                       {0x6Eu, 0x40u},\r
+                       {0x6Fu, 0x01u},\r
+                       {0x80u, 0x31u},\r
+                       {0x81u, 0xC1u},\r
+                       {0x84u, 0x01u},\r
+                       {0x85u, 0x07u},\r
+                       {0x86u, 0x30u},\r
+                       {0x87u, 0x18u},\r
+                       {0x88u, 0x43u},\r
+                       {0x89u, 0xC0u},\r
+                       {0x8Au, 0x3Cu},\r
+                       {0x8Cu, 0x31u},\r
+                       {0x8Du, 0x01u},\r
+                       {0x8Fu, 0xC0u},\r
+                       {0x90u, 0x30u},\r
+                       {0x92u, 0x01u},\r
+                       {0x93u, 0x40u},\r
+                       {0x94u, 0x06u},\r
+                       {0x95u, 0x22u},\r
+                       {0x96u, 0xB9u},\r
+                       {0x97u, 0x08u},\r
+                       {0x98u, 0x05u},\r
+                       {0x99u, 0x08u},\r
+                       {0x9Au, 0x4Au},\r
+                       {0x9Bu, 0x21u},\r
+                       {0x9Cu, 0xC0u},\r
+                       {0x9Du, 0xC1u},\r
+                       {0xA0u, 0x20u},\r
+                       {0xA1u, 0x04u},\r
+                       {0xA4u, 0x11u},\r
+                       {0xA5u, 0xC1u},\r
+                       {0xA6u, 0x20u},\r
+                       {0xA9u, 0x10u},\r
+                       {0xACu, 0x12u},\r
+                       {0xADu, 0x01u},\r
+                       {0xAEu, 0x01u},\r
+                       {0xB0u, 0x03u},\r
+                       {0xB1u, 0x3Fu},\r
+                       {0xB3u, 0x40u},\r
+                       {0xB4u, 0x3Cu},\r
+                       {0xB6u, 0xC4u},\r
+                       {0xB7u, 0x80u},\r
                        {0xB8u, 0x80u},\r
-                       {0xBAu, 0x30u},\r
-                       {0xBBu, 0x08u},\r
-                       {0xBFu, 0x40u},\r
+                       {0xB9u, 0x02u},\r
+                       {0xBAu, 0x02u},\r
+                       {0xBFu, 0x45u},\r
+                       {0xD6u, 0x02u},\r
+                       {0xD7u, 0x24u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
+                       {0xDBu, 0x04u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x04u},\r
-                       {0x01u, 0x01u},\r
-                       {0x03u, 0x06u},\r
+                       {0x00u, 0x02u},\r
+                       {0x03u, 0x08u},\r
+                       {0x04u, 0x08u},\r
+                       {0x05u, 0x10u},\r
                        {0x06u, 0x02u},\r
-                       {0x07u, 0x14u},\r
-                       {0x09u, 0x20u},\r
-                       {0x0Bu, 0xA2u},\r
+                       {0x07u, 0x40u},\r
+                       {0x0Au, 0x02u},\r
                        {0x0Cu, 0x02u},\r
-                       {0x0Du, 0x08u},\r
-                       {0x0Eu, 0x06u},\r
-                       {0x10u, 0x82u},\r
-                       {0x11u, 0x04u},\r
-                       {0x12u, 0x08u},\r
-                       {0x15u, 0x01u},\r
-                       {0x17u, 0x28u},\r
-                       {0x18u, 0x04u},\r
-                       {0x19u, 0x80u},\r
-                       {0x1Bu, 0x03u},\r
-                       {0x1Du, 0x10u},\r
+                       {0x0Du, 0x40u},\r
+                       {0x0Eu, 0x26u},\r
+                       {0x14u, 0x01u},\r
+                       {0x15u, 0x06u},\r
+                       {0x19u, 0x08u},\r
                        {0x1Eu, 0x06u},\r
-                       {0x1Fu, 0x70u},\r
-                       {0x21u, 0x20u},\r
-                       {0x24u, 0x29u},\r
-                       {0x25u, 0x04u},\r
-                       {0x26u, 0x08u},\r
-                       {0x27u, 0x15u},\r
-                       {0x29u, 0x01u},\r
-                       {0x2Bu, 0x21u},\r
-                       {0x2Cu, 0x02u},\r
-                       {0x2Du, 0x05u},\r
-                       {0x2Fu, 0x04u},\r
-                       {0x30u, 0x82u},\r
-                       {0x32u, 0x10u},\r
-                       {0x33u, 0x04u},\r
-                       {0x35u, 0x10u},\r
-                       {0x36u, 0x01u},\r
-                       {0x37u, 0x04u},\r
-                       {0x38u, 0x20u},\r
-                       {0x39u, 0x05u},\r
-                       {0x3Bu, 0x80u},\r
-                       {0x3Du, 0x08u},\r
-                       {0x3Eu, 0x12u},\r
-                       {0x40u, 0x01u},\r
-                       {0x43u, 0x24u},\r
-                       {0x49u, 0x05u},\r
-                       {0x4Au, 0x05u},\r
-                       {0x4Bu, 0x02u},\r
-                       {0x51u, 0x08u},\r
-                       {0x52u, 0x50u},\r
-                       {0x53u, 0x04u},\r
-                       {0x60u, 0x20u},\r
-                       {0x61u, 0x0Au},\r
-                       {0x68u, 0x0Au},\r
-                       {0x69u, 0x05u},\r
-                       {0x6Au, 0x30u},\r
-                       {0x6Bu, 0x68u},\r
-                       {0x70u, 0x80u},\r
-                       {0x72u, 0x02u},\r
-                       {0x8Eu, 0x04u},\r
-                       {0x94u, 0x08u},\r
-                       {0x95u, 0x04u},\r
-                       {0x96u, 0x10u},\r
-                       {0x97u, 0x82u},\r
-                       {0x9Cu, 0x20u},\r
-                       {0x9Du, 0x94u},\r
-                       {0x9Eu, 0x52u},\r
-                       {0x9Fu, 0x45u},\r
-                       {0xA1u, 0x02u},\r
-                       {0xA4u, 0x0Au},\r
-                       {0xA6u, 0x01u},\r
-                       {0xC0u, 0xEFu},\r
-                       {0xC2u, 0xFFu},\r
-                       {0xC4u, 0x7Fu},\r
-                       {0xCAu, 0xFBu},\r
-                       {0xCCu, 0xEFu},\r
-                       {0xCEu, 0xEFu},\r
+                       {0x1Fu, 0x11u},\r
+                       {0x21u, 0x10u},\r
+                       {0x24u, 0x90u},\r
+                       {0x25u, 0x80u},\r
+                       {0x27u, 0x02u},\r
+                       {0x2Cu, 0x09u},\r
+                       {0x2Du, 0x04u},\r
+                       {0x2Fu, 0x41u},\r
+                       {0x35u, 0x02u},\r
+                       {0x36u, 0x14u},\r
+                       {0x37u, 0x40u},\r
+                       {0x39u, 0x10u},\r
+                       {0x3Du, 0xA0u},\r
+                       {0x3Eu, 0x06u},\r
+                       {0x41u, 0x88u},\r
+                       {0x42u, 0x04u},\r
+                       {0x49u, 0x86u},\r
+                       {0x4Au, 0x84u},\r
+                       {0x50u, 0x08u},\r
+                       {0x51u, 0x01u},\r
+                       {0x52u, 0x10u},\r
+                       {0x60u, 0x10u},\r
+                       {0x61u, 0x01u},\r
+                       {0x62u, 0x90u},\r
+                       {0x67u, 0x04u},\r
+                       {0x6Cu, 0x16u},\r
+                       {0x6Du, 0xE4u},\r
+                       {0x6Fu, 0x40u},\r
+                       {0x76u, 0x02u},\r
+                       {0x84u, 0x01u},\r
+                       {0x85u, 0x80u},\r
+                       {0x89u, 0x10u},\r
+                       {0x8Au, 0x06u},\r
+                       {0x8Cu, 0x04u},\r
+                       {0x92u, 0x02u},\r
+                       {0x93u, 0x84u},\r
+                       {0x94u, 0xACu},\r
+                       {0x95u, 0xE6u},\r
+                       {0x96u, 0x0Cu},\r
+                       {0x97u, 0x22u},\r
+                       {0x99u, 0x10u},\r
+                       {0x9Du, 0x0Du},\r
+                       {0x9Eu, 0x02u},\r
+                       {0x9Fu, 0x42u},\r
+                       {0xA1u, 0x08u},\r
+                       {0xA2u, 0x14u},\r
+                       {0xA3u, 0x08u},\r
+                       {0xA4u, 0x08u},\r
+                       {0xA5u, 0x50u},\r
+                       {0xA6u, 0x02u},\r
+                       {0xA8u, 0x02u},\r
+                       {0xA9u, 0x82u},\r
+                       {0xADu, 0x29u},\r
+                       {0xB0u, 0x04u},\r
+                       {0xB2u, 0x90u},\r
+                       {0xB3u, 0x08u},\r
+                       {0xB4u, 0x40u},\r
+                       {0xC0u, 0xFAu},\r
+                       {0xC2u, 0xF1u},\r
+                       {0xC4u, 0xB0u},\r
+                       {0xCAu, 0xF0u},\r
+                       {0xCCu, 0xF0u},\r
+                       {0xCEu, 0xF4u},\r
                        {0xD0u, 0x0Eu},\r
                        {0xD2u, 0x0Cu},\r
-                       {0xD8u, 0x01u},\r
-                       {0xE0u, 0x40u},\r
-                       {0x00u, 0x08u},\r
+                       {0xD8u, 0x2Fu},\r
+                       {0xE6u, 0x08u},\r
+                       {0xEAu, 0x05u},\r
+                       {0x00u, 0x34u},\r
+                       {0x01u, 0xC0u},\r
                        {0x03u, 0x01u},\r
-                       {0x04u, 0x01u},\r
-                       {0x07u, 0x0Cu},\r
-                       {0x08u, 0x04u},\r
-                       {0x09u, 0x60u},\r
-                       {0x11u, 0x14u},\r
-                       {0x12u, 0x08u},\r
-                       {0x13u, 0x43u},\r
-                       {0x14u, 0x08u},\r
-                       {0x15u, 0x11u},\r
-                       {0x17u, 0x22u},\r
-                       {0x18u, 0x07u},\r
-                       {0x19u, 0x28u},\r
-                       {0x1Bu, 0x13u},\r
-                       {0x1Eu, 0x02u},\r
-                       {0x22u, 0x08u},\r
-                       {0x24u, 0x08u},\r
-                       {0x2Au, 0x07u},\r
-                       {0x2Cu, 0x08u},\r
-                       {0x2Fu, 0x82u},\r
-                       {0x30u, 0x07u},\r
-                       {0x33u, 0x0Fu},\r
-                       {0x34u, 0x08u},\r
-                       {0x35u, 0x70u},\r
-                       {0x37u, 0x80u},\r
-                       {0x39u, 0x20u},\r
-                       {0x3Eu, 0x11u},\r
-                       {0x54u, 0x40u},\r
-                       {0x56u, 0x04u},\r
+                       {0x05u, 0x1Fu},\r
+                       {0x06u, 0x34u},\r
+                       {0x07u, 0x20u},\r
+                       {0x08u, 0x14u},\r
+                       {0x09u, 0xC0u},\r
+                       {0x0Au, 0x20u},\r
+                       {0x0Bu, 0x08u},\r
+                       {0x0Cu, 0x80u},\r
+                       {0x0Du, 0x90u},\r
+                       {0x0Fu, 0x40u},\r
+                       {0x10u, 0x20u},\r
+                       {0x12u, 0x02u},\r
+                       {0x13u, 0x60u},\r
+                       {0x14u, 0x4Bu},\r
+                       {0x15u, 0x7Fu},\r
+                       {0x16u, 0x30u},\r
+                       {0x17u, 0x80u},\r
+                       {0x18u, 0x3Fu},\r
+                       {0x1Au, 0x40u},\r
+                       {0x1Bu, 0xFFu},\r
+                       {0x1Cu, 0x14u},\r
+                       {0x1Du, 0xC0u},\r
+                       {0x1Fu, 0x02u},\r
+                       {0x20u, 0x34u},\r
+                       {0x24u, 0x08u},\r
+                       {0x25u, 0xC0u},\r
+                       {0x26u, 0x75u},\r
+                       {0x27u, 0x04u},\r
+                       {0x28u, 0x80u},\r
+                       {0x2Bu, 0x9Fu},\r
+                       {0x2Cu, 0x34u},\r
+                       {0x2Du, 0x80u},\r
+                       {0x32u, 0x78u},\r
+                       {0x33u, 0xFFu},\r
+                       {0x34u, 0x07u},\r
+                       {0x36u, 0x80u},\r
+                       {0x38u, 0x88u},\r
+                       {0x3Au, 0x30u},\r
+                       {0x3Fu, 0x04u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
-                       {0x5Bu, 0x04u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x82u, 0x07u},\r
-                       {0x84u, 0x09u},\r
-                       {0x85u, 0x09u},\r
-                       {0x86u, 0x02u},\r
-                       {0x87u, 0x06u},\r
-                       {0x8Cu, 0x04u},\r
-                       {0x8Du, 0x0Bu},\r
-                       {0x8Eu, 0x08u},\r
-                       {0x8Fu, 0x04u},\r
-                       {0x91u, 0x04u},\r
-                       {0x92u, 0x08u},\r
-                       {0x93u, 0x03u},\r
-                       {0xA4u, 0x0Au},\r
-                       {0xA6u, 0x05u},\r
-                       {0xA9u, 0x0Du},\r
-                       {0xABu, 0x02u},\r
-                       {0xB0u, 0x0Fu},\r
-                       {0xB1u, 0x07u},\r
-                       {0xB7u, 0x08u},\r
-                       {0xBBu, 0x02u},\r
-                       {0xBFu, 0x40u},\r
+                       {0x82u, 0xFFu},\r
+                       {0x84u, 0x30u},\r
+                       {0x86u, 0xC0u},\r
+                       {0x88u, 0x0Fu},\r
+                       {0x89u, 0x11u},\r
+                       {0x8Au, 0xF0u},\r
+                       {0x8Bu, 0x0Eu},\r
+                       {0x8Cu, 0x60u},\r
+                       {0x8Eu, 0x90u},\r
+                       {0x90u, 0x50u},\r
+                       {0x92u, 0xA0u},\r
+                       {0x94u, 0x06u},\r
+                       {0x95u, 0x1Bu},\r
+                       {0x96u, 0x09u},\r
+                       {0x97u, 0x04u},\r
+                       {0x98u, 0x05u},\r
+                       {0x99u, 0x04u},\r
+                       {0x9Au, 0x0Au},\r
+                       {0x9Bu, 0x03u},\r
+                       {0xA4u, 0x03u},\r
+                       {0xA6u, 0x0Cu},\r
+                       {0xA9u, 0x15u},\r
+                       {0xAAu, 0xFFu},\r
+                       {0xABu, 0x0Au},\r
+                       {0xACu, 0xFFu},\r
+                       {0xB1u, 0x08u},\r
+                       {0xB5u, 0x07u},\r
+                       {0xB6u, 0xFFu},\r
+                       {0xB7u, 0x10u},\r
+                       {0xBBu, 0x20u},\r
+                       {0xBEu, 0x40u},\r
+                       {0xBFu, 0x41u},\r
                        {0xD4u, 0x09u},\r
                        {0xD6u, 0x04u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x01u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x0Bu},\r
-                       {0x03u, 0x02u},\r
-                       {0x04u, 0x08u},\r
-                       {0x05u, 0x10u},\r
+                       {0x00u, 0x44u},\r
+                       {0x02u, 0xC1u},\r
+                       {0x03u, 0x08u},\r
+                       {0x04u, 0xA8u},\r
                        {0x07u, 0x40u},\r
-                       {0x0Au, 0x40u},\r
-                       {0x0Cu, 0x02u},\r
-                       {0x0Du, 0x21u},\r
-                       {0x0Eu, 0x12u},\r
-                       {0x13u, 0x08u},\r
-                       {0x15u, 0x04u},\r
-                       {0x16u, 0x42u},\r
-                       {0x17u, 0x20u},\r
-                       {0x19u, 0x02u},\r
-                       {0x1Du, 0x01u},\r
-                       {0x1Fu, 0x10u},\r
-                       {0x21u, 0x02u},\r
-                       {0x23u, 0x01u},\r
-                       {0x24u, 0x01u},\r
-                       {0x25u, 0x34u},\r
+                       {0x08u, 0x54u},\r
+                       {0x09u, 0x02u},\r
+                       {0x0Bu, 0x02u},\r
+                       {0x0Cu, 0x40u},\r
+                       {0x0Du, 0x01u},\r
+                       {0x0Eu, 0x24u},\r
+                       {0x10u, 0x22u},\r
+                       {0x11u, 0x10u},\r
+                       {0x15u, 0x41u},\r
+                       {0x17u, 0x28u},\r
+                       {0x1Au, 0x01u},\r
+                       {0x1Cu, 0x20u},\r
+                       {0x1Du, 0x18u},\r
+                       {0x1Eu, 0x2Au},\r
+                       {0x1Fu, 0x40u},\r
+                       {0x22u, 0x10u},\r
+                       {0x23u, 0x85u},\r
                        {0x27u, 0x20u},\r
                        {0x29u, 0x10u},\r
+                       {0x2Cu, 0x08u},\r
+                       {0x2Du, 0x04u},\r
                        {0x2Fu, 0x01u},\r
-                       {0x31u, 0x02u},\r
-                       {0x35u, 0x10u},\r
-                       {0x36u, 0x01u},\r
-                       {0x37u, 0x04u},\r
-                       {0x38u, 0x08u},\r
-                       {0x3Bu, 0x80u},\r
-                       {0x3Cu, 0x01u},\r
-                       {0x3Du, 0x28u},\r
-                       {0x58u, 0x20u},\r
-                       {0x59u, 0x84u},\r
-                       {0x5Bu, 0x01u},\r
-                       {0x62u, 0x02u},\r
-                       {0x63u, 0x01u},\r
-                       {0x66u, 0x51u},\r
-                       {0x67u, 0x20u},\r
+                       {0x31u, 0x08u},\r
+                       {0x32u, 0x10u},\r
+                       {0x36u, 0x15u},\r
+                       {0x37u, 0x58u},\r
+                       {0x3Bu, 0x20u},\r
+                       {0x3Du, 0xA1u},\r
+                       {0x3Eu, 0x06u},\r
+                       {0x59u, 0x24u},\r
+                       {0x5Bu, 0x82u},\r
+                       {0x63u, 0x41u},\r
                        {0x81u, 0x01u},\r
-                       {0x92u, 0x40u},\r
-                       {0x94u, 0x08u},\r
-                       {0x95u, 0x07u},\r
-                       {0x99u, 0x08u},\r
-                       {0x9Bu, 0x08u},\r
-                       {0x9Du, 0x10u},\r
-                       {0x9Eu, 0x03u},\r
-                       {0x9Fu, 0x40u},\r
-                       {0xA3u, 0x02u},\r
-                       {0xA4u, 0x08u},\r
-                       {0xA6u, 0x03u},\r
-                       {0xA9u, 0x40u},\r
-                       {0xAAu, 0x04u},\r
-                       {0xB6u, 0x01u},\r
-                       {0xC0u, 0x7Du},\r
-                       {0xC2u, 0xF8u},\r
-                       {0xC4u, 0xF4u},\r
-                       {0xCAu, 0x14u},\r
-                       {0xCCu, 0xE1u},\r
-                       {0xCEu, 0xEAu},\r
+                       {0x87u, 0x40u},\r
+                       {0x91u, 0x10u},\r
+                       {0x92u, 0x02u},\r
+                       {0x94u, 0x2Cu},\r
+                       {0x95u, 0xE1u},\r
+                       {0x96u, 0x0Du},\r
+                       {0x98u, 0x10u},\r
+                       {0x9Cu, 0x04u},\r
+                       {0x9Du, 0x80u},\r
+                       {0x9Eu, 0x51u},\r
+                       {0x9Fu, 0x58u},\r
+                       {0xA0u, 0x20u},\r
+                       {0xA4u, 0x18u},\r
+                       {0xA5u, 0x02u},\r
+                       {0xA6u, 0x02u},\r
+                       {0xA7u, 0x08u},\r
+                       {0xA8u, 0x80u},\r
+                       {0xA9u, 0x10u},\r
+                       {0xAAu, 0x30u},\r
+                       {0xC0u, 0xFFu},\r
+                       {0xC2u, 0xFEu},\r
+                       {0xC4u, 0xF7u},\r
+                       {0xCAu, 0x74u},\r
+                       {0xCCu, 0xF6u},\r
+                       {0xCEu, 0xF4u},\r
                        {0xD6u, 0x0Fu},\r
-                       {0xD8u, 0xF9u},\r
-                       {0xE8u, 0x01u},\r
-                       {0xEEu, 0x40u},\r
-                       {0x9Cu, 0x80u},\r
-                       {0xABu, 0x20u},\r
-                       {0xB1u, 0x86u},\r
-                       {0xB3u, 0x20u},\r
-                       {0x88u, 0x80u},\r
-                       {0x9Cu, 0x80u},\r
+                       {0xD8u, 0x09u},\r
+                       {0xEAu, 0x07u},\r
+                       {0xECu, 0x01u},\r
+                       {0xEEu, 0x10u},\r
+                       {0x38u, 0x02u},\r
+                       {0x39u, 0x01u},\r
+                       {0x91u, 0x22u},\r
+                       {0x94u, 0x04u},\r
+                       {0x95u, 0x01u},\r
+                       {0x98u, 0x08u},\r
+                       {0x9Au, 0x22u},\r
+                       {0x9Bu, 0x10u},\r
+                       {0x9Du, 0x0Bu},\r
+                       {0x9Eu, 0x14u},\r
+                       {0x9Fu, 0x08u},\r
+                       {0xA2u, 0x52u},\r
+                       {0xA4u, 0x80u},\r
+                       {0xA8u, 0x04u},\r
+                       {0xAAu, 0x04u},\r
+                       {0xABu, 0x09u},\r
+                       {0xEAu, 0x02u},\r
+                       {0xEEu, 0x10u},\r
+                       {0x06u, 0x02u},\r
+                       {0x0Du, 0x02u},\r
+                       {0x0Eu, 0x08u},\r
+                       {0x0Fu, 0x01u},\r
+                       {0x10u, 0x01u},\r
+                       {0x12u, 0x02u},\r
+                       {0x15u, 0x02u},\r
+                       {0x16u, 0x04u},\r
+                       {0x17u, 0x09u},\r
+                       {0x19u, 0x02u},\r
+                       {0x1Au, 0x01u},\r
+                       {0x1Bu, 0x05u},\r
+                       {0x1Du, 0x01u},\r
+                       {0x1Fu, 0x02u},\r
+                       {0x2Du, 0x02u},\r
+                       {0x2Fu, 0x11u},\r
+                       {0x30u, 0x04u},\r
+                       {0x31u, 0x04u},\r
+                       {0x32u, 0x08u},\r
+                       {0x33u, 0x10u},\r
+                       {0x34u, 0x03u},\r
+                       {0x35u, 0x08u},\r
+                       {0x37u, 0x03u},\r
+                       {0x3Bu, 0x80u},\r
+                       {0x3Eu, 0x10u},\r
+                       {0x56u, 0x08u},\r
+                       {0x58u, 0x04u},\r
+                       {0x59u, 0x04u},\r
+                       {0x5Bu, 0x04u},\r
+                       {0x5Cu, 0x99u},\r
+                       {0x5Du, 0x90u},\r
+                       {0x5Fu, 0x01u},\r
+                       {0x80u, 0x90u},\r
+                       {0x82u, 0x60u},\r
+                       {0x83u, 0xFFu},\r
+                       {0x84u, 0x09u},\r
+                       {0x86u, 0x06u},\r
+                       {0x87u, 0xFFu},\r
+                       {0x88u, 0x30u},\r
+                       {0x89u, 0xFFu},\r
+                       {0x8Au, 0xC0u},\r
+                       {0x8Du, 0x60u},\r
+                       {0x8Eu, 0xFFu},\r
+                       {0x8Fu, 0x90u},\r
+                       {0x90u, 0x0Fu},\r
+                       {0x92u, 0xF0u},\r
+                       {0x95u, 0x50u},\r
+                       {0x96u, 0xFFu},\r
+                       {0x97u, 0xA0u},\r
+                       {0x98u, 0x03u},\r
+                       {0x99u, 0x03u},\r
+                       {0x9Au, 0x0Cu},\r
+                       {0x9Bu, 0x0Cu},\r
+                       {0x9Du, 0x0Fu},\r
+                       {0x9Fu, 0xF0u},\r
+                       {0xA0u, 0x05u},\r
+                       {0xA1u, 0x05u},\r
+                       {0xA2u, 0x0Au},\r
+                       {0xA3u, 0x0Au},\r
+                       {0xA4u, 0x50u},\r
+                       {0xA5u, 0x30u},\r
+                       {0xA6u, 0xA0u},\r
+                       {0xA7u, 0xC0u},\r
+                       {0xA9u, 0x06u},\r
+                       {0xAAu, 0xFFu},\r
+                       {0xABu, 0x09u},\r
+                       {0xB4u, 0xFFu},\r
+                       {0xB5u, 0xFFu},\r
+                       {0xBEu, 0x10u},\r
+                       {0xBFu, 0x10u},\r
+                       {0xD8u, 0x04u},\r
+                       {0xD9u, 0x04u},\r
+                       {0xDBu, 0x04u},\r
+                       {0xDFu, 0x01u},\r
+                       {0x02u, 0x02u},\r
+                       {0x03u, 0x20u},\r
+                       {0x04u, 0x22u},\r
+                       {0x06u, 0x22u},\r
+                       {0x08u, 0x18u},\r
+                       {0x0Au, 0x40u},\r
+                       {0x0Cu, 0x10u},\r
+                       {0x0Du, 0x10u},\r
+                       {0x0Eu, 0xE0u},\r
+                       {0x0Fu, 0x10u},\r
+                       {0x14u, 0x40u},\r
+                       {0x15u, 0x02u},\r
+                       {0x16u, 0x08u},\r
+                       {0x17u, 0x14u},\r
+                       {0x18u, 0x04u},\r
+                       {0x19u, 0x09u},\r
+                       {0x1Eu, 0x04u},\r
+                       {0x20u, 0x02u},\r
+                       {0x21u, 0xA8u},\r
+                       {0x23u, 0x40u},\r
+                       {0x27u, 0x08u},\r
+                       {0x28u, 0x02u},\r
+                       {0x2Cu, 0x40u},\r
+                       {0x2Eu, 0x20u},\r
+                       {0x2Fu, 0x20u},\r
+                       {0x31u, 0xA8u},\r
+                       {0x34u, 0x10u},\r
+                       {0x36u, 0x40u},\r
+                       {0x37u, 0x04u},\r
+                       {0x3Bu, 0x40u},\r
+                       {0x3Du, 0x80u},\r
+                       {0x3Eu, 0x0Au},\r
+                       {0x3Fu, 0x10u},\r
+                       {0x59u, 0x80u},\r
+                       {0x60u, 0x02u},\r
+                       {0x6Cu, 0x91u},\r
+                       {0x6Du, 0x80u},\r
+                       {0x6Fu, 0x24u},\r
+                       {0x74u, 0x40u},\r
+                       {0x75u, 0x02u},\r
+                       {0x76u, 0x14u},\r
+                       {0x85u, 0x02u},\r
+                       {0x88u, 0x41u},\r
+                       {0x89u, 0x80u},\r
+                       {0x8Cu, 0x10u},\r
+                       {0x91u, 0x22u},\r
+                       {0x94u, 0x06u},\r
+                       {0x96u, 0x04u},\r
+                       {0x98u, 0x08u},\r
+                       {0x9Au, 0x22u},\r
+                       {0x9Bu, 0x10u},\r
+                       {0x9Du, 0x0Bu},\r
+                       {0x9Eu, 0x14u},\r
+                       {0x9Fu, 0x0Cu},\r
+                       {0xA2u, 0x52u},\r
+                       {0xA4u, 0x80u},\r
+                       {0xABu, 0x14u},\r
+                       {0xB2u, 0x74u},\r
+                       {0xB4u, 0x01u},\r
+                       {0xC0u, 0xF5u},\r
+                       {0xC2u, 0x7Eu},\r
+                       {0xC4u, 0x70u},\r
+                       {0xCAu, 0xE8u},\r
+                       {0xCCu, 0x7Eu},\r
+                       {0xCEu, 0xF8u},\r
+                       {0xD6u, 0x08u},\r
+                       {0xD8u, 0x08u},\r
+                       {0xE2u, 0x80u},\r
+                       {0xE6u, 0x60u},\r
+                       {0xEAu, 0xE0u},\r
+                       {0xEEu, 0xA0u},\r
                        {0x12u, 0x08u},\r
                        {0x16u, 0x80u},\r
-                       {0x17u, 0x20u},\r
-                       {0x32u, 0x04u},\r
-                       {0x36u, 0x80u},\r
-                       {0x37u, 0x08u},\r
-                       {0x38u, 0x01u},\r
+                       {0x17u, 0x80u},\r
+                       {0x30u, 0x02u},\r
+                       {0x36u, 0x22u},\r
+                       {0x39u, 0x08u},\r
                        {0x3Au, 0x80u},\r
-                       {0x3Cu, 0x04u},\r
-                       {0x3Du, 0x40u},\r
-                       {0x41u, 0x10u},\r
-                       {0x5Au, 0x01u},\r
-                       {0x5Bu, 0x40u},\r
-                       {0x5Cu, 0x02u},\r
-                       {0x62u, 0x02u},\r
-                       {0x65u, 0x04u},\r
-                       {0x81u, 0x40u},\r
-                       {0x8Au, 0x02u},\r
-                       {0x8Du, 0x04u},\r
+                       {0x3Du, 0x08u},\r
+                       {0x3Fu, 0x10u},\r
+                       {0x42u, 0x08u},\r
+                       {0x53u, 0x08u},\r
+                       {0x5Au, 0x08u},\r
+                       {0x5Eu, 0x08u},\r
+                       {0x60u, 0x08u},\r
+                       {0x67u, 0x20u},\r
+                       {0x82u, 0x10u},\r
+                       {0x83u, 0x10u},\r
+                       {0x87u, 0x50u},\r
                        {0xC4u, 0xE0u},\r
                        {0xCCu, 0xE0u},\r
                        {0xCEu, 0xF0u},\r
                        {0xD0u, 0x10u},\r
-                       {0xD4u, 0x80u},\r
+                       {0xD4u, 0x20u},\r
                        {0xD6u, 0xC0u},\r
                        {0xD8u, 0xC0u},\r
-                       {0xE6u, 0x20u},\r
-                       {0x33u, 0x18u},\r
-                       {0x36u, 0x08u},\r
-                       {0x37u, 0x20u},\r
-                       {0x38u, 0x20u},\r
-                       {0x51u, 0x08u},\r
-                       {0x56u, 0x20u},\r
-                       {0x58u, 0x10u},\r
-                       {0x5Cu, 0x02u},\r
-                       {0x84u, 0x02u},\r
-                       {0x89u, 0x10u},\r
-                       {0x94u, 0x04u},\r
-                       {0x95u, 0x20u},\r
-                       {0x96u, 0x09u},\r
-                       {0x9Bu, 0x30u},\r
-                       {0x9Fu, 0x08u},\r
-                       {0xA6u, 0x80u},\r
-                       {0xA8u, 0x01u},\r
+                       {0xE2u, 0x10u},\r
+                       {0xE6u, 0xE0u},\r
+                       {0x33u, 0x11u},\r
+                       {0x37u, 0x88u},\r
+                       {0x3Au, 0x40u},\r
+                       {0x50u, 0x80u},\r
+                       {0x57u, 0x10u},\r
+                       {0x5Au, 0x20u},\r
+                       {0x67u, 0x80u},\r
+                       {0x84u, 0x08u},\r
+                       {0x92u, 0x20u},\r
+                       {0x93u, 0x80u},\r
+                       {0x96u, 0x08u},\r
+                       {0x9Bu, 0x90u},\r
+                       {0x9Cu, 0x08u},\r
+                       {0x9Eu, 0x08u},\r
+                       {0xA3u, 0x10u},\r
+                       {0xA4u, 0x02u},\r
+                       {0xA5u, 0x04u},\r
+                       {0xA6u, 0x26u},\r
+                       {0xA7u, 0x08u},\r
                        {0xAAu, 0x08u},\r
-                       {0xABu, 0x50u},\r
-                       {0xACu, 0x02u},\r
+                       {0xABu, 0x10u},\r
+                       {0xAFu, 0x10u},\r
+                       {0xB1u, 0x04u},\r
                        {0xCCu, 0xF0u},\r
                        {0xCEu, 0x10u},\r
                        {0xD4u, 0xE0u},\r
-                       {0xD6u, 0x80u},\r
-                       {0xE6u, 0x40u},\r
-                       {0xEAu, 0x80u},\r
-                       {0xEEu, 0xC0u},\r
-                       {0x12u, 0x80u},\r
-                       {0x32u, 0x10u},\r
-                       {0x58u, 0x08u},\r
-                       {0x88u, 0x10u},\r
-                       {0x8Au, 0x08u},\r
-                       {0x94u, 0x24u},\r
-                       {0x96u, 0x09u},\r
-                       {0x9Cu, 0x10u},\r
-                       {0x9Fu, 0x08u},\r
-                       {0xA6u, 0x88u},\r
+                       {0xD8u, 0x80u},\r
+                       {0xE6u, 0x10u},\r
+                       {0xEAu, 0x10u},\r
+                       {0x12u, 0x20u},\r
+                       {0x30u, 0x20u},\r
+                       {0x80u, 0x02u},\r
+                       {0x8Eu, 0x04u},\r
+                       {0x96u, 0x08u},\r
+                       {0x9Eu, 0x48u},\r
+                       {0x9Fu, 0x01u},\r
+                       {0xA4u, 0x02u},\r
+                       {0xA5u, 0x04u},\r
+                       {0xA6u, 0x26u},\r
                        {0xA7u, 0x08u},\r
-                       {0xAAu, 0x20u},\r
-                       {0xB5u, 0x08u},\r
+                       {0xABu, 0x08u},\r
+                       {0xB4u, 0x80u},\r
                        {0xC4u, 0x10u},\r
                        {0xCCu, 0x10u},\r
-                       {0xD6u, 0x40u},\r
+                       {0xE2u, 0x20u},\r
                        {0xEAu, 0x20u},\r
-                       {0x86u, 0x04u},\r
-                       {0x87u, 0x08u},\r
-                       {0x8Bu, 0x08u},\r
-                       {0x8Cu, 0x10u},\r
-                       {0x8Eu, 0x10u},\r
-                       {0x94u, 0x24u},\r
-                       {0x96u, 0x28u},\r
-                       {0x9Fu, 0x08u},\r
-                       {0xA7u, 0x08u},\r
-                       {0xA8u, 0x08u},\r
-                       {0xB2u, 0x01u},\r
-                       {0xE6u, 0x50u},\r
-                       {0xEEu, 0x20u},\r
-                       {0x09u, 0x80u},\r
-                       {0x0Au, 0x20u},\r
-                       {0x0Cu, 0x02u},\r
-                       {0x10u, 0x20u},\r
-                       {0x15u, 0x04u},\r
-                       {0x50u, 0x08u},\r
-                       {0x52u, 0x02u},\r
-                       {0x57u, 0x08u},\r
-                       {0x5Cu, 0x40u},\r
-                       {0x82u, 0x02u},\r
-                       {0x83u, 0x08u},\r
-                       {0x8Eu, 0x10u},\r
+                       {0x60u, 0x20u},\r
+                       {0x86u, 0x42u},\r
+                       {0x8Cu, 0x20u},\r
+                       {0x8Du, 0x20u},\r
+                       {0x96u, 0x08u},\r
+                       {0x9Eu, 0x48u},\r
+                       {0x9Fu, 0x01u},\r
+                       {0xA4u, 0x20u},\r
+                       {0xA5u, 0x04u},\r
+                       {0xA6u, 0x02u},\r
+                       {0xABu, 0x08u},\r
+                       {0xD8u, 0x40u},\r
+                       {0xE2u, 0x50u},\r
+                       {0xEEu, 0x80u},\r
+                       {0x08u, 0x82u},\r
+                       {0x0Fu, 0x40u},\r
+                       {0x13u, 0x02u},\r
+                       {0x17u, 0x04u},\r
+                       {0x53u, 0x80u},\r
+                       {0x56u, 0x01u},\r
+                       {0x57u, 0x40u},\r
+                       {0x5Bu, 0x40u},\r
+                       {0x80u, 0x02u},\r
                        {0xC2u, 0x0Eu},\r
                        {0xC4u, 0x0Cu},\r
                        {0xD4u, 0x07u},\r
                        {0xD6u, 0x04u},\r
-                       {0xE2u, 0x02u},\r
-                       {0x00u, 0x08u},\r
-                       {0x03u, 0x08u},\r
-                       {0x05u, 0x02u},\r
-                       {0x06u, 0x02u},\r
-                       {0x09u, 0x12u},\r
-                       {0x0Du, 0x24u},\r
-                       {0x80u, 0x08u},\r
-                       {0x82u, 0x02u},\r
-                       {0x85u, 0x06u},\r
-                       {0x89u, 0x02u},\r
-                       {0x8Bu, 0x08u},\r
-                       {0x8Cu, 0x40u},\r
-                       {0x91u, 0x04u},\r
-                       {0x94u, 0x40u},\r
-                       {0xA0u, 0x20u},\r
-                       {0xA4u, 0x08u},\r
-                       {0xA8u, 0x02u},\r
-                       {0xB5u, 0x80u},\r
+                       {0x02u, 0x02u},\r
+                       {0x03u, 0x20u},\r
+                       {0x04u, 0x80u},\r
+                       {0x07u, 0x80u},\r
+                       {0x09u, 0x10u},\r
+                       {0x0Bu, 0x20u},\r
+                       {0x0Cu, 0x20u},\r
+                       {0x0Fu, 0x20u},\r
+                       {0x80u, 0x40u},\r
+                       {0x87u, 0x90u},\r
+                       {0x8Bu, 0x20u},\r
+                       {0x8Fu, 0x04u},\r
+                       {0x93u, 0x40u},\r
+                       {0x9Bu, 0x06u},\r
+                       {0x9Eu, 0x01u},\r
+                       {0xA7u, 0xC0u},\r
+                       {0xA8u, 0x80u},\r
+                       {0xB7u, 0x40u},\r
                        {0xC0u, 0x0Fu},\r
                        {0xC2u, 0x0Fu},\r
-                       {0xE0u, 0x02u},\r
-                       {0xE2u, 0x05u},\r
-                       {0xEAu, 0x08u},\r
-                       {0x85u, 0x04u},\r
-                       {0x88u, 0x02u},\r
-                       {0x91u, 0x04u},\r
-                       {0xA0u, 0x04u},\r
+                       {0xE2u, 0x01u},\r
+                       {0xE6u, 0x08u},\r
+                       {0xE8u, 0x08u},\r
+                       {0x82u, 0x02u},\r
+                       {0x8Fu, 0x40u},\r
+                       {0x96u, 0x40u},\r
+                       {0x9Bu, 0x02u},\r
+                       {0x9Eu, 0x01u},\r
                        {0xA1u, 0x10u},\r
-                       {0xA8u, 0x20u},\r
-                       {0xADu, 0x20u},\r
-                       {0xE6u, 0x01u},\r
-                       {0x09u, 0x20u},\r
-                       {0x0Bu, 0x20u},\r
-                       {0x0Cu, 0x02u},\r
-                       {0x0Eu, 0x08u},\r
-                       {0x87u, 0x10u},\r
-                       {0x8Du, 0x20u},\r
-                       {0x8Eu, 0x04u},\r
-                       {0xA4u, 0x02u},\r
+                       {0xA2u, 0x02u},\r
+                       {0xA7u, 0x40u},\r
+                       {0xAAu, 0x40u},\r
+                       {0xABu, 0x80u},\r
+                       {0xACu, 0x20u},\r
+                       {0xAFu, 0x40u},\r
+                       {0xB7u, 0x10u},\r
+                       {0xE4u, 0x02u},\r
+                       {0xEAu, 0x08u},\r
+                       {0x09u, 0x08u},\r
+                       {0x0Au, 0x01u},\r
+                       {0x0Eu, 0x40u},\r
+                       {0x0Fu, 0x01u},\r
+                       {0x82u, 0x01u},\r
+                       {0x86u, 0x01u},\r
+                       {0x96u, 0x40u},\r
+                       {0x9Eu, 0x01u},\r
                        {0xA9u, 0x10u},\r
-                       {0xACu, 0x04u},\r
+                       {0xAFu, 0x02u},\r
                        {0xC2u, 0x0Fu},\r
-                       {0xE2u, 0x02u},\r
-                       {0xE6u, 0x02u},\r
-                       {0x83u, 0x40u},\r
-                       {0x98u, 0x20u},\r
-                       {0xA8u, 0x20u},\r
-                       {0xB4u, 0x04u},\r
+                       {0x81u, 0x04u},\r
+                       {0x86u, 0x08u},\r
+                       {0x96u, 0x08u},\r
+                       {0x99u, 0x20u},\r
+                       {0x9Eu, 0x08u},\r
+                       {0xA3u, 0x04u},\r
+                       {0xA5u, 0x04u},\r
+                       {0xABu, 0x04u},\r
+                       {0xAFu, 0x01u},\r
+                       {0xB4u, 0x20u},\r
                        {0xE2u, 0x20u},\r
+                       {0xE6u, 0x40u},\r
+                       {0xEAu, 0x40u},\r
                        {0xEEu, 0x20u},\r
-                       {0x04u, 0x02u},\r
-                       {0x57u, 0x40u},\r
-                       {0x58u, 0x20u},\r
-                       {0x8Cu, 0x01u},\r
-                       {0x98u, 0x20u},\r
-                       {0xA3u, 0x40u},\r
+                       {0x06u, 0x40u},\r
+                       {0x57u, 0x04u},\r
+                       {0x59u, 0x20u},\r
+                       {0x86u, 0x40u},\r
+                       {0x99u, 0x20u},\r
+                       {0xA3u, 0x04u},\r
+                       {0xAEu, 0x04u},\r
                        {0xC0u, 0x20u},\r
                        {0xD4u, 0xC0u},\r
-                       {0x01u, 0x04u},\r
-                       {0x89u, 0x04u},\r
+                       {0xE0u, 0x10u},\r
+                       {0xEEu, 0x10u},\r
+                       {0xADu, 0x08u},\r
+                       {0xB7u, 0x01u},\r
+                       {0xEEu, 0x08u},\r
+                       {0x02u, 0x40u},\r
+                       {0x8Au, 0x40u},\r
                        {0xC0u, 0x08u},\r
-                       {0xE2u, 0x04u},\r
-                       {0x10u, 0x03u},\r
-                       {0x1Au, 0x03u},\r
+                       {0xE6u, 0x01u},\r
+                       {0x10u, 0x01u},\r
+                       {0x11u, 0x01u},\r
+                       {0x1Au, 0x01u},\r
+                       {0x1Bu, 0x01u},\r
+                       {0x1Du, 0x01u},\r
                        {0x00u, 0xFDu},\r
                        {0x01u, 0xBFu},\r
                        {0x02u, 0x2Au},\r
-                       {0x10u, 0x55u},\r
+                       {0x10u, 0x95u},\r
                };\r
 \r
 \r
@@ -2019,30 +2183,18 @@ void cyfitter_cfg(void)
                        {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
                        {(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
                        {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
-                       {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},\r
+                       {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
                        {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
                        {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
                        {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
                };\r
 \r
-               /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
-               static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
-                       0x01u, 0xC0u, 0x00u, 0x02u, 0x40u, 0xC0u, 0x00u, 0x04u, 0x07u, 0x80u, 0x18u, 0x00u, 0x04u, 0x00u, 0x00u, 0xFFu, \r
-                       0x08u, 0x90u, 0x21u, 0x40u, 0x22u, 0x1Fu, 0x08u, 0x20u, 0x40u, 0xC0u, 0x00u, 0x08u, 0x10u, 0xC0u, 0x00u, 0x01u, \r
-                       0x01u, 0x00u, 0x00u, 0x9Fu, 0x01u, 0x7Fu, 0x00u, 0x80u, 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x60u, \r
-                       0x40u, 0x00u, 0x00u, 0x00u, 0x3Fu, 0xFFu, 0x08u, 0x00u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x10u, \r
-                       0x52u, 0x03u, 0x10u, 0x00u, 0x06u, 0xBEu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
-                       0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, \r
-                       0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
-                       0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
-\r
                /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
                static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
                        0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};\r
 \r
                static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
                        /* dest, src, size */\r
-                       {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},\r
                        {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
                };\r
 \r
index 62eb76f..827126f 100644 (file)
 .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
 \r
 /* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
 .set SDCard_BSPIM_RxStsReg__4__POS, 4\r
 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
 .set SDCard_BSPIM_RxStsReg__6__POS, 6\r
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST\r
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
 .set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1\r
 .set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0\r
 .set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
 .set SDCard_BSPIM_TxStsReg__0__POS, 0\r
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK\r
 \r
 /* SCSI_Out_Ctl */\r
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
 .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
 \r
 /* SCSI_Out_DBx */\r
 .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
 .set scsiTarget_StatusReg__0__POS, 0\r
 .set scsiTarget_StatusReg__1__MASK, 0x02\r
 .set scsiTarget_StatusReg__1__POS, 1\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
 .set scsiTarget_StatusReg__2__MASK, 0x04\r
 .set scsiTarget_StatusReg__2__POS, 2\r
 .set scsiTarget_StatusReg__3__MASK, 0x08\r
 .set scsiTarget_StatusReg__4__MASK, 0x10\r
 .set scsiTarget_StatusReg__4__POS, 4\r
 .set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST\r
 \r
 /* Debug_Timer_Interrupt */\r
 .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
 .set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
 .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
 .set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
 .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
 .set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK\r
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST\r
 \r
 /* SCSI_CTL_PHASE */\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK\r
+\r
+/* SCSI_Glitch_Ctl */\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
 \r
 /* SCSI_Parity_Error */\r
 .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
 .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST\r
 \r
 /* Miscellaneous */\r
 .set BCLK__BUS_CLK__HZ, 50000000\r
index 0c155fc..1faaf51 100644 (file)
@@ -381,34 +381,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
 \r
 /* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
@@ -416,9 +416,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
 SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
@@ -436,8 +436,6 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
 SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
 SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
@@ -1877,15 +1875,6 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
@@ -1898,37 +1887,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL\r
 SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK\r
 \r
 /* SCSI_Out_Ctl */\r
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
 \r
 /* SCSI_Out_DBx */\r
 SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
@@ -2728,8 +2717,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0\r
 scsiTarget_StatusReg__1__MASK EQU 0x02\r
 scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
 scsiTarget_StatusReg__2__MASK EQU 0x04\r
 scsiTarget_StatusReg__2__POS EQU 2\r
 scsiTarget_StatusReg__3__MASK EQU 0x08\r
@@ -2737,9 +2724,9 @@ scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__4__MASK EQU 0x10\r
 scsiTarget_StatusReg__4__POS EQU 4\r
 scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST\r
 \r
 /* Debug_Timer_Interrupt */\r
 Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
@@ -2860,8 +2847,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
@@ -2869,49 +2856,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
 \r
 /* SCSI_CTL_PHASE */\r
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+\r
+/* SCSI_Glitch_Ctl */\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
 \r
 /* SCSI_Parity_Error */\r
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
 \r
 /* Miscellaneous */\r
 BCLK__BUS_CLK__HZ EQU 50000000\r
index ac8e851..88254b2 100644 (file)
@@ -381,34 +381,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
 \r
 ; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
@@ -416,9 +416,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
 SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
@@ -436,8 +436,6 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
 SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
 SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
@@ -1877,15 +1875,6 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
@@ -1898,37 +1887,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL\r
 SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK\r
 \r
 ; SCSI_Out_Ctl\r
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
 \r
 ; SCSI_Out_DBx\r
 SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
@@ -2728,8 +2717,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0\r
 scsiTarget_StatusReg__1__MASK EQU 0x02\r
 scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
 scsiTarget_StatusReg__2__MASK EQU 0x04\r
 scsiTarget_StatusReg__2__POS EQU 2\r
 scsiTarget_StatusReg__3__MASK EQU 0x08\r
@@ -2737,9 +2724,9 @@ scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__4__MASK EQU 0x10\r
 scsiTarget_StatusReg__4__POS EQU 4\r
 scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST\r
 \r
 ; Debug_Timer_Interrupt\r
 Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
@@ -2860,8 +2847,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU&n