Save a cycle in fpga memory interface origin/HEAD origin/master v6.1.1
authorMichael McMaster <michael@codesrc.com>
Sat, 20 May 2017 03:39:22 +0000 (13:39 +1000)
committerMichael McMaster <michael@codesrc.com>
Sat, 20 May 2017 03:39:22 +0000 (13:39 +1000)
CHANGELOG
STM32CubeMX/SCSI2SD-V6/Src/fsmc.c
rtl/fpga_bitmap.o
src/firmware/scsiPhy.c

index 92cf01d..6af0a61 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,4 +1,5 @@
-201705XX               6.1.1
+20170520               6.1.1
+       - Performance improvements to improve throughput at all scsi speeds
        - Add new "turbo" speed option to boost speeds.
                - May not be reliable, and use is not supported.
                - Async timings trimmed
index 8a7bf90..1e200f7 100755 (executable)
@@ -71,8 +71,15 @@ void MX_FSMC_Init(void)
   Timing.AddressSetupTime = 2;
   Timing.AddressHoldTime = 1;
 
-  // 1 for synchroniser skew, 1 to skip hold time, 1 to process read, 1 to output
-  Timing.DataSetupTime = 5;//4 doesn't work ? ?? ?
+  // Writes to device:
+  //   1 for synchroniser skew (dbx also delayed)
+  //   1 to skip hold time
+  //   1 to write data.
+
+  // Reads from device:
+  //   3 for syncroniser
+  //   1 to write back to fsmc bus.
+  Timing.DataSetupTime = 4;
 
   // Allow a clock for us to release signals, plus 3 for the synchroniser to
   // realise the cycle has ended. Need to avoid both devices acting as outputs
index c535bdb..aa8447b 100644 (file)
Binary files a/rtl/fpga_bitmap.o and b/rtl/fpga_bitmap.o differ
index 58d56f6..d0e7002 100755 (executable)
@@ -594,7 +594,7 @@ void scsiPhyReset()
        scsiSetDefaultTiming();\r
 \r
        // DMA Benchmark code\r
-       // Currently 11MB/s.\r
+       // Currently 14.9MB/s.\r
        #ifdef DMA_BENCHMARK\r
        while(1)\r
        {\r
@@ -770,8 +770,11 @@ int scsiSelfTest()
                return 32;\r
        }\r
        *SCSI_CTRL_BSY = 1;\r
+       s2s_delay_ms(1);\r
        if (! scsiStatusBSY())\r
        {\r
+               *SCSI_CTRL_BSY = 0;\r
+\r
                // Error, BSY doesn't work.\r
                return 32;\r
        }\r
@@ -851,7 +854,6 @@ int scsiSelfTest()
        }\r
        */\r
 \r
-\r
        // FPGA comms test code\r
        for(i = 0; i < 10000; ++i)\r
        {\r