-201507XX 4.4
+20150813 4.4
- Added configuration option to allow SCSI2 mode. This option is OFF by
default, and should only be enabled when using the SCSI2SD with a SCSI2 host
controller. Extra timing delays are added in the default SCSI1/SASI mode to
SCSI2SD now negotiates back to async transfers instead of simply
rejecting the message.
- Fixed INQUIRY response to commands lacking an allocation length.
+ - Firmware development updated to PSoC Creator 3.2 (from 3.1)
20150614 4.3
- Added configurable disk geometry.
Amiga 2000 (B2000 rev 6.4 ECS) with DKB RapidFire SCSI 1 card
Amiga 4000 equipped with CyberStorm PPC using 68pin adapter.
Atari TT030 System V
+ Atari TT running TOS 3.06 with HDDRIVER software version 9.06
Atari MEGA STE
needs J3 TERMPWR jumper
1GB limit (--blocks=2048000). The OS will fail to read the boot sector if the disk is >= 1GB.
+ Atari Falcon, TOS 4.02, HDDRIVER 9.06 driver
Sharp X68000
SASI models supported. See gamesx.com for information on building a custom cable.
needs J3 TERMPWR jumper
\r
#include <string.h>\r
\r
-static const uint16_t FIRMWARE_VERSION = 0x0430;\r
+static const uint16_t FIRMWARE_VERSION = 0x0440;\r
\r
// 1 flash row\r
static const uint8_t DEFAULT_CONFIG[256] =\r
\r
SCSI_SEL_ISR_StartEx(scsiSelectionISR);\r
\r
-/*\r
// Disable the glitch filter for ACK to improve performance.\r
- // TODO NEED SOME CONFIG\r
- SCSI_Glitch_Ctl_Write(1);\r
- CY_SET_REG8(scsiTarget_datapath__D0_REG, 0);\r
-*/\r
+ if (getConfigByIndex(0)->flags & CONFIG_DISABLE_GLITCH)\r
+ {\r
+ SCSI_Glitch_Ctl_Write(1);\r
+ CY_SET_REG8(scsiTarget_datapath__D0_REG, 0);\r
+ }\r
\r
}\r
\r
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling Debug_Timer_Interrupt_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use Debug_Timer_Interrupt_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling Debug_Timer_Interrupt_Start
-* or Debug_Timer_Interrupt_StartEx will override any effect this method
-* would have had. This method should only be called after
-* Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx will
+* override any effect this API would have had. This API should only be called
+* after Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 Debug_Timer_Interrupt_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void Debug_Timer_Interrupt_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
********************************************************************************\r
*\r
* Summary:\r
-* Set up the interrupt and enable it.\r
+* Set up the interrupt and enable it. This function disables the interrupt, \r
+* sets the default interrupt vector, sets the priority from the value in the\r
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the \r
+* interrupt controller.\r
*\r
* Parameters: \r
* None\r
********************************************************************************\r
*\r
* Summary:\r
-* Set up the interrupt and enable it.\r
+* Sets up the interrupt and enables it. This function disables the interrupt,\r
+* sets the interrupt vector based on the address passed in, sets the priority \r
+* from the value in the Design Wide Resources Interrupt Editor, then enables \r
+* the interrupt to the interrupt controller.\r
+* \r
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be \r
+* used to provide consistent definition across compilers:\r
+* \r
+* Function definition example:\r
+* CY_ISR(MyISR)\r
+* {\r
+* }\r
+* Function prototype example:\r
+* CY_ISR_PROTO(MyISR);\r
*\r
* Parameters: \r
* address: Address of the ISR to set in the interrupt vector table.\r
* Disables and removes the interrupt.\r
*\r
* Parameters: \r
+* None\r
*\r
* Return:\r
* None\r
* Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start\r
* will override any effect this method would have had. To set the vector \r
* before the component has been started use SCSI_RST_ISR_StartEx instead.\r
+* \r
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be \r
+* used to provide consistent definition across compilers:\r
+*\r
+* Function definition example:\r
+* CY_ISR(MyISR)\r
+* {\r
+* }\r
+*\r
+* Function prototype example:\r
+* CY_ISR_PROTO(MyISR);\r
*\r
* Parameters:\r
* address: Address of the ISR to set in the interrupt vector table.\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets the Priority of the Interrupt. Note calling SCSI_RST_ISR_Start\r
-* or SCSI_RST_ISR_StartEx will override any effect this method \r
-* would have had. This method should only be called after \r
-* SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. To set \r
-* the initial priority for the component use the cydwr file in the tool.\r
+* Sets the Priority of the Interrupt. \r
+*\r
+* Note calling SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx will \r
+* override any effect this API would have had. This API should only be called\r
+* after SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. \r
+* To set the initial priority for the component, use the Design-Wide Resources\r
+* Interrupt Editor.\r
+*\r
+* Note This API has no effect on Non-maskable interrupt NMI).\r
*\r
* Parameters:\r
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
+* priority: Priority of the interrupt, 0 being the highest priority\r
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.\r
+* PSoC 4: Priority is from 0 to 3.\r
*\r
* Return:\r
* None\r
* None\r
*\r
* Return:\r
-* Priority of the interrupt. 0 - 7, 0 being the highest.\r
+* Priority of the interrupt, 0 being the highest priority\r
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.\r
+* PSoC 4: Priority is from 0 to 3.\r
*\r
*******************************************************************************/\r
uint8 SCSI_RST_ISR_GetPriority(void)\r
********************************************************************************\r
*\r
* Summary:\r
-* Enables the interrupt.\r
+* Enables the interrupt to the interrupt controller. Do not call this function\r
+* unless ISR_Start() has been called or the functionality of the ISR_Start() \r
+* function, which sets the vector and the priority, has been called.\r
*\r
* Parameters:\r
* None\r
********************************************************************************\r
*\r
* Summary:\r
-* Disables the Interrupt.\r
+* Disables the Interrupt in the interrupt controller.\r
*\r
* Parameters:\r
* None\r
* Return:\r
* None\r
*\r
+* Side Effects:\r
+* If interrupts are enabled and the interrupt is set up properly, the ISR is\r
+* entered (depending on the priority of this interrupt and other pending \r
+* interrupts).\r
+*\r
*******************************************************************************/\r
void SCSI_RST_ISR_SetPending(void)\r
{\r
********************************************************************************\r
*\r
* Summary:\r
-* Clears a pending interrupt.\r
+* Clears a pending interrupt in the interrupt controller.\r
+*\r
+* Note Some interrupt sources are clear-on-read and require the block \r
+* interrupt/status register to be read/cleared with the appropriate block API \r
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in \r
+* pending state even though the interrupt itself is cleared using this API.\r
*\r
* Parameters:\r
* None\r
*\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_RX_DMA_COMPLETE_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
-* or SCSI_RX_DMA_COMPLETE_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SCSI_RX_DMA_COMPLETE_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SCSI_SEL_ISR_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_SEL_ISR_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SCSI_SEL_ISR_Start
-* or SCSI_SEL_ISR_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SCSI_SEL_ISR_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SCSI_SEL_ISR_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_TX_DMA_COMPLETE_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
-* or SCSI_TX_DMA_COMPLETE_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SCSI_TX_DMA_COMPLETE_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SD_RX_DMA_COMPLETE_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
-* or SD_RX_DMA_COMPLETE_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SD_RX_DMA_COMPLETE_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SD_RX_DMA_COMPLETE_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SD_TX_DMA_COMPLETE_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
-* or SD_TX_DMA_COMPLETE_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SD_TX_DMA_COMPLETE_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SD_TX_DMA_COMPLETE_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************\r
* FILENAME: cydevice.h\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 3.1\r
+* PSoC Creator 3.2\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* FILENAME: cydevice_trm.h\r
* \r
-* PSoC Creator 3.1\r
+* PSoC Creator 3.2\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* FILENAME: cydevicegnu.inc\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 3.1\r
+* PSoC Creator 3.2\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* FILENAME: cydevicegnu_trm.inc\r
* \r
-* PSoC Creator 3.1\r
+* PSoC Creator 3.2\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
;\r
; FILENAME: cydeviceiar.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 3.1\r
+; PSoC Creator 3.2\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; FILENAME: cydeviceiar_trm.inc\r
; \r
-; PSoC Creator 3.1\r
+; PSoC Creator 3.2\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; FILENAME: cydevicerv.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 3.1\r
+; PSoC Creator 3.2\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; FILENAME: cydevicerv_trm.inc\r
; \r
-; PSoC Creator 3.1\r
+; PSoC Creator 3.2\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
#ifndef INCLUDED_CYFITTER_H\r
#define INCLUDED_CYFITTER_H\r
-#include <cydevice.h>\r
-#include <cydevice_trm.h>\r
+#include "cydevice.h"\r
+#include "cydevice_trm.h"\r
\r
/* LED1 */\r
#define LED1__0__MASK 0x08u\r
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL\r
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL\r
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
#define scsiTarget_StatusReg__0__POS 0\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB02_MSK\r
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST\r
\r
/* Debug_Timer_Interrupt */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL\r
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
#define BCLK__BUS_CLK__KHZ 50000U\r
#define BCLK__BUS_CLK__MHZ 50U\r
-#define CY_VERSION "PSoC Creator 3.1"\r
+#define CY_PROJECT_NAME "SCSI2SD"\r
+#define CY_VERSION "PSoC Creator 3.2"\r
+#define CYDEV_CHIP_DIE_GEN4 2u\r
#define CYDEV_CHIP_DIE_LEOPARD 1u\r
-#define CYDEV_CHIP_DIE_PANTHER 6u\r
-#define CYDEV_CHIP_DIE_PSOC4A 3u\r
-#define CYDEV_CHIP_DIE_PSOC5LP 5u\r
+#define CYDEV_CHIP_DIE_PANTHER 12u\r
+#define CYDEV_CHIP_DIE_PSOC4A 5u\r
+#define CYDEV_CHIP_DIE_PSOC5LP 11u\r
#define CYDEV_CHIP_DIE_UNKNOWN 0u\r
#define CYDEV_CHIP_FAMILY_PSOC3 1u\r
#define CYDEV_CHIP_FAMILY_PSOC4 2u\r
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5\r
#define CYDEV_CHIP_JTAG_ID 0x2E133069u\r
#define CYDEV_CHIP_MEMBER_3A 1u\r
-#define CYDEV_CHIP_MEMBER_4A 3u\r
-#define CYDEV_CHIP_MEMBER_4D 2u\r
-#define CYDEV_CHIP_MEMBER_4F 4u\r
-#define CYDEV_CHIP_MEMBER_5A 6u\r
-#define CYDEV_CHIP_MEMBER_5B 5u\r
+#define CYDEV_CHIP_MEMBER_4A 5u\r
+#define CYDEV_CHIP_MEMBER_4C 9u\r
+#define CYDEV_CHIP_MEMBER_4D 3u\r
+#define CYDEV_CHIP_MEMBER_4E 4u\r
+#define CYDEV_CHIP_MEMBER_4F 6u\r
+#define CYDEV_CHIP_MEMBER_4G 2u\r
+#define CYDEV_CHIP_MEMBER_4L 8u\r
+#define CYDEV_CHIP_MEMBER_4M 7u\r
+#define CYDEV_CHIP_MEMBER_5A 11u\r
+#define CYDEV_CHIP_MEMBER_5B 10u\r
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u\r
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B\r
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED\r
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT\r
+#define CYDEV_CHIP_REV_GEN4_ES 17u\r
+#define CYDEV_CHIP_REV_GEN4_ES2 33u\r
+#define CYDEV_CHIP_REV_GEN4_PRODUCTION 17u\r
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u\r
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u\r
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u\r
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u\r
#define CYDEV_CHIP_REVISION_4A_ES0 17u\r
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u\r
+#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u\r
+#define CYDEV_CHIP_REVISION_4G_ES 17u\r
+#define CYDEV_CHIP_REVISION_4G_ES2 33u\r
+#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u\r
+#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_5A_ES0 0u\r
#define CYDEV_CHIP_REVISION_5A_ES1 1u\r
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u\r
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1\r
#define CYDEV_DEBUG_ENABLE_MASK 0x20u\r
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG\r
-#define CYDEV_DEBUGGING_DPS_Disable 3\r
-#define CYDEV_DEBUGGING_DPS_JTAG_4 1\r
-#define CYDEV_DEBUGGING_DPS_JTAG_5 0\r
#define CYDEV_DEBUGGING_DPS_SWD 2\r
#define CYDEV_DEBUGGING_DPS_SWD_SWV 6\r
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV\r
#define CYDEV_INTR_RISING 0x0000007Eu\r
#define CYDEV_PROJ_TYPE 2\r
#define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
+#define CYDEV_PROJ_TYPE_LAUNCHER 5\r
#define CYDEV_PROJ_TYPE_LOADABLE 2\r
+#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4\r
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3\r
#define CYDEV_PROJ_TYPE_STANDARD 0\r
#define CYDEV_PROTECTION_ENABLE 0\r
/*******************************************************************************\r
* FILENAME: cyfitter_cfg.c\r
-* PSoC Creator 3.1\r
+* \r
+* PSoC Creator 3.2\r
*\r
-* Description:\r
-* This file is automatically generated by PSoC Creator with device \r
-* initialization code. Except for the user defined sections in\r
-* CyClockStartupError(), this file should not be modified.\r
+* DESCRIPTION:\r
+* This file contains device initialization code.\r
+* Except for the user defined sections in CyClockStartupError(), this file should not be modified.\r
+* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
********************************************************************************/\r
\r
#include <string.h>\r
-#include <cytypes.h>\r
-#include <cydevice_trm.h>\r
-#include <cyfitter.h>\r
-#include <CyLib.h>\r
-#include <cyfitter_cfg.h>\r
+#include "cytypes.h"\r
+#include "cydevice_trm.h"\r
+#include "cyfitter.h"\r
+#include "CyLib.h"\r
+#include "cyfitter_cfg.h"\r
\r
#define CY_NEED_CYCLOCKSTARTUPERROR 1\r
\r
0x4000520Cu, /* Base address: 0x40005200 Count: 12 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x40010039u, /* Base address: 0x40010000 Count: 57 */\r
- 0x40010135u, /* Base address: 0x40010100 Count: 53 */\r
- 0x40010243u, /* Base address: 0x40010200 Count: 67 */\r
- 0x40010354u, /* Base address: 0x40010300 Count: 84 */\r
- 0x4001043Fu, /* Base address: 0x40010400 Count: 63 */\r
- 0x40010551u, /* Base address: 0x40010500 Count: 81 */\r
+ 0x4001003Bu, /* Base address: 0x40010000 Count: 59 */\r
+ 0x40010142u, /* Base address: 0x40010100 Count: 66 */\r
+ 0x4001023Eu, /* Base address: 0x40010200 Count: 62 */\r
+ 0x4001035Au, /* Base address: 0x40010300 Count: 90 */\r
+ 0x40010447u, /* Base address: 0x40010400 Count: 71 */\r
+ 0x4001054Fu, /* Base address: 0x40010500 Count: 79 */\r
0x4001064Au, /* Base address: 0x40010600 Count: 74 */\r
- 0x4001074Du, /* Base address: 0x40010700 Count: 77 */\r
- 0x40010804u, /* Base address: 0x40010800 Count: 4 */\r
- 0x4001091Eu, /* Base address: 0x40010900 Count: 30 */\r
- 0x40010A54u, /* Base address: 0x40010A00 Count: 84 */\r
- 0x40010B53u, /* Base address: 0x40010B00 Count: 83 */\r
- 0x40010C4Eu, /* Base address: 0x40010C00 Count: 78 */\r
- 0x40010D52u, /* Base address: 0x40010D00 Count: 82 */\r
- 0x40010E42u, /* Base address: 0x40010E00 Count: 66 */\r
+ 0x40010749u, /* Base address: 0x40010700 Count: 73 */\r
+ 0x40010851u, /* Base address: 0x40010800 Count: 81 */\r
+ 0x40010941u, /* Base address: 0x40010900 Count: 65 */\r
+ 0x40010A43u, /* Base address: 0x40010A00 Count: 67 */\r
+ 0x40010B4Au, /* Base address: 0x40010B00 Count: 74 */\r
+ 0x40010C4Du, /* Base address: 0x40010C00 Count: 77 */\r
+ 0x40010D4Bu, /* Base address: 0x40010D00 Count: 75 */\r
+ 0x40010E44u, /* Base address: 0x40010E00 Count: 68 */\r
0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */\r
- 0x4001145Du, /* Base address: 0x40011400 Count: 93 */\r
- 0x40011552u, /* Base address: 0x40011500 Count: 82 */\r
- 0x40011653u, /* Base address: 0x40011600 Count: 83 */\r
- 0x40011744u, /* Base address: 0x40011700 Count: 68 */\r
- 0x40011912u, /* Base address: 0x40011900 Count: 18 */\r
- 0x40011A4Au, /* Base address: 0x40011A00 Count: 74 */\r
- 0x40011B47u, /* Base address: 0x40011B00 Count: 71 */\r
+ 0x4001142Du, /* Base address: 0x40011400 Count: 45 */\r
+ 0x4001154Du, /* Base address: 0x40011500 Count: 77 */\r
+ 0x40011649u, /* Base address: 0x40011600 Count: 73 */\r
+ 0x40011746u, /* Base address: 0x40011700 Count: 70 */\r
+ 0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
+ 0x40011908u, /* Base address: 0x40011900 Count: 8 */\r
+ 0x40011B03u, /* Base address: 0x40011B00 Count: 3 */\r
0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
- 0x4001411Du, /* Base address: 0x40014100 Count: 29 */\r
+ 0x4001411Au, /* Base address: 0x40014100 Count: 26 */\r
0x40014211u, /* Base address: 0x40014200 Count: 17 */\r
- 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */\r
- 0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
- 0x40014517u, /* Base address: 0x40014500 Count: 23 */\r
- 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */\r
- 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */\r
- 0x4001480Eu, /* Base address: 0x40014800 Count: 14 */\r
+ 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */\r
+ 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */\r
+ 0x4001451Cu, /* Base address: 0x40014500 Count: 28 */\r
+ 0x4001460Cu, /* Base address: 0x40014600 Count: 12 */\r
+ 0x4001470Cu, /* Base address: 0x40014700 Count: 12 */\r
+ 0x4001480Cu, /* Base address: 0x40014800 Count: 12 */\r
0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
- 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */\r
+ 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
0x40014D04u, /* Base address: 0x40014D00 Count: 4 */\r
- 0x40015005u, /* Base address: 0x40015000 Count: 5 */\r
+ 0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x1Bu},\r
- {0x00u, 0x14u},\r
- {0x01u, 0x11u},\r
- {0x18u, 0x08u},\r
- {0x19u, 0x04u},\r
+ {0x0Au, 0x36u},\r
+ {0x00u, 0x11u},\r
+ {0x01u, 0x02u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x0Cu},\r
{0x1Cu, 0x71u},\r
- {0x20u, 0x60u},\r
- {0x21u, 0xA0u},\r
+ {0x20u, 0xA8u},\r
+ {0x21u, 0x60u},\r
{0x2Cu, 0x0Eu},\r
- {0x30u, 0x06u},\r
- {0x31u, 0x03u},\r
+ {0x30u, 0x0Au},\r
+ {0x31u, 0x09u},\r
{0x34u, 0x80u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x02u},\r
{0x85u, 0x0Fu},\r
- {0x00u, 0x01u},\r
- {0x02u, 0x02u},\r
- {0x04u, 0x04u},\r
- {0x05u, 0x04u},\r
- {0x14u, 0x02u},\r
+ {0x04u, 0x50u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x28u},\r
+ {0x0Du, 0x01u},\r
+ {0x0Eu, 0x38u},\r
+ {0x10u, 0x02u},\r
+ {0x14u, 0x48u},\r
{0x15u, 0x08u},\r
- {0x16u, 0x01u},\r
- {0x18u, 0x02u},\r
- {0x1Au, 0x01u},\r
- {0x1Cu, 0x10u},\r
- {0x21u, 0x01u},\r
- {0x24u, 0x02u},\r
- {0x26u, 0x01u},\r
- {0x2Bu, 0x02u},\r
- {0x2Cu, 0x02u},\r
- {0x2Eu, 0x09u},\r
- {0x30u, 0x03u},\r
- {0x31u, 0x04u},\r
- {0x32u, 0x08u},\r
- {0x33u, 0x08u},\r
- {0x34u, 0x04u},\r
- {0x35u, 0x02u},\r
- {0x36u, 0x10u},\r
+ {0x16u, 0x10u},\r
+ {0x17u, 0x04u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x04u},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Cu, 0x20u},\r
+ {0x1Du, 0x08u},\r
+ {0x1Eu, 0x40u},\r
+ {0x1Fu, 0x04u},\r
+ {0x21u, 0x08u},\r
+ {0x23u, 0x04u},\r
+ {0x26u, 0x40u},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0x10u},\r
+ {0x2Du, 0x08u},\r
+ {0x2Fu, 0x04u},\r
+ {0x30u, 0x04u},\r
+ {0x31u, 0x10u},\r
+ {0x32u, 0x01u},\r
+ {0x33u, 0x02u},\r
+ {0x34u, 0x02u},\r
+ {0x35u, 0x0Cu},\r
+ {0x36u, 0x78u},\r
{0x37u, 0x01u},\r
- {0x3Au, 0x02u},\r
- {0x3Eu, 0x50u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Eu, 0x15u},\r
{0x3Fu, 0x45u},\r
- {0x40u, 0x34u},\r
- {0x41u, 0x06u},\r
- {0x42u, 0x50u},\r
- {0x45u, 0xCDu},\r
- {0x46u, 0xE2u},\r
- {0x47u, 0x0Fu},\r
+ {0x40u, 0x62u},\r
+ {0x41u, 0x03u},\r
+ {0x42u, 0x40u},\r
+ {0x45u, 0xEFu},\r
+ {0x46u, 0x2Cu},\r
+ {0x47u, 0x0Du},\r
{0x48u, 0x1Fu},\r
{0x49u, 0xFFu},\r
{0x4Au, 0xFFu},\r
{0x59u, 0x04u},\r
{0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
+ {0x5Cu, 0x91u},\r
{0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
{0x62u, 0xC0u},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0xADu, 0x01u},\r
- {0xB3u, 0x01u},\r
- {0xBFu, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDFu, 0x01u},\r
- {0x01u, 0x02u},\r
- {0x02u, 0x10u},\r
- {0x09u, 0x80u},\r
- {0x0Au, 0x18u},\r
- {0x11u, 0x40u},\r
- {0x12u, 0x20u},\r
- {0x19u, 0x12u},\r
- {0x1Au, 0x12u},\r
- {0x1Bu, 0x04u},\r
- {0x21u, 0x02u},\r
- {0x22u, 0xA8u},\r
- {0x27u, 0x10u},\r
- {0x2Bu, 0x44u},\r
- {0x2Fu, 0x01u},\r
- {0x31u, 0x08u},\r
- {0x3Au, 0x04u},\r
+ {0x01u, 0x80u},\r
+ {0x03u, 0x10u},\r
+ {0x08u, 0x22u},\r
+ {0x0Au, 0x10u},\r
+ {0x0Bu, 0x02u},\r
+ {0x10u, 0x10u},\r
+ {0x12u, 0x08u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x20u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x84u},\r
+ {0x1Bu, 0x02u},\r
+ {0x20u, 0x08u},\r
+ {0x21u, 0xA2u},\r
+ {0x22u, 0x04u},\r
+ {0x28u, 0x80u},\r
+ {0x29u, 0x40u},\r
+ {0x2Bu, 0x04u},\r
+ {0x30u, 0x08u},\r
+ {0x31u, 0x20u},\r
+ {0x33u, 0x40u},\r
+ {0x34u, 0x10u},\r
+ {0x37u, 0x20u},\r
+ {0x39u, 0x40u},\r
+ {0x3Bu, 0x04u},\r
{0x41u, 0x04u},\r
- {0x43u, 0x01u},\r
- {0x48u, 0xD4u},\r
- {0x49u, 0x04u},\r
- {0x4Au, 0x01u},\r
- {0x50u, 0x40u},\r
- {0x53u, 0xA4u},\r
- {0x5Au, 0x46u},\r
- {0x5Bu, 0x10u},\r
- {0x61u, 0x12u},\r
- {0x62u, 0x88u},\r
- {0x69u, 0x86u},\r
- {0x6Bu, 0x08u},\r
- {0x6Cu, 0x30u},\r
- {0x6Eu, 0x08u},\r
- {0x6Fu, 0x0Au},\r
- {0x72u, 0x02u},\r
- {0x73u, 0x64u},\r
- {0x82u, 0x04u},\r
- {0x83u, 0x08u},\r
- {0x85u, 0x02u},\r
- {0x87u, 0x02u},\r
- {0x89u, 0x01u},\r
+ {0x42u, 0x10u},\r
+ {0x43u, 0x11u},\r
+ {0x4Au, 0x50u},\r
+ {0x4Bu, 0x20u},\r
+ {0x50u, 0x20u},\r
+ {0x51u, 0x18u},\r
+ {0x53u, 0x68u},\r
+ {0x58u, 0x40u},\r
+ {0x59u, 0x14u},\r
+ {0x5Au, 0x01u},\r
+ {0x60u, 0x04u},\r
+ {0x61u, 0x82u},\r
+ {0x63u, 0x10u},\r
+ {0x68u, 0x42u},\r
+ {0x69u, 0x14u},\r
+ {0x70u, 0x50u},\r
+ {0x72u, 0x80u},\r
+ {0x73u, 0x20u},\r
+ {0x83u, 0x40u},\r
+ {0x84u, 0x40u},\r
+ {0x86u, 0x04u},\r
+ {0x87u, 0x1Au},\r
+ {0x88u, 0x40u},\r
+ {0x8Bu, 0x40u},\r
+ {0x8Cu, 0xC0u},\r
{0x8Du, 0x40u},\r
- {0x8Fu, 0x20u},\r
- {0xC0u, 0x0Cu},\r
- {0xC2u, 0x07u},\r
- {0xC4u, 0x05u},\r
- {0xCAu, 0x15u},\r
- {0xCCu, 0x02u},\r
- {0xCEu, 0x02u},\r
- {0xD0u, 0x03u},\r
- {0xD2u, 0x0Cu},\r
+ {0x8Eu, 0x02u},\r
+ {0xC0u, 0x05u},\r
+ {0xC2u, 0x0Fu},\r
+ {0xC4u, 0x06u},\r
+ {0xCAu, 0x0Du},\r
+ {0xCCu, 0x0Eu},\r
+ {0xCEu, 0x0Au},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x04u},\r
{0xD6u, 0x0Fu},\r
{0xD8u, 0x0Fu},\r
- {0xE4u, 0x0Cu},\r
- {0xE6u, 0x02u},\r
- {0x04u, 0x09u},\r
- {0x05u, 0x0Cu},\r
- {0x06u, 0x02u},\r
- {0x07u, 0x30u},\r
- {0x09u, 0x13u},\r
- {0x0Bu, 0x44u},\r
- {0x0Cu, 0x0Au},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x05u},\r
- {0x13u, 0x7Fu},\r
- {0x14u, 0x04u},\r
- {0x16u, 0x08u},\r
- {0x17u, 0x02u},\r
- {0x1Au, 0x07u},\r
- {0x1Du, 0x6Cu},\r
- {0x1Fu, 0x13u},\r
- {0x23u, 0x20u},\r
- {0x25u, 0x03u},\r
- {0x26u, 0x08u},\r
- {0x29u, 0x71u},\r
- {0x34u, 0x0Fu},\r
+ {0xE2u, 0x06u},\r
+ {0xE4u, 0x02u},\r
+ {0xE6u, 0x81u},\r
+ {0x02u, 0x0Eu},\r
+ {0x04u, 0x0Bu},\r
+ {0x06u, 0x10u},\r
+ {0x07u, 0x7Fu},\r
+ {0x09u, 0x8Cu},\r
+ {0x0Bu, 0x30u},\r
+ {0x11u, 0x71u},\r
+ {0x13u, 0x80u},\r
+ {0x14u, 0x08u},\r
+ {0x15u, 0x03u},\r
+ {0x19u, 0xECu},\r
+ {0x1Au, 0x03u},\r
+ {0x1Bu, 0x13u},\r
+ {0x1Eu, 0x1Fu},\r
+ {0x20u, 0x14u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x0Bu},\r
+ {0x23u, 0x80u},\r
+ {0x24u, 0x01u},\r
+ {0x26u, 0x04u},\r
+ {0x27u, 0x20u},\r
+ {0x2Au, 0x04u},\r
+ {0x2Bu, 0x02u},\r
+ {0x2Du, 0x93u},\r
+ {0x2Fu, 0x44u},\r
+ {0x30u, 0x1Fu},\r
+ {0x31u, 0x80u},\r
+ {0x33u, 0x7Fu},\r
+ {0x34u, 0x1Fu},\r
{0x37u, 0x7Fu},\r
- {0x56u, 0x08u},\r
+ {0x3Fu, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
{0x5Cu, 0x11u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x83u, 0x08u},\r
- {0x84u, 0x09u},\r
- {0x85u, 0x44u},\r
- {0x86u, 0x02u},\r
- {0x87u, 0x88u},\r
- {0x8Au, 0x07u},\r
- {0x8Bu, 0x07u},\r
- {0x8Cu, 0x40u},\r
- {0x8Eu, 0x80u},\r
- {0x8Fu, 0x80u},\r
- {0x90u, 0x20u},\r
- {0x94u, 0x10u},\r
- {0x97u, 0x70u},\r
- {0x99u, 0x99u},\r
- {0x9Au, 0x40u},\r
- {0x9Bu, 0x22u},\r
- {0x9Du, 0xAAu},\r
- {0x9Fu, 0x55u},\r
- {0xA0u, 0x0Au},\r
- {0xA2u, 0x05u},\r
- {0xA6u, 0x08u},\r
- {0xA8u, 0x04u},\r
- {0xAAu, 0x08u},\r
- {0xAEu, 0x80u},\r
- {0xB0u, 0x20u},\r
- {0xB2u, 0x0Fu},\r
- {0xB3u, 0xF0u},\r
- {0xB4u, 0x10u},\r
- {0xB5u, 0x0Fu},\r
- {0xB6u, 0xC0u},\r
- {0xBEu, 0x51u},\r
+ {0x82u, 0x04u},\r
+ {0x83u, 0x70u},\r
+ {0x85u, 0x99u},\r
+ {0x87u, 0x22u},\r
+ {0x8Bu, 0x80u},\r
+ {0x97u, 0x07u},\r
+ {0x99u, 0xAAu},\r
+ {0x9Au, 0x02u},\r
+ {0x9Bu, 0x55u},\r
+ {0xA5u, 0x44u},\r
+ {0xA7u, 0x88u},\r
+ {0xABu, 0x08u},\r
+ {0xACu, 0x01u},\r
+ {0xB1u, 0xF0u},\r
+ {0xB2u, 0x04u},\r
+ {0xB3u, 0x0Fu},\r
+ {0xB4u, 0x01u},\r
+ {0xB6u, 0x02u},\r
+ {0xBEu, 0x10u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDCu, 0x19u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x03u, 0x0Au},\r
- {0x04u, 0x04u},\r
- {0x07u, 0x01u},\r
- {0x08u, 0x0Au},\r
- {0x09u, 0x20u},\r
- {0x0Cu, 0x10u},\r
+ {0x03u, 0x40u},\r
+ {0x04u, 0x84u},\r
+ {0x05u, 0x41u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Du, 0x08u},\r
{0x0Eu, 0x08u},\r
- {0x0Fu, 0x10u},\r
- {0x12u, 0x82u},\r
- {0x13u, 0x14u},\r
- {0x17u, 0x08u},\r
- {0x19u, 0x40u},\r
- {0x1Au, 0x44u},\r
- {0x1Bu, 0x08u},\r
- {0x1Eu, 0x08u},\r
- {0x21u, 0x30u},\r
- {0x22u, 0x08u},\r
- {0x26u, 0x80u},\r
- {0x27u, 0x01u},\r
+ {0x13u, 0x40u},\r
+ {0x15u, 0x28u},\r
+ {0x17u, 0x02u},\r
+ {0x19u, 0x10u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Bu, 0x80u},\r
+ {0x1Cu, 0x04u},\r
+ {0x1Fu, 0x31u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0x05u},\r
+ {0x24u, 0x80u},\r
+ {0x27u, 0x12u},\r
+ {0x2Au, 0x20u},\r
+ {0x2Bu, 0x20u},\r
{0x2Cu, 0x20u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x80u},\r
- {0x32u, 0x98u},\r
- {0x35u, 0x06u},\r
- {0x36u, 0x80u},\r
- {0x39u, 0xA8u},\r
- {0x3Au, 0x02u},\r
- {0x3Cu, 0x88u},\r
- {0x3Fu, 0x10u},\r
- {0x5Au, 0x80u},\r
- {0x5Bu, 0x26u},\r
- {0x5Fu, 0x80u},\r
- {0x61u, 0x80u},\r
- {0x62u, 0x14u},\r
- {0x63u, 0xA0u},\r
- {0x64u, 0x01u},\r
- {0x67u, 0x02u},\r
- {0x83u, 0x30u},\r
- {0x85u, 0x40u},\r
- {0x87u, 0x03u},\r
- {0x88u, 0x10u},\r
- {0x8Au, 0x10u},\r
- {0x8Bu, 0x02u},\r
- {0x90u, 0xA0u},\r
- {0x91u, 0x84u},\r
- {0x93u, 0x44u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Fu, 0x49u},\r
+ {0x32u, 0x04u},\r
+ {0x33u, 0x10u},\r
+ {0x35u, 0x01u},\r
+ {0x36u, 0x04u},\r
+ {0x37u, 0x10u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x0Au},\r
+ {0x3Cu, 0x28u},\r
+ {0x42u, 0x08u},\r
+ {0x43u, 0x10u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x80u},\r
+ {0x5Bu, 0x20u},\r
+ {0x5Cu, 0x08u},\r
+ {0x5Eu, 0xA2u},\r
+ {0x60u, 0x22u},\r
+ {0x62u, 0x20u},\r
+ {0x63u, 0x18u},\r
+ {0x65u, 0x40u},\r
+ {0x6Du, 0x04u},\r
+ {0x6Eu, 0x08u},\r
+ {0x6Fu, 0x06u},\r
+ {0x81u, 0x20u},\r
+ {0x82u, 0x10u},\r
+ {0x87u, 0xB0u},\r
+ {0x88u, 0x04u},\r
+ {0x8Au, 0x04u},\r
+ {0x8Eu, 0x04u},\r
+ {0x8Fu, 0x14u},\r
+ {0x90u, 0x20u},\r
+ {0x91u, 0x31u},\r
+ {0x93u, 0x80u},\r
{0x95u, 0x08u},\r
- {0x96u, 0x4Cu},\r
- {0x97u, 0x02u},\r
- {0x99u, 0x26u},\r
- {0x9Au, 0x02u},\r
- {0x9Bu, 0x08u},\r
- {0x9Eu, 0x14u},\r
- {0x9Fu, 0x01u},\r
- {0xA0u, 0x60u},\r
- {0xA2u, 0x20u},\r
- {0xA3u, 0x80u},\r
- {0xA4u, 0x04u},\r
- {0xA5u, 0x88u},\r
- {0xA6u, 0x01u},\r
- {0xA7u, 0x40u},\r
- {0xABu, 0xC0u},\r
- {0xACu, 0x10u},\r
- {0xADu, 0x20u},\r
- {0xAFu, 0x04u},\r
+ {0x97u, 0x26u},\r
+ {0x9Au, 0xA2u},\r
+ {0x9Cu, 0x22u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Fu, 0x11u},\r
+ {0xA0u, 0xA6u},\r
+ {0xA1u, 0x28u},\r
+ {0xA2u, 0x51u},\r
+ {0xA3u, 0x08u},\r
+ {0xA6u, 0x08u},\r
+ {0xA7u, 0x04u},\r
+ {0xA9u, 0x80u},\r
+ {0xACu, 0x08u},\r
+ {0xADu, 0x40u},\r
+ {0xAEu, 0x01u},\r
{0xB0u, 0x80u},\r
- {0xB1u, 0x80u},\r
- {0xB7u, 0x20u},\r
- {0xC0u, 0xA7u},\r
- {0xC2u, 0x6Eu},\r
- {0xC4u, 0x2Fu},\r
- {0xCAu, 0xE0u},\r
- {0xCCu, 0xDEu},\r
- {0xCEu, 0x7Fu},\r
- {0xD6u, 0x1Fu},\r
- {0xD8u, 0x1Fu},\r
- {0xE0u, 0x02u},\r
- {0xE2u, 0x01u},\r
- {0xE4u, 0x01u},\r
- {0xE6u, 0x02u},\r
- {0xE8u, 0x0Cu},\r
- {0xECu, 0x0Cu},\r
- {0xEEu, 0x82u},\r
- {0x04u, 0x02u},\r
- {0x05u, 0x0Bu},\r
- {0x07u, 0x90u},\r
- {0x09u, 0x20u},\r
- {0x0Au, 0x04u},\r
- {0x0Bu, 0x03u},\r
- {0x0Cu, 0x02u},\r
- {0x0Fu, 0x04u},\r
- {0x12u, 0x20u},\r
+ {0xB1u, 0x21u},\r
+ {0xB6u, 0x01u},\r
+ {0xB7u, 0x28u},\r
+ {0xC0u, 0x38u},\r
+ {0xC2u, 0xE2u},\r
+ {0xC4u, 0x71u},\r
+ {0xCAu, 0xF6u},\r
+ {0xCCu, 0xE6u},\r
+ {0xCEu, 0x67u},\r
+ {0xD6u, 0xFEu},\r
+ {0xD8u, 0x1Eu},\r
+ {0xE2u, 0x42u},\r
+ {0xE4u, 0x0Au},\r
+ {0xE6u, 0x11u},\r
+ {0xE8u, 0x04u},\r
+ {0xEAu, 0x1Au},\r
+ {0xEEu, 0x08u},\r
+ {0x00u, 0x02u},\r
+ {0x01u, 0x08u},\r
+ {0x02u, 0x01u},\r
+ {0x05u, 0x01u},\r
+ {0x09u, 0x40u},\r
+ {0x0Bu, 0x84u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Du, 0x91u},\r
+ {0x0Eu, 0x10u},\r
+ {0x0Fu, 0x22u},\r
+ {0x10u, 0x02u},\r
+ {0x12u, 0x01u},\r
+ {0x14u, 0x02u},\r
{0x15u, 0x08u},\r
- {0x16u, 0x08u},\r
- {0x19u, 0x21u},\r
- {0x1Au, 0x10u},\r
- {0x1Bu, 0x44u},\r
- {0x1Cu, 0x02u},\r
- {0x1Du, 0x14u},\r
- {0x1Fu, 0xABu},\r
+ {0x16u, 0x01u},\r
+ {0x18u, 0x01u},\r
+ {0x19u, 0x02u},\r
+ {0x1Au, 0x0Au},\r
+ {0x1Bu, 0x05u},\r
+ {0x1Eu, 0x20u},\r
+ {0x1Fu, 0x70u},\r
{0x20u, 0x02u},\r
- {0x21u, 0x40u},\r
- {0x23u, 0xBFu},\r
- {0x26u, 0x01u},\r
- {0x28u, 0x14u},\r
- {0x2Au, 0x28u},\r
- {0x2Bu, 0x0Eu},\r
- {0x30u, 0x02u},\r
- {0x32u, 0x0Cu},\r
- {0x33u, 0x1Fu},\r
- {0x34u, 0x01u},\r
- {0x35u, 0xE0u},\r
- {0x36u, 0x30u},\r
- {0x38u, 0x02u},\r
- {0x3Bu, 0x20u},\r
- {0x3Eu, 0x45u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x15u},\r
+ {0x24u, 0x20u},\r
+ {0x25u, 0xA0u},\r
+ {0x26u, 0x40u},\r
+ {0x27u, 0x55u},\r
+ {0x29u, 0x08u},\r
+ {0x2Au, 0x40u},\r
+ {0x2Fu, 0x80u},\r
+ {0x30u, 0x18u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x60u},\r
+ {0x33u, 0x07u},\r
+ {0x34u, 0x03u},\r
+ {0x36u, 0x04u},\r
+ {0x37u, 0xF0u},\r
+ {0x39u, 0x02u},\r
+ {0x3Au, 0x20u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Eu, 0x05u},\r
+ {0x3Fu, 0x01u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x19u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x01u},\r
- {0x85u, 0x01u},\r
- {0x87u, 0x02u},\r
- {0x88u, 0x02u},\r
- {0x89u, 0x04u},\r
- {0x8Bu, 0x03u},\r
- {0x95u, 0x08u},\r
- {0x97u, 0x03u},\r
- {0x9Bu, 0x01u},\r
- {0x9Cu, 0x0Eu},\r
- {0x9Fu, 0x0Cu},\r
- {0xA4u, 0x08u},\r
- {0xAAu, 0x04u},\r
- {0xABu, 0x02u},\r
- {0xAEu, 0x0Eu},\r
- {0xB0u, 0x01u},\r
- {0xB1u, 0x0Fu},\r
- {0xB4u, 0x0Eu},\r
- {0xBEu, 0x10u},\r
+ {0x84u, 0x40u},\r
+ {0x86u, 0x1Fu},\r
+ {0x88u, 0x03u},\r
+ {0x8Au, 0x0Cu},\r
+ {0x8Cu, 0x06u},\r
+ {0x8Eu, 0x09u},\r
+ {0x92u, 0x70u},\r
+ {0x98u, 0x0Fu},\r
+ {0xA0u, 0x05u},\r
+ {0xA2u, 0x0Au},\r
+ {0xA3u, 0x01u},\r
+ {0xA4u, 0x10u},\r
+ {0xA6u, 0x2Fu},\r
+ {0xA8u, 0x20u},\r
+ {0xAAu, 0x4Fu},\r
+ {0xB0u, 0x7Fu},\r
+ {0xB1u, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x09u},\r
+ {0xDCu, 0x91u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x40u},\r
- {0x02u, 0x10u},\r
- {0x03u, 0x08u},\r
- {0x05u, 0x02u},\r
- {0x06u, 0x08u},\r
- {0x08u, 0x10u},\r
- {0x09u, 0x02u},\r
- {0x0Au, 0x11u},\r
- {0x0Du, 0x40u},\r
- {0x10u, 0x80u},\r
- {0x12u, 0x24u},\r
- {0x17u, 0x98u},\r
- {0x19u, 0x08u},\r
- {0x1Au, 0x88u},\r
- {0x1Bu, 0x40u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0x40u},\r
- {0x20u, 0x0Cu},\r
- {0x21u, 0x14u},\r
- {0x22u, 0x10u},\r
- {0x23u, 0x10u},\r
- {0x27u, 0x80u},\r
- {0x29u, 0x02u},\r
- {0x2Au, 0x20u},\r
- {0x2Cu, 0x08u},\r
- {0x31u, 0x04u},\r
- {0x32u, 0x90u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x88u},\r
- {0x38u, 0xA0u},\r
- {0x39u, 0x18u},\r
- {0x3Cu, 0x20u},\r
- {0x3Eu, 0x0Cu},\r
- {0x44u, 0x02u},\r
- {0x45u, 0x40u},\r
- {0x58u, 0x80u},\r
- {0x5Bu, 0x24u},\r
- {0x60u, 0x0Au},\r
- {0x61u, 0x08u},\r
- {0x82u, 0x40u},\r
- {0x83u, 0x04u},\r
- {0x86u, 0x02u},\r
- {0x88u, 0x04u},\r
- {0x89u, 0x14u},\r
- {0x8Du, 0x08u},\r
- {0x8Fu, 0x40u},\r
- {0x90u, 0xA0u},\r
- {0x91u, 0x04u},\r
- {0x93u, 0x40u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x08u},\r
- {0x96u, 0x28u},\r
- {0x97u, 0x10u},\r
- {0x98u, 0x11u},\r
- {0x99u, 0x26u},\r
- {0x9Cu, 0x0Au},\r
- {0x9Eu, 0x20u},\r
- {0xA1u, 0x20u},\r
- {0xA2u, 0xA0u},\r
- {0xA3u, 0x08u},\r
- {0xA4u, 0x04u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x02u},\r
- {0xAAu, 0x01u},\r
- {0xABu, 0x04u},\r
- {0xAEu, 0x08u},\r
- {0xAFu, 0x80u},\r
- {0xB6u, 0x40u},\r
- {0xC0u, 0x57u},\r
- {0xC2u, 0x8Fu},\r
- {0xC4u, 0xEEu},\r
- {0xCAu, 0x25u},\r
- {0xCCu, 0x7Eu},\r
- {0xCEu, 0x6Eu},\r
- {0xD6u, 0x0Eu},\r
- {0xD8u, 0x0Eu},\r
- {0xE0u, 0x02u},\r
- {0xE2u, 0x41u},\r
- {0xE8u, 0x08u},\r
- {0xEAu, 0x07u},\r
- {0xEEu, 0x41u},\r
- {0x00u, 0x0Du},\r
- {0x04u, 0x0Du},\r
- {0x07u, 0xFFu},\r
- {0x08u, 0x0Du},\r
- {0x0Bu, 0xFFu},\r
- {0x0Du, 0x33u},\r
- {0x0Fu, 0xCCu},\r
- {0x10u, 0x02u},\r
- {0x11u, 0x55u},\r
- {0x12u, 0x0Du},\r
- {0x13u, 0xAAu},\r
- {0x15u, 0x69u},\r
- {0x16u, 0x80u},\r
- {0x17u, 0x96u},\r
- {0x18u, 0x01u},\r
- {0x19u, 0x0Fu},\r
- {0x1Au, 0x32u},\r
- {0x1Bu, 0xF0u},\r
- {0x1Du, 0xFFu},\r
- {0x1Eu, 0x10u},\r
- {0x20u, 0x0Du},\r
- {0x23u, 0xFFu},\r
- {0x24u, 0x62u},\r
- {0x26u, 0x08u},\r
- {0x28u, 0x02u},\r
- {0x29u, 0xFFu},\r
- {0x2Au, 0x54u},\r
- {0x2Cu, 0x0Du},\r
- {0x30u, 0x0Fu},\r
+ {0x01u, 0x40u},\r
+ {0x03u, 0x80u},\r
+ {0x04u, 0xA4u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x16u},\r
+ {0x0Eu, 0x88u},\r
+ {0x10u, 0x14u},\r
+ {0x12u, 0x40u},\r
+ {0x15u, 0x08u},\r
+ {0x17u, 0x12u},\r
+ {0x19u, 0x01u},\r
+ {0x1Au, 0xA4u},\r
+ {0x1Bu, 0x90u},\r
+ {0x1Eu, 0x80u},\r
+ {0x1Fu, 0x02u},\r
+ {0x20u, 0x20u},\r
+ {0x21u, 0x04u},\r
+ {0x22u, 0x80u},\r
+ {0x23u, 0x80u},\r
+ {0x25u, 0x01u},\r
+ {0x27u, 0x40u},\r
+ {0x28u, 0x40u},\r
+ {0x2Au, 0x88u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Fu, 0x80u},\r
+ {0x30u, 0x08u},\r
+ {0x31u, 0x20u},\r
{0x32u, 0x80u},\r
- {0x35u, 0xFFu},\r
- {0x36u, 0x70u},\r
- {0x3Au, 0x02u},\r
- {0x3Bu, 0x20u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Cu, 0x10u},\r
- {0x5Fu, 0x01u},\r
- {0x80u, 0xFFu},\r
- {0x84u, 0x30u},\r
- {0x86u, 0xC0u},\r
- {0x87u, 0x80u},\r
- {0x88u, 0x0Fu},\r
+ {0x39u, 0x04u},\r
+ {0x3Bu, 0xA2u},\r
+ {0x59u, 0x64u},\r
+ {0x5Au, 0x01u},\r
+ {0x62u, 0x48u},\r
+ {0x63u, 0x44u},\r
+ {0x69u, 0x40u},\r
+ {0x81u, 0x04u},\r
+ {0x83u, 0x80u},\r
+ {0x84u, 0x14u},\r
+ {0x86u, 0x80u},\r
{0x89u, 0x44u},\r
- {0x8Au, 0xF0u},\r
- {0x8Bu, 0x88u},\r
- {0x8Cu, 0xFFu},\r
- {0x8Fu, 0x08u},\r
- {0x90u, 0x50u},\r
- {0x92u, 0xA0u},\r
- {0x93u, 0x07u},\r
- {0x94u, 0x09u},\r
- {0x96u, 0x06u},\r
- {0x97u, 0x70u},\r
- {0x98u, 0x05u},\r
- {0x99u, 0x99u},\r
- {0x9Au, 0x0Au},\r
- {0x9Bu, 0x22u},\r
- {0x9Du, 0xAAu},\r
- {0x9Fu, 0x55u},\r
- {0xA4u, 0x03u},\r
- {0xA6u, 0x0Cu},\r
- {0xAAu, 0xFFu},\r
- {0xACu, 0x90u},\r
- {0xAEu, 0x60u},\r
- {0xB0u, 0xFFu},\r
- {0xB1u, 0x0Fu},\r
- {0xB3u, 0xF0u},\r
- {0xBEu, 0x01u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x10u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x01u, 0x80u},\r
- {0x02u, 0x44u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x28u},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x14u},\r
- {0x09u, 0x02u},\r
- {0x0Cu, 0x08u},\r
- {0x0Eu, 0x46u},\r
- {0x10u, 0x20u},\r
- {0x11u, 0x10u},\r
- {0x12u, 0x01u},\r
- {0x15u, 0x41u},\r
- {0x17u, 0x18u},\r
- {0x18u, 0x40u},\r
- {0x1Eu, 0x62u},\r
- {0x21u, 0x08u},\r
- {0x22u, 0x01u},\r
- {0x26u, 0x20u},\r
- {0x2Du, 0x02u},\r
- {0x2Eu, 0x20u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x91u},\r
- {0x34u, 0x09u},\r
- {0x36u, 0xA0u},\r
- {0x39u, 0x04u},\r
- {0x3Bu, 0x50u},\r
- {0x3Cu, 0x08u},\r
- {0x3Du, 0x80u},\r
- {0x3Fu, 0x10u},\r
- {0x58u, 0x80u},\r
- {0x59u, 0x22u},\r
- {0x5Au, 0x08u},\r
- {0x63u, 0x02u},\r
- {0x80u, 0x80u},\r
- {0x85u, 0x10u},\r
- {0x88u, 0x20u},\r
- {0x89u, 0x08u},\r
- {0x8Au, 0x01u},\r
- {0x8Bu, 0x01u},\r
- {0x8Eu, 0x01u},\r
- {0x91u, 0x14u},\r
- {0x92u, 0x20u},\r
- {0x93u, 0x50u},\r
- {0x94u, 0x40u},\r
- {0x95u, 0x80u},\r
- {0x96u, 0x15u},\r
- {0x98u, 0x19u},\r
- {0x99u, 0x32u},\r
- {0x9Au, 0x20u},\r
- {0x9Eu, 0x14u},\r
- {0x9Fu, 0x18u},\r
- {0xA0u, 0x04u},\r
- {0xA1u, 0x40u},\r
- {0xA2u, 0x80u},\r
- {0xA4u, 0x98u},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0x12u},\r
- {0xAAu, 0x60u},\r
- {0xABu, 0x20u},\r
- {0xACu, 0x80u},\r
- {0xB1u, 0x08u},\r
- {0xB5u, 0x20u},\r
- {0xB7u, 0x08u},\r
- {0xC0u, 0x7Fu},\r
- {0xC2u, 0xFEu},\r
- {0xC4u, 0xF7u},\r
- {0xCAu, 0xA0u},\r
- {0xCCu, 0xFFu},\r
- {0xCEu, 0x7Eu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x08u},\r
- {0xE2u, 0x58u},\r
- {0xE6u, 0x01u},\r
- {0xEAu, 0x05u},\r
- {0xEEu, 0x02u},\r
- {0x39u, 0x80u},\r
- {0x3Fu, 0x40u},\r
- {0x59u, 0x04u},\r
- {0x5Fu, 0x01u},\r
- {0x24u, 0x02u},\r
- {0x7Au, 0x30u},\r
- {0x80u, 0x14u},\r
- {0x88u, 0x20u},\r
- {0x89u, 0x10u},\r
- {0x8Au, 0x08u},\r
- {0x8Cu, 0x01u},\r
- {0x90u, 0x10u},\r
- {0x91u, 0x02u},\r
- {0x94u, 0x08u},\r
- {0x95u, 0x01u},\r
- {0x97u, 0x01u},\r
- {0x98u, 0x28u},\r
- {0x9Au, 0x22u},\r
+ {0x8Bu, 0x40u},\r
+ {0x90u, 0x04u},\r
+ {0x91u, 0x15u},\r
+ {0x92u, 0x12u},\r
+ {0x93u, 0x30u},\r
+ {0x95u, 0x08u},\r
+ {0x96u, 0x20u},\r
+ {0x97u, 0x44u},\r
+ {0x98u, 0x42u},\r
+ {0x99u, 0x20u},\r
+ {0x9Au, 0x9Au},\r
{0x9Bu, 0x10u},\r
- {0x9Du, 0x0Bu},\r
- {0x9Eu, 0x18u},\r
- {0xA2u, 0x62u},\r
- {0xA4u, 0x80u},\r
- {0xABu, 0x02u},\r
+ {0x9Du, 0x01u},\r
+ {0x9Fu, 0x41u},\r
+ {0xA0u, 0x02u},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x24u},\r
+ {0xA4u, 0x10u},\r
+ {0xA6u, 0x08u},\r
+ {0xA8u, 0x08u},\r
+ {0xA9u, 0x02u},\r
+ {0xACu, 0x40u},\r
+ {0xAEu, 0x10u},\r
+ {0xAFu, 0x02u},\r
+ {0xB1u, 0x80u},\r
{0xB2u, 0x04u},\r
- {0xB6u, 0x01u},\r
- {0xB7u, 0x10u},\r
- {0xE0u, 0x24u},\r
- {0xE2u, 0xC8u},\r
- {0xE4u, 0x20u},\r
- {0xE8u, 0x10u},\r
- {0xEAu, 0x01u},\r
- {0xECu, 0x60u},\r
- {0xEEu, 0x02u},\r
- {0x00u, 0x04u},\r
- {0x02u, 0x08u},\r
- {0x04u, 0x02u},\r
- {0x06u, 0x01u},\r
- {0x07u, 0x20u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x04u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x08u},\r
- {0x0Cu, 0x02u},\r
- {0x0Du, 0x03u},\r
+ {0xC0u, 0xE9u},\r
+ {0xC2u, 0x5Fu},\r
+ {0xC4u, 0x7Eu},\r
+ {0xCAu, 0x8Fu},\r
+ {0xCCu, 0x0Eu},\r
+ {0xCEu, 0x0Fu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE2u, 0x18u},\r
+ {0xE4u, 0x08u},\r
+ {0xE6u, 0x23u},\r
+ {0xEAu, 0x03u},\r
+ {0xEEu, 0x08u},\r
+ {0x03u, 0x02u},\r
+ {0x05u, 0x01u},\r
+ {0x06u, 0x0Cu},\r
+ {0x09u, 0x10u},\r
+ {0x0Bu, 0x28u},\r
+ {0x0Du, 0x07u},\r
{0x0Eu, 0x01u},\r
- {0x0Fu, 0x0Cu},\r
- {0x11u, 0x02u},\r
- {0x12u, 0x20u},\r
- {0x13u, 0x01u},\r
- {0x14u, 0x02u},\r
- {0x16u, 0x01u},\r
- {0x1Au, 0x10u},\r
+ {0x11u, 0x08u},\r
+ {0x14u, 0x28u},\r
+ {0x16u, 0x13u},\r
+ {0x17u, 0x07u},\r
+ {0x18u, 0x60u},\r
+ {0x19u, 0x18u},\r
+ {0x1Bu, 0x20u},\r
+ {0x1Cu, 0x14u},\r
{0x1Du, 0x08u},\r
- {0x1Fu, 0x04u},\r
- {0x21u, 0x01u},\r
- {0x22u, 0x08u},\r
- {0x23u, 0x02u},\r
- {0x24u, 0x02u},\r
- {0x26u, 0x01u},\r
- {0x27u, 0x10u},\r
- {0x2Au, 0x04u},\r
- {0x2Cu, 0x10u},\r
- {0x2Eu, 0x20u},\r
- {0x30u, 0x30u},\r
- {0x31u, 0x20u},\r
- {0x32u, 0x03u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x0Cu},\r
- {0x35u, 0x0Fu},\r
- {0x3Au, 0x08u},\r
- {0x3Eu, 0x11u},\r
+ {0x1Eu, 0x43u},\r
+ {0x1Fu, 0x30u},\r
+ {0x22u, 0x82u},\r
+ {0x23u, 0x08u},\r
+ {0x25u, 0x10u},\r
+ {0x27u, 0x28u},\r
+ {0x28u, 0x11u},\r
+ {0x29u, 0x04u},\r
+ {0x2Au, 0x22u},\r
+ {0x32u, 0x0Fu},\r
+ {0x34u, 0x70u},\r
+ {0x35u, 0x07u},\r
+ {0x36u, 0x80u},\r
+ {0x37u, 0x38u},\r
+ {0x38u, 0x20u},\r
+ {0x3Bu, 0x80u},\r
{0x3Fu, 0x10u},\r
- {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
- {0x5Du, 0x90u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x60u},\r
- {0x83u, 0x90u},\r
- {0x84u, 0x03u},\r
- {0x85u, 0x03u},\r
- {0x86u, 0x0Cu},\r
- {0x87u, 0x0Cu},\r
- {0x88u, 0x06u},\r
- {0x89u, 0x06u},\r
- {0x8Au, 0x09u},\r
- {0x8Bu, 0x09u},\r
+ {0x80u, 0x33u},\r
+ {0x82u, 0xCCu},\r
+ {0x83u, 0xFFu},\r
+ {0x84u, 0xFFu},\r
+ {0x87u, 0xFFu},\r
+ {0x8Au, 0xFFu},\r
+ {0x8Bu, 0xFFu},\r
{0x8Cu, 0x0Fu},\r
- {0x92u, 0x70u},\r
- {0x95u, 0x05u},\r
- {0x97u, 0x0Au},\r
+ {0x8Du, 0x0Fu},\r
+ {0x8Eu, 0xF0u},\r
+ {0x8Fu, 0xF0u},\r
+ {0x90u, 0xFFu},\r
+ {0x96u, 0xFFu},\r
+ {0x9Du, 0xFFu},\r
+ {0xA1u, 0x55u},\r
+ {0xA2u, 0xFFu},\r
+ {0xA3u, 0xAAu},\r
+ {0xA4u, 0x96u},\r
+ {0xA5u, 0xFFu},\r
+ {0xA6u, 0x69u},\r
+ {0xA8u, 0x55u},\r
+ {0xA9u, 0x33u},\r
+ {0xAAu, 0xAAu},\r
+ {0xABu, 0xCCu},\r
+ {0xADu, 0x69u},\r
+ {0xAFu, 0x96u},\r
+ {0xB0u, 0xFFu},\r
+ {0xB7u, 0xFFu},\r
+ {0xBAu, 0x02u},\r
+ {0xBBu, 0x80u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x20u},\r
+ {0x01u, 0x08u},\r
+ {0x02u, 0x40u},\r
+ {0x03u, 0x12u},\r
+ {0x05u, 0x44u},\r
+ {0x0Au, 0x80u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x22u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0x20u},\r
+ {0x13u, 0x10u},\r
+ {0x16u, 0x88u},\r
+ {0x17u, 0x20u},\r
+ {0x18u, 0x80u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Du, 0x44u},\r
+ {0x1Eu, 0x08u},\r
+ {0x21u, 0x40u},\r
+ {0x23u, 0x02u},\r
+ {0x25u, 0x10u},\r
+ {0x26u, 0x80u},\r
+ {0x27u, 0x01u},\r
+ {0x28u, 0x02u},\r
+ {0x29u, 0x08u},\r
+ {0x2Au, 0x12u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Du, 0x01u},\r
+ {0x2Fu, 0x10u},\r
+ {0x32u, 0x40u},\r
+ {0x35u, 0x05u},\r
+ {0x36u, 0x80u},\r
+ {0x37u, 0x10u},\r
+ {0x39u, 0x89u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Cu, 0x60u},\r
+ {0x3Eu, 0x08u},\r
+ {0x3Fu, 0x02u},\r
+ {0x5Bu, 0x40u},\r
+ {0x62u, 0x40u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Fu, 0x01u},\r
+ {0x91u, 0x19u},\r
+ {0x92u, 0x80u},\r
+ {0x93u, 0x74u},\r
+ {0x94u, 0xA0u},\r
+ {0x97u, 0x02u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x12u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Fu, 0x03u},\r
+ {0xA0u, 0x12u},\r
+ {0xA2u, 0x28u},\r
+ {0xA7u, 0x08u},\r
+ {0xA8u, 0x08u},\r
+ {0xABu, 0x10u},\r
+ {0xAEu, 0x01u},\r
+ {0xB2u, 0x01u},\r
+ {0xB3u, 0x02u},\r
+ {0xB5u, 0x01u},\r
+ {0xC0u, 0xAFu},\r
+ {0xC2u, 0xECu},\r
+ {0xC4u, 0x5Eu},\r
+ {0xCAu, 0xEFu},\r
+ {0xCCu, 0xF8u},\r
+ {0xCEu, 0xFFu},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x0Du},\r
+ {0xEAu, 0x0Du},\r
+ {0xECu, 0x01u},\r
+ {0x00u, 0x0Fu},\r
+ {0x01u, 0x03u},\r
+ {0x02u, 0xF0u},\r
+ {0x03u, 0x0Cu},\r
+ {0x04u, 0x30u},\r
+ {0x05u, 0xFFu},\r
+ {0x06u, 0xC0u},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Cu, 0x03u},\r
+ {0x0Du, 0x05u},\r
+ {0x0Eu, 0x0Cu},\r
+ {0x0Fu, 0x0Au},\r
+ {0x10u, 0x05u},\r
+ {0x12u, 0x0Au},\r
+ {0x14u, 0x09u},\r
+ {0x15u, 0x50u},\r
+ {0x16u, 0x06u},\r
+ {0x17u, 0xA0u},\r
+ {0x19u, 0x30u},\r
+ {0x1Au, 0xFFu},\r
+ {0x1Bu, 0xC0u},\r
+ {0x1Du, 0x0Fu},\r
+ {0x1Eu, 0xFFu},\r
+ {0x1Fu, 0xF0u},\r
+ {0x20u, 0x90u},\r
+ {0x21u, 0x90u},\r
+ {0x22u, 0x60u},\r
+ {0x23u, 0x60u},\r
+ {0x24u, 0x50u},\r
+ {0x26u, 0xA0u},\r
+ {0x27u, 0xFFu},\r
+ {0x29u, 0x09u},\r
+ {0x2Bu, 0x06u},\r
+ {0x2Du, 0xFFu},\r
+ {0x36u, 0xFFu},\r
+ {0x37u, 0xFFu},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x40u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0x06u},\r
+ {0x82u, 0x18u},\r
+ {0x84u, 0x02u},\r
+ {0x85u, 0x02u},\r
+ {0x86u, 0x04u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Eu, 0x20u},\r
+ {0x90u, 0x40u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x01u},\r
+ {0x94u, 0x04u},\r
+ {0x96u, 0x02u},\r
{0x98u, 0x20u},\r
- {0x99u, 0x50u},\r
- {0x9Au, 0x4Fu},\r
- {0x9Bu, 0xA0u},\r
- {0x9Cu, 0x05u},\r
- {0x9Du, 0x0Fu},\r
- {0x9Eu, 0x0Au},\r
- {0x9Fu, 0xF0u},\r
- {0xA1u, 0x30u},\r
- {0xA3u, 0xC0u},\r
+ {0x9Au, 0x40u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Eu, 0x20u},\r
+ {0xA0u, 0x10u},\r
+ {0xA2u, 0x08u},\r
{0xA8u, 0x40u},\r
- {0xAAu, 0x1Fu},\r
- {0xACu, 0x10u},\r
- {0xAEu, 0x2Fu},\r
- {0xB0u, 0x7Fu},\r
+ {0xA9u, 0x08u},\r
+ {0xAAu, 0x21u},\r
+ {0xACu, 0x08u},\r
+ {0xAEu, 0x10u},\r
+ {0xAFu, 0x04u},\r
+ {0xB0u, 0x1Eu},\r
+ {0xB1u, 0x04u},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x60u},\r
+ {0xB5u, 0x02u},\r
+ {0xB6u, 0x01u},\r
+ {0xB7u, 0x08u},\r
+ {0xBAu, 0x20u},\r
+ {0xBEu, 0x01u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x99u},\r
+ {0xDDu, 0x90u},\r
+ {0xDFu, 0x01u},\r
+ {0x01u, 0x80u},\r
+ {0x02u, 0x40u},\r
+ {0x03u, 0x20u},\r
+ {0x04u, 0x22u},\r
+ {0x06u, 0x4Au},\r
+ {0x07u, 0x90u},\r
+ {0x08u, 0x06u},\r
+ {0x0Au, 0x0Au},\r
+ {0x0Cu, 0x18u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x01u},\r
+ {0x0Fu, 0x6Au},\r
+ {0x10u, 0x80u},\r
+ {0x12u, 0x09u},\r
+ {0x14u, 0x40u},\r
+ {0x17u, 0x05u},\r
+ {0x19u, 0xA0u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Bu, 0x03u},\r
+ {0x1Fu, 0x80u},\r
+ {0x21u, 0x40u},\r
+ {0x22u, 0x09u},\r
+ {0x23u, 0x04u},\r
+ {0x26u, 0x40u},\r
+ {0x28u, 0x02u},\r
+ {0x29u, 0x20u},\r
+ {0x2Cu, 0x58u},\r
+ {0x2Fu, 0x02u},\r
+ {0x32u, 0x01u},\r
+ {0x37u, 0x94u},\r
+ {0x39u, 0x08u},\r
+ {0x3Eu, 0x0Au},\r
+ {0x3Fu, 0x40u},\r
+ {0x58u, 0x80u},\r
+ {0x60u, 0x02u},\r
+ {0x81u, 0x40u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Fu, 0x80u},\r
+ {0x90u, 0x22u},\r
+ {0x91u, 0x08u},\r
+ {0x96u, 0x09u},\r
+ {0x98u, 0x04u},\r
+ {0x9Au, 0x03u},\r
+ {0x9Bu, 0x15u},\r
+ {0xA0u, 0x80u},\r
+ {0xA3u, 0x24u},\r
+ {0xA5u, 0x02u},\r
+ {0xA7u, 0x12u},\r
+ {0xA8u, 0x02u},\r
+ {0xA9u, 0x08u},\r
+ {0xB0u, 0x80u},\r
+ {0xB1u, 0x80u},\r
+ {0xB7u, 0x40u},\r
+ {0xC0u, 0xFDu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0x3Bu},\r
+ {0xCAu, 0xFCu},\r
+ {0xCCu, 0x71u},\r
+ {0xCEu, 0xD2u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x6Cu},\r
+ {0xE8u, 0x20u},\r
+ {0xEAu, 0x0Cu},\r
+ {0xECu, 0xC0u},\r
+ {0x00u, 0x01u},\r
+ {0x01u, 0x0Fu},\r
+ {0x02u, 0x02u},\r
+ {0x03u, 0xF0u},\r
+ {0x06u, 0x01u},\r
+ {0x09u, 0xFFu},\r
+ {0x0Du, 0x60u},\r
+ {0x0Eu, 0x02u},\r
+ {0x0Fu, 0x90u},\r
+ {0x11u, 0x05u},\r
+ {0x13u, 0x0Au},\r
+ {0x15u, 0x50u},\r
+ {0x17u, 0xA0u},\r
+ {0x19u, 0x30u},\r
+ {0x1Bu, 0xC0u},\r
+ {0x21u, 0x03u},\r
+ {0x23u, 0x0Cu},\r
+ {0x25u, 0x06u},\r
+ {0x27u, 0x09u},\r
+ {0x2Bu, 0xFFu},\r
+ {0x2Fu, 0xFFu},\r
+ {0x33u, 0xFFu},\r
+ {0x34u, 0x03u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x04u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0x10u},\r
+ {0x81u, 0x0Fu},\r
+ {0x82u, 0x20u},\r
+ {0x83u, 0xF0u},\r
+ {0x85u, 0x50u},\r
+ {0x87u, 0xA0u},\r
+ {0x88u, 0x0Au},\r
+ {0x8Au, 0x05u},\r
+ {0x91u, 0x05u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x0Au},\r
+ {0x96u, 0x10u},\r
+ {0x99u, 0x03u},\r
+ {0x9Au, 0x07u},\r
+ {0x9Bu, 0x0Cu},\r
+ {0x9Du, 0x06u},\r
+ {0x9Eu, 0x08u},\r
+ {0x9Fu, 0x09u},\r
+ {0xA0u, 0x09u},\r
+ {0xA2u, 0x02u},\r
+ {0xA4u, 0x04u},\r
+ {0xA5u, 0x60u},\r
+ {0xA6u, 0x08u},\r
+ {0xA7u, 0x90u},\r
+ {0xADu, 0x30u},\r
+ {0xAFu, 0xC0u},\r
+ {0xB2u, 0x30u},\r
{0xB3u, 0xFFu},\r
+ {0xB4u, 0x0Fu},\r
+ {0xBEu, 0x04u},\r
{0xBFu, 0x04u},\r
{0xD4u, 0x01u},\r
{0xD8u, 0x04u},\r
{0xDCu, 0x01u},\r
{0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x10u},\r
- {0x01u, 0x08u},\r
- {0x02u, 0x42u},\r
- {0x03u, 0x80u},\r
- {0x04u, 0x08u},\r
- {0x06u, 0x02u},\r
+ {0x00u, 0x81u},\r
+ {0x03u, 0x20u},\r
+ {0x04u, 0x02u},\r
{0x07u, 0x08u},\r
- {0x08u, 0x22u},\r
- {0x09u, 0x28u},\r
- {0x0Cu, 0x20u},\r
- {0x0Eu, 0x42u},\r
- {0x10u, 0x08u},\r
- {0x11u, 0x41u},\r
- {0x13u, 0x04u},\r
- {0x14u, 0x05u},\r
- {0x18u, 0x90u},\r
- {0x1Au, 0x08u},\r
- {0x1Bu, 0x02u},\r
- {0x1Eu, 0x40u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Du, 0x40u},\r
+ {0x0Eu, 0x28u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x40u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Cu, 0x10u},\r
+ {0x1Eu, 0x08u},\r
+ {0x1Fu, 0x20u},\r
{0x21u, 0x08u},\r
- {0x22u, 0x22u},\r
- {0x27u, 0x10u},\r
- {0x29u, 0x18u},\r
- {0x2Au, 0x11u},\r
- {0x2Cu, 0x08u},\r
- {0x2Du, 0x02u},\r
- {0x2Eu, 0x20u},\r
- {0x30u, 0x80u},\r
- {0x32u, 0x01u},\r
- {0x35u, 0x10u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x04u},\r
- {0x39u, 0x20u},\r
- {0x3Au, 0x40u},\r
- {0x3Bu, 0x04u},\r
- {0x3Eu, 0x08u},\r
- {0x3Fu, 0x21u},\r
- {0x58u, 0x80u},\r
- {0x5Bu, 0x20u},\r
- {0x5Eu, 0x40u},\r
+ {0x24u, 0x20u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Bu, 0x16u},\r
+ {0x2Cu, 0x22u},\r
+ {0x31u, 0x02u},\r
+ {0x33u, 0x14u},\r
+ {0x34u, 0x80u},\r
+ {0x36u, 0x11u},\r
+ {0x38u, 0x23u},\r
+ {0x39u, 0x42u},\r
+ {0x3Cu, 0x09u},\r
+ {0x58u, 0x01u},\r
+ {0x59u, 0x50u},\r
+ {0x5Au, 0x08u},\r
+ {0x5Du, 0x80u},\r
{0x60u, 0x02u},\r
- {0x62u, 0x80u},\r
- {0x63u, 0x04u},\r
- {0x69u, 0x40u},\r
- {0x7Au, 0x40u},\r
- {0x7Bu, 0x80u},\r
- {0x85u, 0x10u},\r
- {0x88u, 0x05u},\r
- {0x8Bu, 0x40u},\r
- {0x91u, 0x02u},\r
- {0x92u, 0x02u},\r
- {0x94u, 0x80u},\r
- {0x96u, 0x0Cu},\r
- {0x97u, 0x40u},\r
- {0x98u, 0x88u},\r
- {0x9Au, 0x22u},\r
- {0x9Bu, 0x2Cu},\r
- {0x9Cu, 0x06u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x10u},\r
- {0xA0u, 0x20u},\r
- {0xA1u, 0x20u},\r
- {0xA2u, 0x41u},\r
- {0xA4u, 0x80u},\r
- {0xA6u, 0x80u},\r
- {0xA7u, 0x02u},\r
- {0xAAu, 0x40u},\r
+ {0x6Cu, 0x80u},\r
+ {0x6Du, 0x40u},\r
+ {0x6Fu, 0x15u},\r
+ {0x74u, 0x76u},\r
+ {0x76u, 0x01u},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x01u},\r
+ {0x86u, 0x10u},\r
+ {0x89u, 0x01u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Cu, 0x10u},\r
+ {0x90u, 0x02u},\r
+ {0x91u, 0x8Cu},\r
+ {0x94u, 0x20u},\r
+ {0x95u, 0x01u},\r
+ {0x96u, 0x05u},\r
+ {0x98u, 0x05u},\r
+ {0x99u, 0x50u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x15u},\r
+ {0xA2u, 0x01u},\r
+ {0xA3u, 0x04u},\r
+ {0xA4u, 0x84u},\r
+ {0xA5u, 0x02u},\r
+ {0xA7u, 0x50u},\r
+ {0xA9u, 0x10u},\r
{0xACu, 0x80u},\r
- {0xAEu, 0x20u},\r
- {0xB6u, 0x40u},\r
- {0xC0u, 0xEFu},\r
- {0xC2u, 0xDEu},\r
- {0xC4u, 0xCFu},\r
- {0xCAu, 0x83u},\r
- {0xCCu, 0x79u},\r
- {0xCEu, 0xEEu},\r
- {0xD6u, 0x1Cu},\r
- {0xD8u, 0x0Cu},\r
- {0xE0u, 0x20u},\r
- {0xE2u, 0x01u},\r
- {0xE4u, 0xE0u},\r
- {0xEAu, 0x17u},\r
- {0xEEu, 0x42u},\r
- {0x00u, 0x08u},\r
- {0x01u, 0x33u},\r
- {0x02u, 0x16u},\r
- {0x03u, 0xCCu},\r
- {0x05u, 0xFFu},\r
- {0x06u, 0x40u},\r
- {0x09u, 0x0Fu},\r
- {0x0Au, 0x04u},\r
- {0x0Bu, 0xF0u},\r
- {0x0Eu, 0x07u},\r
- {0x0Fu, 0xFFu},\r
- {0x10u, 0x07u},\r
- {0x12u, 0x18u},\r
- {0x15u, 0x96u},\r
- {0x16u, 0x07u},\r
- {0x17u, 0x69u},\r
- {0x18u, 0x0Cu},\r
- {0x1Au, 0x13u},\r
- {0x1Bu, 0xFFu},\r
- {0x1Cu, 0x20u},\r
- {0x1Eu, 0x40u},\r
- {0x20u, 0x01u},\r
- {0x25u, 0x55u},\r
- {0x26u, 0x20u},\r
- {0x27u, 0xAAu},\r
- {0x28u, 0x0Fu},\r
- {0x2Au, 0x10u},\r
- {0x2Bu, 0xFFu},\r
- {0x2Cu, 0x01u},\r
- {0x2Du, 0xFFu},\r
- {0x2Eu, 0x02u},\r
- {0x30u, 0x1Fu},\r
- {0x34u, 0x60u},\r
- {0x35u, 0xFFu},\r
- {0x3Au, 0x02u},\r
+ {0xAEu, 0x80u},\r
+ {0xAFu, 0x04u},\r
+ {0xB1u, 0x08u},\r
+ {0xC0u, 0x5Du},\r
+ {0xC2u, 0xF0u},\r
+ {0xC4u, 0x30u},\r
+ {0xCAu, 0x5Fu},\r
+ {0xCCu, 0xB7u},\r
+ {0xCEu, 0xCDu},\r
+ {0xD6u, 0x1Fu},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x90u},\r
+ {0xE4u, 0x80u},\r
+ {0xE6u, 0x21u},\r
+ {0xEEu, 0xA2u},\r
+ {0x00u, 0x0Fu},\r
+ {0x02u, 0xF0u},\r
+ {0x04u, 0x30u},\r
+ {0x05u, 0x0Fu},\r
+ {0x06u, 0xC0u},\r
+ {0x07u, 0x10u},\r
+ {0x09u, 0x07u},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Bu, 0x18u},\r
+ {0x0Fu, 0x07u},\r
+ {0x10u, 0x05u},\r
+ {0x12u, 0x0Au},\r
+ {0x14u, 0x06u},\r
+ {0x15u, 0x0Cu},\r
+ {0x16u, 0x09u},\r
+ {0x17u, 0x13u},\r
+ {0x1Au, 0xFFu},\r
+ {0x1Bu, 0x04u},\r
+ {0x1Cu, 0xFFu},\r
+ {0x20u, 0x60u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x90u},\r
+ {0x23u, 0x16u},\r
+ {0x24u, 0x50u},\r
+ {0x25u, 0x01u},\r
+ {0x26u, 0xA0u},\r
+ {0x27u, 0x02u},\r
+ {0x29u, 0x01u},\r
+ {0x2Cu, 0x03u},\r
+ {0x2Eu, 0x0Cu},\r
+ {0x2Fu, 0x07u},\r
+ {0x32u, 0xFFu},\r
+ {0x35u, 0x1Fu},\r
{0x3Bu, 0x20u},\r
- {0x3Eu, 0x10u},\r
+ {0x3Eu, 0x04u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
+ {0x5Cu, 0x10u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x10u},\r
- {0x85u, 0x02u},\r
- {0x87u, 0x01u},\r
- {0x8Cu, 0x10u},\r
- {0x90u, 0x10u},\r
- {0x92u, 0x60u},\r
+ {0x80u, 0x02u},\r
+ {0x81u, 0x02u},\r
+ {0x82u, 0x01u},\r
+ {0x83u, 0x04u},\r
+ {0x84u, 0x01u},\r
+ {0x86u, 0x02u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Eu, 0x01u},\r
+ {0x92u, 0x04u},\r
{0x93u, 0x04u},\r
- {0x98u, 0x3Au},\r
- {0x99u, 0x01u},\r
- {0x9Au, 0x45u},\r
- {0x9Bu, 0x02u},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0x07u},\r
+ {0x94u, 0x02u},\r
+ {0x96u, 0x01u},\r
+ {0x97u, 0x08u},\r
+ {0x98u, 0x02u},\r
+ {0x9Au, 0x01u},\r
{0x9Fu, 0x01u},\r
- {0xA1u, 0x02u},\r
- {0xA3u, 0x01u},\r
- {0xA6u, 0x08u},\r
- {0xA8u, 0x24u},\r
- {0xAAu, 0x58u},\r
- {0xACu, 0x29u},\r
- {0xADu, 0x02u},\r
- {0xAEu, 0x52u},\r
- {0xAFu, 0x01u},\r
- {0xB0u, 0x70u},\r
- {0xB3u, 0x04u},\r
- {0xB5u, 0x03u},\r
- {0xB6u, 0x0Fu},\r
- {0xBAu, 0x02u},\r
- {0xBBu, 0x20u},\r
+ {0xA7u, 0x02u},\r
+ {0xACu, 0x04u},\r
+ {0xAEu, 0x08u},\r
+ {0xB1u, 0x08u},\r
+ {0xB2u, 0x0Cu},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x03u},\r
+ {0xB5u, 0x06u},\r
+ {0xBAu, 0x20u},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x10u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x91u},\r
+ {0xDCu, 0x99u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x02u},\r
- {0x03u, 0x02u},\r
- {0x04u, 0x80u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x90u},\r
- {0x0Au, 0x82u},\r
- {0x0Bu, 0x06u},\r
- {0x0Eu, 0x61u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x04u},\r
- {0x11u, 0x04u},\r
- {0x13u, 0x40u},\r
- {0x14u, 0x14u},\r
- {0x15u, 0x01u},\r
+ {0x00u, 0x84u},\r
+ {0x02u, 0x80u},\r
+ {0x03u, 0x04u},\r
+ {0x04u, 0x22u},\r
+ {0x07u, 0x10u},\r
+ {0x09u, 0x0Au},\r
+ {0x0Au, 0x08u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x01u},\r
+ {0x0Fu, 0x28u},\r
+ {0x12u, 0x01u},\r
+ {0x15u, 0x40u},\r
{0x16u, 0x02u},\r
- {0x17u, 0x04u},\r
- {0x1Au, 0x82u},\r
- {0x1Eu, 0x40u},\r
- {0x1Fu, 0x10u},\r
+ {0x17u, 0x05u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x10u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Fu, 0x04u},\r
+ {0x20u, 0x80u},\r
{0x21u, 0x28u},\r
{0x25u, 0x10u},\r
- {0x27u, 0x08u},\r
- {0x29u, 0x82u},\r
- {0x2Cu, 0x04u},\r
- {0x2Eu, 0x04u},\r
- {0x2Fu, 0x02u},\r
- {0x31u, 0x21u},\r
- {0x32u, 0x80u},\r
- {0x35u, 0x04u},\r
- {0x36u, 0x10u},\r
- {0x38u, 0x08u},\r
- {0x3Du, 0x20u},\r
- {0x3Eu, 0x80u},\r
- {0x3Fu, 0x45u},\r
- {0x59u, 0x40u},\r
- {0x63u, 0x01u},\r
- {0x6Cu, 0x02u},\r
- {0x6Eu, 0x80u},\r
- {0x81u, 0x04u},\r
- {0x84u, 0x20u},\r
+ {0x2Bu, 0x10u},\r
+ {0x2Cu, 0x01u},\r
+ {0x2Du, 0xA9u},\r
+ {0x32u, 0x84u},\r
+ {0x33u, 0x01u},\r
+ {0x34u, 0x20u},\r
+ {0x37u, 0x08u},\r
+ {0x38u, 0x02u},\r
+ {0x3Au, 0x01u},\r
+ {0x3Du, 0x24u},\r
+ {0x3Fu, 0x80u},\r
+ {0x58u, 0x80u},\r
+ {0x5Eu, 0x40u},\r
+ {0x62u, 0x80u},\r
+ {0x66u, 0x80u},\r
+ {0x82u, 0x50u},\r
+ {0x85u, 0x24u},\r
{0x86u, 0x04u},\r
- {0x87u, 0x04u},\r
- {0x88u, 0x0Au},\r
- {0x89u, 0x41u},\r
- {0x8Au, 0x01u},\r
- {0x8Fu, 0x20u},\r
- {0x90u, 0x08u},\r
- {0x91u, 0x05u},\r
- {0x94u, 0x80u},\r
- {0x97u, 0x62u},\r
- {0x98u, 0x18u},\r
- {0x99u, 0x92u},\r
- {0x9Au, 0x02u},\r
- {0x9Cu, 0x06u},\r
- {0x9Du, 0x01u},\r
- {0xA0u, 0x01u},\r
- {0xA2u, 0x11u},\r
- {0xA4u, 0xAAu},\r
- {0xA5u, 0x08u},\r
- {0xA9u, 0x10u},\r
- {0xABu, 0x50u},\r
- {0xADu, 0x11u},\r
- {0xAEu, 0x01u},\r
- {0xB2u, 0x08u},\r
- {0xB3u, 0x08u},\r
- {0xB5u, 0x40u},\r
+ {0x8Au, 0x42u},\r
+ {0x8Du, 0x08u},\r
+ {0x8Eu, 0x20u},\r
+ {0x8Fu, 0x0Cu},\r
+ {0x90u, 0x02u},\r
+ {0x91u, 0x88u},\r
+ {0x95u, 0x44u},\r
+ {0x96u, 0x04u},\r
+ {0x98u, 0x24u},\r
+ {0x99u, 0xE0u},\r
+ {0x9Eu, 0xE0u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA2u, 0x01u},\r
+ {0xA4u, 0x84u},\r
+ {0xA6u, 0x40u},\r
+ {0xA9u, 0x01u},\r
+ {0xADu, 0x40u},\r
+ {0xAFu, 0x03u},\r
+ {0xB1u, 0x84u},\r
+ {0xB3u, 0x20u},\r
+ {0xB4u, 0x30u},\r
{0xB6u, 0x40u},\r
- {0xC0u, 0xF9u},\r
- {0xC2u, 0xFBu},\r
- {0xC4u, 0xF7u},\r
- {0xCAu, 0x79u},\r
- {0xCCu, 0x6Du},\r
- {0xCEu, 0xF2u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x08u},\r
- {0xE0u, 0x20u},\r
- {0xE2u, 0x01u},\r
- {0xE4u, 0x28u},\r
- {0xE6u, 0x82u},\r
- {0xE8u, 0x60u},\r
+ {0xC0u, 0x7Fu},\r
+ {0xC2u, 0xFEu},\r
+ {0xC4u, 0xB1u},\r
+ {0xCAu, 0xF2u},\r
+ {0xCCu, 0x6Bu},\r
+ {0xCEu, 0x71u},\r
+ {0xD6u, 0x18u},\r
+ {0xD8u, 0x18u},\r
+ {0xE0u, 0xC9u},\r
+ {0xE2u, 0x06u},\r
+ {0xE4u, 0x40u},\r
+ {0xE6u, 0x81u},\r
+ {0xE8u, 0x40u},\r
{0xECu, 0x80u},\r
- {0xEEu, 0x01u},\r
- {0x02u, 0x02u},\r
- {0x03u, 0x04u},\r
- {0x09u, 0x02u},\r
- {0x0Bu, 0x01u},\r
- {0x0Du, 0x01u},\r
- {0x0Fu, 0x02u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x01u},\r
- {0x13u, 0x08u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x04u},\r
- {0x17u, 0x01u},\r
- {0x1Au, 0x08u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x04u},\r
+ {0x02u, 0x08u},\r
+ {0x03u, 0x08u},\r
+ {0x06u, 0x02u},\r
+ {0x08u, 0x08u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Eu, 0x04u},\r
+ {0x0Fu, 0x01u},\r
+ {0x10u, 0x01u},\r
+ {0x12u, 0x02u},\r
+ {0x17u, 0x02u},\r
+ {0x18u, 0x08u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Bu, 0x10u},\r
{0x1Fu, 0x08u},\r
- {0x21u, 0x02u},\r
- {0x23u, 0x01u},\r
- {0x29u, 0x02u},\r
- {0x2Bu, 0x01u},\r
- {0x30u, 0x08u},\r
- {0x31u, 0x03u},\r
- {0x32u, 0x04u},\r
- {0x34u, 0x01u},\r
- {0x36u, 0x02u},\r
+ {0x24u, 0x08u},\r
+ {0x26u, 0x04u},\r
+ {0x2Bu, 0x04u},\r
+ {0x2Eu, 0x01u},\r
+ {0x31u, 0x02u},\r
+ {0x32u, 0x03u},\r
+ {0x33u, 0x10u},\r
+ {0x35u, 0x01u},\r
+ {0x36u, 0x0Cu},\r
{0x37u, 0x0Cu},\r
- {0x3Bu, 0x02u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Eu, 0x04u},\r
{0x3Fu, 0x40u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x5Cu, 0x99u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x55u},\r
- {0x86u, 0xAAu},\r
- {0x88u, 0x33u},\r
- {0x8Au, 0xCCu},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0xFFu},\r
- {0x8Du, 0x19u},\r
- {0x8Fu, 0x02u},\r
- {0x92u, 0xFFu},\r
- {0x93u, 0x10u},\r
- {0x94u, 0x69u},\r
- {0x96u, 0x96u},\r
- {0x97u, 0x10u},\r
- {0x98u, 0xFFu},\r
- {0x9Bu, 0x07u},\r
- {0x9Cu, 0x0Fu},\r
- {0x9Eu, 0xF0u},\r
- {0xA5u, 0x1Au},\r
- {0xA6u, 0xFFu},\r
- {0xA7u, 0x05u},\r
- {0xA9u, 0x14u},\r
- {0xAAu, 0xFFu},\r
- {0xABu, 0x08u},\r
- {0xB1u, 0x10u},\r
- {0xB3u, 0x0Fu},\r
- {0xB6u, 0xFFu},\r
- {0xBAu, 0x80u},\r
- {0xBFu, 0x01u},\r
+ {0x80u, 0x10u},\r
+ {0x83u, 0x10u},\r
+ {0x84u, 0x0Au},\r
+ {0x86u, 0x05u},\r
+ {0x87u, 0x02u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Fu, 0x08u},\r
+ {0x93u, 0x01u},\r
+ {0x96u, 0x07u},\r
+ {0x9Au, 0x08u},\r
+ {0xA0u, 0x09u},\r
+ {0xA2u, 0x02u},\r
+ {0xA4u, 0x04u},\r
+ {0xA6u, 0x08u},\r
+ {0xADu, 0x01u},\r
+ {0xAFu, 0x02u},\r
+ {0xB0u, 0x10u},\r
+ {0xB1u, 0x04u},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB3u, 0x10u},\r
+ {0xB5u, 0x03u},\r
+ {0xB7u, 0x08u},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x10u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDCu, 0x91u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x02u},\r
- {0x04u, 0x80u},\r
- {0x06u, 0x08u},\r
- {0x07u, 0x11u},\r
- {0x08u, 0x02u},\r
- {0x09u, 0x08u},\r
- {0x0Au, 0x04u},\r
- {0x0Cu, 0x28u},\r
- {0x0Eu, 0x02u},\r
- {0x0Fu, 0x40u},\r
- {0x14u, 0x24u},\r
- {0x18u, 0x08u},\r
- {0x19u, 0x82u},\r
- {0x1Au, 0x04u},\r
- {0x1Bu, 0x04u},\r
- {0x1Eu, 0x02u},\r
- {0x20u, 0x40u},\r
- {0x22u, 0x41u},\r
- {0x25u, 0x01u},\r
- {0x27u, 0x20u},\r
- {0x29u, 0x01u},\r
- {0x2Bu, 0x04u},\r
- {0x2Cu, 0x24u},\r
- {0x30u, 0x82u},\r
- {0x31u, 0x08u},\r
- {0x34u, 0x10u},\r
- {0x37u, 0x29u},\r
- {0x38u, 0x40u},\r
- {0x3Au, 0x10u},\r
- {0x3Bu, 0x02u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x40u},\r
- {0x45u, 0x01u},\r
- {0x46u, 0x40u},\r
- {0x59u, 0x20u},\r
- {0x5Bu, 0x40u},\r
- {0x5Du, 0x51u},\r
- {0x5Fu, 0x08u},\r
- {0x60u, 0x08u},\r
- {0x62u, 0x90u},\r
- {0x66u, 0x40u},\r
- {0x81u, 0x20u},\r
- {0x82u, 0x02u},\r
- {0x84u, 0x21u},\r
- {0x86u, 0x10u},\r
- {0x87u, 0x10u},\r
- {0x89u, 0x04u},\r
- {0x8Eu, 0x90u},\r
- {0xC0u, 0xE8u},\r
- {0xC2u, 0xFEu},\r
- {0xC4u, 0x60u},\r
- {0xCAu, 0x65u},\r
- {0xCCu, 0xEBu},\r
- {0xCEu, 0x3Du},\r
- {0xD6u, 0xFCu},\r
- {0xD8u, 0x1Cu},\r
- {0xE0u, 0x20u},\r
- {0xE2u, 0x40u},\r
- {0xE4u, 0x10u},\r
- {0xE6u, 0x01u},\r
- {0x02u, 0x02u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x02u},\r
- {0x1Eu, 0x01u},\r
- {0x32u, 0x03u},\r
+ {0x00u, 0xA1u},\r
+ {0x03u, 0x10u},\r
+ {0x06u, 0xA0u},\r
+ {0x09u, 0x20u},\r
+ {0x0Au, 0x40u},\r
+ {0x0Cu, 0x04u},\r
+ {0x0Eu, 0x10u},\r
+ {0x0Fu, 0x04u},\r
+ {0x11u, 0x40u},\r
+ {0x12u, 0x20u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x40u},\r
+ {0x18u, 0x21u},\r
+ {0x19u, 0x40u},\r
+ {0x1Eu, 0x10u},\r
+ {0x1Fu, 0x0Au},\r
+ {0x20u, 0xA0u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x60u},\r
+ {0x23u, 0x40u},\r
+ {0x24u, 0x50u},\r
+ {0x25u, 0x41u},\r
+ {0x27u, 0x08u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Eu, 0x40u},\r
+ {0x30u, 0x80u},\r
+ {0x31u, 0x28u},\r
{0x35u, 0x01u},\r
- {0x3Eu, 0x04u},\r
- {0x40u, 0x36u},\r
- {0x41u, 0x02u},\r
- {0x42u, 0x10u},\r
- {0x44u, 0x05u},\r
- {0x45u, 0xDEu},\r
- {0x46u, 0xF0u},\r
- {0x47u, 0xCBu},\r
- {0x48u, 0x3Bu},\r
- {0x49u, 0xFFu},\r
- {0x4Au, 0xFFu},\r
- {0x4Bu, 0xFFu},\r
- {0x4Cu, 0x22u},\r
- {0x4Eu, 0xF0u},\r
- {0x4Fu, 0x08u},\r
- {0x50u, 0x04u},\r
- {0x54u, 0x40u},\r
- {0x56u, 0x04u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Au, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x90u},\r
- {0x5Fu, 0x01u},\r
- {0x62u, 0xC0u},\r
- {0x64u, 0x40u},\r
- {0x65u, 0x01u},\r
- {0x66u, 0x10u},\r
- {0x67u, 0x11u},\r
- {0x68u, 0xC0u},\r
- {0x69u, 0x01u},\r
- {0x6Bu, 0x11u},\r
- {0x6Cu, 0x40u},\r
- {0x6Du, 0x01u},\r
+ {0x36u, 0x01u},\r
+ {0x38u, 0x02u},\r
+ {0x3Bu, 0x40u},\r
+ {0x3Cu, 0x58u},\r
+ {0x3Fu, 0x02u},\r
+ {0x58u, 0x40u},\r
+ {0x5Bu, 0x20u},\r
+ {0x5Eu, 0x80u},\r
+ {0x61u, 0x20u},\r
+ {0x63u, 0x02u},\r
+ {0x67u, 0x02u},\r
+ {0x6Cu, 0x01u},\r
{0x6Eu, 0x40u},\r
- {0x6Fu, 0x01u},\r
- {0x80u, 0x31u},\r
- {0x81u, 0xC1u},\r
- {0x84u, 0x01u},\r
- {0x85u, 0x07u},\r
- {0x86u, 0x30u},\r
- {0x87u, 0x18u},\r
- {0x88u, 0x43u},\r
- {0x89u, 0xC0u},\r
- {0x8Au, 0x3Cu},\r
- {0x8Cu, 0x31u},\r
- {0x8Du, 0x01u},\r
- {0x8Fu, 0xC0u},\r
- {0x90u, 0x30u},\r
- {0x92u, 0x01u},\r
- {0x93u, 0x40u},\r
- {0x94u, 0x06u},\r
- {0x95u, 0x22u},\r
- {0x96u, 0xB9u},\r
- {0x97u, 0x08u},\r
- {0x98u, 0x05u},\r
- {0x99u, 0x08u},\r
- {0x9Au, 0x4Au},\r
- {0x9Bu, 0x21u},\r
- {0x9Cu, 0xC0u},\r
- {0x9Du, 0xC1u},\r
- {0xA0u, 0x20u},\r
- {0xA1u, 0x04u},\r
- {0xA4u, 0x11u},\r
- {0xA5u, 0xC1u},\r
- {0xA6u, 0x20u},\r
- {0xA9u, 0x10u},\r
- {0xACu, 0x12u},\r
- {0xADu, 0x01u},\r
+ {0x81u, 0x01u},\r
+ {0x83u, 0x08u},\r
+ {0x85u, 0x20u},\r
+ {0x86u, 0x04u},\r
+ {0x88u, 0x40u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Cu, 0x10u},\r
+ {0x8Du, 0x40u},\r
+ {0x8Fu, 0x01u},\r
+ {0xC0u, 0x3Fu},\r
+ {0xC2u, 0x6Au},\r
+ {0xC4u, 0x35u},\r
+ {0xCAu, 0x14u},\r
+ {0xCCu, 0x8Eu},\r
+ {0xCEu, 0xF9u},\r
+ {0xD6u, 0x1Cu},\r
+ {0xD8u, 0x1Cu},\r
+ {0xE2u, 0x50u},\r
+ {0xE4u, 0x30u},\r
+ {0x81u, 0x01u},\r
+ {0x82u, 0xFFu},\r
+ {0x85u, 0x04u},\r
+ {0x86u, 0x60u},\r
+ {0x88u, 0x80u},\r
+ {0x89u, 0x22u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Cu, 0x90u},\r
+ {0x8Du, 0x10u},\r
+ {0x8Eu, 0x40u},\r
+ {0x91u, 0x01u},\r
+ {0x92u, 0x9Fu},\r
+ {0x94u, 0x7Fu},\r
+ {0x95u, 0x07u},\r
+ {0x96u, 0x80u},\r
+ {0x97u, 0x18u},\r
+ {0x98u, 0xC0u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x04u},\r
+ {0x9Du, 0x40u},\r
+ {0xA0u, 0xC0u},\r
+ {0xA1u, 0x01u},\r
+ {0xA2u, 0x02u},\r
+ {0xA4u, 0xC0u},\r
+ {0xA5u, 0x01u},\r
+ {0xA6u, 0x08u},\r
+ {0xA8u, 0x1Fu},\r
+ {0xA9u, 0x40u},\r
+ {0xAAu, 0x20u},\r
+ {0xACu, 0xC0u},\r
+ {0xADu, 0x08u},\r
{0xAEu, 0x01u},\r
- {0xB0u, 0x03u},\r
- {0xB1u, 0x3Fu},\r
+ {0xAFu, 0x21u},\r
+ {0xB2u, 0xFFu},\r
{0xB3u, 0x40u},\r
- {0xB4u, 0x3Cu},\r
- {0xB6u, 0xC4u},\r
- {0xB7u, 0x80u},\r
- {0xB8u, 0x80u},\r
- {0xB9u, 0x02u},\r
- {0xBAu, 0x02u},\r
- {0xBFu, 0x45u},\r
+ {0xB7u, 0x3Fu},\r
+ {0xB9u, 0x88u},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x40u},\r
{0xD6u, 0x02u},\r
{0xD7u, 0x24u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x02u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x08u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x02u},\r
- {0x07u, 0x40u},\r
- {0x0Au, 0x02u},\r
- {0x0Cu, 0x02u},\r
- {0x0Du, 0x40u},\r
- {0x0Eu, 0x26u},\r
- {0x14u, 0x01u},\r
- {0x15u, 0x06u},\r
- {0x19u, 0x08u},\r
- {0x1Eu, 0x06u},\r
- {0x1Fu, 0x11u},\r
- {0x21u, 0x10u},\r
- {0x24u, 0x90u},\r
- {0x25u, 0x80u},\r
- {0x27u, 0x02u},\r
- {0x2Cu, 0x09u},\r
- {0x2Du, 0x04u},\r
- {0x2Fu, 0x41u},\r
- {0x35u, 0x02u},\r
- {0x36u, 0x14u},\r
- {0x37u, 0x40u},\r
- {0x39u, 0x10u},\r
- {0x3Du, 0xA0u},\r
- {0x3Eu, 0x06u},\r
- {0x41u, 0x88u},\r
- {0x42u, 0x04u},\r
- {0x49u, 0x86u},\r
- {0x4Au, 0x84u},\r
- {0x50u, 0x08u},\r
- {0x51u, 0x01u},\r
+ {0x01u, 0x46u},\r
+ {0x02u, 0x08u},\r
+ {0x05u, 0x02u},\r
+ {0x07u, 0x19u},\r
+ {0x09u, 0x81u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Cu, 0x20u},\r
+ {0x0Eu, 0x80u},\r
+ {0x0Fu, 0x20u},\r
+ {0x10u, 0x08u},\r
+ {0x12u, 0x21u},\r
+ {0x15u, 0x01u},\r
+ {0x16u, 0x02u},\r
+ {0x17u, 0x24u},\r
+ {0x19u, 0x82u},\r
+ {0x1Au, 0x44u},\r
+ {0x1Bu, 0x11u},\r
+ {0x1Eu, 0x10u},\r
+ {0x21u, 0x04u},\r
+ {0x22u, 0x2Bu},\r
+ {0x23u, 0x3Cu},\r
+ {0x25u, 0x04u},\r
+ {0x26u, 0x80u},\r
+ {0x27u, 0x10u},\r
+ {0x2Bu, 0x91u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Eu, 0x52u},\r
+ {0x30u, 0x28u},\r
+ {0x31u, 0x80u},\r
+ {0x36u, 0xA8u},\r
+ {0x37u, 0x01u},\r
+ {0x39u, 0x40u},\r
+ {0x3Au, 0x01u},\r
+ {0x3Bu, 0x14u},\r
+ {0x3Cu, 0x80u},\r
+ {0x3Du, 0x0Au},\r
+ {0x3Eu, 0x80u},\r
+ {0x3Fu, 0x20u},\r
+ {0x41u, 0x04u},\r
+ {0x42u, 0x44u},\r
+ {0x48u, 0x40u},\r
+ {0x49u, 0x08u},\r
+ {0x4Au, 0x46u},\r
+ {0x51u, 0x80u},\r
{0x52u, 0x10u},\r
- {0x60u, 0x10u},\r
- {0x61u, 0x01u},\r
- {0x62u, 0x90u},\r
- {0x67u, 0x04u},\r
- {0x6Cu, 0x16u},\r
- {0x6Du, 0xE4u},\r
- {0x6Fu, 0x40u},\r
- {0x76u, 0x02u},\r
- {0x84u, 0x01u},\r
- {0x85u, 0x80u},\r
- {0x89u, 0x10u},\r
- {0x8Au, 0x06u},\r
- {0x8Cu, 0x04u},\r
- {0x92u, 0x02u},\r
- {0x93u, 0x84u},\r
- {0x94u, 0xACu},\r
- {0x95u, 0xE6u},\r
- {0x96u, 0x0Cu},\r
- {0x97u, 0x22u},\r
- {0x99u, 0x10u},\r
- {0x9Du, 0x0Du},\r
- {0x9Eu, 0x02u},\r
- {0x9Fu, 0x42u},\r
- {0xA1u, 0x08u},\r
- {0xA2u, 0x14u},\r
- {0xA3u, 0x08u},\r
- {0xA4u, 0x08u},\r
- {0xA5u, 0x50u},\r
- {0xA6u, 0x02u},\r
- {0xA8u, 0x02u},\r
- {0xA9u, 0x82u},\r
- {0xADu, 0x29u},\r
- {0xB0u, 0x04u},\r
- {0xB2u, 0x90u},\r
- {0xB3u, 0x08u},\r
- {0xB4u, 0x40u},\r
- {0xC0u, 0xFAu},\r
- {0xC2u, 0xF1u},\r
- {0xC4u, 0xB0u},\r
- {0xCAu, 0xF0u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0xF4u},\r
- {0xD0u, 0x0Eu},\r
+ {0x53u, 0x01u},\r
+ {0x67u, 0x08u},\r
+ {0x6Cu, 0x28u},\r
+ {0x6Du, 0x47u},\r
+ {0x6Fu, 0x85u},\r
+ {0x76u, 0x03u},\r
+ {0x88u, 0x10u},\r
+ {0x89u, 0x80u},\r
+ {0x8Eu, 0x04u},\r
+ {0x93u, 0x08u},\r
+ {0x96u, 0x42u},\r
+ {0x97u, 0x02u},\r
+ {0x9Cu, 0x10u},\r
+ {0x9Du, 0x88u},\r
+ {0x9Eu, 0x92u},\r
+ {0x9Fu, 0x21u},\r
+ {0xA4u, 0x28u},\r
+ {0xA5u, 0x01u},\r
+ {0xA7u, 0x11u},\r
+ {0xAAu, 0x01u},\r
+ {0xADu, 0x01u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0x7Bu},\r
+ {0xC4u, 0xF7u},\r
+ {0xCAu, 0xFBu},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0xFFu},\r
+ {0xD0u, 0x07u},\r
{0xD2u, 0x0Cu},\r
- {0xD8u, 0x2Fu},\r
- {0xE6u, 0x08u},\r
- {0xEAu, 0x05u},\r
- {0x00u, 0x34u},\r
- {0x01u, 0xC0u},\r
- {0x03u, 0x01u},\r
- {0x05u, 0x1Fu},\r
- {0x06u, 0x34u},\r
- {0x07u, 0x20u},\r
- {0x08u, 0x14u},\r
- {0x09u, 0xC0u},\r
- {0x0Au, 0x20u},\r
+ {0xD8u, 0x20u},\r
+ {0xE0u, 0x40u},\r
+ {0xECu, 0x02u},\r
+ {0x01u, 0x1Du},\r
+ {0x04u, 0x04u},\r
+ {0x06u, 0x03u},\r
+ {0x09u, 0x02u},\r
{0x0Bu, 0x08u},\r
- {0x0Cu, 0x80u},\r
- {0x0Du, 0x90u},\r
- {0x0Fu, 0x40u},\r
- {0x10u, 0x20u},\r
- {0x12u, 0x02u},\r
- {0x13u, 0x60u},\r
- {0x14u, 0x4Bu},\r
- {0x15u, 0x7Fu},\r
- {0x16u, 0x30u},\r
- {0x17u, 0x80u},\r
- {0x18u, 0x3Fu},\r
- {0x1Au, 0x40u},\r
- {0x1Bu, 0xFFu},\r
- {0x1Cu, 0x14u},\r
- {0x1Du, 0xC0u},\r
- {0x1Fu, 0x02u},\r
- {0x20u, 0x34u},\r
- {0x24u, 0x08u},\r
- {0x25u, 0xC0u},\r
- {0x26u, 0x75u},\r
- {0x27u, 0x04u},\r
- {0x28u, 0x80u},\r
- {0x2Bu, 0x9Fu},\r
- {0x2Cu, 0x34u},\r
- {0x2Du, 0x80u},\r
- {0x32u, 0x78u},\r
- {0x33u, 0xFFu},\r
- {0x34u, 0x07u},\r
- {0x36u, 0x80u},\r
- {0x38u, 0x88u},\r
- {0x3Au, 0x30u},\r
- {0x3Fu, 0x04u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Fu, 0x04u},\r
+ {0x11u, 0x0Du},\r
+ {0x13u, 0x10u},\r
+ {0x14u, 0x6Du},\r
+ {0x16u, 0x02u},\r
+ {0x19u, 0x01u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Cu, 0x0Bu},\r
+ {0x1Du, 0x02u},\r
+ {0x1Eu, 0x54u},\r
+ {0x1Fu, 0x0Du},\r
+ {0x21u, 0x1Du},\r
+ {0x25u, 0x1Du},\r
+ {0x28u, 0x09u},\r
+ {0x29u, 0x1Du},\r
+ {0x2Au, 0x36u},\r
+ {0x2Fu, 0x10u},\r
+ {0x31u, 0x0Fu},\r
+ {0x32u, 0x07u},\r
+ {0x34u, 0x70u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0x08u},\r
+ {0x3Au, 0x08u},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x10u},\r
+ {0x54u, 0x40u},\r
+ {0x56u, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
{0x5Fu, 0x01u},\r
{0x82u, 0xFFu},\r
- {0x84u, 0x30u},\r
- {0x86u, 0xC0u},\r
+ {0x83u, 0x70u},\r
+ {0x84u, 0xFFu},\r
+ {0x85u, 0x99u},\r
+ {0x87u, 0x22u},\r
{0x88u, 0x0Fu},\r
- {0x89u, 0x11u},\r
{0x8Au, 0xF0u},\r
- {0x8Bu, 0x0Eu},\r
- {0x8Cu, 0x60u},\r
- {0x8Eu, 0x90u},\r
- {0x90u, 0x50u},\r
- {0x92u, 0xA0u},\r
- {0x94u, 0x06u},\r
- {0x95u, 0x1Bu},\r
- {0x96u, 0x09u},\r
- {0x97u, 0x04u},\r
- {0x98u, 0x05u},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0x0Au},\r
- {0x9Bu, 0x03u},\r
- {0xA4u, 0x03u},\r
- {0xA6u, 0x0Cu},\r
- {0xA9u, 0x15u},\r
- {0xAAu, 0xFFu},\r
- {0xABu, 0x0Au},\r
- {0xACu, 0xFFu},\r
- {0xB1u, 0x08u},\r
- {0xB5u, 0x07u},\r
- {0xB6u, 0xFFu},\r
- {0xB7u, 0x10u},\r
- {0xBBu, 0x20u},\r
- {0xBEu, 0x40u},\r
- {0xBFu, 0x41u},\r
+ {0x8Bu, 0x80u},\r
+ {0x90u, 0xFFu},\r
+ {0x93u, 0x08u},\r
+ {0x96u, 0xFFu},\r
+ {0x97u, 0x07u},\r
+ {0x98u, 0x33u},\r
+ {0x99u, 0xAAu},\r
+ {0x9Au, 0xCCu},\r
+ {0x9Bu, 0x55u},\r
+ {0x9Eu, 0xFFu},\r
+ {0xA8u, 0x69u},\r
+ {0xA9u, 0x44u},\r
+ {0xAAu, 0x96u},\r
+ {0xABu, 0x88u},\r
+ {0xACu, 0x55u},\r
+ {0xAEu, 0xAAu},\r
+ {0xB1u, 0xF0u},\r
+ {0xB2u, 0xFFu},\r
+ {0xB3u, 0x0Fu},\r
+ {0xBAu, 0x08u},\r
{0xD4u, 0x09u},\r
{0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x44u},\r
- {0x02u, 0xC1u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0xA8u},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x54u},\r
- {0x09u, 0x02u},\r
- {0x0Bu, 0x02u},\r
- {0x0Cu, 0x40u},\r
- {0x0Du, 0x01u},\r
- {0x0Eu, 0x24u},\r
- {0x10u, 0x22u},\r
- {0x11u, 0x10u},\r
- {0x15u, 0x41u},\r
- {0x17u, 0x28u},\r
- {0x1Au, 0x01u},\r
- {0x1Cu, 0x20u},\r
- {0x1Du, 0x18u},\r
- {0x1Eu, 0x2Au},\r
- {0x1Fu, 0x40u},\r
- {0x22u, 0x10u},\r
- {0x23u, 0x85u},\r
- {0x27u, 0x20u},\r
- {0x29u, 0x10u},\r
- {0x2Cu, 0x08u},\r
- {0x2Du, 0x04u},\r
+ {0x01u, 0x01u},\r
+ {0x03u, 0x18u},\r
+ {0x05u, 0x04u},\r
+ {0x08u, 0x04u},\r
+ {0x0Au, 0x81u},\r
+ {0x0Bu, 0x24u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x22u},\r
+ {0x12u, 0x08u},\r
+ {0x13u, 0x40u},\r
+ {0x17u, 0x20u},\r
+ {0x18u, 0x20u},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Du, 0x84u},\r
+ {0x1Eu, 0x08u},\r
+ {0x1Fu, 0x04u},\r
+ {0x21u, 0x09u},\r
+ {0x25u, 0x20u},\r
+ {0x27u, 0x80u},\r
+ {0x28u, 0x04u},\r
+ {0x2Cu, 0x28u},\r
+ {0x2Eu, 0x02u},\r
{0x2Fu, 0x01u},\r
+ {0x30u, 0x02u},\r
{0x31u, 0x08u},\r
- {0x32u, 0x10u},\r
- {0x36u, 0x15u},\r
- {0x37u, 0x58u},\r
- {0x3Bu, 0x20u},\r
- {0x3Du, 0xA1u},\r
- {0x3Eu, 0x06u},\r
- {0x59u, 0x24u},\r
- {0x5Bu, 0x82u},\r
- {0x63u, 0x41u},\r
- {0x81u, 0x01u},\r
- {0x87u, 0x40u},\r
- {0x91u, 0x10u},\r
- {0x92u, 0x02u},\r
- {0x94u, 0x2Cu},\r
- {0x95u, 0xE1u},\r
- {0x96u, 0x0Du},\r
- {0x98u, 0x10u},\r
- {0x9Cu, 0x04u},\r
- {0x9Du, 0x80u},\r
- {0x9Eu, 0x51u},\r
- {0x9Fu, 0x58u},\r
- {0xA0u, 0x20u},\r
- {0xA4u, 0x18u},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0x02u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x80u},\r
- {0xA9u, 0x10u},\r
- {0xAAu, 0x30u},\r
- {0xC0u, 0xFFu},\r
- {0xC2u, 0xFEu},\r
- {0xC4u, 0xF7u},\r
- {0xCAu, 0x74u},\r
- {0xCCu, 0xF6u},\r
- {0xCEu, 0xF4u},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x09u},\r
- {0xEAu, 0x07u},\r
- {0xECu, 0x01u},\r
- {0xEEu, 0x10u},\r
- {0x38u, 0x02u},\r
- {0x39u, 0x01u},\r
- {0x91u, 0x22u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x01u},\r
- {0x98u, 0x08u},\r
- {0x9Au, 0x22u},\r
+ {0x33u, 0x10u},\r
+ {0x37u, 0xA1u},\r
+ {0x39u, 0x1Au},\r
+ {0x3Du, 0x02u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x20u},\r
+ {0x45u, 0x20u},\r
+ {0x46u, 0x08u},\r
+ {0x58u, 0x10u},\r
+ {0x59u, 0x88u},\r
+ {0x5Au, 0x02u},\r
+ {0x60u, 0x80u},\r
+ {0x61u, 0x80u},\r
+ {0x66u, 0x19u},\r
+ {0x67u, 0x02u},\r
+ {0x82u, 0x04u},\r
+ {0x85u, 0x08u},\r
+ {0x8Cu, 0x80u},\r
+ {0x91u, 0x19u},\r
+ {0x92u, 0x81u},\r
+ {0x93u, 0x64u},\r
+ {0x94u, 0x20u},\r
{0x9Bu, 0x10u},\r
- {0x9Du, 0x0Bu},\r
- {0x9Eu, 0x14u},\r
- {0x9Fu, 0x08u},\r
- {0xA2u, 0x52u},\r
- {0xA4u, 0x80u},\r
- {0xA8u, 0x04u},\r
+ {0x9Eu, 0x80u},\r
+ {0x9Fu, 0x20u},\r
+ {0xA0u, 0x02u},\r
+ {0xA2u, 0x08u},\r
+ {0xA7u, 0x11u},\r
+ {0xA8u, 0x40u},\r
{0xAAu, 0x04u},\r
- {0xABu, 0x09u},\r
- {0xEAu, 0x02u},\r
- {0xEEu, 0x10u},\r
- {0x06u, 0x02u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x08u},\r
- {0x0Fu, 0x01u},\r
- {0x10u, 0x01u},\r
- {0x12u, 0x02u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x04u},\r
- {0x17u, 0x09u},\r
- {0x19u, 0x02u},\r
- {0x1Au, 0x01u},\r
- {0x1Bu, 0x05u},\r
- {0x1Du, 0x01u},\r
- {0x1Fu, 0x02u},\r
- {0x2Du, 0x02u},\r
- {0x2Fu, 0x11u},\r
- {0x30u, 0x04u},\r
- {0x31u, 0x04u},\r
- {0x32u, 0x08u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x03u},\r
- {0x35u, 0x08u},\r
- {0x37u, 0x03u},\r
- {0x3Bu, 0x80u},\r
- {0x3Eu, 0x10u},\r
- {0x56u, 0x08u},\r
- {0x58u, 0x04u},\r
+ {0xABu, 0x40u},\r
+ {0xB1u, 0x04u},\r
+ {0xB2u, 0x01u},\r
+ {0xB5u, 0x10u},\r
+ {0xC0u, 0x2Eu},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0x43u},\r
+ {0xCAu, 0xF4u},\r
+ {0xCCu, 0xB7u},\r
+ {0xCEu, 0xB7u},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0xF9u},\r
+ {0xE0u, 0x02u},\r
+ {0xE2u, 0x18u},\r
+ {0xEEu, 0x31u},\r
+ {0x39u, 0x20u},\r
+ {0x3Fu, 0x10u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x90u},\r
- {0x82u, 0x60u},\r
- {0x83u, 0xFFu},\r
- {0x84u, 0x09u},\r
- {0x86u, 0x06u},\r
- {0x87u, 0xFFu},\r
- {0x88u, 0x30u},\r
- {0x89u, 0xFFu},\r
- {0x8Au, 0xC0u},\r
- {0x8Du, 0x60u},\r
- {0x8Eu, 0xFFu},\r
- {0x8Fu, 0x90u},\r
- {0x90u, 0x0Fu},\r
- {0x92u, 0xF0u},\r
- {0x95u, 0x50u},\r
- {0x96u, 0xFFu},\r
- {0x97u, 0xA0u},\r
- {0x98u, 0x03u},\r
- {0x99u, 0x03u},\r
- {0x9Au, 0x0Cu},\r
- {0x9Bu, 0x0Cu},\r
- {0x9Du, 0x0Fu},\r
- {0x9Fu, 0xF0u},\r
- {0xA0u, 0x05u},\r
- {0xA1u, 0x05u},\r
- {0xA2u, 0x0Au},\r
- {0xA3u, 0x0Au},\r
- {0xA4u, 0x50u},\r
- {0xA5u, 0x30u},\r
- {0xA6u, 0xA0u},\r
- {0xA7u, 0xC0u},\r
- {0xA9u, 0x06u},\r
- {0xAAu, 0xFFu},\r
- {0xABu, 0x09u},\r
- {0xB4u, 0xFFu},\r
- {0xB5u, 0xFFu},\r
- {0xBEu, 0x10u},\r
- {0xBFu, 0x10u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDFu, 0x01u},\r
- {0x02u, 0x02u},\r
- {0x03u, 0x20u},\r
- {0x04u, 0x22u},\r
- {0x06u, 0x22u},\r
- {0x08u, 0x18u},\r
- {0x0Au, 0x40u},\r
- {0x0Cu, 0x10u},\r
- {0x0Du, 0x10u},\r
- {0x0Eu, 0xE0u},\r
- {0x0Fu, 0x10u},\r
- {0x14u, 0x40u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x08u},\r
- {0x17u, 0x14u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x09u},\r
- {0x1Eu, 0x04u},\r
- {0x20u, 0x02u},\r
- {0x21u, 0xA8u},\r
- {0x23u, 0x40u},\r
{0x27u, 0x08u},\r
- {0x28u, 0x02u},\r
- {0x2Cu, 0x40u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x20u},\r
- {0x31u, 0xA8u},\r
- {0x34u, 0x10u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x04u},\r
- {0x3Bu, 0x40u},\r
- {0x3Du, 0x80u},\r
- {0x3Eu, 0x0Au},\r
- {0x3Fu, 0x10u},\r
- {0x59u, 0x80u},\r
- {0x60u, 0x02u},\r
- {0x6Cu, 0x91u},\r
- {0x6Du, 0x80u},\r
- {0x6Fu, 0x24u},\r
- {0x74u, 0x40u},\r
- {0x75u, 0x02u},\r
- {0x76u, 0x14u},\r
- {0x85u, 0x02u},\r
- {0x88u, 0x41u},\r
- {0x89u, 0x80u},\r
- {0x8Cu, 0x10u},\r
- {0x91u, 0x22u},\r
- {0x94u, 0x06u},\r
- {0x96u, 0x04u},\r
- {0x98u, 0x08u},\r
- {0x9Au, 0x22u},\r
- {0x9Bu, 0x10u},\r
- {0x9Du, 0x0Bu},\r
-
projects / SCSI2SD-V6.git / commitdiff