-20150x0x 4.5
+20151105 4.5
- Fix bug in SCSI MODE SENSE that returned the wrong mode type
- Fixes CDROM emulation
- Added selection delay parameter. This should be set to 1ms for older
1 spare sector per cylinder
2051459 usable sectors on volume
Apollo 400/425s running DOMAIN/OS
+ Motorola System V/68 R3V7 and R3V8.
+ Since the installation have information about limited number of drives(most of them with custom commands) it requires a pre-installed disk image to be dd-ed on it. Works with MVME167 and MVME177
+ Motorola System V/88 R40V4.0 through R40V4.4
+ It requires to describe the disk into a configuration file. The process is described here - http://m88k.com/howto-001.html
Samplers
May require scsi2sd-config --apple flag
Yamaha A5000, A3000, EX5, EX5R
EMU ESI4000
+ Synclavier 9600.
+ Disable Parity. Max size == 9GB.
+
Other
// Optional bootup delay\r
int delaySeconds = 0;\r
while (delaySeconds < scsiDev.boardCfg.startupDelay) {\r
- CyDelay(1000);\r
+ // Keep the USB connection working, otherwise it's very hard to revert\r
+ // silly extra-long startup delay settings.\r
+ int i;\r
+ for (i = 0; i < 200; i++) {\r
+ CyDelay(5);\r
+ scsiDev.watchdogTick++;\r
+ configPoll();\r
+ }\r
++delaySeconds;\r
}\r
\r
uint32_t lastSDPoll = getTime_ms();\r
sdCheckPresent();\r
\r
-\r
while (1)\r
{\r
scsiDev.watchdogTick++;\r
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB07_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__2__POS 2\r
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB08_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB08_ST\r
\r
/* SD_SCK */\r
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB05_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB05_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB05_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
#define scsiTarget_StatusReg__0__POS 0\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB02_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
\r
/* Debug_Timer_Interrupt */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB04_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB04_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 41u\r
+#define CY_CFG_BASE_ADDR_COUNT 42u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
0x40004501u, /* Base address: 0x40004500 Count: 1 */\r
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
0x4000520Bu, /* Base address: 0x40005200 Count: 11 */\r
- 0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
- 0x40010037u, /* Base address: 0x40010000 Count: 55 */\r
- 0x4001013Cu, /* Base address: 0x40010100 Count: 60 */\r
- 0x40010245u, /* Base address: 0x40010200 Count: 69 */\r
+ 0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
+ 0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
+ 0x4001003Du, /* Base address: 0x40010000 Count: 61 */\r
+ 0x40010138u, /* Base address: 0x40010100 Count: 56 */\r
+ 0x40010248u, /* Base address: 0x40010200 Count: 72 */\r
0x40010356u, /* Base address: 0x40010300 Count: 86 */\r
- 0x40010455u, /* Base address: 0x40010400 Count: 85 */\r
- 0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
- 0x4001064Bu, /* Base address: 0x40010600 Count: 75 */\r
- 0x40010756u, /* Base address: 0x40010700 Count: 86 */\r
- 0x40010922u, /* Base address: 0x40010900 Count: 34 */\r
- 0x40010A4Eu, /* Base address: 0x40010A00 Count: 78 */\r
- 0x40010B51u, /* Base address: 0x40010B00 Count: 81 */\r
- 0x40010C53u, /* Base address: 0x40010C00 Count: 83 */\r
- 0x40010D59u, /* Base address: 0x40010D00 Count: 89 */\r
- 0x40010E50u, /* Base address: 0x40010E00 Count: 80 */\r
- 0x40010F40u, /* Base address: 0x40010F00 Count: 64 */\r
- 0x40011454u, /* Base address: 0x40011400 Count: 84 */\r
- 0x40011548u, /* Base address: 0x40011500 Count: 72 */\r
- 0x4001164Fu, /* Base address: 0x40011600 Count: 79 */\r
+ 0x40010445u, /* Base address: 0x40010400 Count: 69 */\r
+ 0x4001054Au, /* Base address: 0x40010500 Count: 74 */\r
+ 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */\r
+ 0x4001074Fu, /* Base address: 0x40010700 Count: 79 */\r
+ 0x40010856u, /* Base address: 0x40010800 Count: 86 */\r
+ 0x40010954u, /* Base address: 0x40010900 Count: 84 */\r
+ 0x40010A4Cu, /* Base address: 0x40010A00 Count: 76 */\r
+ 0x40010B4Bu, /* Base address: 0x40010B00 Count: 75 */\r
+ 0x40010C51u, /* Base address: 0x40010C00 Count: 81 */\r
+ 0x40010D56u, /* Base address: 0x40010D00 Count: 86 */\r
+ 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */\r
+ 0x40010F42u, /* Base address: 0x40010F00 Count: 66 */\r
+ 0x4001145Eu, /* Base address: 0x40011400 Count: 94 */\r
+ 0x4001154Au, /* Base address: 0x40011500 Count: 74 */\r
+ 0x40011650u, /* Base address: 0x40011600 Count: 80 */\r
0x4001174Au, /* Base address: 0x40011700 Count: 74 */\r
- 0x4001184Eu, /* Base address: 0x40011800 Count: 78 */\r
- 0x40011943u, /* Base address: 0x40011900 Count: 67 */\r
- 0x40011A04u, /* Base address: 0x40011A00 Count: 4 */\r
- 0x40011B0Fu, /* Base address: 0x40011B00 Count: 15 */\r
- 0x40014017u, /* Base address: 0x40014000 Count: 23 */\r
- 0x4001411Du, /* Base address: 0x40014100 Count: 29 */\r
- 0x40014215u, /* Base address: 0x40014200 Count: 21 */\r
- 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */\r
+ 0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
+ 0x40011913u, /* Base address: 0x40011900 Count: 19 */\r
+ 0x40011B0Cu, /* Base address: 0x40011B00 Count: 12 */\r
+ 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
+ 0x4001411Au, /* Base address: 0x40014100 Count: 26 */\r
+ 0x40014213u, /* Base address: 0x40014200 Count: 19 */\r
+ 0x4001430Au, /* Base address: 0x40014300 Count: 10 */\r
0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
- 0x40014514u, /* Base address: 0x40014500 Count: 20 */\r
- 0x40014610u, /* Base address: 0x40014600 Count: 16 */\r
- 0x40014710u, /* Base address: 0x40014700 Count: 16 */\r
- 0x40014809u, /* Base address: 0x40014800 Count: 9 */\r
- 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */\r
- 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
- 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */\r
- 0x40015006u, /* Base address: 0x40015000 Count: 6 */\r
+ 0x4001451Bu, /* Base address: 0x40014500 Count: 27 */\r
+ 0x4001460Cu, /* Base address: 0x40014600 Count: 12 */\r
+ 0x4001470Fu, /* Base address: 0x40014700 Count: 15 */\r
+ 0x40014807u, /* Base address: 0x40014800 Count: 7 */\r
+ 0x40014909u, /* Base address: 0x40014900 Count: 9 */\r
+ 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */\r
+ 0x40014D03u, /* Base address: 0x40014D00 Count: 3 */\r
+ 0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
{0x0Au, 0x36u},\r
- {0x00u, 0x13u},\r
- {0x01u, 0x06u},\r
+ {0x00u, 0x05u},\r
+ {0x01u, 0x13u},\r
{0x18u, 0x08u},\r
{0x1Cu, 0x71u},\r
- {0x20u, 0xA0u},\r
- {0x21u, 0xC8u},\r
+ {0x20u, 0x50u},\r
+ {0x21u, 0x90u},\r
{0x2Cu, 0x0Eu},\r
- {0x30u, 0x05u},\r
- {0x31u, 0x03u},\r
+ {0x30u, 0x0Cu},\r
+ {0x31u, 0x09u},\r
{0x34u, 0x80u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x01u},\r
{0x87u, 0x0Fu},\r
- {0x06u, 0x07u},\r
- {0x08u, 0xAAu},\r
- {0x0Au, 0x55u},\r
- {0x0Cu, 0x99u},\r
- {0x0Eu, 0x22u},\r
- {0x10u, 0x44u},\r
- {0x12u, 0x88u},\r
- {0x17u, 0x01u},\r
- {0x1Au, 0x70u},\r
- {0x26u, 0x80u},\r
- {0x2Au, 0x08u},\r
- {0x31u, 0x01u},\r
- {0x32u, 0x0Fu},\r
- {0x34u, 0xF0u},\r
+ {0x00u, 0x20u},\r
+ {0x02u, 0x40u},\r
+ {0x03u, 0x04u},\r
+ {0x04u, 0x01u},\r
+ {0x05u, 0x08u},\r
+ {0x08u, 0x0Au},\r
+ {0x09u, 0x09u},\r
+ {0x0Au, 0x35u},\r
+ {0x0Bu, 0x72u},\r
+ {0x0Cu, 0x48u},\r
+ {0x0Eu, 0x36u},\r
+ {0x10u, 0x07u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0x18u},\r
+ {0x13u, 0x66u},\r
+ {0x14u, 0x4Fu},\r
+ {0x16u, 0x30u},\r
+ {0x17u, 0x7Fu},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Du, 0x62u},\r
+ {0x1Eu, 0x02u},\r
+ {0x21u, 0x20u},\r
+ {0x22u, 0x20u},\r
+ {0x23u, 0x40u},\r
+ {0x24u, 0x05u},\r
+ {0x25u, 0x74u},\r
+ {0x27u, 0x09u},\r
+ {0x29u, 0x20u},\r
+ {0x2Au, 0x27u},\r
+ {0x2Bu, 0x40u},\r
+ {0x30u, 0x1Fu},\r
+ {0x31u, 0x60u},\r
+ {0x33u, 0x1Fu},\r
+ {0x36u, 0x60u},\r
+ {0x3Au, 0x82u},\r
+ {0x3Bu, 0x02u},\r
{0x40u, 0x32u},\r
{0x41u, 0x04u},\r
- {0x42u, 0x50u},\r
- {0x45u, 0xEFu},\r
- {0x46u, 0xDCu},\r
- {0x47u, 0x02u},\r
+ {0x42u, 0x10u},\r
+ {0x45u, 0x2Du},\r
+ {0x46u, 0xFCu},\r
+ {0x47u, 0x0Eu},\r
{0x48u, 0x1Fu},\r
{0x49u, 0xFFu},\r
{0x4Au, 0xFFu},\r
{0x59u, 0x04u},\r
{0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x91u},\r
+ {0x5Cu, 0x11u},\r
{0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
{0x60u, 0x08u},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0x83u, 0x08u},\r
+ {0x02u, 0x04u},\r
+ {0x03u, 0x91u},\r
+ {0x04u, 0x30u},\r
+ {0x0Au, 0x80u},\r
+ {0x0Bu, 0x11u},\r
+ {0x11u, 0x10u},\r
+ {0x12u, 0xA8u},\r
+ {0x1Au, 0x80u},\r
+ {0x1Bu, 0x80u},\r
+ {0x20u, 0x30u},\r
+ {0x23u, 0x90u},\r
+ {0x28u, 0x48u},\r
+ {0x2Au, 0x04u},\r
+ {0x2Bu, 0x10u},\r
+ {0x32u, 0x88u},\r
+ {0x33u, 0x11u},\r
+ {0x38u, 0x10u},\r
+ {0x3Bu, 0x05u},\r
+ {0x40u, 0x10u},\r
+ {0x42u, 0x04u},\r
+ {0x43u, 0x81u},\r
+ {0x4Au, 0x20u},\r
+ {0x4Bu, 0x05u},\r
+ {0x50u, 0x80u},\r
+ {0x53u, 0x28u},\r
+ {0x58u, 0x40u},\r
+ {0x59u, 0x20u},\r
+ {0x5Au, 0x02u},\r
+ {0x5Bu, 0x84u},\r
+ {0x60u, 0x04u},\r
+ {0x61u, 0x49u},\r
+ {0x69u, 0x84u},\r
+ {0x6Au, 0x20u},\r
+ {0x6Bu, 0x40u},\r
+ {0x71u, 0x80u},\r
+ {0x72u, 0x88u},\r
+ {0x73u, 0x20u},\r
+ {0x80u, 0x80u},\r
+ {0x81u, 0xC0u},\r
+ {0x85u, 0x04u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Eu, 0x10u},\r
+ {0x8Fu, 0x22u},\r
+ {0xC0u, 0x0Fu},\r
+ {0xC2u, 0x0Du},\r
+ {0xC4u, 0x0Eu},\r
+ {0xCAu, 0x07u},\r
+ {0xCCu, 0x0Fu},\r
+ {0xCEu, 0x07u},\r
+ {0xD0u, 0x0Fu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE0u, 0x05u},\r
+ {0xE2u, 0x02u},\r
+ {0xE4u, 0x03u},\r
+ {0xE6u, 0x08u},\r
+ {0x00u, 0x96u},\r
+ {0x02u, 0x69u},\r
+ {0x04u, 0x55u},\r
+ {0x05u, 0x33u},\r
+ {0x06u, 0xAAu},\r
+ {0x07u, 0xCCu},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Bu, 0xFFu},\r
+ {0x0Cu, 0x33u},\r
+ {0x0Du, 0x0Fu},\r
+ {0x0Eu, 0xCCu},\r
+ {0x0Fu, 0xF0u},\r
+ {0x13u, 0xFFu},\r
+ {0x14u, 0x0Fu},\r
+ {0x16u, 0xF0u},\r
+ {0x17u, 0xFFu},\r
+ {0x18u, 0xFFu},\r
+ {0x1Du, 0xFFu},\r
+ {0x1Eu, 0xFFu},\r
+ {0x25u, 0xFFu},\r
+ {0x29u, 0x55u},\r
+ {0x2Au, 0xFFu},\r
+ {0x2Bu, 0xAAu},\r
+ {0x2Cu, 0xFFu},\r
+ {0x2Du, 0x69u},\r
+ {0x2Fu, 0x96u},\r
+ {0x32u, 0xFFu},\r
+ {0x37u, 0xFFu},\r
+ {0x3Au, 0x08u},\r
+ {0x3Bu, 0x80u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0xE0u},\r
+ {0x84u, 0x40u},\r
+ {0x86u, 0x80u},\r
+ {0x89u, 0x44u},\r
+ {0x8Au, 0xFFu},\r
+ {0x8Bu, 0x88u},\r
+ {0x8Cu, 0x06u},\r
+ {0x8Eu, 0xF8u},\r
{0x8Fu, 0x80u},\r
- {0x93u, 0x70u},\r
+ {0x91u, 0x99u},\r
+ {0x93u, 0x22u},\r
+ {0x94u, 0x01u},\r
{0x97u, 0x07u},\r
+ {0x98u, 0xC6u},\r
+ {0x9Au, 0x19u},\r
+ {0x9Bu, 0x70u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Eu, 0x80u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA0u, 0x14u},\r
{0xA5u, 0xAAu},\r
+ {0xA6u, 0x09u},\r
{0xA7u, 0x55u},\r
- {0xA9u, 0x44u},\r
- {0xABu, 0x88u},\r
- {0xADu, 0x99u},\r
- {0xAFu, 0x22u},\r
+ {0xA8u, 0x09u},\r
+ {0xAAu, 0xF2u},\r
{0xB3u, 0x0Fu},\r
- {0xB7u, 0xF0u},\r
+ {0xB4u, 0x3Fu},\r
+ {0xB5u, 0xF0u},\r
+ {0xB6u, 0xC0u},\r
+ {0xBAu, 0x80u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x10u},\r
+ {0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x18u},\r
+ {0x01u, 0x10u},\r
+ {0x02u, 0x90u},\r
{0x03u, 0x01u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x20u},\r
- {0x0Au, 0x08u},\r
- {0x10u, 0x28u},\r
- {0x18u, 0x20u},\r
- {0x19u, 0x08u},\r
- {0x1Au, 0x08u},\r
- {0x20u, 0x40u},\r
- {0x26u, 0x88u},\r
- {0x27u, 0x02u},\r
- {0x2Du, 0x04u},\r
- {0x2Eu, 0x80u},\r
- {0x2Fu, 0x28u},\r
- {0x33u, 0x04u},\r
- {0x35u, 0x04u},\r
- {0x36u, 0x08u},\r
- {0x37u, 0x02u},\r
- {0x3Du, 0x40u},\r
- {0x3Eu, 0x02u},\r
- {0x41u, 0x08u},\r
- {0x42u, 0x80u},\r
- {0x43u, 0x29u},\r
- {0x4Au, 0x50u},\r
- {0x4Bu, 0x80u},\r
- {0x50u, 0x80u},\r
- {0x52u, 0x20u},\r
- {0x53u, 0x04u},\r
- {0x5Au, 0x25u},\r
- {0x5Bu, 0x40u},\r
- {0x5Du, 0x80u},\r
- {0x5Eu, 0x0Au},\r
- {0x5Fu, 0x20u},\r
+ {0x04u, 0x20u},\r
+ {0x05u, 0x04u},\r
+ {0x06u, 0x40u},\r
+ {0x07u, 0x02u},\r
+ {0x09u, 0x04u},\r
+ {0x0Au, 0x06u},\r
+ {0x0Eu, 0x26u},\r
+ {0x10u, 0x80u},\r
+ {0x12u, 0x20u},\r
+ {0x13u, 0x18u},\r
+ {0x15u, 0x90u},\r
+ {0x1Au, 0x06u},\r
+ {0x1Bu, 0x30u},\r
+ {0x1Eu, 0x20u},\r
+ {0x21u, 0x20u},\r
+ {0x22u, 0x04u},\r
+ {0x24u, 0x02u},\r
+ {0x25u, 0x40u},\r
+ {0x2Bu, 0x10u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0x21u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x04u},\r
+ {0x33u, 0x41u},\r
+ {0x36u, 0x89u},\r
+ {0x37u, 0x01u},\r
+ {0x38u, 0x20u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Fu, 0x18u},\r
+ {0x58u, 0x10u},\r
+ {0x5Bu, 0x80u},\r
+ {0x5Cu, 0x50u},\r
+ {0x5Du, 0x09u},\r
{0x60u, 0x08u},\r
- {0x61u, 0x40u},\r
- {0x63u, 0x50u},\r
- {0x64u, 0x02u},\r
- {0x69u, 0x61u},\r
- {0x6Bu, 0x10u},\r
- {0x70u, 0x28u},\r
- {0x72u, 0x42u},\r
- {0x80u, 0x02u},\r
- {0x81u, 0x02u},\r
- {0x84u, 0x08u},\r
- {0x86u, 0x20u},\r
- {0x8Bu, 0x24u},\r
- {0x8Eu, 0x10u},\r
- {0xC0u, 0x07u},\r
- {0xC2u, 0x0Au},\r
- {0xC4u, 0x06u},\r
- {0xCAu, 0x70u},\r
- {0xCCu, 0xC2u},\r
- {0xCEu, 0x90u},\r
- {0xD0u, 0x07u},\r
- {0xD2u, 0x08u},\r
- {0xD6u, 0xFFu},\r
- {0xD8u, 0x1Fu},\r
- {0xE4u, 0x06u},\r
- {0xE6u, 0x09u},\r
- {0x04u, 0x24u},\r
+ {0x62u, 0x40u},\r
+ {0x63u, 0x08u},\r
+ {0x65u, 0x80u},\r
+ {0x81u, 0x08u},\r
+ {0x82u, 0x40u},\r
+ {0x83u, 0x80u},\r
+ {0x85u, 0x20u},\r
+ {0x87u, 0x08u},\r
+ {0x89u, 0x20u},\r
+ {0x8Bu, 0x80u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Eu, 0x04u},\r
+ {0x90u, 0x20u},\r
+ {0x91u, 0x10u},\r
+ {0x93u, 0x10u},\r
+ {0x94u, 0x04u},\r
+ {0x96u, 0x06u},\r
+ {0x98u, 0x04u},\r
+ {0x9Au, 0x80u},\r
+ {0x9Bu, 0x42u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Du, 0x61u},\r
+ {0x9Fu, 0x15u},\r
+ {0xA0u, 0x80u},\r
+ {0xA2u, 0x28u},\r
+ {0xA3u, 0x08u},\r
+ {0xA5u, 0x08u},\r
+ {0xA6u, 0x80u},\r
+ {0xA7u, 0x10u},\r
+ {0xAAu, 0x40u},\r
+ {0xACu, 0x10u},\r
+ {0xAEu, 0x04u},\r
+ {0xB0u, 0x04u},\r
+ {0xB3u, 0x20u},\r
+ {0xB6u, 0x28u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0xE7u},\r
+ {0xC4u, 0xCEu},\r
+ {0xCAu, 0x72u},\r
+ {0xCCu, 0xDFu},\r
+ {0xCEu, 0x7Cu},\r
+ {0xD6u, 0xFCu},\r
+ {0xD8u, 0x1Cu},\r
+ {0xE0u, 0x08u},\r
+ {0xE6u, 0x03u},\r
+ {0xE8u, 0x0Au},\r
+ {0xEAu, 0x10u},\r
+ {0xEEu, 0x06u},\r
+ {0x01u, 0x02u},\r
+ {0x02u, 0x02u},\r
+ {0x03u, 0x01u},\r
{0x05u, 0x01u},\r
- {0x06u, 0x08u},\r
- {0x09u, 0x07u},\r
- {0x0Bu, 0x18u},\r
- {0x0Cu, 0x01u},\r
- {0x0Du, 0x2Fu},\r
- {0x0Eu, 0x02u},\r
- {0x0Fu, 0x10u},\r
- {0x13u, 0x07u},\r
- {0x19u, 0x05u},\r
- {0x1Au, 0x20u},\r
- {0x1Eu, 0x1Du},\r
- {0x23u, 0x20u},\r
- {0x24u, 0x28u},\r
- {0x25u, 0x2Au},\r
- {0x26u, 0x14u},\r
- {0x27u, 0x15u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x02u},\r
- {0x2Cu, 0x10u},\r
- {0x2Du, 0x28u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x16u},\r
+ {0x07u, 0x06u},\r
+ {0x11u, 0x04u},\r
+ {0x13u, 0x08u},\r
+ {0x17u, 0x10u},\r
+ {0x1Eu, 0x01u},\r
+ {0x21u, 0x02u},\r
+ {0x23u, 0x01u},\r
+ {0x29u, 0x02u},\r
+ {0x2Bu, 0x01u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Fu, 0x29u},\r
+ {0x30u, 0x01u},\r
{0x31u, 0x20u},\r
- {0x32u, 0x03u},\r
- {0x35u, 0x1Fu},\r
- {0x36u, 0x3Cu},\r
- {0x3Bu, 0x20u},\r
- {0x3Eu, 0x04u},\r
- {0x3Fu, 0x01u},\r
+ {0x33u, 0x03u},\r
+ {0x34u, 0x02u},\r
+ {0x35u, 0x10u},\r
+ {0x37u, 0x0Cu},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Fu, 0x40u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
{0x5Cu, 0x11u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x83u, 0x80u},\r
- {0x86u, 0x04u},\r
- {0x87u, 0x07u},\r
- {0x89u, 0xAAu},\r
- {0x8Au, 0x08u},\r
- {0x8Bu, 0x55u},\r
- {0x8Cu, 0x2Au},\r
- {0x8Eu, 0x54u},\r
- {0x8Fu, 0x70u},\r
- {0x95u, 0x99u},\r
- {0x96u, 0x02u},\r
- {0x97u, 0x22u},\r
- {0x9Au, 0x20u},\r
- {0x9Bu, 0x08u},\r
- {0x9Eu, 0x10u},\r
- {0xA6u, 0x01u},\r
- {0xAAu, 0x40u},\r
- {0xADu, 0x44u},\r
- {0xAFu, 0x88u},\r
- {0xB0u, 0x18u},\r
- {0xB1u, 0xF0u},\r
- {0xB2u, 0x01u},\r
- {0xB3u, 0x0Fu},\r
- {0xB4u, 0x60u},\r
- {0xB6u, 0x06u},\r
- {0xBEu, 0x51u},\r
+ {0x81u, 0x0Du},\r
+ {0x85u, 0x02u},\r
+ {0x87u, 0x54u},\r
+ {0x8Bu, 0x10u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Eu, 0x01u},\r
+ {0x8Fu, 0x0Du},\r
+ {0x94u, 0x02u},\r
+ {0x95u, 0x62u},\r
+ {0x96u, 0x09u},\r
+ {0x97u, 0x08u},\r
+ {0x98u, 0x01u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Bu, 0x32u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Eu, 0x05u},\r
+ {0xA1u, 0x0Du},\r
+ {0xA5u, 0x0Du},\r
+ {0xA8u, 0x02u},\r
+ {0xA9u, 0x0Du},\r
+ {0xAAu, 0x11u},\r
+ {0xADu, 0x0Du},\r
+ {0xB0u, 0x04u},\r
+ {0xB2u, 0x10u},\r
+ {0xB4u, 0x03u},\r
+ {0xB5u, 0x70u},\r
+ {0xB6u, 0x08u},\r
+ {0xB7u, 0x0Fu},\r
+ {0xBAu, 0x20u},\r
+ {0xBBu, 0x80u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x19u},\r
+ {0xDCu, 0x01u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x20u},\r
- {0x01u, 0x40u},\r
- {0x02u, 0x11u},\r
- {0x06u, 0x01u},\r
- {0x07u, 0x20u},\r
- {0x09u, 0x24u},\r
- {0x0Bu, 0x02u},\r
- {0x0Du, 0x10u},\r
- {0x0Eu, 0x01u},\r
- {0x11u, 0x02u},\r
- {0x12u, 0x04u},\r
- {0x13u, 0x05u},\r
- {0x14u, 0x05u},\r
- {0x15u, 0x04u},\r
- {0x18u, 0x08u},\r
- {0x19u, 0x0Au},\r
- {0x1Bu, 0x80u},\r
- {0x1Eu, 0x11u},\r
- {0x20u, 0x60u},\r
- {0x21u, 0x05u},\r
- {0x25u, 0x11u},\r
- {0x28u, 0x01u},\r
- {0x2Cu, 0x80u},\r
- {0x2Du, 0x04u},\r
- {0x2Eu, 0x80u},\r
- {0x2Fu, 0x04u},\r
- {0x30u, 0x08u},\r
- {0x33u, 0x10u},\r
- {0x36u, 0x23u},\r
- {0x38u, 0x40u},\r
- {0x39u, 0x19u},\r
+ {0x01u, 0x06u},\r
+ {0x03u, 0x20u},\r
+ {0x04u, 0x40u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Eu, 0x1Au},\r
+ {0x14u, 0x08u},\r
+ {0x19u, 0x22u},\r
+ {0x1Cu, 0x40u},\r
+ {0x1Eu, 0x1Au},\r
+ {0x20u, 0x01u},\r
+ {0x21u, 0x45u},\r
+ {0x22u, 0x91u},\r
+ {0x25u, 0x50u},\r
+ {0x28u, 0x02u},\r
+ {0x29u, 0x22u},\r
+ {0x2Cu, 0xA8u},\r
+ {0x2Du, 0x40u},\r
+ {0x30u, 0x02u},\r
+ {0x32u, 0x08u},\r
+ {0x36u, 0x20u},\r
+ {0x37u, 0x08u},\r
+ {0x39u, 0x0Au},\r
+ {0x3Cu, 0x08u},\r
{0x3Du, 0xA0u},\r
- {0x3Fu, 0x08u},\r
- {0x58u, 0x20u},\r
- {0x5Au, 0x80u},\r
- {0x5Cu, 0x06u},\r
- {0x5Eu, 0xA0u},\r
- {0x61u, 0x10u},\r
- {0x62u, 0x40u},\r
- {0x63u, 0x04u},\r
- {0x67u, 0x01u},\r
- {0x80u, 0x04u},\r
- {0x81u, 0x98u},\r
- {0x84u, 0x20u},\r
- {0x86u, 0x20u},\r
- {0x8Au, 0x40u},\r
- {0x8Bu, 0x40u},\r
- {0x8Cu, 0x84u},\r
+ {0x3Eu, 0x02u},\r
+ {0x58u, 0x10u},\r
+ {0x5Au, 0x84u},\r
+ {0x5Eu, 0x40u},\r
+ {0x5Fu, 0x20u},\r
+ {0x60u, 0x02u},\r
+ {0x61u, 0x24u},\r
+ {0x62u, 0x04u},\r
+ {0x64u, 0x08u},\r
+ {0x67u, 0x02u},\r
+ {0x68u, 0x02u},\r
+ {0x6Du, 0x08u},\r
+ {0x6Fu, 0x1Au},\r
+ {0x83u, 0x0Au},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x08u},\r
+ {0x86u, 0x04u},\r
+ {0x8Bu, 0x20u},\r
{0x8Du, 0x10u},\r
- {0x8Fu, 0x40u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x35u},\r
- {0x92u, 0x40u},\r
- {0x93u, 0x08u},\r
- {0x96u, 0x04u},\r
- {0x97u, 0xC0u},\r
- {0x99u, 0x04u},\r
- {0x9Bu, 0x10u},\r
- {0x9Cu, 0x01u},\r
- {0x9Du, 0x82u},\r
- {0x9Eu, 0x80u},\r
- {0x9Fu, 0x04u},\r
- {0xA0u, 0x80u},\r
- {0xA1u, 0x20u},\r
- {0xA2u, 0xF0u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x05u},\r
- {0xADu, 0x40u},\r
- {0xAEu, 0x01u},\r
- {0xB1u, 0x10u},\r
- {0xB3u, 0x30u},\r
- {0xB4u, 0xC0u},\r
- {0xB7u, 0x40u},\r
- {0xC0u, 0xA7u},\r
- {0xC2u, 0xC7u},\r
- {0xC4u, 0xE6u},\r
- {0xCAu, 0xF8u},\r
- {0xCCu, 0xA6u},\r
- {0xCEu, 0x7Fu},\r
- {0xD6u, 0xFCu},\r
- {0xD8u, 0x1Cu},\r
- {0xE2u, 0x0Cu},\r
- {0xE4u, 0x04u},\r
- {0xE6u, 0x2Au},\r
- {0xEAu, 0x08u},\r
- {0xEEu, 0x48u},\r
- {0x00u, 0x40u},\r
- {0x01u, 0x04u},\r
- {0x02u, 0x80u},\r
- {0x05u, 0x30u},\r
- {0x06u, 0x1Cu},\r
- {0x07u, 0x05u},\r
- {0x0Bu, 0x04u},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0x43u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x20u},\r
- {0x14u, 0x03u},\r
- {0x15u, 0x07u},\r
- {0x16u, 0x40u},\r
- {0x17u, 0x18u},\r
- {0x18u, 0x01u},\r
- {0x19u, 0x04u},\r
- {0x1Au, 0x02u},\r
- {0x1Cu, 0x90u},\r
- {0x1Eu, 0x63u},\r
+ {0x90u, 0x22u},\r
+ {0x92u, 0x80u},\r
+ {0x94u, 0x14u},\r
+ {0x95u, 0x89u},\r
+ {0x97u, 0x02u},\r
+ {0x98u, 0x04u},\r
+ {0x9Du, 0x45u},\r
+ {0x9Eu, 0x30u},\r
+ {0x9Fu, 0x15u},\r
+ {0xA2u, 0x10u},\r
+ {0xA3u, 0x20u},\r
+ {0xA5u, 0x0Cu},\r
+ {0xA6u, 0x84u},\r
+ {0xA7u, 0x80u},\r
+ {0xABu, 0x18u},\r
+ {0xACu, 0x10u},\r
+ {0xAEu, 0x04u},\r
+ {0xB1u, 0x84u},\r
+ {0xB3u, 0x01u},\r
+ {0xC0u, 0x88u},\r
+ {0xC2u, 0xE1u},\r
+ {0xC4u, 0x40u},\r
+ {0xCAu, 0xFDu},\r
+ {0xCCu, 0x63u},\r
+ {0xCEu, 0xF3u},\r
+ {0xD6u, 0x3Eu},\r
+ {0xD8u, 0x3Eu},\r
+ {0xE2u, 0x22u},\r
+ {0xE6u, 0x16u},\r
+ {0xECu, 0x09u},\r
+ {0xEEu, 0x06u},\r
+ {0x00u, 0x02u},\r
+ {0x02u, 0x01u},\r
+ {0x05u, 0x34u},\r
+ {0x07u, 0x08u},\r
+ {0x09u, 0x01u},\r
+ {0x0Bu, 0x38u},\r
+ {0x11u, 0x05u},\r
+ {0x13u, 0x38u},\r
+ {0x14u, 0x02u},\r
+ {0x15u, 0x10u},\r
+ {0x16u, 0x01u},\r
+ {0x17u, 0x20u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Cu, 0x01u},\r
+ {0x1Du, 0x30u},\r
+ {0x1Eu, 0x02u},\r
{0x1Fu, 0x08u},\r
- {0x20u, 0x01u},\r
- {0x22u, 0x02u},\r
- {0x23u, 0x02u},\r
- {0x24u, 0x2Bu},\r
- {0x26u, 0x54u},\r
- {0x28u, 0xA4u},\r
- {0x29u, 0x03u},\r
- {0x2Au, 0x4Bu},\r
- {0x2Bu, 0x28u},\r
- {0x2Du, 0x04u},\r
- {0x30u, 0xC0u},\r
- {0x31u, 0x07u},\r
- {0x32u, 0x3Cu},\r
- {0x34u, 0x03u},\r
- {0x35u, 0x07u},\r
- {0x37u, 0x38u},\r
- {0x3Au, 0x22u},\r
- {0x3Bu, 0x33u},\r
- {0x54u, 0x01u},\r
+ {0x21u, 0x02u},\r
+ {0x23u, 0x30u},\r
+ {0x28u, 0x02u},\r
+ {0x2Au, 0x01u},\r
+ {0x2Bu, 0x40u},\r
+ {0x2Cu, 0x02u},\r
+ {0x2Du, 0x10u},\r
+ {0x2Eu, 0x05u},\r
+ {0x2Fu, 0x20u},\r
+ {0x32u, 0x04u},\r
+ {0x33u, 0x40u},\r
+ {0x35u, 0x30u},\r
+ {0x36u, 0x03u},\r
+ {0x37u, 0x0Fu},\r
+ {0x39u, 0x80u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Bu, 0x20u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x01u},\r
- {0x5Du, 0x10u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x05u},\r
- {0x82u, 0x80u},\r
- {0x83u, 0x0Au},\r
- {0x84u, 0x01u},\r
- {0x86u, 0x12u},\r
- {0x89u, 0x03u},\r
- {0x8Bu, 0x0Cu},\r
- {0x8Cu, 0x04u},\r
- {0x8Du, 0x0Fu},\r
- {0x8Eu, 0x28u},\r
- {0x8Fu, 0xF0u},\r
- {0x92u, 0x40u},\r
- {0x93u, 0xFFu},\r
- {0x9Bu, 0xFFu},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x09u},\r
- {0x9Eu, 0x04u},\r
- {0x9Fu, 0x06u},\r
- {0xA0u, 0x02u},\r
- {0xA2u, 0x01u},\r
- {0xA3u, 0xFFu},\r
- {0xA5u, 0x30u},\r
- {0xA7u, 0xC0u},\r
- {0xA9u, 0x50u},\r
- {0xABu, 0xA0u},\r
- {0xACu, 0x53u},\r
- {0xADu, 0x90u},\r
- {0xAEu, 0xACu},\r
- {0xAFu, 0x60u},\r
- {0xB0u, 0x0Fu},\r
- {0xB2u, 0x30u},\r
- {0xB4u, 0xC0u},\r
- {0xB5u, 0xFFu},\r
- {0xBEu, 0x15u},\r
- {0xBFu, 0x10u},\r
+ {0x81u, 0x01u},\r
+ {0x82u, 0x3Fu},\r
+ {0x84u, 0x04u},\r
+ {0x86u, 0x08u},\r
+ {0x88u, 0x10u},\r
+ {0x8Au, 0x20u},\r
+ {0x8Cu, 0x10u},\r
+ {0x8Eu, 0x20u},\r
+ {0x8Fu, 0x01u},\r
+ {0x90u, 0x04u},\r
+ {0x92u, 0x08u},\r
+ {0x95u, 0x01u},\r
+ {0x98u, 0x01u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Cu, 0x01u},\r
+ {0x9Du, 0x01u},\r
+ {0x9Eu, 0x02u},\r
+ {0xA0u, 0x3Fu},\r
+ {0xA1u, 0x02u},\r
+ {0xA4u, 0x3Fu},\r
+ {0xAAu, 0x3Fu},\r
+ {0xAEu, 0x3Fu},\r
+ {0xB0u, 0x30u},\r
+ {0xB1u, 0x01u},\r
+ {0xB3u, 0x02u},\r
+ {0xB4u, 0x0Cu},\r
+ {0xB6u, 0x03u},\r
+ {0xBAu, 0xA2u},\r
+ {0xBFu, 0x01u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x91u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x0Au},\r
- {0x02u, 0x02u},\r
- {0x05u, 0x04u},\r
- {0x06u, 0x81u},\r
- {0x08u, 0x08u},\r
- {0x09u, 0x40u},\r
- {0x0Au, 0x44u},\r
- {0x0Eu, 0x82u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x40u},\r
- {0x13u, 0x20u},\r
- {0x15u, 0x42u},\r
- {0x19u, 0x0Au},\r
- {0x1Au, 0x04u},\r
- {0x1Du, 0x19u},\r
- {0x20u, 0x44u},\r
- {0x21u, 0x02u},\r
- {0x22u, 0x50u},\r
- {0x26u, 0x10u},\r
- {0x28u, 0x02u},\r
- {0x29u, 0x20u},\r
- {0x2Bu, 0x80u},\r
- {0x2Cu, 0x04u},\r
- {0x2Eu, 0x82u},\r
- {0x2Fu, 0x2Au},\r
- {0x30u, 0x20u},\r
- {0x32u, 0x44u},\r
- {0x33u, 0x01u},\r
- {0x35u, 0x01u},\r
- {0x36u, 0xE0u},\r
- {0x38u, 0x84u},\r
- {0x39u, 0x11u},\r
- {0x3Cu, 0x20u},\r
- {0x3Du, 0x40u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x11u},\r
- {0x5Bu, 0x40u},\r
- {0x65u, 0x02u},\r
- {0x67u, 0x80u},\r
- {0x6Du, 0x40u},\r
- {0x80u, 0x02u},\r
- {0x81u, 0x18u},\r
- {0x84u, 0x08u},\r
- {0x8Bu, 0x04u},\r
- {0x8Eu, 0x42u},\r
- {0x8Fu, 0x04u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x06u},\r
- {0x92u, 0x41u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x01u},\r
+ {0x02u, 0x04u},\r
+ {0x03u, 0x02u},\r
+ {0x07u, 0x40u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x20u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Eu, 0x12u},\r
+ {0x11u, 0x94u},\r
+ {0x12u, 0x80u},\r
+ {0x14u, 0x01u},\r
+ {0x17u, 0x20u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x41u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Eu, 0x12u},\r
+ {0x1Fu, 0x84u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0x04u},\r
+ {0x25u, 0x40u},\r
+ {0x27u, 0x25u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Du, 0x01u},\r
+ {0x2Fu, 0x09u},\r
+ {0x30u, 0xA8u},\r
+ {0x36u, 0x80u},\r
+ {0x37u, 0x15u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x50u},\r
+ {0x3Au, 0x02u},\r
+ {0x3Du, 0x14u},\r
+ {0x58u, 0x84u},\r
+ {0x59u, 0x20u},\r
+ {0x5Eu, 0x40u},\r
+ {0x60u, 0x02u},\r
+ {0x61u, 0x04u},\r
+ {0x62u, 0x18u},\r
+ {0x64u, 0x01u},\r
+ {0x85u, 0x20u},\r
+ {0x8Bu, 0x01u},\r
+ {0x8Du, 0x04u},\r
+ {0x8Eu, 0x40u},\r
+ {0x90u, 0x23u},\r
+ {0x91u, 0x05u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x02u},\r
+ {0x94u, 0x04u},\r
{0x95u, 0x40u},\r
- {0x96u, 0x04u},\r
- {0x97u, 0x80u},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0x60u},\r
- {0x9Bu, 0x60u},\r
- {0x9Cu, 0x04u},\r
- {0x9Eu, 0x14u},\r
- {0x9Fu, 0x04u},\r
- {0xA0u, 0x10u},\r
- {0xA1u, 0x60u},\r
- {0xA2u, 0x80u},\r
- {0xA6u, 0x06u},\r
- {0xA7u, 0x24u},\r
- {0xA8u, 0x02u},\r
- {0xAAu, 0x30u},\r
- {0xABu, 0x21u},\r
- {0xACu, 0x01u},\r
- {0xADu, 0x48u},\r
- {0xB3u, 0x80u},\r
- {0xB4u, 0x18u},\r
- {0xB5u, 0x04u},\r
- {0xB6u, 0xC0u},\r
+ {0x96u, 0x08u},\r
+ {0x98u, 0x04u},\r
+ {0x9Au, 0x04u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Du, 0x41u},\r
+ {0x9Eu, 0x12u},\r
+ {0x9Fu, 0x0Du},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x90u},\r
+ {0xA4u, 0xACu},\r
+ {0xA6u, 0x28u},\r
+ {0xA7u, 0x80u},\r
+ {0xAEu, 0x24u},\r
+ {0xB1u, 0x01u},\r
+ {0xB4u, 0x11u},\r
+ {0xB6u, 0x40u},\r
{0xB7u, 0x20u},\r
- {0xC0u, 0xBDu},\r
- {0xC2u, 0x9Fu},\r
- {0xC4u, 0x9Eu},\r
- {0xCAu, 0xFDu},\r
- {0xCCu, 0xBFu},\r
- {0xCEu, 0xBFu},\r
- {0xD6u, 0x08u},\r
- {0xE2u, 0xD4u},\r
- {0xE4u, 0x04u},\r
- {0xE6u, 0x09u},\r
- {0xE8u, 0x01u},\r
- {0xEAu, 0x82u},\r
- {0x00u, 0xFFu},\r
- {0x07u, 0x02u},\r
- {0x0Au, 0xFFu},\r
+ {0xC0u, 0x1Fu},\r
+ {0xC2u, 0xABu},\r
+ {0xC4u, 0xCFu},\r
+ {0xCAu, 0xB1u},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0x69u},\r
+ {0xD6u, 0x1Eu},\r
+ {0xD8u, 0x1Eu},\r
+ {0xE2u, 0x01u},\r
+ {0xE6u, 0x03u},\r
+ {0xEAu, 0x0Bu},\r
+ {0xEEu, 0x08u},\r
+ {0x01u, 0x02u},\r
+ {0x03u, 0x01u},\r
+ {0x04u, 0x06u},\r
+ {0x09u, 0x02u},\r
{0x0Bu, 0x01u},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0xFFu},\r
- {0x10u, 0x60u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x90u},\r
- {0x14u, 0x03u},\r
- {0x16u, 0x0Cu},\r
- {0x19u, 0x04u},\r
- {0x1Cu, 0x05u},\r
- {0x1Eu, 0x0Au},\r
- {0x20u, 0x06u},\r
- {0x22u, 0x09u},\r
- {0x24u, 0x50u},\r
- {0x25u, 0x04u},\r
- {0x26u, 0xA0u},\r
- {0x28u, 0x30u},\r
- {0x2Au, 0xC0u},\r
- {0x2Cu, 0x0Fu},\r
- {0x2Eu, 0xF0u},\r
- {0x33u, 0x01u},\r
- {0x34u, 0xFFu},\r
- {0x35u, 0x02u},\r
- {0x37u, 0x04u},\r
- {0x39u, 0x80u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x40u},\r
+ {0x0Cu, 0x2Au},\r
+ {0x0Eu, 0x11u},\r
+ {0x10u, 0x19u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0x24u},\r
+ {0x13u, 0x02u},\r
+ {0x14u, 0x20u},\r
+ {0x15u, 0x02u},\r
+ {0x16u, 0x18u},\r
+ {0x17u, 0x09u},\r
+ {0x18u, 0x09u},\r
+ {0x19u, 0x02u},\r
+ {0x1Au, 0x32u},\r
+ {0x1Bu, 0x05u},\r
+ {0x23u, 0x10u},\r
+ {0x26u, 0x40u},\r
+ {0x2Au, 0x80u},\r
+ {0x2Cu, 0x40u},\r
+ {0x2Eu, 0x80u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x38u},\r
+ {0x33u, 0x04u},\r
+ {0x34u, 0x07u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0xC0u},\r
+ {0x37u, 0x03u},\r
+ {0x38u, 0x20u},\r
+ {0x3Au, 0x08u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Eu, 0x40u},\r
+ {0x54u, 0x09u},\r
+ {0x56u, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Cu, 0x90u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x04u},\r
- {0x81u, 0x0Cu},\r
- {0x84u, 0x09u},\r
- {0x85u, 0x40u},\r
- {0x86u, 0x06u},\r
- {0x87u, 0x30u},\r
- {0x8Au, 0x06u},\r
- {0x8Bu, 0x0Cu},\r
- {0x8Cu, 0x06u},\r
- {0x8Du, 0x50u},\r
- {0x8Fu, 0x2Fu},\r
- {0x90u, 0x02u},\r
- {0x91u, 0x0Cu},\r
- {0x94u, 0x01u},\r
- {0x95u, 0x11u},\r
- {0x96u, 0x0Eu},\r
- {0x97u, 0x62u},\r
- {0x99u, 0x04u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x06u},\r
- {0x9Du, 0x0Cu},\r
- {0xA0u, 0x06u},\r
- {0xA1u, 0x08u},\r
- {0xA4u, 0x02u},\r
- {0xA6u, 0x04u},\r
- {0xA8u, 0x07u},\r
- {0xA9u, 0x31u},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x4Eu},\r
- {0xADu, 0x04u},\r
- {0xB3u, 0x0Fu},\r
- {0xB4u, 0x0Fu},\r
- {0xB5u, 0x70u},\r
- {0xB8u, 0x20u},\r
- {0xBBu, 0x20u},\r
- {0xD6u, 0x02u},\r
- {0xD7u, 0x24u},\r
+ {0x84u, 0x06u},\r
+ {0x86u, 0x09u},\r
+ {0x87u, 0xFFu},\r
+ {0x88u, 0x05u},\r
+ {0x89u, 0x50u},\r
+ {0x8Au, 0x0Au},\r
+ {0x8Bu, 0xA0u},\r
+ {0x8Cu, 0x60u},\r
+ {0x8Eu, 0x90u},\r
+ {0x90u, 0x0Fu},\r
+ {0x91u, 0x90u},\r
+ {0x92u, 0xF0u},\r
+ {0x93u, 0x60u},\r
+ {0x94u, 0x50u},\r
+ {0x95u, 0x30u},\r
+ {0x96u, 0xA0u},\r
+ {0x97u, 0xC0u},\r
+ {0x98u, 0x03u},\r
+ {0x99u, 0x09u},\r
+ {0x9Au, 0x0Cu},\r
+ {0x9Bu, 0x06u},\r
+ {0x9Du, 0x0Fu},\r
+ {0x9Fu, 0xF0u},\r
+ {0xA2u, 0xFFu},\r
+ {0xA3u, 0xFFu},\r
+ {0xA4u, 0x30u},\r
+ {0xA5u, 0x03u},\r
+ {0xA6u, 0xC0u},\r
+ {0xA7u, 0x0Cu},\r
+ {0xA8u, 0xFFu},\r
+ {0xA9u, 0x05u},\r
+ {0xABu, 0x0Au},\r
+ {0xAEu, 0xFFu},\r
+ {0xAFu, 0xFFu},\r
+ {0xB3u, 0xFFu},\r
+ {0xB4u, 0xFFu},\r
+ {0xBEu, 0x10u},\r
+ {0xBFu, 0x04u},\r
+ {0xD4u, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
{0x01u, 0x10u},\r
- {0x03u, 0x81u},\r
- {0x05u, 0x11u},\r
- {0x06u, 0x02u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x21u},\r
- {0x0Eu, 0x40u},\r
- {0x0Fu, 0x11u},\r
- {0x10u, 0xA0u},\r
- {0x12u, 0x08u},\r
- {0x14u, 0x18u},\r
- {0x15u, 0x40u},\r
- {0x16u, 0x40u},\r
- {0x18u, 0x04u},\r
+ {0x03u, 0x21u},\r
+ {0x04u, 0x04u},\r
+ {0x05u, 0x80u},\r
+ {0x08u, 0x20u},\r
+ {0x0Au, 0x80u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Cu, 0x10u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x80u},\r
+ {0x11u, 0x04u},\r
+ {0x12u, 0x45u},\r
+ {0x14u, 0x24u},\r
+ {0x17u, 0x40u},\r
{0x19u, 0x20u},\r
- {0x1Au, 0x04u},\r
- {0x1Fu, 0x10u},\r
- {0x22u, 0x0Cu},\r
- {0x23u, 0x04u},\r
- {0x24u, 0x02u},\r
- {0x25u, 0x14u},\r
- {0x27u, 0x04u},\r
- {0x28u, 0x02u},\r
- {0x29u, 0x20u},\r
- {0x2Bu, 0x80u},\r
- {0x2Eu, 0x40u},\r
- {0x2Fu, 0x12u},\r
- {0x30u, 0xA0u},\r
- {0x32u, 0x04u},\r
- {0x33u, 0x01u},\r
- {0x36u, 0x12u},\r
- {0x38u, 0x40u},\r
- {0x39u, 0x11u},\r
- {0x3Bu, 0x04u},\r
- {0x3Cu, 0x80u},\r
- {0x3Du, 0x08u},\r
- {0x3Eu, 0x20u},\r
- {0x62u, 0xC0u},\r
- {0x63u, 0x04u},\r
- {0x68u, 0x21u},\r
- {0x69u, 0x11u},\r
- {0x6Au, 0x01u},\r
- {0x6Bu, 0x01u},\r
- {0x70u, 0xC0u},\r
- {0x78u, 0x10u},\r
- {0x7Bu, 0x08u},\r
- {0x80u, 0x01u},\r
- {0x86u, 0x01u},\r
- {0x88u, 0x20u},\r
- {0x89u, 0x10u},\r
- {0x8Cu, 0x80u},\r
- {0x90u, 0x60u},\r
- {0x91u, 0x40u},\r
- {0x92u, 0x20u},\r
- {0x93u, 0x11u},\r
- {0x94u, 0x80u},\r
- {0x95u, 0x11u},\r
- {0x96u, 0x08u},\r
- {0x97u, 0x08u},\r
- {0x98u, 0x02u},\r
- {0x99u, 0x09u},\r
- {0x9Au, 0x22u},\r
- {0x9Du, 0x20u},\r
- {0x9Eu, 0x15u},\r
- {0x9Fu, 0x05u},\r
- {0xA1u, 0x22u},\r
- {0xA2u, 0x90u},\r
- {0xA3u, 0x04u},\r
- {0xA4u, 0x20u},\r
- {0xA6u, 0x25u},\r
- {0xA7u, 0xAAu},\r
- {0xADu, 0x01u},\r
- {0xB2u, 0x02u},\r
- {0xB4u, 0x04u},\r
- {0xC0u, 0xDFu},\r
- {0xC2u, 0xBDu},\r
- {0xC4u, 0xFEu},\r
- {0xCAu, 0x4Du},\r
- {0xCCu, 0xAFu},\r
- {0xCEu, 0x7Fu},\r
- {0xD8u, 0x04u},\r
- {0xE0u, 0x08u},\r
- {0xE2u, 0x01u},\r
- {0xEAu, 0x32u},\r
- {0xECu, 0x02u},\r
- {0x81u, 0x40u},\r
- {0x82u, 0x40u},\r
- {0x84u, 0x04u},\r
- {0x85u, 0x01u},\r
- {0x88u, 0x08u},\r
- {0x8Au, 0x16u},\r
- {0x8Eu, 0x01u},\r
- {0x8Fu, 0x40u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x06u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x01u},\r
- {0x96u, 0x08u},\r
- {0x9Bu, 0x02u},\r
+ {0x1Cu, 0x04u},\r
+ {0x1Eu, 0x22u},\r
+ {0x1Fu, 0x04u},\r
+ {0x20u, 0x10u},\r
+ {0x24u, 0x08u},\r
+ {0x25u, 0x01u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x02u},\r
+ {0x28u, 0x20u},\r
+ {0x29u, 0x04u},\r
+ {0x2Au, 0x41u},\r
+ {0x2Bu, 0x05u},\r
+ {0x2Du, 0x02u},\r
+ {0x30u, 0x04u},\r
+ {0x32u, 0x44u},\r
+ {0x33u, 0x61u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x02u},\r
+ {0x39u, 0x28u},\r
+ {0x3Au, 0x04u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Du, 0x02u},\r
+ {0x3Fu, 0x20u},\r
+ {0x59u, 0x40u},\r
+ {0x5Cu, 0x0Au},\r
+ {0x5Eu, 0x90u},\r
+ {0x64u, 0x40u},\r
+ {0x67u, 0x02u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Fu, 0x10u},\r
+ {0x91u, 0x3Cu},\r
+ {0x92u, 0x88u},\r
+ {0x93u, 0x02u},\r
+ {0x94u, 0x10u},\r
+ {0x97u, 0x80u},\r
+ {0x99u, 0x04u},\r
+ {0x9Bu, 0x01u},\r
{0x9Cu, 0x40u},\r
- {0x9Du, 0x08u},\r
- {0x9Eu, 0x20u},\r
- {0xA0u, 0x02u},\r
- {0xA2u, 0x80u},\r
- {0xA4u, 0x08u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x10u},\r
- {0xA7u, 0x42u},\r
- {0xABu, 0x04u},\r
- {0xADu, 0x04u},\r
- {0xB0u, 0x40u},\r
- {0xB4u, 0x16u},\r
- {0xB5u, 0x40u},\r
- {0xE0u, 0x80u},\r
- {0xE2u, 0x04u},\r
- {0xE4u, 0x60u},\r
- {0xEAu, 0x33u},\r
- {0xECu, 0x40u},\r
- {0xEEu, 0x20u},\r
- {0x00u, 0x08u},\r
- {0x02u, 0x10u},\r
- {0x08u, 0x01u},\r
+ {0x9Du, 0x20u},\r
+ {0x9Eu, 0x01u},\r
+ {0x9Fu, 0x42u},\r
+ {0xA2u, 0x40u},\r
+ {0xA3u, 0x25u},\r
+ {0xA5u, 0x04u},\r
+ {0xA6u, 0x21u},\r
+ {0xA7u, 0x40u},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0x05u},\r
+ {0xACu, 0x40u},\r
+ {0xAEu, 0x40u},\r
+ {0xB2u, 0x01u},\r
+ {0xB6u, 0x82u},\r
+ {0xB7u, 0x02u},\r
+ {0xC0u, 0xA7u},\r
+ {0xC2u, 0x7Eu},\r
+ {0xC4u, 0xEFu},\r
+ {0xCAu, 0x8Fu},\r
+ {0xCCu, 0xEFu},\r
+ {0xCEu, 0xA6u},\r
+ {0xD6u, 0xF8u},\r
+ {0xD8u, 0x90u},\r
+ {0xE0u, 0x10u},\r
+ {0xE2u, 0x81u},\r
+ {0xE6u, 0x43u},\r
+ {0xE8u, 0x40u},\r
+ {0xEAu, 0x12u},\r
+ {0xECu, 0x10u},\r
+ {0xEEu, 0xC0u},\r
+ {0x00u, 0x0Fu},\r
+ {0x02u, 0xF0u},\r
+ {0x04u, 0x09u},\r
+ {0x06u, 0x06u},\r
+ {0x07u, 0xFFu},\r
+ {0x08u, 0x05u},\r
+ {0x09u, 0x50u},\r
{0x0Au, 0x0Au},\r
- {0x0Cu, 0x02u},\r
- {0x0Du, 0x01u},\r
- {0x0Eu, 0x01u},\r
- {0x0Fu, 0x02u},\r
- {0x14u, 0x02u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x01u},\r
- {0x17u, 0x01u},\r
- {0x18u, 0x02u},\r
- {0x1Au, 0x01u},\r
- {0x1Du, 0x02u},\r
- {0x1Fu, 0x01u},\r
- {0x20u, 0x02u},\r
- {0x21u, 0x02u},\r
- {0x22u, 0x11u},\r
- {0x23u, 0x01u},\r
- {0x29u, 0x02u},\r
- {0x2Au, 0x04u},\r
- {0x2Bu, 0x01u},\r
- {0x30u, 0x04u},\r
- {0x31u, 0x03u},\r
- {0x34u, 0x03u},\r
- {0x36u, 0x18u},\r
- {0x3Au, 0x20u},\r
- {0x3Bu, 0x02u},\r
- {0x3Eu, 0x40u},\r
- {0x56u, 0x08u},\r
+ {0x0Bu, 0xA0u},\r
+ {0x0Cu, 0x90u},\r
+ {0x0Eu, 0x60u},\r
+ {0x10u, 0x03u},\r
+ {0x11u, 0x60u},\r
+ {0x12u, 0x0Cu},\r
+ {0x13u, 0x90u},\r
+ {0x15u, 0x30u},\r
+ {0x16u, 0xFFu},\r
+ {0x17u, 0xC0u},\r
+ {0x18u, 0xFFu},\r
+ {0x19u, 0x06u},\r
+ {0x1Bu, 0x09u},\r
+ {0x1Du, 0x0Fu},\r
+ {0x1Fu, 0xF0u},\r
+ {0x23u, 0xFFu},\r
+ {0x24u, 0x30u},\r
+ {0x25u, 0x03u},\r
+ {0x26u, 0xC0u},\r
+ {0x27u, 0x0Cu},\r
+ {0x28u, 0x50u},\r
+ {0x29u, 0x05u},\r
+ {0x2Au, 0xA0u},\r
+ {0x2Bu, 0x0Au},\r
+ {0x2Cu, 0xFFu},\r
+ {0x2Du, 0xFFu},\r
+ {0x31u, 0xFFu},\r
+ {0x32u, 0xFFu},\r
+ {0x3Eu, 0x04u},\r
+ {0x3Fu, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x10u},\r
- {0x81u, 0x35u},\r
- {0x82u, 0x0Cu},\r
- {0x85u, 0x08u},\r
- {0x87u, 0x34u},\r
- {0x89u, 0x0Au},\r
- {0x8Bu, 0x11u},\r
+ {0x81u, 0x02u},\r
+ {0x84u, 0x04u},\r
+ {0x86u, 0x38u},\r
+ {0x88u, 0x10u},\r
+ {0x8Au, 0x20u},\r
{0x8Cu, 0x10u},\r
- {0x8Du, 0x35u},\r
- {0x8Eu, 0x08u},\r
- {0x91u, 0x02u},\r
- {0x93u, 0x01u},\r
- {0x94u, 0x10u},\r
- {0x95u, 0x05u},\r
- {0x96u, 0x0Au},\r
- {0x97u, 0x0Au},\r
- {0x98u, 0x08u},\r
- {0x99u, 0x35u},\r
- {0x9Au, 0x10u},\r
- {0x9Du, 0x34u},\r
- {0x9Fu, 0x01u},\r
- {0xA9u, 0x35u},\r
- {0xACu, 0x10u},\r
- {0xADu, 0x0Bu},\r
- {0xAEu, 0x09u},\r
- {0xAFu, 0x20u},\r
- {0xB0u, 0x04u},\r
- {0xB2u, 0x01u},\r
- {0xB3u, 0x3Cu},\r
- {0xB4u, 0x18u},\r
- {0xB6u, 0x02u},\r
- {0xB7u, 0x03u},\r
+ {0x8Du, 0x05u},\r
+ {0x8Eu, 0x20u},\r
+ {0x96u, 0x07u},\r
+ {0x98u, 0x09u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x32u},\r
+ {0x9Bu, 0x04u},\r
+ {0x9Eu, 0x30u},\r
+ {0xA0u, 0x30u},\r
+ {0xA1u, 0x01u},\r
+ {0xA3u, 0x04u},\r
+ {0xAAu, 0x08u},\r
+ {0xACu, 0x3Au},\r
+ {0xAEu, 0x05u},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x30u},\r
+ {0xB5u, 0x02u},\r
+ {0xB7u, 0x04u},\r
{0xBAu, 0x20u},\r
- {0xBBu, 0x88u},\r
+ {0xBFu, 0x44u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x09u},\r
+ {0xDCu, 0x91u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x02u},\r
- {0x01u, 0x20u},\r
- {0x03u, 0x02u},\r
- {0x04u, 0x41u},\r
- {0x08u, 0x20u},\r
- {0x09u, 0x08u},\r
+ {0x01u, 0x10u},\r
+ {0x03u, 0x61u},\r
+ {0x05u, 0x90u},\r
+ {0x06u, 0x20u},\r
+ {0x08u, 0x12u},\r
+ {0x09u, 0x04u},\r
{0x0Cu, 0x20u},\r
- {0x0Eu, 0x14u},\r
- {0x10u, 0x04u},\r
- {0x12u, 0x40u},\r
- {0x14u, 0x01u},\r
- {0x18u, 0x02u},\r
- {0x19u, 0xA1u},\r
- {0x1Bu, 0x80u},\r
- {0x1Cu, 0x41u},\r
- {0x1Eu, 0x14u},\r
- {0x20u, 0x80u},\r
+ {0x0Eu, 0x21u},\r
+ {0x10u, 0x09u},\r
+ {0x11u, 0x04u},\r
+ {0x14u, 0x10u},\r
+ {0x15u, 0x08u},\r
+ {0x16u, 0x8Au},\r
+ {0x19u, 0x08u},\r
+ {0x1Du, 0x14u},\r
+ {0x1Eu, 0x24u},\r
{0x21u, 0x01u},\r
- {0x23u, 0x40u},\r
- {0x25u, 0x04u},\r
- {0x27u, 0x02u},\r
- {0x29u, 0x01u},\r
- {0x2Bu, 0x04u},\r
- {0x2Cu, 0x0Au},\r
- {0x30u, 0x04u},\r
- {0x32u, 0x84u},\r
- {0x34u, 0x40u},\r
- {0x35u, 0x08u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x02u},\r
- {0x3Bu, 0x40u},\r
- {0x3Du, 0x09u},\r
- {0x3Eu, 0x20u},\r
+ {0x26u, 0x44u},\r
+ {0x27u, 0x04u},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0x04u},\r
+ {0x2Au, 0x01u},\r
+ {0x2Bu, 0x05u},\r
+ {0x2Fu, 0x40u},\r
+ {0x32u, 0x44u},\r
+ {0x33u, 0x21u},\r
+ {0x36u, 0x20u},\r
+ {0x39u, 0x28u},\r
+ {0x3Eu, 0x01u},\r
{0x3Fu, 0x80u},\r
- {0x58u, 0x10u},\r
- {0x5Au, 0x40u},\r
- {0x5Bu, 0x04u},\r
- {0x5Du, 0x40u},\r
- {0x60u, 0x02u},\r
- {0x62u, 0x18u},\r
- {0x64u, 0x01u},\r
- {0x68u, 0x01u},\r
- {0x6Cu, 0x04u},\r
- {0x6Eu, 0x08u},\r
- {0x6Fu, 0x01u},\r
- {0x83u, 0x02u},\r
- {0x87u, 0x80u},\r
- {0x88u, 0x10u},\r
- {0x8Eu, 0x04u},\r
- {0x92u, 0x40u},\r
- {0x94u, 0x06u},\r
- {0x95u, 0x02u},\r
- {0x97u, 0x40u},\r
- {0x98u, 0x20u},\r
- {0x9Au, 0x40u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0xA0u},\r
- {0x9Eu, 0x10u},\r
+ {0x5Cu, 0x80u},\r
+ {0x66u, 0x40u},\r
+ {0x68u, 0x88u},\r
+ {0x69u, 0x24u},\r
+ {0x6Au, 0x08u},\r
+ {0x6Bu, 0x01u},\r
+ {0x71u, 0x60u},\r
+ {0x72u, 0x50u},\r
+ {0x79u, 0x10u},\r
+ {0x7Bu, 0x04u},\r
+ {0x80u, 0x80u},\r
+ {0x86u, 0x04u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Du, 0x04u},\r
+ {0x91u, 0x08u},\r
+ {0x92u, 0x81u},\r
+ {0x94u, 0x10u},\r
+ {0x95u, 0x22u},\r
+ {0x96u, 0x50u},\r
+ {0x99u, 0x80u},\r
+ {0x9Au, 0x28u},\r
+ {0x9Du, 0x68u},\r
+ {0x9Eu, 0xC2u},\r
{0x9Fu, 0x01u},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0x04u},\r
- {0xA4u, 0x60u},\r
- {0xA6u, 0x0Cu},\r
- {0xAAu, 0x10u},\r
- {0xAFu, 0x20u},\r
- {0xB0u, 0x04u},\r
- {0xB5u, 0x40u},\r
- {0xB6u, 0x50u},\r
- {0xC0u, 0x9Bu},\r
- {0xC2u, 0x66u},\r
- {0xC4u, 0x8Au},\r
- {0xCAu, 0x35u},\r
- {0xCCu, 0xFAu},\r
- {0xCEu, 0xF8u},\r
- {0xD6u, 0x1Eu},\r
- {0xD8u, 0x1Eu},\r
- {0xE2u, 0x44u},\r
- {0xE4u, 0x04u},\r
- {0xE8u, 0x01u},\r
- {0xEAu, 0x10u},\r
- {0xEEu, 0x14u},\r
- {0x00u, 0xD3u},\r
- {0x01u, 0x53u},\r
- {0x02u, 0x20u},\r
- {0x03u, 0x24u},\r
- {0x05u, 0x20u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x02u},\r
- {0x0Cu, 0xC3u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x7Fu},\r
- {0x11u, 0x01u},\r
- {0x13u, 0x02u},\r
- {0x14u, 0x04u},\r
- {0x16u, 0xE3u},\r
- {0x17u, 0x04u},\r
- {0x19u, 0x24u},\r
- {0x1Au, 0x04u},\r
- {0x1Bu, 0x4Bu},\r
- {0x1Cu, 0x40u},\r
- {0x1Eu, 0x80u},\r
- {0x20u, 0x08u},\r
- {0x22u, 0xC3u},\r
- {0x23u, 0x10u},\r
- {0x24u, 0x40u},\r
- {0x26u, 0x80u},\r
- {0x28u, 0x01u},\r
+ {0xA0u, 0x20u},\r
+ {0xA3u, 0x25u},\r
+ {0xA4u, 0x80u},\r
+ {0xA5u, 0x20u},\r
+ {0xA6u, 0x01u},\r
+ {0xA8u, 0x81u},\r
+ {0xAFu, 0x80u},\r
+ {0xB0u, 0x20u},\r
+ {0xB1u, 0x08u},\r
+ {0xC0u, 0xEFu},\r
+ {0xC2u, 0xEEu},\r
+ {0xC4u, 0xD7u},\r
+ {0xCAu, 0x8Fu},\r
+ {0xCCu, 0x2Fu},\r
+ {0xCEu, 0x96u},\r
+ {0xD6u, 0x10u},\r
+ {0xD8u, 0x10u},\r
+ {0xE2u, 0x20u},\r
+ {0xE6u, 0x27u},\r
+ {0xECu, 0x20u},\r
+ {0xEEu, 0x02u},\r
+ {0x00u, 0x03u},\r
+ {0x04u, 0x10u},\r
+ {0x06u, 0x23u},\r
+ {0x0Au, 0x20u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Cu, 0x2Bu},\r
+ {0x0Du, 0x0Au},\r
+ {0x0Eu, 0x14u},\r
+ {0x0Fu, 0x05u},\r
+ {0x13u, 0x20u},\r
+ {0x14u, 0x24u},\r
+ {0x16u, 0x0Bu},\r
+ {0x1Au, 0x5Cu},\r
+ {0x1Bu, 0x17u},\r
+ {0x1Eu, 0x03u},\r
+ {0x20u, 0x01u},\r
+ {0x22u, 0x02u},\r
+ {0x24u, 0x01u},\r
+ {0x25u, 0x09u},\r
+ {0x26u, 0x02u},\r
+ {0x27u, 0x02u},\r
{0x29u, 0x04u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x1Bu},\r
- {0x2Cu, 0x14u},\r
- {0x2Du, 0x0Bu},\r
- {0x2Eu, 0xE3u},\r
- {0x32u, 0x3Cu},\r
- {0x33u, 0x7Cu},\r
- {0x34u, 0x03u},\r
+ {0x2Au, 0x80u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Cu, 0x40u},\r
+ {0x2Du, 0x10u},\r
+ {0x2Eu, 0x80u},\r
+ {0x2Fu, 0x20u},\r
+ {0x32u, 0x03u},\r
+ {0x34u, 0x3Cu},\r
+ {0x35u, 0x0Fu},\r
{0x36u, 0xC0u},\r
- {0x37u, 0x03u},\r
- {0x38u, 0x08u},\r
- {0x3Au, 0xA0u},\r
- {0x3Bu, 0x80u},\r
+ {0x37u, 0x30u},\r
+ {0x3Au, 0x08u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x40u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Fu, 0x01u},\r
- {0x83u, 0xFFu},\r
- {0x85u, 0x69u},\r
- {0x87u, 0x96u},\r
- {0x88u, 0x55u},\r
- {0x8Au, 0xAAu},\r
- {0x8Cu, 0xFFu},\r
- {0x90u, 0x33u},\r
- {0x91u, 0x0Fu},\r
- {0x92u, 0xCCu},\r
- {0x93u, 0xF0u},\r
- {0x96u, 0xFFu},\r
- {0x97u, 0xFFu},\r
- {0x98u, 0x0Fu},\r
- {0x99u, 0x55u},\r
- {0x9Au, 0xF0u},\r
- {0x9Bu, 0xAAu},\r
- {0xA0u, 0xFFu},\r
- {0xA1u, 0xFFu},\r
- {0xA4u, 0x96u},\r
- {0xA5u, 0x33u},\r
- {0xA6u, 0x69u},\r
- {0xA7u, 0xCCu},\r
- {0xAAu, 0xFFu},\r
- {0xABu, 0xFFu},\r
- {0xADu, 0xFFu},\r
- {0xAEu, 0xFFu},\r
- {0xB1u, 0xFFu},\r
- {0xB4u, 0xFFu},\r
- {0xBAu, 0x20u},\r
- {0xBBu, 0x02u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x01u, 0x90u},\r
- {0x02u, 0x08u},\r
- {0x05u, 0x91u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x14u},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x0Au},\r
- {0x10u, 0x40u},\r
- {0x13u, 0x64u},\r
- {0x15u, 0x82u},\r
- {0x16u, 0x14u},\r
- {0x17u, 0x10u},\r
- {0x1Au, 0x04u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0x12u},\r
- {0x1Fu, 0xA8u},\r
- {0x22u, 0x02u},\r
- {0x24u, 0x20u},\r
- {0x25u, 0x0Cu},\r
- {0x27u, 0x22u},\r
- {0x28u, 0x40u},\r
- {0x29u, 0x81u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x18u},\r
- {0x2Du, 0x82u},\r
- {0x2Fu, 0x08u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x02u},\r
- {0x33u, 0x10u},\r
- {0x36u, 0x04u},\r
- {0x37u, 0x22u},\r
- {0x39u, 0x0Au},\r
- {0x3Cu, 0x80u},\r
- {0x3Du, 0x10u},\r
- {0x3Eu, 0x0Au},\r
- {0x58u, 0x04u},\r
- {0x5Au, 0x20u},\r
- {0x5Bu, 0x40u},\r
- {0x62u, 0x44u},\r
- {0x63u, 0x04u},\r
- {0x80u, 0x04u},\r
- {0x82u, 0x80u},\r
- {0x83u, 0x40u},\r
- {0x86u, 0x40u},\r
- {0x89u, 0x04u},\r
- {0x8Bu, 0x03u},\r
- {0x8Du, 0x01u},\r
- {0x8Fu, 0x04u},\r
- {0x94u, 0x22u},\r
- {0x95u, 0x02u},\r
- {0x96u, 0x14u},\r
- {0x98u, 0x20u},\r
- {0x99u, 0x02u},\r
- {0x9Au, 0x0Au},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0xA0u},\r
+ {0x81u, 0x10u},\r
+ {0x84u, 0x06u},\r
+ {0x85u, 0x01u},\r
+ {0x86u, 0x09u},\r
+ {0x87u, 0x02u},\r
+ {0x89u, 0x10u},\r
+ {0x8Cu, 0x0Fu},\r
+ {0x8Du, 0x23u},\r
+ {0x8Eu, 0xF0u},\r
+ {0x8Fu, 0x4Cu},\r
+ {0x90u, 0x30u},\r
+ {0x92u, 0xC0u},\r
+ {0x93u, 0x40u},\r
+ {0x94u, 0x50u},\r
+ {0x96u, 0xA0u},\r
+ {0x98u, 0x60u},\r
+ {0x9Au, 0x90u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Du, 0x08u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA1u, 0x02u},\r
+ {0xA3u, 0x01u},\r
+ {0xA4u, 0x03u},\r
+ {0xA5u, 0x10u},\r
+ {0xA6u, 0x0Cu},\r
+ {0xA8u, 0x05u},\r
+ {0xA9u, 0x10u},\r
+ {0xAAu, 0x0Au},\r
+ {0xADu, 0x04u},\r
+ {0xAFu, 0x08u},\r
+ {0xB0u, 0xFFu},\r
+ {0xB1u, 0x10u},\r
+ {0xB3u, 0x0Fu},\r
+ {0xB5u, 0x60u},\r
+ {0xB9u, 0x02u},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x15u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x40u},\r
+ {0x05u, 0x10u},\r
+ {0x06u, 0xA2u},\r
+ {0x08u, 0x08u},\r
+ {0x09u, 0x20u},\r
+ {0x0Au, 0x50u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x09u},\r
+ {0x0Fu, 0x08u},\r
+ {0x12u, 0x18u},\r
+ {0x13u, 0x08u},\r
+ {0x14u, 0x10u},\r
+ {0x15u, 0xA0u},\r
+ {0x16u, 0x40u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Eu, 0x08u},\r
+ {0x1Fu, 0x08u},\r
+ {0x20u, 0x08u},\r
+ {0x21u, 0x04u},\r
+ {0x22u, 0x01u},\r
+ {0x24u, 0x0Au},\r
+ {0x26u, 0x20u},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0x68u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Cu, 0x24u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Eu, 0x20u},\r
+ {0x30u, 0x80u},\r
+ {0x33u, 0x21u},\r
+ {0x34u, 0x01u},\r
+ {0x36u, 0x20u},\r
+ {0x38u, 0x18u},\r
+ {0x39u, 0xC2u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Fu, 0x20u},\r
+ {0x5Cu, 0x80u},\r
+ {0x5Du, 0x05u},\r
+ {0x5Eu, 0x20u},\r
+ {0x64u, 0x02u},\r
+ {0x78u, 0x02u},\r
+ {0x7Au, 0x80u},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x01u},\r
+ {0x87u, 0x08u},\r
+ {0x88u, 0x05u},\r
+ {0x8Bu, 0x08u},\r
+ {0x90u, 0x04u},\r
+ {0x91u, 0x84u},\r
+ {0x92u, 0x81u},\r
+ {0x96u, 0x42u},\r
+ {0x98u, 0x04u},\r
+ {0x99u, 0x90u},\r
+ {0x9Au, 0x08u},\r
+ {0x9Cu, 0x08u},\r
{0x9Eu, 0x10u},\r
- {0xA1u, 0x01u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0x20u},\r
- {0xA5u, 0x04u},\r
- {0xA6u, 0x06u},\r
- {0xA7u, 0xA0u},\r
- {0xAAu, 0x40u},\r
- {0xABu, 0x04u},\r
- {0xACu, 0x40u},\r
- {0xADu, 0x20u},\r
- {0xAEu, 0x04u},\r
- {0xB2u, 0x02u},\r
- {0xB3u, 0x0Cu},\r
- {0xB4u, 0x20u},\r
- {0xB6u, 0x20u},\r
- {0xB7u, 0x02u},\r
- {0xC0u, 0xD3u},\r
+ {0xA1u, 0x40u},\r
+ {0xA2u, 0x98u},\r
+ {0xA3u, 0x30u},\r
+ {0xA4u, 0xA0u},\r
+ {0xA5u, 0x28u},\r
+ {0xA6u, 0x01u},\r
+ {0xA7u, 0x80u},\r
+ {0xAAu, 0x01u},\r
+ {0xABu, 0x01u},\r
+ {0xACu, 0x04u},\r
+ {0xADu, 0x41u},\r
+ {0xAEu, 0x05u},\r
+ {0xB2u, 0x10u},\r
+ {0xB4u, 0x80u},\r
+ {0xB7u, 0x40u},\r
+ {0xC0u, 0xF5u},\r
{0xC2u, 0xEEu},\r
- {0xC4u, 0xFFu},\r
- {0xCAu, 0xBFu},\r
- {0xCCu, 0xE7u},\r
- {0xCEu, 0xF3u},\r
- {0xD6u, 0x0Eu},\r
- {0xD8u, 0x0Eu},\r
- {0xE0u, 0x40u},\r
- {0xE2u, 0x30u},\r
+ {0xC4u, 0xF6u},\r
+ {0xCAu, 0x7Fu},\r
+ {0xCCu, 0xADu},\r
+ {0xCEu, 0x3Fu},\r
+ {0xD6u, 0xF0u},\r
+ {0xD8u, 0x10u},\r
{0xE4u, 0x80u},\r
- {0xE6u, 0x2Bu},\r
- {0xE8u, 0x40u},\r
- {0xEAu, 0x95u},\r
- {0xECu, 0x40u},\r
- {0xEEu, 0x80u},\r
- {0x01u, 0x3Fu},\r
- {0x04u, 0x69u},\r
- {0x05u, 0x3Fu},\r
- {0x06u, 0x96u},\r
- {0x08u, 0x0Fu},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0xF0u},\r
- {0x0Bu, 0x02u},\r
- {0x0Cu, 0xFFu},\r
- {0x0Fu, 0x3Fu},\r
- {0x14u, 0x55u},\r
- {0x16u, 0xAAu},\r
- {0x17u, 0x3Fu},\r
- {0x18u, 0xFFu},\r
- {0x1Bu, 0x3Fu},\r
- {0x1Cu, 0x33u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0xCCu},\r
- {0x1Fu, 0x20u},\r
- {0x21u, 0x04u},\r
- {0x22u, 0xFFu},\r
+ {0xE6u, 0x21u},\r
+ {0xE8u, 0x80u},\r
+ {0xECu, 0x09u},\r
+ {0xEEu, 0xC0u},\r
+ {0x00u, 0x80u},\r
+ {0x02u, 0x40u},\r
+ {0x06u, 0x1Cu},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Du, 0x0Au},\r
+ {0x0Eu, 0x41u},\r
+ {0x0Fu, 0x14u},\r
+ {0x14u, 0x24u},\r
+ {0x16u, 0x08u},\r
+ {0x18u, 0x80u},\r
+ {0x1Au, 0x40u},\r
+ {0x1Bu, 0x04u},\r
+ {0x1Cu, 0x40u},\r
+ {0x1Eu, 0x80u},\r
+ {0x1Fu, 0x10u},\r
+ {0x20u, 0x80u},\r
+ {0x22u, 0x42u},\r
{0x23u, 0x08u},\r
- {0x25u, 0x10u},\r
- {0x26u, 0xFFu},\r
- {0x27u, 0x20u},\r
- {0x29u, 0x04u},\r
- {0x2Au, 0xFFu},\r
- {0x2Bu, 0x08u},\r
- {0x2Du, 0x01u},\r
- {0x2Fu, 0x02u},\r
- {0x32u, 0xFFu},\r
- {0x33u, 0x0Cu},\r
- {0x35u, 0x03u},\r
- {0x37u, 0x30u},\r
- {0x3Au, 0x08u},\r
- {0x3Bu, 0xA8u},\r
+ {0x26u, 0x20u},\r
+ {0x27u, 0x02u},\r
+ {0x28u, 0x10u},\r
+ {0x2Au, 0x20u},\r
+ {0x2Cu, 0x28u},\r
+ {0x2Eu, 0x14u},\r
+ {0x2Fu, 0x01u},\r
+ {0x30u, 0x01u},\r
+ {0x31u, 0x01u},\r
+ {0x32u, 0x3Cu},\r
+ {0x33u, 0x18u},\r
+ {0x34u, 0x02u},\r
+ {0x36u, 0xC0u},\r
+ {0x37u, 0x06u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Fu, 0x44u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0xE0u},\r
- {0x83u, 0x70u},\r
- {0x84u, 0x14u},\r
- {0x85u, 0x40u},\r
- {0x87u, 0x1Fu},\r
- {0x88u, 0x09u},\r
- {0x89u, 0x10u},\r
- {0x8Au, 0xF2u},\r
- {0x8Bu, 0x2Fu},\r
- {0x91u, 0x03u},\r
- {0x92u, 0x09u},\r
- {0x93u, 0x0Cu},\r
- {0x94u, 0x06u},\r
- {0x95u, 0x0Fu},\r
- {0x96u, 0xF8u},\r
- {0x98u, 0x40u},\r
- {0x99u, 0x20u},\r
- {0x9Au, 0x80u},\r
- {0x9Bu, 0x4Fu},\r
- {0x9Cu, 0x40u},\r
- {0x9Eu, 0x80u},\r
- {0xA2u, 0xFFu},\r
- {0xA5u, 0x06u},\r
- {0xA7u, 0x09u},\r
- {0xA8u, 0x01u},\r
- {0xA9u, 0x05u},\r
- {0xABu, 0x0Au},\r
- {0xACu, 0xC6u},\r
- {0xAEu, 0x19u},\r
- {0xB1u, 0x7Fu},\r
- {0xB2u, 0x3Fu},\r
- {0xB4u, 0xC0u},\r
- {0xBAu, 0x20u},\r
+ {0x81u, 0x44u},\r
+ {0x83u, 0x08u},\r
+ {0x86u, 0x10u},\r
+ {0x87u, 0x17u},\r
+ {0x8Bu, 0x40u},\r
+ {0x8Cu, 0x0Au},\r
+ {0x8Du, 0x4Au},\r
+ {0x8Eu, 0x05u},\r
+ {0x8Fu, 0x05u},\r
+ {0x91u, 0x10u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x20u},\r
+ {0x94u, 0x09u},\r
+ {0x96u, 0x02u},\r
+ {0x97u, 0x20u},\r
+ {0x9Au, 0x07u},\r
+ {0xA0u, 0x04u},\r
+ {0xA2u, 0x08u},\r
+ {0xA5u, 0x49u},\r
+ {0xA7u, 0x02u},\r
+ {0xAAu, 0x08u},\r
+ {0xABu, 0x08u},\r
+ {0xACu, 0x10u},\r
+ {0xAEu, 0x20u},\r
+ {0xB0u, 0x30u},\r
+ {0xB1u, 0x30u},\r
+ {0xB3u, 0x0Fu},\r
+ {0xB4u, 0x0Fu},\r
+ {0xB7u, 0x40u},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x41u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
{0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x80u},\r
- {0x02u, 0x10u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x22u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x20u},\r
- {0x08u, 0x08u},\r
- {0x0Bu, 0x09u},\r
- {0x0Cu, 0x08u},\r
- {0x0Du, 0x20u},\r
- {0x0Eu, 0x90u},\r
- {0x0Fu, 0x02u},\r
- {0x10u, 0x08u},\r
- {0x11u, 0x08u},\r
- {0x12u, 0x40u},\r
- {0x14u, 0x04u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x42u},\r
- {0x1Bu, 0x08u},\r
- {0x1Du, 0x20u},\r
- {0x1Eu, 0x20u},\r
- {0x1Fu, 0x04u},\r
- {0x21u, 0x10u},\r
- {0x22u, 0x44u},\r
- {0x23u, 0x0Au},\r
- {0x25u, 0x01u},\r
- {0x28u, 0x4Au},\r
- {0x2Bu, 0x10u},\r
- {0x2Eu, 0x04u},\r
- {0x2Fu, 0x08u},\r
- {0x30u, 0x08u},\r
- {0x31u, 0x10u},\r
- {0x32u, 0x40u},\r
- {0x34u, 0x04u},\r
- {0x36u, 0x16u},\r
- {0x38u, 0x02u},\r
- {0x39u, 0x20u},\r
- {0x3Au, 0x40u},\r
- {0x3Bu, 0x08u},\r
- {0x3Du, 0x0Au},\r
- {0x3Eu, 0x10u},\r
- {0x58u, 0x10u},\r
- {0x5Au, 0x40u},\r
- {0x5Bu, 0x04u},\r
- {0x60u, 0x08u},\r
- {0x63u, 0x23u},\r
- {0x81u, 0x20u},\r
- {0x86u, 0x48u},\r
- {0x87u, 0x80u},\r
- {0x88u, 0x30u},\r
- {0x89u, 0x02u},\r
- {0x8Fu, 0x20u},\r
- {0xC0u, 0x77u},\r
- {0xC2u, 0xF7u},\r
- {0xC4u, 0xDEu},\r
- {0xCAu, 0x6Fu},\r
- {0xCCu, 0xEEu},\r
- {0xCEu, 0xEFu},\r
- {0xD6u, 0x0Eu},\r
- {0xD8u, 0x0Eu},\r
- {0xE0u, 0x80u},\r
- {0xE2u, 0x40u},\r
- {0xE4u, 0x04u},\r
- {0xE6u, 0x20u},\r
- {0x02u, 0x02u},\r
- {0x06u, 0x30u},\r
- {0x08u, 0x04u},\r
+ {0x00u, 0x84u},\r
+ {0x01u, 0x08u},\r
+ {0x02u, 0x40u},\r
+ {0x04u, 0x40u},\r
+ {0x06u, 0x10u},\r
{0x09u, 0x08u},\r
- {0x0Au, 0x08u},\r
- {0x0Bu, 0x22u},\r
- {0x0Cu, 0x01u},\r
- {0x0Eu, 0x02u},\r
- {0x10u, 0x20u},\r
- {0x11u, 0x14u},\r
- {0x12u, 0x0Cu},\r
- {0x13u, 0x08u},\r
- {0x14u, 0x10u},\r
- {0x15u, 0x09u},\r
- {0x16u, 0x0Cu},\r
- {0x17u, 0x10u},\r
- {0x19u, 0x37u},\r
- {0x1Au, 0x01u},\r
- {0x1Eu, 0x04u},\r
- {0x27u, 0x07u},\r
- {0x2Au, 0x48u},\r
- {0x30u, 0x03u},\r
- {0x34u, 0x3Cu},\r
- {0x35u, 0x38u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x07u},\r
- {0x39u, 0x20u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x40u},\r
- {0x40u, 0x24u},\r
+ {0x0Au, 0x05u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x48u},\r
+ {0x10u, 0x54u},\r
+ {0x11u, 0x80u},\r
+ {0x15u, 0x85u},\r
+ {0x16u, 0x24u},\r
+ {0x19u, 0x0Au},\r
+ {0x1Au, 0x05u},\r
+ {0x1Bu, 0x40u},\r
+ {0x1Eu, 0x08u},\r
+ {0x1Fu, 0x21u},\r
+ {0x20u, 0x82u},\r
+ {0x22u, 0x04u},\r
+ {0x25u, 0x06u},\r
+ {0x26u, 0x88u},\r
+ {0x29u, 0x08u},\r
+ {0x2Au, 0x40u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Cu, 0x60u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Eu, 0x10u},\r
+ {0x30u, 0x80u},\r
+ {0x31u, 0x20u},\r
+ {0x34u, 0x08u},\r
+ {0x37u, 0x01u},\r
+ {0x39u, 0x80u},\r
+ {0x3Cu, 0x40u},\r
+ {0x3Du, 0x89u},\r
+ {0x3Eu, 0x20u},\r
+ {0x58u, 0x80u},\r
+ {0x5Du, 0x40u},\r
+ {0x62u, 0x40u},\r
+ {0x64u, 0x02u},\r
+ {0x65u, 0x80u},\r
+ {0x69u, 0x80u},\r
+ {0x6Au, 0x80u},\r
+ {0x6Bu, 0x01u},\r
+ {0x81u, 0x40u},\r
+ {0x82u, 0x24u},\r
+ {0x83u, 0x10u},\r
+ {0x84u, 0x01u},\r
+ {0x85u, 0x02u},\r
+ {0x86u, 0x08u},\r
+ {0x88u, 0x10u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Du, 0x10u},\r
+ {0x8Eu, 0x10u},\r
+ {0xC0u, 0xADu},\r
+ {0xC2u, 0x77u},\r
+ {0xC4u, 0xDFu},\r
+ {0xCAu, 0x6Bu},\r
+ {0xCCu, 0xCCu},\r
+ {0xCEu, 0xF8u},\r
+ {0xD6u, 0x18u},\r
+ {0xD8u, 0x18u},\r
+ {0xE0u, 0x60u},\r
+ {0xE2u, 0x10u},\r
+ {0xE4u, 0x10u},\r
+ {0xE6u, 0x04u},\r
+ {0x01u, 0x5Cu},\r
+ {0x05u, 0x11u},\r
+ {0x07u, 0x22u},\r
+ {0x09u, 0x50u},\r
+ {0x0Bu, 0x0Cu},\r
+ {0x0Du, 0x0Cu},\r
+ {0x0Fu, 0x50u},\r
+ {0x15u, 0x30u},\r
+ {0x17u, 0x0Fu},\r
+ {0x19u, 0x54u},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Du, 0x5Cu},\r
+ {0x21u, 0x08u},\r
+ {0x27u, 0x40u},\r
+ {0x29u, 0x21u},\r
+ {0x2Bu, 0x1Eu},\r
+ {0x2Du, 0x24u},\r
+ {0x2Fu, 0x10u},\r
+ {0x31u, 0x30u},\r
+ {0x33u, 0x40u},\r
+ {0x35u, 0x0Fu},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Fu, 0x04u},\r
+ {0x40u, 0x23u},\r
{0x41u, 0x06u},\r
- {0x42u, 0x30u},\r
+ {0x42u, 0x40u},\r
{0x44u, 0x01u},\r
- {0x45u, 0xFEu},\r
- {0x46u, 0xDCu},\r
- {0x47u, 0x0Bu},\r
- {0x48u, 0x1Fu},\r
+ {0x45u, 0xBDu},\r
+ {0x46u, 0xF0u},\r
+ {0x47u, 0xCEu},\r
+ {0x48u, 0x3Bu},\r
{0x49u, 0xFFu},\r
{0x4Au, 0xFFu},\r
{0x4Bu, 0xFFu},\r
{0x4Eu, 0xF0u},\r
{0x4Fu, 0x08u},\r
{0x50u, 0x04u},\r
- {0x58u, 0x04u},\r
+ {0x54u, 0x40u},\r
+ {0x56u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Au, 0x04u},\r
+ {0x5Bu, 0x04u},\r
{0x5Fu, 0x01u},\r
{0x62u, 0xC0u},\r
{0x64u, 0x40u},\r
{0x6Du, 0x01u},\r
{0x6Eu, 0x40u},\r
{0x6Fu, 0x01u},\r
- {0x81u, 0x02u},\r
- {0x83u, 0x09u},\r
- {0x8Du, 0x02u},\r
- {0x8Fu, 0x01u},\r
- {0x91u, 0x02u},\r
- {0x93u, 0x11u},\r
- {0x95u, 0x02u},\r
- {0x97u, 0x05u},\r
- {0x99u, 0x01u},\r
- {0x9Bu, 0x02u},\r
- {0xA8u, 0x01u},\r
- {0xB1u, 0x10u},\r
- {0xB2u, 0x01u},\r
- {0xB3u, 0x03u},\r
- {0xB5u, 0x08u},\r
- {0xB7u, 0x04u},\r
- {0xBBu, 0x08u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x99u},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x01u, 0x40u},\r
- {0x02u, 0x08u},\r
- {0x03u, 0x40u},\r
- {0x08u, 0x28u},\r
- {0x09u, 0x02u},\r
- {0x0Au, 0x02u},\r
- {0x10u, 0x08u},\r
- {0x17u, 0x20u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x01u},\r
- {0x1Au, 0x02u},\r
- {0x1Bu, 0x10u},\r
- {0x1Fu, 0x04u},\r
- {0x21u, 0x40u},\r
- {0x22u, 0x10u},\r
- {0x24u, 0x40u},\r
- {0x26u, 0x04u},\r
- {0x27u, 0x2Au},\r
- {0x2Bu, 0x10u},\r
- {0x31u, 0x02u},\r
- {0x32u, 0x18u},\r
- {0x37u, 0x2Au},\r
- {0x39u, 0x20u},\r
- {0x3Cu, 0x40u},\r
- {0x3Fu, 0x01u},\r
- {0x40u, 0x0Au},\r
- {0x41u, 0x12u},\r
- {0x42u, 0x14u},\r
- {0x49u, 0x04u},\r
- {0x4Au, 0x88u},\r
- {0x50u, 0x08u},\r
- {0x53u, 0x90u},\r
- {0x5Cu, 0x80u},\r
- {0x67u, 0x01u},\r
- {0x6Eu, 0x02u},\r
- {0x6Fu, 0x2Au},\r
- {0x76u, 0x25u},\r
- {0x77u, 0x40u},\r
- {0x84u, 0x88u},\r
- {0x8Au, 0x80u},\r
+ {0x80u, 0x20u},\r
+ {0x82u, 0x01u},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x04u},\r
+ {0x86u, 0x42u},\r
+ {0x87u, 0x23u},\r
+ {0x89u, 0x48u},\r
+ {0x8Bu, 0x03u},\r
{0x8Cu, 0x02u},\r
- {0x8Du, 0x41u},\r
- {0x91u, 0x40u},\r
- {0x92u, 0x14u},\r
- {0x97u, 0x28u},\r
- {0x98u, 0x20u},\r
- {0x9Du, 0x04u},\r
- {0x9Eu, 0x25u},\r
- {0x9Fu, 0x40u},\r
- {0xA1u, 0x02u},\r
- {0xA2u, 0x08u},\r
- {0xA6u, 0x05u},\r
- {0xA7u, 0xAAu},\r
- {0xAAu, 0x10u},\r
- {0xABu, 0x80u},\r
- {0xB2u, 0x04u},\r
- {0xB5u, 0x08u},\r
- {0xB6u, 0x01u},\r
- {0xC0u, 0x0Fu},\r
- {0xC2u, 0x0Fu},\r
- {0xC4u, 0x42u},\r
- {0xCAu, 0x02u},\r
- {0xCCu, 0xE7u},\r
- {0xCEu, 0x94u},\r
- {0xD0u, 0x0Fu},\r
- {0xD2u, 0x04u},\r
- {0xD6u, 0x10u},\r
- {0xD8u, 0x10u},\r
- {0xE0u, 0x12u},\r
- {0xE6u, 0x52u},\r
- {0xEAu, 0x04u},\r
- {0x00u, 0x0Fu},\r
- {0x01u, 0x05u},\r
- {0x02u, 0xF0u},\r
- {0x03u, 0x0Au},\r
- {0x07u, 0xFFu},\r
- {0x08u, 0xFFu},\r
- {0x09u, 0x03u},\r
- {0x0Bu, 0x0Cu},\r
- {0x0Cu, 0x60u},\r
- {0x0Du, 0x0Fu},\r
- {0x0Eu, 0x90u},\r
- {0x0Fu, 0xF0u},\r
- {0x11u, 0xFFu},\r
- {0x12u, 0xFFu},\r
- {0x14u, 0x03u},\r
- {0x16u, 0x0Cu},\r
- {0x19u, 0xFFu},\r
- {0x1Au, 0xFFu},\r
- {0x1Cu, 0x05u},\r
- {0x1Du, 0x09u},\r
- {0x1Eu, 0x0Au},\r
- {0x1Fu, 0x06u},\r
- {0x20u, 0x06u},\r
- {0x22u, 0x09u},\r
- {0x24u, 0x30u},\r
- {0x25u, 0x30u},\r
- {0x26u, 0xC0u},\r
- {0x27u, 0xC0u},\r
- {0x28u, 0x50u},\r
- {0x29u, 0x50u},\r
- {0x2Au, 0xA0u},\r
- {0x2Bu, 0xA0u},\r
- {0x2Du, 0x90u},\r
- {0x2Fu, 0x60u},\r
- {0x30u, 0xFFu},\r
- {0x31u, 0xFFu},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x01u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Fu, 0x01u},\r
- {0x82u, 0x0Au},\r
- {0x85u, 0x60u},\r
- {0x87u, 0x90u},\r
- {0x88u, 0x01u},\r
- {0x89u, 0x05u},\r
- {0x8Au, 0x04u},\r
- {0x8Bu, 0x0Au},\r
- {0x8Du, 0x0Fu},\r
- {0x8Fu, 0xF0u},\r
- {0x90u, 0x01u},\r
- {0x92u, 0x04u},\r
- {0x96u, 0x02u},\r
- {0x98u, 0x05u},\r
- {0x99u, 0x06u},\r
- {0x9Bu, 0x09u},\r
- {0x9Cu, 0x0Au},\r
- {0x9Du, 0x30u},\r
- {0x9Fu, 0xC0u},\r
- {0xA0u, 0x0Au},\r
- {0xA4u, 0x0Au},\r
- {0xA5u, 0x03u},\r
- {0xA7u, 0x0Cu},\r
- {0xA8u, 0x0Au},\r
- {0xA9u, 0x50u},\r
- {0xABu, 0xA0u},\r
- {0xB0u, 0x04u},\r
- {0xB2u, 0x08u},\r
- {0xB4u, 0x02u},\r
- {0xB5u, 0xFFu},\r
- {0xB6u, 0x01u},\r
- {0xBEu, 0x55u},\r
- {0xBFu, 0x10u},\r
- {0xD4u, 0x09u},\r
- {0xD6u, 0x04u},\r
+ {0x90u, 0x02u},\r
+ {0x91u, 0x80u},\r
+ {0x94u, 0x44u},\r
+ {0x96u, 0x10u},\r
+ {0x97u, 0x7Cu},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x11u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Cu, 0x02u},\r
+ {0xA0u, 0x08u},\r
+ {0xA3u, 0x02u},\r
+ {0xA5u, 0x80u},\r
+ {0xA8u, 0x0Eu},\r
+ {0xA9u, 0x70u},\r
+ {0xAAu, 0x30u},\r
+ {0xACu, 0x02u},\r
+ {0xAFu, 0x01u},\r
+ {0xB0u, 0x01u},\r
+ {0xB3u, 0x70u},\r
+ {0xB4u, 0x7Eu},\r
+ {0xB5u, 0x0Fu},\r
+ {0xB7u, 0x80u},\r
+ {0xB8u, 0x20u},\r
+ {0xB9u, 0x80u},\r
+ {0xBEu, 0x10u},\r
+ {0xBFu, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x02u},\r
- {0x02u, 0x08u},\r
- {0x05u, 0x90u},\r
- {0x06u, 0x80u},\r
- {0x09u, 0x0Au},\r
- {0x0Au, 0x05u},\r
- {0x0Bu, 0x20u},\r
- {0x0Cu, 0x01u},\r
- {0x0Fu, 0x19u},\r
- {0x10u, 0xA0u},\r
- {0x11u, 0x10u},\r
- {0x14u, 0x44u},\r
- {0x15u, 0x04u},\r
- {0x18u, 0x10u},\r
- {0x19u, 0x40u},\r
- {0x1Au, 0x58u},\r
- {0x1Cu, 0x80u},\r
+ {0x04u, 0x04u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x02u},\r
+ {0x0Cu, 0xA1u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Fu, 0x40u},\r
+ {0x15u, 0x60u},\r
+ {0x17u, 0x02u},\r
+ {0x1Fu, 0x22u},\r
+ {0x20u, 0x18u},\r
+ {0x21u, 0x10u},\r
{0x22u, 0x20u},\r
- {0x26u, 0x02u},\r
- {0x28u, 0x20u},\r
- {0x29u, 0x08u},\r
- {0x2Au, 0x30u},\r
- {0x2Cu, 0x04u},\r
- {0x2Du, 0x84u},\r
- {0x2Fu, 0x2Au},\r
- {0x31u, 0x20u},\r
- {0x33u, 0x40u},\r
- {0x34u, 0x41u},\r
- {0x35u, 0x11u},\r
- {0x36u, 0xA0u},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x40u},\r
- {0x3Au, 0x84u},\r
- {0x3Du, 0x40u},\r
- {0x3Fu, 0x19u},\r
- {0x58u, 0x02u},\r
- {0x59u, 0x04u},\r
- {0x5Au, 0x60u},\r
- {0x61u, 0x40u},\r
- {0x63u, 0x40u},\r
- {0x80u, 0x12u},\r
- {0x87u, 0x40u},\r
- {0x8Du, 0x40u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x50u},\r
- {0x92u, 0x05u},\r
- {0x93u, 0x11u},\r
- {0x97u, 0x08u},\r
- {0x99u, 0x09u},\r
- {0x9Du, 0x10u},\r
- {0x9Eu, 0x15u},\r
- {0xA0u, 0xA1u},\r
- {0xA1u, 0x22u},\r
- {0xA2u, 0x88u},\r
+ {0x23u, 0x44u},\r
+ {0x26u, 0x84u},\r
+ {0x27u, 0x0Au},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0x04u},\r
+ {0x2Au, 0x01u},\r
+ {0x2Bu, 0x04u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0x22u},\r
+ {0x30u, 0xA0u},\r
+ {0x31u, 0x08u},\r
+ {0x36u, 0x21u},\r
+ {0x37u, 0x08u},\r
+ {0x39u, 0x50u},\r
+ {0x3Au, 0x02u},\r
+ {0x3Bu, 0x04u},\r
+ {0x3Cu, 0x24u},\r
+ {0x40u, 0x04u},\r
+ {0x41u, 0x09u},\r
+ {0x42u, 0x01u},\r
+ {0x48u, 0x04u},\r
+ {0x49u, 0x06u},\r
+ {0x51u, 0x20u},\r
+ {0x52u, 0x01u},\r
+ {0x53u, 0x04u},\r
+ {0x60u, 0x92u},\r
+ {0x61u, 0x20u},\r
+ {0x82u, 0x20u},\r
+ {0x84u, 0x04u},\r
+ {0x86u, 0x01u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Du, 0x04u},\r
+ {0x8Eu, 0x04u},\r
+ {0x90u, 0x04u},\r
+ {0x91u, 0x52u},\r
+ {0x97u, 0x48u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Cu, 0x80u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Eu, 0x01u},\r
+ {0xA0u, 0xB0u},\r
+ {0xA1u, 0x08u},\r
+ {0xA2u, 0x01u},\r
{0xA3u, 0x04u},\r
- {0xA4u, 0x40u},\r
- {0xA6u, 0x27u},\r
- {0xA7u, 0xAAu},\r
- {0xA8u, 0x0Cu},\r
- {0xABu, 0x20u},\r
- {0xAEu, 0x04u},\r
- {0xB0u, 0x01u},\r
- {0xB5u, 0x14u},\r
- {0xC0u, 0xDAu},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0x7Eu},\r
- {0xCAu, 0x76u},\r
- {0xCCu, 0xBCu},\r
- {0xCEu, 0xFEu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x09u},\r
- {0xE2u, 0x08u},\r
- {0xE8u, 0x04u},\r
- {0xECu, 0x08u},\r
- {0x00u, 0x10u},\r
+ {0xA6u, 0xA0u},\r
+ {0xABu, 0x01u},\r
+ {0xB2u, 0x08u},\r
+ {0xB3u, 0x20u},\r
+ {0xB4u, 0x04u},\r
+ {0xC0u, 0xB0u},\r
+ {0xC2u, 0xF0u},\r
+ {0xC4u, 0xD0u},\r
+ {0xCAu, 0xFFu},\r
+ {0xCCu, 0xEEu},\r
+ {0xCEu, 0x6Fu},\r
+ {0xD0u, 0x0Fu},\r
+ {0xD2u, 0x04u},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE2u, 0x44u},\r
+ {0xE4u, 0x02u},\r
+ {0xE8u, 0x01u},\r
+ {0x00u, 0x03u},\r
{0x01u, 0xC0u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x07u},\r
- {0x05u, 0xC0u},\r
- {0x06u, 0x18u},\r
- {0x07u, 0x04u},\r
- {0x08u, 0x22u},\r
- {0x0Au, 0x08u},\r
- {0x0Cu, 0x40u},\r
- {0x0Du, 0xC0u},\r
- {0x0Fu, 0x01u},\r
- {0x10u, 0x40u},\r
- {0x11u, 0x80u},\r
- {0x14u, 0x04u},\r
- {0x17u, 0xFFu},\r
- {0x18u, 0x01u},\r
- {0x1Bu, 0x60u},\r
- {0x1Cu, 0x01u},\r
- {0x1Fu, 0x9Fu},\r
- {0x20u, 0x01u},\r
- {0x21u, 0x1Fu},\r
- {0x23u, 0x20u},\r
- {0x24u, 0x08u},\r
- {0x25u, 0x90u},\r
- {0x26u, 0x21u},\r
- {0x27u, 0x40u},\r
- {0x28u, 0x01u},\r
- {0x29u, 0xC0u},\r
- {0x2Bu, 0x02u},\r
- {0x2Cu, 0x01u},\r
- {0x2Du, 0x7Fu},\r
- {0x2Fu, 0x80u},\r
- {0x30u, 0x3Fu},\r
- {0x32u, 0x40u},\r
- {0x37u, 0xFFu},\r
- {0x38u, 0x0Au},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x40u},\r
- {0x54u, 0x40u},\r
- {0x56u, 0x04u},\r
+ {0x02u, 0x0Cu},\r
+ {0x03u, 0x01u},\r
+ {0x04u, 0x05u},\r
+ {0x06u, 0x0Au},\r
+ {0x07u, 0xFFu},\r
+ {0x08u, 0x40u},\r
+ {0x09u, 0xC0u},\r
+ {0x0Au, 0x1Fu},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Cu, 0x10u},\r
+ {0x0Du, 0x80u},\r
+ {0x0Eu, 0x2Fu},\r
+ {0x13u, 0x9Fu},\r
+ {0x14u, 0x06u},\r
+ {0x15u, 0x7Fu},\r
+ {0x16u, 0x09u},\r
+ {0x17u, 0x80u},\r
+ {0x19u, 0x1Fu},\r
+ {0x1Au, 0x70u},\r
+ {0x1Bu, 0x20u},\r
+ {0x1Fu, 0x60u},\r
+ {0x21u, 0xC0u},\r
+ {0x23u, 0x02u},\r
+ {0x24u, 0x20u},\r
+ {0x25u, 0xC0u},\r
+ {0x26u, 0x4Fu},\r
+ {0x27u, 0x04u},\r
+ {0x28u, 0x0Fu},\r
+ {0x2Du, 0x90u},\r
+ {0x2Fu, 0x40u},\r
+ {0x31u, 0xFFu},\r
+ {0x34u, 0x7Fu},\r
+ {0x3Fu, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x10u},\r
+ {0x80u, 0xFFu},\r
{0x81u, 0x04u},\r
- {0x82u, 0x20u},\r
- {0x84u, 0x01u},\r
- {0x86u, 0x02u},\r
- {0x8Cu, 0x02u},\r
- {0x8Eu, 0x09u},\r
- {0x90u, 0x02u},\r
- {0x92u, 0x05u},\r
- {0x94u, 0x02u},\r
- {0x96u, 0x01u},\r
- {0x9Cu, 0x02u},\r
- {0x9Eu, 0x01u},\r
- {0x9Fu, 0x01u},\r
- {0xA2u, 0x20u},\r
- {0xA6u, 0x10u},\r
- {0xAFu, 0x02u},\r
- {0xB0u, 0x04u},\r
- {0xB1u, 0x02u},\r
- {0xB2u, 0x08u},\r
- {0xB3u, 0x01u},\r
- {0xB4u, 0x03u},\r
- {0xB6u, 0x30u},\r
- {0xB7u, 0x04u},\r
+ {0x83u, 0x20u},\r
+ {0x84u, 0x33u},\r
+ {0x85u, 0x39u},\r
+ {0x86u, 0xCCu},\r
+ {0x87u, 0x06u},\r
+ {0x88u, 0x0Fu},\r
+ {0x8Au, 0xF0u},\r
+ {0x8Bu, 0x46u},\r
+ {0x8Du, 0x46u},\r
+ {0x8Eu, 0xFFu},\r
+ {0x90u, 0x69u},\r
+ {0x92u, 0x96u},\r
+ {0x95u, 0x01u},\r
+ {0x97u, 0x5Eu},\r
+ {0x98u, 0x55u},\r
+ {0x99u, 0x42u},\r
+ {0x9Au, 0xAAu},\r
+ {0x9Bu, 0x04u},\r
+ {0x9Du, 0x46u},\r
+ {0xA1u, 0x46u},\r
+ {0xA2u, 0xFFu},\r
+ {0xA4u, 0xFFu},\r
+ {0xA5u, 0x77u},\r
+ {0xA7u, 0x08u},\r
+ {0xAAu, 0xFFu},\r
+ {0xADu, 0x42u},\r
+ {0xB3u, 0x70u},\r
+ {0xB4u, 0xFFu},\r
+ {0xB5u, 0x0Fu},\r
+ {0xB9u, 0x20u},\r
{0xBAu, 0x20u},\r
- {0xBEu, 0x40u},\r
- {0xD6u, 0x08u},\r
+ {0xBBu, 0x0Cu},\r
+ {0xD6u, 0x02u},\r
+ {0xD7u, 0x20u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x99u},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x44u},\r
- {0x01u, 0x02u},\r
- {0x04u, 0x20u},\r
- {0x05u, 0x08u},\r
- {0x07u, 0x81u},\r
- {0x09u, 0x82u},\r
- {0x0Au, 0x10u},\r
- {0x0Eu, 0xA4u},\r
- {0x0Fu, 0x02u},\r
- {0x11u, 0x06u},\r
- {0x14u, 0x04u},\r
- {0x16u, 0x01u},\r
- {0x17u, 0x0Au},\r
- {0x18u, 0x46u},\r
- {0x1Au, 0x10u},\r
- {0x1Eu, 0xA0u},\r
- {0x21u, 0x42u},\r
- {0x22u, 0x04u},\r
- {0x27u, 0x01u},\r
- {0x29u, 0x40u},\r
- {0x2Cu, 0x06u},\r
- {0x2Fu, 0xA0u},\r
- {0x32u, 0x80u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x8Au},\r
- {0x39u, 0x02u},\r
- {0x3Eu, 0x06u},\r
- {0x3Fu, 0x80u},\r
- {0x5Au, 0x40u},\r
- {0x61u, 0xC0u},\r
- {0x64u, 0x20u},\r
- {0x66u, 0x80u},\r
- {0x67u, 0x88u},\r
- {0x87u, 0x40u},\r
- {0x8Du, 0x02u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x06u},\r
- {0x92u, 0x44u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x80u},\r
- {0x96u, 0x08u},\r
- {0x98u, 0x04u},\r
- {0x99u, 0x08u},\r
- {0x9Au, 0x03u},\r
- {0x9Bu, 0x0Au},\r
- {0xA0u, 0x02u},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0xE1u},\r
- {0xAAu, 0x20u},\r
- {0xABu, 0x08u},\r
- {0xADu, 0x08u},\r
- {0xAFu, 0x80u},\r
- {0xB0u, 0x40u},\r
- {0xB3u, 0x21u},\r
- {0xB5u, 0x08u},\r
- {0xB7u, 0x02u},\r
- {0xC0u, 0xFDu},\r
- {0xC2u, 0xFDu},\r
- {0xC4u, 0xFCu},\r
- {0xCAu, 0xF8u},\r
- {0xCCu, 0xF8u},\r
- {0xCEu, 0xD1u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0xF8u},\r
- {0xE0u, 0x40u},\r
- {0xE8u, 0x80u},\r
- {0xECu, 0x50u},\r
- {0xB9u, 0x08u},\r
- {0xBFu, 0x04u},\r
- {0xD9u, 0x04u},\r
+ {0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x26u, 0x08u},\r
- {0x87u, 0x80u},\r
+ {0x00u, 0x01u},\r
+ {0x01u, 0x20u},\r
+ {0x02u, 0x10u},\r
+ {0x03u, 0x01u},\r
+ {0x04u, 0x2Au},\r
+ {0x06u, 0x04u},\r
+ {0x07u, 0x01u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x20u},\r
+ {0x0Eu, 0x28u},\r
+ {0x11u, 0x05u},\r
+ {0x12u, 0x04u},\r
+ {0x15u, 0x04u},\r
+ {0x17u, 0x10u},\r
+ {0x18u, 0x08u},\r
+ {0x19u, 0x20u},\r
+ {0x1Eu, 0x08u},\r
+ {0x1Fu, 0x20u},\r
+ {0x20u, 0x2Cu},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x08u},\r
+ {0x26u, 0x01u},\r
+ {0x28u, 0x10u},\r
+ {0x2Au, 0x82u},\r
+ {0x2Cu, 0xA0u},\r
+ {0x2Du, 0x40u},\r
+ {0x30u, 0xA0u},\r
+ {0x31u, 0x08u},\r
+ {0x34u, 0x10u},\r
+ {0x35u, 0x02u},\r
+ {0x36u, 0xA8u},\r
+ {0x37u, 0x08u},\r
+ {0x38u, 0x04u},\r
+ {0x39u, 0x50u},\r
+ {0x3Au, 0x01u},\r
+ {0x3Bu, 0x01u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Eu, 0x92u},\r
+ {0x3Fu, 0x48u},\r
+ {0x63u, 0x02u},\r
+ {0x68u, 0xA8u},\r
+ {0x69u, 0x50u},\r
+ {0x6Au, 0x10u},\r
+ {0x72u, 0x02u},\r
+ {0x88u, 0x80u},\r
{0x8Bu, 0x04u},\r
- {0x97u, 0x08u},\r
- {0x9Fu, 0x80u},\r
- {0xA6u, 0x08u},\r
- {0xAAu, 0x08u},\r
- {0xB0u, 0x20u},\r
- {0xB4u, 0x01u},\r
- {0xB5u, 0x01u},\r
- {0xB6u, 0x80u},\r
+ {0x90u, 0x23u},\r
+ {0x91u, 0x07u},\r
+ {0x95u, 0x40u},\r
+ {0x98u, 0x02u},\r
+ {0x9Au, 0x10u},\r
+ {0x9Bu, 0x11u},\r
+ {0x9Eu, 0x02u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x10u},\r
+ {0xA3u, 0x01u},\r
+ {0xA4u, 0xACu},\r
+ {0xA6u, 0x20u},\r
+ {0xABu, 0x58u},\r
+ {0xB1u, 0x01u},\r
+ {0xB3u, 0x04u},\r
+ {0xB4u, 0x80u},\r
+ {0xB6u, 0x10u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0x6Au},\r
+ {0xC4u, 0x6Eu},\r
+ {0xCAu, 0xDBu},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0xFFu},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x28u},\r
+ {0xE8u, 0x04u},\r
+ {0xEEu, 0x01u},\r
+ {0x39u, 0x20u},\r
+ {0x3Fu, 0x10u},\r
+ {0x59u, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x27u, 0x08u},\r
+ {0x87u, 0x08u},\r
+ {0x88u, 0x08u},\r
+ {0x90u, 0x04u},\r
+ {0x96u, 0x10u},\r
+ {0x97u, 0x80u},\r
+ {0x9Cu, 0x18u},\r
+ {0x9Du, 0xC0u},\r
+ {0xA6u, 0x20u},\r
+ {0xA7u, 0x40u},\r
+ {0xA8u, 0x04u},\r
+ {0xA9u, 0x04u},\r
+ {0xAAu, 0x01u},\r
+ {0xB0u, 0x02u},\r
+ {0xB1u, 0x02u},\r
+ {0xB5u, 0x10u},\r
{0xE0u, 0x80u},\r
- {0xE6u, 0x02u},\r
- {0xE8u, 0x90u},\r
- {0xECu, 0x10u},\r
- {0x12u, 0x02u},\r
+ {0xE8u, 0xE0u},\r
+ {0xEAu, 0x10u},\r
+ {0x80u, 0x04u},\r
+ {0x84u, 0x10u},\r
+ {0x86u, 0x20u},\r
+ {0x90u, 0x04u},\r
+ {0x9Cu, 0x10u},\r
+ {0xA6u, 0x20u},\r
+ {0xAAu, 0x10u},\r
+ {0xB1u, 0xC0u},\r
+ {0xB3u, 0x40u},\r
+ {0xB7u, 0x40u},\r
+ {0xE8u, 0x80u},\r
+ {0xECu, 0xC0u},\r
+ {0x12u, 0x08u},\r
{0x16u, 0x80u},\r
- {0x17u, 0x20u},\r
- {0x31u, 0x08u},\r
- {0x34u, 0x18u},\r
+ {0x17u, 0x80u},\r
+ {0x33u, 0x04u},\r
+ {0x35u, 0x08u},\r
+ {0x36u, 0x80u},\r
{0x3Au, 0x81u},\r
- {0x3Eu, 0x01u},\r
+ {0x3Du, 0x04u},\r
{0x3Fu, 0x20u},\r
- {0x42u, 0x08u},\r
- {0x53u, 0x01u},\r
- {0x5Bu, 0x08u},\r
- {0x5Du, 0x02u},\r
- {0x62u, 0x20u},\r
- {0x66u, 0x04u},\r
- {0x77u, 0x10u},\r
- {0x7Eu, 0x02u},\r
+ {0x43u, 0x20u},\r
+ {0x52u, 0x20u},\r
+ {0x5Bu, 0x01u},\r
+ {0x60u, 0x20u},\r
+ {0x64u, 0x08u},\r
+ {0x65u, 0x40u},\r
+ {0x82u, 0x01u},\r
+ {0x85u, 0x40u},\r
+ {0x87u, 0x01u},\r
{0xC4u, 0xE0u},\r
{0xCCu, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
- {0xD4u, 0x80u},\r
+ {0xD4u, 0x20u},\r
{0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0x30u, 0x02u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x02u},\r
- {0x37u, 0x20u},\r
- {0x3Bu, 0x20u},\r
- {0x57u, 0x20u},\r
- {0x5Au, 0x80u},\r
- {0x5Eu, 0x10u},\r
- {0x66u, 0x80u},\r
- {0x82u, 0x30u},\r
- {0x84u, 0x02u},\r
- {0x8Au, 0x80u},\r
- {0x96u, 0x01u},\r
- {0x97u, 0x02u},\r
- {0x9Bu, 0x30u},\r
- {0x9Cu, 0x18u},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0x0Cu},\r
- {0x9Fu, 0x08u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x20u},\r
- {0xA7u, 0x10u},\r
- {0xB6u, 0x01u},\r
+ {0xE2u, 0x60u},\r
+ {0xE6u, 0x10u},\r
+ {0x33u, 0x18u},\r
+ {0x35u, 0x04u},\r
+ {0x37u, 0x80u},\r
+ {0x39u, 0x80u},\r
+ {0x54u, 0x02u},\r
+ {0x57u, 0x10u},\r
+ {0x5Bu, 0x40u},\r
+ {0x63u, 0x80u},\r
+ {0x95u, 0x04u},\r
+ {0x9Bu, 0xD0u},\r
+ {0x9Cu, 0x20u},\r
+ {0x9Du, 0x08u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA6u, 0x80u},\r
+ {0xA7u, 0x20u},\r
+ {0xA8u, 0x08u},\r
+ {0xAAu, 0x08u},\r
+ {0xABu, 0x50u},\r
+ {0xAEu, 0x20u},\r
+ {0xB7u, 0x10u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0x10u},\r
{0xD4u, 0xC0u},\r
- {0xD6u, 0xA0u},\r
- {0xE2u, 0x80u},\r
- {0xE6u, 0xC0u},\r
- {0x10u, 0x10u},\r
- {0x30u, 0x20u},\r
- {0x80u, 0x02u},\r
- {0x82u, 0x04u},\r
- {0x88u, 0x08u},\r
- {0x8Du, 0x80u},\r
- {0x8Fu, 0x20u},\r
- {0x96u, 0x81u},\r
- {0x97u, 0x22u},\r
- {0x9Cu, 0x18u},\r
- {0x9Eu, 0x0Cu},\r
- {0x9Fu, 0x08u},\r
- {0xA4u, 0x02u},\r
- {0xA5u, 0x08u},\r
- {0xA7u, 0x20u},\r
- {0xABu, 0x10u},\r
- {0xB1u, 0x02u},\r
+ {0xD6u, 0x20u},\r
+ {0xD8u, 0x40u},\r
+ {0xEEu, 0xE0u},\r
+ {0x12u, 0x80u},\r
+ {0x32u, 0x10u},\r
+ {0x82u, 0x10u},\r
+ {0x83u, 0x50u},\r
+ {0x85u, 0x08u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Cu, 0x20u},\r
+ {0x95u, 0x84u},\r
+ {0x9Du, 0x0Cu},\r
+ {0x9Fu, 0x04u},\r
+ {0xA6u, 0x80u},\r
+ {0xA7u, 0x78u},\r
+ {0xA8u, 0x22u},\r
{0xC4u, 0x10u},\r
{0xCCu, 0x10u},\r
- {0xE2u, 0xA0u},\r
- {0xEEu, 0x80u},\r
- {0x81u, 0x08u},\r
- {0x83u, 0x01u},\r
- {0x96u, 0x01u},\r
- {0x97u, 0x02u},\r
- {0x9Eu, 0x08u},\r
- {0x9Fu, 0x08u},\r
- {0xA1u, 0x80u},\r
- {0xA5u, 0x08u},\r
- {0xACu, 0x20u},\r
- {0xB3u, 0x10u},\r
- {0xB6u, 0x40u},\r
+ {0xE2u, 0x20u},\r
+ {0xE6u, 0xB0u},\r
+ {0xEAu, 0x20u},\r
+ {0xEEu, 0x20u},\r
+ {0x81u, 0x44u},\r
+ {0x95u, 0x84u},\r
+ {0x9Du, 0x04u},\r
+ {0xA0u, 0x20u},\r
+ {0xABu, 0x04u},\r
+ {0xAFu, 0x20u},\r
{0xE2u, 0x80u},\r
- {0xE6u, 0x20u},\r
- {0xEAu, 0x40u},\r
- {0x08u, 0x28u},\r
+ {0xE6u, 0x80u},\r
+ {0xEAu, 0x80u},\r
+ {0xEEu, 0x10u},\r
+ {0x08u, 0x04u},\r
+ {0x09u, 0x80u},\r
{0x0Fu, 0x20u},\r
- {0x13u, 0x01u},\r
- {0x17u, 0x08u},\r
- {0x53u, 0x21u},\r
- {0x55u, 0x08u},\r
- {0x5Cu, 0x40u},\r
- {0x83u, 0x01u},\r
- {0x8Bu, 0x10u},\r
+ {0x12u, 0x20u},\r
+ {0x17u, 0x01u},\r
+ {0x50u, 0x04u},\r
+ {0x57u, 0x20u},\r
+ {0x58u, 0x20u},\r
+ {0x5Fu, 0x40u},\r
+ {0x80u, 0x40u},\r
{0xC2u, 0x0Eu},\r
{0xC4u, 0x0Cu},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0xE2u, 0x04u},\r
- {0x01u, 0x82u},\r
- {0x06u, 0x08u},\r
+ {0x00u, 0x40u},\r
+ {0x02u, 0x10u},\r
+ {0x05u, 0x20u},\r
{0x07u, 0x20u},\r
- {0x08u, 0x80u},\r
- {0x0Bu, 0x20u},\r
- {0x0Eu, 0x01u},\r
- {0x0Fu, 0x80u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x20u},\r
+ {0x0Du, 0x01u},\r
+ {0x0Eu, 0x02u},\r
{0x83u, 0x10u},\r
- {0x84u, 0x20u},\r
- {0x85u, 0x01u},\r
+ {0x8Au, 0x10u},\r
+ {0x8Bu, 0x60u},\r
{0x94u, 0x40u},\r
- {0x97u, 0x20u},\r
- {0x98u, 0x28u},\r
- {0x9Bu, 0x08u},\r
+ {0x97u, 0x40u},\r
+ {0x9Bu, 0x01u},\r
+ {0xA2u, 0x20u},\r
{0xA3u, 0x10u},\r
- {0xA5u, 0x08u},\r
- {0xA7u, 0x60u},\r
- {0xABu, 0x41u},\r
- {0xC0u, 0x0Fu},\r
- {0xC2u, 0x0Fu},\r
- {0x82u, 0x40u},\r
- {0x83u, 0x20u},\r
- {0x8Au, 0x08u},\r
- {0x94u, 0x40u},\r
- {0x95u, 0x02u},\r
- {0x98u, 0x08u},\r
- {0x9Au, 0x08u},\r
- {0x9Bu, 0x28u},\r
{0xA7u, 0x20u},\r
- {0xA9u, 0x0Au},\r
- {0xB2u, 0x01u},\r
- {0xB4u, 0x80u},\r
+ {0xA8u, 0x04u},\r
+ {0xACu, 0x20u},\r
+ {0xB0u, 0x04u},\r
{0xB5u, 0x80u},\r
- {0xE2u, 0x04u},\r
+ {0xC0u, 0x0Fu},\r
+ {0xC2u, 0x0Fu},\r
+ {0xE0u, 0x05u},\r
+ {0xE6u, 0x04u},\r
{0xEAu, 0x08u},\r
- {0xEEu, 0x03u},\r
- {0x08u, 0x10u},\r
- {0x0Au, 0x40u},\r
- {0x0Du, 0x01u},\r
- {0x0Eu, 0x04u},\r
- {0x83u, 0x08u},\r
- {0x94u, 0x40u},\r
- {0x95u, 0x02u},\r
- {0x96u, 0x44u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x10u},\r
- {0xABu, 0x20u},\r
- {0xAEu, 0x04u},\r
- {0xB0u, 0x10u},\r
- {0xB4u, 0x08u},\r
+ {0xEEu, 0x01u},\r
+ {0x82u, 0x05u},\r
+ {0x84u, 0x02u},\r
+ {0x8Bu, 0x11u},\r
+ {0x91u, 0x02u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x20u},\r
+ {0x9Bu, 0x21u},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x01u},\r
+ {0xAEu, 0x20u},\r
+ {0xE2u, 0x04u},\r
+ {0xE6u, 0x04u},\r
+ {0x0Bu, 0x21u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x20u},\r
+ {0x83u, 0x11u},\r
+ {0x85u, 0x01u},\r
+ {0x8Cu, 0x04u},\r
+ {0x91u, 0x02u},\r
+ {0x97u, 0x20u},\r
+ {0x99u, 0x20u},\r
+ {0xA6u, 0x04u},\r
+ {0xAFu, 0x20u},\r
+ {0xB5u, 0x20u},\r
{0xC2u, 0x0Fu},\r
- {0xEAu, 0x06u},\r
- {0x65u, 0x01u},\r
- {0x86u, 0x09u},\r
- {0x96u, 0x01u},\r
- {0x9Eu, 0x08u},\r
- {0x9Fu, 0x08u},\r
- {0xA1u, 0x80u},\r
+ {0xE6u, 0x02u},\r
+ {0xEEu, 0x02u},\r
+ {0x67u, 0x80u},\r
+ {0x87u, 0x40u},\r
+ {0x89u, 0x04u},\r
+ {0x95u, 0x04u},\r
+ {0xA0u, 0x20u},\r
{0xD8u, 0x80u},\r
{0xE2u, 0x10u},\r
- {0xE6u, 0x40u},\r
- {0x04u, 0x08u},\r
- {0x51u, 0x80u},\r
- {0x56u, 0x80u},\r
- {0x8Cu, 0x04u},\r
- {0x8Eu, 0x80u},\r
- {0x8Fu, 0x08u},\r
- {0x9Fu, 0x08u},\r
- {0xA1u, 0x80u},\r
- {0xA9u, 0x01u},\r
+ {0x06u, 0x40u},\r
+ {0x50u, 0x20u},\r
+ {0x57u, 0x80u},\r
+ {0x86u, 0x40u},\r
+ {0x8Fu, 0x80u},\r
+ {0xA0u, 0x20u},\r
{0xC0u, 0x20u},\r
{0xD4u, 0x60u},\r
- {0xEAu, 0x20u},\r
- {0x94u, 0x40u},\r
- {0x00u, 0x08u},\r
- {0x84u, 0x04u},\r
- {0xB4u, 0x40u},\r
+ {0xE0u, 0x10u},\r
+ {0x94u, 0x04u},\r
+ {0xB5u, 0x20u},\r
+ {0xEAu, 0x08u},\r
+ {0x00u, 0x04u},\r
+ {0x94u, 0x04u},\r
{0xC0u, 0x08u},\r
- {0xE8u, 0x02u},\r
- {0x10u, 0x01u},\r
- {0x11u, 0x01u},\r
- {0x1Au, 0x01u},\r
- {0x1Bu, 0x01u},\r
- {0x1Cu, 0x01u},\r
- {0x1Du, 0x01u},\r
+ {0x10u, 0x03u},\r
+ {0x1Au, 0x03u},\r
{0x00u, 0xFDu},\r
{0x01u, 0xBFu},\r
{0x02u, 0x2Au},\r
\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x01u, 0x01u, 0x02u, 0x01u};\r
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB07_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB08_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB08_ST\r
\r
/* SD_SCK */\r
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB05_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB05_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB05_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
.set scsiTarget_StatusReg__0__POS, 0\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__2__POS, 2\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__4__MASK, 0x10\r
.set scsiTarget_StatusReg__4__POS, 4\r
.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB02_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB02_ST\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST\r
\r
/* Debug_Timer_Interrupt */\r
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST\r
\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST\r
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB04_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST\r
\r
/* Miscellaneous */\r
.set BCLK__BUS_CLK__HZ, 50000000\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
\r
/* SD_SCK */\r
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
\r
/* Debug_Timer_Interrupt */\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST\r
\r
/* Miscellaneous */\r
BCLK__BUS_CLK__HZ EQU 50000000\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
\r
; SD_SCK\r
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
\r
; Debug_Timer_Interrupt\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
\r
; SCSI_Glitch_Ctl\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
; SCSI_Parity_Error\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST\r
\r
; Miscellaneous\r
BCLK__BUS_CLK__HZ EQU 50000000\r
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
- <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006464" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006484" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006494" bitWidth="8" desc="" hidden="false">\r
- <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
- <value name="ENABLED" value="1" desc="Enable counter" />\r
- <value name="DISABLED" value="0" desc="Disable counter" />\r
- </field>\r
- <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
- <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
- <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
- </field>\r
- <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
- <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
- <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
- </field>\r
- <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
- <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
- <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
- </field>\r
- <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
- <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
- <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
- </field>\r
- <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
- <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
- <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
- </field>\r
- </register>\r
- </block>\r
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />\r
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />\r
</block>\r
- <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" hidden="false" />\r
+ </block>\r
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />\r
+ </block>\r
+ <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Filtered_STATUS_REG" address="0x40006461" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_MASK_REG" address="0x40006481" bitWidth="8" desc="" hidden="false" />\r
- <register&nbs
projects / SCSI2SD-V6.git / commitdiff