Add second SPI master for 5.2 board
[SCSI2SD.git] / software / SCSI2SD / v5.2 / SCSI2SD.cydsn / Generated_Source / PSoC5 / NOR_SPI.h
1 /*******************************************************************************
2 * File Name: NOR_SPI.h
3 * Version 2.50
4 *
5 * Description:
6 *  Contains the function prototypes, constants and register definition
7 *  of the SPI Master Component.
8 *
9 * Note:
10 *  None
11 *
12 ********************************************************************************
13 * Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
14 * You may use this file only in accordance with the license, terms, conditions,
15 * disclaimers, and limitations in the end user license agreement accompanying
16 * the software package with which this file was provided.
17 *******************************************************************************/
18
19 #if !defined(CY_SPIM_NOR_SPI_H)
20 #define CY_SPIM_NOR_SPI_H
21
22 #include "cyfitter.h"
23 #include "cytypes.h"
24 #include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */
25
26
27 /***************************************
28 *   Conditional Compilation Parameters
29 ***************************************/
30
31 #define NOR_SPI_INTERNAL_CLOCK             (0u)
32
33 #if(0u != NOR_SPI_INTERNAL_CLOCK)
34     #include "NOR_SPI_IntClock.h"
35 #endif /* (0u != NOR_SPI_INTERNAL_CLOCK) */
36
37 #define NOR_SPI_MODE                       (1u)
38 #define NOR_SPI_DATA_WIDTH                 (8u)
39 #define NOR_SPI_MODE_USE_ZERO              (1u)
40 #define NOR_SPI_BIDIRECTIONAL_MODE         (0u)
41
42 /* Internal interrupt handling */
43 #define NOR_SPI_TX_BUFFER_SIZE             (4u)
44 #define NOR_SPI_RX_BUFFER_SIZE             (4u)
45 #define NOR_SPI_INTERNAL_TX_INT_ENABLED    (0u)
46 #define NOR_SPI_INTERNAL_RX_INT_ENABLED    (0u)
47
48 #define NOR_SPI_SINGLE_REG_SIZE            (8u)
49 #define NOR_SPI_USE_SECOND_DATAPATH        (NOR_SPI_DATA_WIDTH > NOR_SPI_SINGLE_REG_SIZE)
50
51 #define NOR_SPI_FIFO_SIZE                  (4u)
52 #define NOR_SPI_TX_SOFTWARE_BUF_ENABLED    ((0u != NOR_SPI_INTERNAL_TX_INT_ENABLED) && \
53                                                      (NOR_SPI_TX_BUFFER_SIZE > NOR_SPI_FIFO_SIZE))
54
55 #define NOR_SPI_RX_SOFTWARE_BUF_ENABLED    ((0u != NOR_SPI_INTERNAL_RX_INT_ENABLED) && \
56                                                      (NOR_SPI_RX_BUFFER_SIZE > NOR_SPI_FIFO_SIZE))
57
58
59 /***************************************
60 *        Data Struct Definition
61 ***************************************/
62
63 /* Sleep Mode API Support */
64 typedef struct
65 {
66     uint8 enableState;
67     uint8 cntrPeriod;
68 } NOR_SPI_BACKUP_STRUCT;
69
70
71 /***************************************
72 *        Function Prototypes
73 ***************************************/
74
75 void  NOR_SPI_Init(void)                           ;
76 void  NOR_SPI_Enable(void)                         ;
77 void  NOR_SPI_Start(void)                          ;
78 void  NOR_SPI_Stop(void)                           ;
79
80 void  NOR_SPI_EnableTxInt(void)                    ;
81 void  NOR_SPI_EnableRxInt(void)                    ;
82 void  NOR_SPI_DisableTxInt(void)                   ;
83 void  NOR_SPI_DisableRxInt(void)                   ;
84
85 void  NOR_SPI_Sleep(void)                          ;
86 void  NOR_SPI_Wakeup(void)                         ;
87 void  NOR_SPI_SaveConfig(void)                     ;
88 void  NOR_SPI_RestoreConfig(void)                  ;
89
90 void  NOR_SPI_SetTxInterruptMode(uint8 intSrc)     ;
91 void  NOR_SPI_SetRxInterruptMode(uint8 intSrc)     ;
92 uint8 NOR_SPI_ReadTxStatus(void)                   ;
93 uint8 NOR_SPI_ReadRxStatus(void)                   ;
94 void  NOR_SPI_WriteTxData(uint8 txData)  \
95                                                             ;
96 uint8 NOR_SPI_ReadRxData(void) \
97                                                             ;
98 uint8 NOR_SPI_GetRxBufferSize(void)                ;
99 uint8 NOR_SPI_GetTxBufferSize(void)                ;
100 void  NOR_SPI_ClearRxBuffer(void)                  ;
101 void  NOR_SPI_ClearTxBuffer(void)                  ;
102 void  NOR_SPI_ClearFIFO(void)                              ;
103 void  NOR_SPI_PutArray(const uint8 buffer[], uint8 byteCount) \
104                                                             ;
105
106 #if(0u != NOR_SPI_BIDIRECTIONAL_MODE)
107     void  NOR_SPI_TxEnable(void)                   ;
108     void  NOR_SPI_TxDisable(void)                  ;
109 #endif /* (0u != NOR_SPI_BIDIRECTIONAL_MODE) */
110
111 CY_ISR_PROTO(NOR_SPI_TX_ISR);
112 CY_ISR_PROTO(NOR_SPI_RX_ISR);
113
114
115 /***************************************
116 *   Variable with external linkage
117 ***************************************/
118
119 extern uint8 NOR_SPI_initVar;
120
121
122 /***************************************
123 *           API Constants
124 ***************************************/
125
126 #define NOR_SPI_TX_ISR_NUMBER     ((uint8) (NOR_SPI_TxInternalInterrupt__INTC_NUMBER))
127 #define NOR_SPI_RX_ISR_NUMBER     ((uint8) (NOR_SPI_RxInternalInterrupt__INTC_NUMBER))
128
129 #define NOR_SPI_TX_ISR_PRIORITY   ((uint8) (NOR_SPI_TxInternalInterrupt__INTC_PRIOR_NUM))
130 #define NOR_SPI_RX_ISR_PRIORITY   ((uint8) (NOR_SPI_RxInternalInterrupt__INTC_PRIOR_NUM))
131
132
133 /***************************************
134 *    Initial Parameter Constants
135 ***************************************/
136
137 #define NOR_SPI_INT_ON_SPI_DONE    ((uint8) (0u   << NOR_SPI_STS_SPI_DONE_SHIFT))
138 #define NOR_SPI_INT_ON_TX_EMPTY    ((uint8) (0u   << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT))
139 #define NOR_SPI_INT_ON_TX_NOT_FULL ((uint8) (0u << \
140                                                                            NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT))
141 #define NOR_SPI_INT_ON_BYTE_COMP   ((uint8) (0u  << NOR_SPI_STS_BYTE_COMPLETE_SHIFT))
142 #define NOR_SPI_INT_ON_SPI_IDLE    ((uint8) (0u   << NOR_SPI_STS_SPI_IDLE_SHIFT))
143
144 /* Disable TX_NOT_FULL if software buffer is used */
145 #define NOR_SPI_INT_ON_TX_NOT_FULL_DEF ((NOR_SPI_TX_SOFTWARE_BUF_ENABLED) ? \
146                                                                         (0u) : (NOR_SPI_INT_ON_TX_NOT_FULL))
147
148 /* TX interrupt mask */
149 #define NOR_SPI_TX_INIT_INTERRUPTS_MASK    (NOR_SPI_INT_ON_SPI_DONE  | \
150                                                      NOR_SPI_INT_ON_TX_EMPTY  | \
151                                                      NOR_SPI_INT_ON_TX_NOT_FULL_DEF | \
152                                                      NOR_SPI_INT_ON_BYTE_COMP | \
153                                                      NOR_SPI_INT_ON_SPI_IDLE)
154
155 #define NOR_SPI_INT_ON_RX_FULL         ((uint8) (0u << \
156                                                                           NOR_SPI_STS_RX_FIFO_FULL_SHIFT))
157 #define NOR_SPI_INT_ON_RX_NOT_EMPTY    ((uint8) (0u << \
158                                                                           NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT))
159 #define NOR_SPI_INT_ON_RX_OVER         ((uint8) (0u << \
160                                                                           NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT))
161
162 /* RX interrupt mask */
163 #define NOR_SPI_RX_INIT_INTERRUPTS_MASK    (NOR_SPI_INT_ON_RX_FULL      | \
164                                                      NOR_SPI_INT_ON_RX_NOT_EMPTY | \
165                                                      NOR_SPI_INT_ON_RX_OVER)
166 /* Nubmer of bits to receive/transmit */
167 #define NOR_SPI_BITCTR_INIT            (((uint8) (NOR_SPI_DATA_WIDTH << 1u)) - 1u)
168
169
170 /***************************************
171 *             Registers
172 ***************************************/
173 #if(CY_PSOC3 || CY_PSOC5)
174     #define NOR_SPI_TXDATA_REG (* (reg8 *) \
175                                                 NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG)
176     #define NOR_SPI_TXDATA_PTR (  (reg8 *) \
177                                                 NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG)
178     #define NOR_SPI_RXDATA_REG (* (reg8 *) \
179                                                 NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG)
180     #define NOR_SPI_RXDATA_PTR (  (reg8 *) \
181                                                 NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG)
182 #else   /* PSOC4 */
183     #if(NOR_SPI_USE_SECOND_DATAPATH)
184         #define NOR_SPI_TXDATA_REG (* (reg16 *) \
185                                           NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
186         #define NOR_SPI_TXDATA_PTR (  (reg16 *) \
187                                           NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
188         #define NOR_SPI_RXDATA_REG (* (reg16 *) \
189                                           NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
190         #define NOR_SPI_RXDATA_PTR (  (reg16 *) \
191                                           NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
192     #else
193         #define NOR_SPI_TXDATA_REG (* (reg8 *) \
194                                                 NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG)
195         #define NOR_SPI_TXDATA_PTR (  (reg8 *) \
196                                                 NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG)
197         #define NOR_SPI_RXDATA_REG (* (reg8 *) \
198                                                 NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG)
199         #define NOR_SPI_RXDATA_PTR (  (reg8 *) \
200                                                 NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG)
201     #endif /* (NOR_SPI_USE_SECOND_DATAPATH) */
202 #endif     /* (CY_PSOC3 || CY_PSOC5) */
203
204 #define NOR_SPI_AUX_CONTROL_DP0_REG (* (reg8 *) \
205                                         NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
206 #define NOR_SPI_AUX_CONTROL_DP0_PTR (  (reg8 *) \
207                                         NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
208
209 #if(NOR_SPI_USE_SECOND_DATAPATH)
210     #define NOR_SPI_AUX_CONTROL_DP1_REG  (* (reg8 *) \
211                                         NOR_SPI_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
212     #define NOR_SPI_AUX_CONTROL_DP1_PTR  (  (reg8 *) \
213                                         NOR_SPI_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
214 #endif /* (NOR_SPI_USE_SECOND_DATAPATH) */
215
216 #define NOR_SPI_COUNTER_PERIOD_REG     (* (reg8 *) NOR_SPI_BSPIM_BitCounter__PERIOD_REG)
217 #define NOR_SPI_COUNTER_PERIOD_PTR     (  (reg8 *) NOR_SPI_BSPIM_BitCounter__PERIOD_REG)
218 #define NOR_SPI_COUNTER_CONTROL_REG    (* (reg8 *) NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
219 #define NOR_SPI_COUNTER_CONTROL_PTR    (  (reg8 *) NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
220
221 #define NOR_SPI_TX_STATUS_REG          (* (reg8 *) NOR_SPI_BSPIM_TxStsReg__STATUS_REG)
222 #define NOR_SPI_TX_STATUS_PTR          (  (reg8 *) NOR_SPI_BSPIM_TxStsReg__STATUS_REG)
223 #define NOR_SPI_RX_STATUS_REG          (* (reg8 *) NOR_SPI_BSPIM_RxStsReg__STATUS_REG)
224 #define NOR_SPI_RX_STATUS_PTR          (  (reg8 *) NOR_SPI_BSPIM_RxStsReg__STATUS_REG)
225
226 #define NOR_SPI_CONTROL_REG            (* (reg8 *) \
227                                       NOR_SPI_BSPIM_BidirMode_CtrlReg__CONTROL_REG)
228 #define NOR_SPI_CONTROL_PTR            (  (reg8 *) \
229                                       NOR_SPI_BSPIM_BidirMode_CtrlReg__CONTROL_REG)
230
231 #define NOR_SPI_TX_STATUS_MASK_REG     (* (reg8 *) NOR_SPI_BSPIM_TxStsReg__MASK_REG)
232 #define NOR_SPI_TX_STATUS_MASK_PTR     (  (reg8 *) NOR_SPI_BSPIM_TxStsReg__MASK_REG)
233 #define NOR_SPI_RX_STATUS_MASK_REG     (* (reg8 *) NOR_SPI_BSPIM_RxStsReg__MASK_REG)
234 #define NOR_SPI_RX_STATUS_MASK_PTR     (  (reg8 *) NOR_SPI_BSPIM_RxStsReg__MASK_REG)
235
236 #define NOR_SPI_TX_STATUS_ACTL_REG     (* (reg8 *) NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
237 #define NOR_SPI_TX_STATUS_ACTL_PTR     (  (reg8 *) NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
238 #define NOR_SPI_RX_STATUS_ACTL_REG     (* (reg8 *) NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
239 #define NOR_SPI_RX_STATUS_ACTL_PTR     (  (reg8 *) NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
240
241 #if(NOR_SPI_USE_SECOND_DATAPATH)
242     #define NOR_SPI_AUX_CONTROLDP1     (NOR_SPI_AUX_CONTROL_DP1_REG)
243 #endif /* (NOR_SPI_USE_SECOND_DATAPATH) */
244
245
246 /***************************************
247 *       Register Constants
248 ***************************************/
249
250 /* Status Register Definitions */
251 #define NOR_SPI_STS_SPI_DONE_SHIFT             (0x00u)
252 #define NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT        (0x01u)
253 #define NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT     (0x02u)
254 #define NOR_SPI_STS_BYTE_COMPLETE_SHIFT        (0x03u)
255 #define NOR_SPI_STS_SPI_IDLE_SHIFT             (0x04u)
256 #define NOR_SPI_STS_RX_FIFO_FULL_SHIFT         (0x04u)
257 #define NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT    (0x05u)
258 #define NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT      (0x06u)
259
260 #define NOR_SPI_STS_SPI_DONE           ((uint8) (0x01u << NOR_SPI_STS_SPI_DONE_SHIFT))
261 #define NOR_SPI_STS_TX_FIFO_EMPTY      ((uint8) (0x01u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT))
262 #define NOR_SPI_STS_TX_FIFO_NOT_FULL   ((uint8) (0x01u << NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT))
263 #define NOR_SPI_STS_BYTE_COMPLETE      ((uint8) (0x01u << NOR_SPI_STS_BYTE_COMPLETE_SHIFT))
264 #define NOR_SPI_STS_SPI_IDLE           ((uint8) (0x01u << NOR_SPI_STS_SPI_IDLE_SHIFT))
265 #define NOR_SPI_STS_RX_FIFO_FULL       ((uint8) (0x01u << NOR_SPI_STS_RX_FIFO_FULL_SHIFT))
266 #define NOR_SPI_STS_RX_FIFO_NOT_EMPTY  ((uint8) (0x01u << NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT))
267 #define NOR_SPI_STS_RX_FIFO_OVERRUN    ((uint8) (0x01u << NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT))
268
269 /* TX and RX masks for clear on read bits */
270 #define NOR_SPI_TX_STS_CLR_ON_RD_BYTES_MASK    (0x09u)
271 #define NOR_SPI_RX_STS_CLR_ON_RD_BYTES_MASK    (0x40u)
272
273 /* StatusI Register Interrupt Enable Control Bits */
274 /* As defined by the Register map for the AUX Control Register */
275 #define NOR_SPI_INT_ENABLE     (0x10u) /* Enable interrupt from statusi */
276 #define NOR_SPI_TX_FIFO_CLR    (0x01u) /* F0 - TX FIFO */
277 #define NOR_SPI_RX_FIFO_CLR    (0x02u) /* F1 - RX FIFO */
278 #define NOR_SPI_FIFO_CLR       (NOR_SPI_TX_FIFO_CLR | NOR_SPI_RX_FIFO_CLR)
279
280 /* Bit Counter (7-bit) Control Register Bit Definitions */
281 /* As defined by the Register map for the AUX Control Register */
282 #define NOR_SPI_CNTR_ENABLE    (0x20u) /* Enable CNT7 */
283
284 /* Bi-Directional mode control bit */
285 #define NOR_SPI_CTRL_TX_SIGNAL_EN  (0x01u)
286
287 /* Datapath Auxillary Control Register definitions */
288 #define NOR_SPI_AUX_CTRL_FIFO0_CLR         (0x01u)
289 #define NOR_SPI_AUX_CTRL_FIFO1_CLR         (0x02u)
290 #define NOR_SPI_AUX_CTRL_FIFO0_LVL         (0x04u)
291 #define NOR_SPI_AUX_CTRL_FIFO1_LVL         (0x08u)
292 #define NOR_SPI_STATUS_ACTL_INT_EN_MASK    (0x10u)
293
294 /* Component disabled */
295 #define NOR_SPI_DISABLED   (0u)
296
297
298 /***************************************
299 *       Macros
300 ***************************************/
301
302 /* Returns true if componentn enabled */
303 #define NOR_SPI_IS_ENABLED (0u != (NOR_SPI_TX_STATUS_ACTL_REG & NOR_SPI_INT_ENABLE))
304
305 /* Retuns TX status register */
306 #define NOR_SPI_GET_STATUS_TX(swTxSts) ( (uint8)(NOR_SPI_TX_STATUS_REG | \
307                                                           ((swTxSts) & NOR_SPI_TX_STS_CLR_ON_RD_BYTES_MASK)) )
308 /* Retuns RX status register */
309 #define NOR_SPI_GET_STATUS_RX(swRxSts) ( (uint8)(NOR_SPI_RX_STATUS_REG | \
310                                                           ((swRxSts) & NOR_SPI_RX_STS_CLR_ON_RD_BYTES_MASK)) )
311
312
313 /***************************************
314 * The following code is DEPRECATED and 
315 * should not be used in new projects.
316 ***************************************/
317
318 #define NOR_SPI_WriteByte   NOR_SPI_WriteTxData
319 #define NOR_SPI_ReadByte    NOR_SPI_ReadRxData
320 void  NOR_SPI_SetInterruptMode(uint8 intSrc)       ;
321 uint8 NOR_SPI_ReadStatus(void)                     ;
322 void  NOR_SPI_EnableInt(void)                      ;
323 void  NOR_SPI_DisableInt(void)                     ;
324
325 #define NOR_SPI_TXDATA                 (NOR_SPI_TXDATA_REG)
326 #define NOR_SPI_RXDATA                 (NOR_SPI_RXDATA_REG)
327 #define NOR_SPI_AUX_CONTROLDP0         (NOR_SPI_AUX_CONTROL_DP0_REG)
328 #define NOR_SPI_TXBUFFERREAD           (NOR_SPI_txBufferRead)
329 #define NOR_SPI_TXBUFFERWRITE          (NOR_SPI_txBufferWrite)
330 #define NOR_SPI_RXBUFFERREAD           (NOR_SPI_rxBufferRead)
331 #define NOR_SPI_RXBUFFERWRITE          (NOR_SPI_rxBufferWrite)
332
333 #define NOR_SPI_COUNTER_PERIOD         (NOR_SPI_COUNTER_PERIOD_REG)
334 #define NOR_SPI_COUNTER_CONTROL        (NOR_SPI_COUNTER_CONTROL_REG)
335 #define NOR_SPI_STATUS                 (NOR_SPI_TX_STATUS_REG)
336 #define NOR_SPI_CONTROL                (NOR_SPI_CONTROL_REG)
337 #define NOR_SPI_STATUS_MASK            (NOR_SPI_TX_STATUS_MASK_REG)
338 #define NOR_SPI_STATUS_ACTL            (NOR_SPI_TX_STATUS_ACTL_REG)
339
340 #define NOR_SPI_INIT_INTERRUPTS_MASK  (NOR_SPI_INT_ON_SPI_DONE     | \
341                                                 NOR_SPI_INT_ON_TX_EMPTY     | \
342                                                 NOR_SPI_INT_ON_TX_NOT_FULL_DEF  | \
343                                                 NOR_SPI_INT_ON_RX_FULL      | \
344                                                 NOR_SPI_INT_ON_RX_NOT_EMPTY | \
345                                                 NOR_SPI_INT_ON_RX_OVER      | \
346                                                 NOR_SPI_INT_ON_BYTE_COMP)
347                                                 
348 #define NOR_SPI_DataWidth                  (NOR_SPI_DATA_WIDTH)
349 #define NOR_SPI_InternalClockUsed          (NOR_SPI_INTERNAL_CLOCK)
350 #define NOR_SPI_InternalTxInterruptEnabled (NOR_SPI_INTERNAL_TX_INT_ENABLED)
351 #define NOR_SPI_InternalRxInterruptEnabled (NOR_SPI_INTERNAL_RX_INT_ENABLED)
352 #define NOR_SPI_ModeUseZero                (NOR_SPI_MODE_USE_ZERO)
353 #define NOR_SPI_BidirectionalMode          (NOR_SPI_BIDIRECTIONAL_MODE)
354 #define NOR_SPI_Mode                       (NOR_SPI_MODE)
355 #define NOR_SPI_DATAWIDHT                  (NOR_SPI_DATA_WIDTH)
356 #define NOR_SPI_InternalInterruptEnabled   (0u)
357
358 #define NOR_SPI_TXBUFFERSIZE   (NOR_SPI_TX_BUFFER_SIZE)
359 #define NOR_SPI_RXBUFFERSIZE   (NOR_SPI_RX_BUFFER_SIZE)
360
361 #define NOR_SPI_TXBUFFER       NOR_SPI_txBuffer
362 #define NOR_SPI_RXBUFFER       NOR_SPI_rxBuffer
363
364 #endif /* (CY_SPIM_NOR_SPI_H) */
365
366
367 /* [] END OF FILE */