2 /*******************************************************************************
3 * File Name: cyfitter_cfg.c
8 * This file contains device initialization code.
9 * Except for the user defined sections in CyClockStartupError(), this file should not be modified.
10 * This file is automatically generated by PSoC Creator.
12 ********************************************************************************
13 * Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
14 * You may use this file only in accordance with the license, terms, conditions,
15 * disclaimers, and limitations in the end user license agreement accompanying
16 * the software package with which this file was provided.
17 ********************************************************************************/
21 #include "cydevice_trm.h"
24 #include "cyfitter_cfg.h"
26 #define CY_NEED_CYCLOCKSTARTUPERROR 1
29 #if defined(__GNUC__) || defined(__ARMCC_VERSION)
31 #define CYPACKED_ATTR __attribute__ ((packed))
32 #define CYALIGNED __attribute__ ((aligned))
33 #define CY_CFG_UNUSED __attribute__ ((unused))
34 #ifndef CY_CFG_SECTION
35 #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))
38 #if defined(__ARMCC_VERSION)
39 #define CY_CFG_MEMORY_BARRIER() __memory_changed()
41 #define CY_CFG_MEMORY_BARRIER() __sync_synchronize()
44 #elif defined(__ICCARM__)
45 #include <intrinsics.h>
47 #define CYPACKED __packed
49 #define CYALIGNED _Pragma("data_alignment=4")
50 #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")
51 #define CY_CFG_SECTION _Pragma("location=\".psocinit\"")
53 #define CY_CFG_MEMORY_BARRIER() __DMB()
56 #error Unsupported toolchain
74 static void CYMEMZERO(void *s, size_t n);
76 static void CYMEMZERO(void *s, size_t n)
78 (void)memset(s, 0, n);
81 static void CYCONFIGCPY(void *dest, const void *src, size_t n);
83 static void CYCONFIGCPY(void *dest, const void *src, size_t n)
85 (void)memcpy(dest, src, n);
88 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);
90 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
92 (void)memcpy(dest, src, n);
98 /* Clock startup error codes */
99 #define CYCLOCKSTART_NO_ERROR 0u
100 #define CYCLOCKSTART_XTAL_ERROR 1u
101 #define CYCLOCKSTART_32KHZ_ERROR 2u
102 #define CYCLOCKSTART_PLL_ERROR 3u
103 #define CYCLOCKSTART_FLL_ERROR 4u
104 #define CYCLOCKSTART_WCO_ERROR 5u
107 #ifdef CY_NEED_CYCLOCKSTARTUPERROR
108 /*******************************************************************************
109 * Function Name: CyClockStartupError
110 ********************************************************************************
112 * If an error is encountered during clock configuration (crystal startup error,
113 * PLL lock error, etc.), the system will end up here. Unless reimplemented by
114 * the customer, this function will stop in an infinite loop.
122 *******************************************************************************/
124 static void CyClockStartupError(uint8 errorCode);
126 static void CyClockStartupError(uint8 errorCode)
128 /* To remove the compiler warning if errorCode not used. */
129 errorCode = errorCode;
131 /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */
132 /* we will end up here to allow the customer to implement something to */
133 /* deal with the clock condition. */
135 #ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK
136 CY_CFG_Clock_Startup_ErrorCallback();
138 /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */
139 /* `#START CyClockStartupError` */
141 /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */
142 /* we will end up here to allow the customer to implement something to */
143 /* deal with the clock condition. */
148 #endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */
152 #define CY_CFG_BASE_ADDR_COUNT 43u
153 CYPACKED typedef struct
157 } CYPACKED_ATTR cy_cfg_addrvalue_t;
161 /*******************************************************************************
162 * Function Name: cfg_write_bytes32
163 ********************************************************************************
165 * This function is used for setting up the chip configuration areas that
166 * contain relatively sparse data.
174 *******************************************************************************/
175 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]);
176 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[])
178 /* For 32-bit little-endian architectures */
180 for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++)
182 uint32 baseAddr = addr_table[i];
183 uint8 count = (uint8)baseAddr;
184 baseAddr &= 0xFFFFFF00u;
187 CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value);
194 /*******************************************************************************
195 * Function Name: ClockSetup
196 ********************************************************************************
199 * Performs the initialization of all of the clocks in the device based on the
200 * settings in the Clock tab of the DWR. This includes enabling the requested
201 * clocks and setting the necessary dividers to produce the desired frequency.
209 *******************************************************************************/
210 static void ClockSetup(void);
211 static void ClockSetup(void)
217 /* Configure Digital Clocks based on settings from Clock DWR */
218 CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u);
219 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u);
220 CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u);
221 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u);
222 CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0001u);
223 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x18u);
224 CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x0031u);
225 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0 + 0x2u), 0x18u);
227 /* Configure ILO based on settings from Clock DWR */
228 CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);
230 /* Configure IMO based on settings from Clock DWR */
231 CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u);
232 CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));
234 /* Configure PLL based on settings from Clock DWR */
235 CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0B19u);
236 CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);
237 /* Wait up to 250us for the PLL to lock */
239 for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--)
241 pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));
242 CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */
244 /* If we ran out of time the PLL didn't lock so go to the error function */
247 CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
250 /* Configure Bus/Master Clock based on settings from Clock DWR */
251 CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);
252 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u);
253 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u);
254 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u);
255 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u);
257 /* Configure USB Clock based on settings from Clock DWR */
258 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);
259 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);
261 CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x0Fu)));
265 /* Analog API Functions */
268 /*******************************************************************************
269 * Function Name: AnalogSetDefault
270 ********************************************************************************
273 * Sets up the analog portions of the chip to default values based on chip
274 * configuration options from the project.
282 *******************************************************************************/
283 static void AnalogSetDefault(void);
284 static void AnalogSetDefault(void)
286 uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));
287 CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));
288 CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));
289 CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);
293 /*******************************************************************************
294 * Function Name: SetAnalogRoutingPumps
295 ********************************************************************************
298 * Enables or disables the analog pumps feeding analog routing switches.
299 * Intended to be called at startup, based on the Vdda system configuration;
300 * may be called during operation when the user informs us that the Vdda voltage
301 * crossed the pump threshold.
304 * enabled - 1 to enable the pumps, 0 to disable the pumps
309 *******************************************************************************/
310 void SetAnalogRoutingPumps(uint8 enabled)
312 uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0);
319 regValue &= (uint8)~0x00u;
321 CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);
327 /*******************************************************************************
328 * Function Name: cyfitter_cfg
329 ********************************************************************************
331 * This function is called by the start-up code for the selected device. It
332 * performs all of the necessary device configuration based on the design
333 * settings. This includes settings from the Design Wide Resources (DWR) such
334 * as Clocks and Pins as well as any component configuration that is necessary.
342 *******************************************************************************/
344 void cyfitter_cfg(void)
346 /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */
347 static const uint8 CYCODE BS_IOPINS0_0_VAL[] = {
348 0x44u, 0xAAu, 0xAAu, 0x00u, 0x22u, 0x00u, 0x00u, 0x01u};
350 /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */
351 static const uint8 CYCODE BS_IOPINS0_7_VAL[] = {
352 0x04u, 0x00u, 0x10u, 0x22u, 0x2Eu, 0x0Cu, 0x22u, 0x00u, 0x00u, 0x0Cu};
354 /* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */
355 static const uint8 CYCODE BS_IOPINS1_7_VAL[] = {
356 0x00u, 0x00u, 0x00u, 0x00u, 0x10u};
358 /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */
359 static const uint8 CYCODE BS_IOPINS0_8_VAL[] = {
360 0x40u, 0x00u, 0x04u, 0x28u, 0x28u, 0x08u, 0x20u, 0x00u, 0xC0u, 0x00u};
362 /* IOPINS0_1 Address: CYREG_PRT1_DM0 Size (bytes): 8 */
363 static const uint8 CYCODE BS_IOPINS0_1_VAL[] = {
364 0x00u, 0x0Bu, 0x0Bu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
366 /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */
367 static const uint8 CYCODE BS_IOPINS0_2_VAL[] = {
368 0x55u, 0xAAu, 0xAAu, 0x00u, 0xAAu, 0x00u, 0x00u, 0x01u};
370 /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */
371 static const uint8 CYCODE BS_IOPINS0_3_VAL[] = {
372 0x08u, 0x00u, 0x01u, 0xFEu, 0xFEu, 0x02u, 0xC6u, 0x00u, 0x00u, 0x01u};
374 /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */
375 static const uint8 CYCODE BS_IOPINS0_4_VAL[] = {
376 0xA8u, 0x43u, 0x43u, 0x00u, 0x03u, 0x00u, 0x00u, 0x01u};
378 /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */
379 static const uint8 CYCODE BS_IOPINS0_6_VAL[] = {
380 0x5Au, 0xA4u, 0xA4u, 0x00u, 0xA4u, 0x00u, 0x00u, 0x01u};
382 /* PHUB_CFGMEM1 Address: CYREG_PHUB_CFGMEM1_CFG0 Size (bytes): 4 */
383 static const uint8 CYCODE BS_PHUB_CFGMEM1_VAL[] = {
384 0x00u, 0x01u, 0x00u, 0x00u};
386 /* PHUB_CFGMEM2 Address: CYREG_PHUB_CFGMEM2_CFG0 Size (bytes): 4 */
387 static const uint8 CYCODE BS_PHUB_CFGMEM2_VAL[] = {
388 0x00u, 0x02u, 0x00u, 0x00u};
390 /* PHUB_CFGMEM3 Address: CYREG_PHUB_CFGMEM3_CFG0 Size (bytes): 4 */
391 static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = {
392 0x00u, 0x03u, 0x00u, 0x00u};
394 /* PHUB_CFGMEM4 Address: CYREG_PHUB_CFGMEM4_CFG0 Size (bytes): 4 */
395 static const uint8 CYCODE BS_PHUB_CFGMEM4_VAL[] = {
396 0x00u, 0x04u, 0x00u, 0x00u};
398 /* PHUB_CFGMEM5 Address: CYREG_PHUB_CFGMEM5_CFG0 Size (bytes): 4 */
399 static const uint8 CYCODE BS_PHUB_CFGMEM5_VAL[] = {
400 0x00u, 0x05u, 0x00u, 0x00u};
402 #ifdef CYGlobalIntDisable
403 /* Disable interrupts by default. Let user enable if/when they want. */
408 /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
409 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x61u : 0x60u));
410 /* Setup clocks based on selections from Clock DWR */
412 /* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */
413 CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0xC1u : 0xC0u));
414 /* Enable/Disable Debug functionality based on settings from System DWR */
415 CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u));
418 static const uint32 CYCODE cy_cfg_addr_table[] = {
419 0x40004501u, /* Base address: 0x40004500 Count: 1 */
420 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
421 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */
422 0x40006402u, /* Base address: 0x40006400 Count: 2 */
423 0x40006501u, /* Base address: 0x40006500 Count: 1 */
424 0x4001003Du, /* Base address: 0x40010000 Count: 61 */
425 0x4001013Fu, /* Base address: 0x40010100 Count: 63 */
426 0x4001025Au, /* Base address: 0x40010200 Count: 90 */
427 0x40010354u, /* Base address: 0x40010300 Count: 84 */
428 0x40010419u, /* Base address: 0x40010400 Count: 25 */
429 0x40010556u, /* Base address: 0x40010500 Count: 86 */
430 0x40010653u, /* Base address: 0x40010600 Count: 83 */
431 0x40010759u, /* Base address: 0x40010700 Count: 89 */
432 0x4001084Eu, /* Base address: 0x40010800 Count: 78 */
433 0x4001095Eu, /* Base address: 0x40010900 Count: 94 */
434 0x40010A41u, /* Base address: 0x40010A00 Count: 65 */
435 0x40010B5Cu, /* Base address: 0x40010B00 Count: 92 */
436 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */
437 0x40010D61u, /* Base address: 0x40010D00 Count: 97 */
438 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */
439 0x40010F41u, /* Base address: 0x40010F00 Count: 65 */
440 0x40011411u, /* Base address: 0x40011400 Count: 17 */
441 0x40011550u, /* Base address: 0x40011500 Count: 80 */
442 0x40011650u, /* Base address: 0x40011600 Count: 80 */
443 0x40011754u, /* Base address: 0x40011700 Count: 84 */
444 0x40011848u, /* Base address: 0x40011800 Count: 72 */
445 0x40011954u, /* Base address: 0x40011900 Count: 84 */
446 0x40011A4Eu, /* Base address: 0x40011A00 Count: 78 */
447 0x40011B48u, /* Base address: 0x40011B00 Count: 72 */
448 0x4001401Cu, /* Base address: 0x40014000 Count: 28 */
449 0x4001411Fu, /* Base address: 0x40014100 Count: 31 */
450 0x40014218u, /* Base address: 0x40014200 Count: 24 */
451 0x40014312u, /* Base address: 0x40014300 Count: 18 */
452 0x40014412u, /* Base address: 0x40014400 Count: 18 */
453 0x40014515u, /* Base address: 0x40014500 Count: 21 */
454 0x4001460Du, /* Base address: 0x40014600 Count: 13 */
455 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */
456 0x40014817u, /* Base address: 0x40014800 Count: 23 */
457 0x40014914u, /* Base address: 0x40014900 Count: 20 */
458 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */
459 0x40014D07u, /* Base address: 0x40014D00 Count: 7 */
460 0x40015006u, /* Base address: 0x40015000 Count: 6 */
461 0x40015102u, /* Base address: 0x40015100 Count: 2 */
464 static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
2513 CYPACKED typedef struct {
2514 void CYFAR *address;
2516 } CYPACKED_ATTR cfg_memset_t;
2519 CYPACKED typedef struct {
2521 const void CYCODE *src;
2523 } CYPACKED_ATTR cfg_memcpy_t;
2525 static const cfg_memset_t CYCODE cfg_memset_list[] = {
2527 {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
2528 {(void CYFAR *)(CYREG_PRT5_DR), 16u},
2529 {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1024u},
2530 {(void CYFAR *)(CYDEV_UCFG_B0_P2_U1_BASE), 2944u},
2531 {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},
2532 {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
2533 {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
2534 {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},
2537 /* IDMUX_IRQ Address: CYREG_IDMUX_IRQ_CTL0 Size (bytes): 8 */
2538 static const uint8 CYCODE BS_IDMUX_IRQ_VAL[] = {
2539 0xFFu, 0xFFu, 0xABu, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u};
2541 /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */
2542 static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = {
2543 0x34u, 0x00u, 0x40u, 0x00u, 0x3Du, 0x30u, 0x42u, 0x00u, 0x03u, 0x00u, 0x0Cu, 0x00u, 0x40u, 0x15u, 0x80u, 0x0Au,
2544 0x10u, 0x00u, 0x20u, 0x00u, 0x00u, 0x09u, 0x00u, 0x16u, 0x00u, 0x04u, 0x77u, 0x03u, 0x10u, 0x00u, 0x20u, 0x00u,
2545 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x8Bu, 0x0Bu, 0x74u, 0x24u, 0x88u, 0x00u, 0x77u, 0x00u,
2546 0x30u, 0x00u, 0x00u, 0x38u, 0x0Fu, 0x07u, 0xC0u, 0x00u, 0x00u, 0x08u, 0xA2u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u,
2547 0x52u, 0x04u, 0x60u, 0x00u, 0x03u, 0xBEu, 0xFDu, 0xBCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
2548 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x12u, 0x10u, 0x00u, 0x01u,
2549 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
2550 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
2552 /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */
2553 static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {
2554 0x02u, 0x00u, 0x00u, 0x00u, 0x02u, 0x80u, 0x00u, 0x00u, 0x10u, 0xC0u, 0x42u, 0x08u, 0x01u, 0x7Fu, 0x00u, 0x80u,
2555 0x44u, 0x90u, 0x10u, 0x40u, 0x01u, 0x1Fu, 0x00u, 0x20u, 0x02u, 0xC0u, 0x00u, 0x04u, 0x02u, 0xC0u, 0x00u, 0x02u,
2556 0x08u, 0xC0u, 0x00u, 0x01u, 0x20u, 0x00u, 0x00u, 0x9Fu, 0x0Eu, 0x00u, 0x30u, 0xFFu, 0x02u, 0x00u, 0x00u, 0x60u,
2557 0x01u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, 0x7Eu, 0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x04u,
2558 0x64u, 0x03u, 0x50u, 0x00u, 0x02u, 0xCBu, 0xF0u, 0xEDu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
2559 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x01u, 0x01u, 0x00u, 0x01u,
2560 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
2561 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
2563 /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
2564 static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
2565 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x07u, 0x01u, 0x07u, 0x01u, 0x04u, 0x01u, 0x04u, 0x01u};
2567 static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
2568 /* dest, src, size */
2569 {(void CYFAR *)(CYREG_IDMUX_IRQ_CTL0), BS_IDMUX_IRQ_VAL, 8u},
2570 {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u},
2571 {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},
2572 {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},
2577 /* Zero out critical memory blocks before beginning configuration */
2578 for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
2580 const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
2581 CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
2584 /* Copy device configuration data into registers */
2585 for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
2587 const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
2588 void * CYDATA destPtr = mc->dest;
2589 const void CYCODE * CYDATA srcPtr = mc->src;
2590 uint16 CYDATA numBytes = mc->size;
2591 CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);
2594 cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
2596 /* Perform normal device configuration. Order is not critical for these items. */
2597 CYMEMZERO((void CYFAR *)(CYREG_PHUB_CFGMEM0_CFG0), 4u);
2598 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM1_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM1_VAL), 4u);
2599 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM2_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM2_VAL), 4u);
2600 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM3_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM3_VAL), 4u);
2601 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM4_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM4_VAL), 4u);
2602 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM5_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM5_VAL), 4u);
2604 /* Enable digital routing */
2605 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);
2606 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);
2608 /* Enable UDB array */
2609 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u);
2610 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);
2614 /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
2615 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u);
2616 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u);
2617 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR + 0x0000000Bu), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u);
2618 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);
2619 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT1_DM0), (const void CYCODE *)(BS_IOPINS0_1_VAL), 8u);
2620 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u);
2621 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u);
2622 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);
2623 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);
2624 /* Switch Boost to the precision bandgap reference from its internal reference */
2625 CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));
2627 /* Perform basic analog initialization to defaults */
2630 /* Configure alternate active mode */
2631 CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u);