Add second SPI master for 5.2 board
[SCSI2SD.git] / software / SCSI2SD / v5.2 / SCSI2SD.cydsn / Generated_Source / PSoC5 / cyfitter.h
index c917e54..6704c4a 100644 (file)
 #define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
 #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
 
+/* NOR_SI */
+#define NOR_SI__0__INTTYPE CYREG_PICU3_INTTYPE6
+#define NOR_SI__0__MASK 0x40u
+#define NOR_SI__0__PC CYREG_PRT3_PC6
+#define NOR_SI__0__PORT 3u
+#define NOR_SI__0__SHIFT 6u
+#define NOR_SI__AG CYREG_PRT3_AG
+#define NOR_SI__AMUX CYREG_PRT3_AMUX
+#define NOR_SI__BIE CYREG_PRT3_BIE
+#define NOR_SI__BIT_MASK CYREG_PRT3_BIT_MASK
+#define NOR_SI__BYP CYREG_PRT3_BYP
+#define NOR_SI__CTL CYREG_PRT3_CTL
+#define NOR_SI__DM0 CYREG_PRT3_DM0
+#define NOR_SI__DM1 CYREG_PRT3_DM1
+#define NOR_SI__DM2 CYREG_PRT3_DM2
+#define NOR_SI__DR CYREG_PRT3_DR
+#define NOR_SI__INP_DIS CYREG_PRT3_INP_DIS
+#define NOR_SI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
+#define NOR_SI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define NOR_SI__LCD_EN CYREG_PRT3_LCD_EN
+#define NOR_SI__MASK 0x40u
+#define NOR_SI__PORT 3u
+#define NOR_SI__PRT CYREG_PRT3_PRT
+#define NOR_SI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define NOR_SI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define NOR_SI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define NOR_SI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define NOR_SI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define NOR_SI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define NOR_SI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define NOR_SI__PS CYREG_PRT3_PS
+#define NOR_SI__SHIFT 6u
+#define NOR_SI__SLW CYREG_PRT3_SLW
+
+/* NOR_SO */
+#define NOR_SO__0__INTTYPE CYREG_PICU15_INTTYPE2
+#define NOR_SO__0__MASK 0x04u
+#define NOR_SO__0__PC CYREG_IO_PC_PRT15_PC2
+#define NOR_SO__0__PORT 15u
+#define NOR_SO__0__SHIFT 2u
+#define NOR_SO__AG CYREG_PRT15_AG
+#define NOR_SO__AMUX CYREG_PRT15_AMUX
+#define NOR_SO__BIE CYREG_PRT15_BIE
+#define NOR_SO__BIT_MASK CYREG_PRT15_BIT_MASK
+#define NOR_SO__BYP CYREG_PRT15_BYP
+#define NOR_SO__CTL CYREG_PRT15_CTL
+#define NOR_SO__DM0 CYREG_PRT15_DM0
+#define NOR_SO__DM1 CYREG_PRT15_DM1
+#define NOR_SO__DM2 CYREG_PRT15_DM2
+#define NOR_SO__DR CYREG_PRT15_DR
+#define NOR_SO__INP_DIS CYREG_PRT15_INP_DIS
+#define NOR_SO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
+#define NOR_SO__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define NOR_SO__LCD_EN CYREG_PRT15_LCD_EN
+#define NOR_SO__MASK 0x04u
+#define NOR_SO__PORT 15u
+#define NOR_SO__PRT CYREG_PRT15_PRT
+#define NOR_SO__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define NOR_SO__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define NOR_SO__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define NOR_SO__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define NOR_SO__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define NOR_SO__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define NOR_SO__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define NOR_SO__PS CYREG_PRT15_PS
+#define NOR_SO__SHIFT 2u
+#define NOR_SO__SLW CYREG_PRT15_SLW
+
 /* SDCard */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST
 #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
 #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_RxStsReg__6__POS 6
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u
 #define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
+#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
 #define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
 #define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
 #define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
 #define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
 #define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
 #define SDCard_BSPIM_TxStsReg__0__POS 0
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
 #define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
 #define SDCard_BSPIM_TxStsReg__2__POS 2
 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_TxStsReg__4__POS 4
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB06_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB06_ST
 
 /* SD_SCK */
 #define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1
 #define SD_SCK__SHIFT 1u
 #define SD_SCK__SLW CYREG_PRT3_SLW
 
+/* NOR_CTL */
+#define NOR_CTL_Sync_ctrl_reg__0__MASK 0x01u
+#define NOR_CTL_Sync_ctrl_reg__0__POS 0
+#define NOR_CTL_Sync_ctrl_reg__1__MASK 0x02u
+#define NOR_CTL_Sync_ctrl_reg__1__POS 1
+#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
+#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
+#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
+#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
+#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
+#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
+#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
+#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
+#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
+#define NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
+#define NOR_CTL_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB06_CTL
+#define NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
+#define NOR_CTL_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB06_CTL
+#define NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
+#define NOR_CTL_Sync_ctrl_reg__MASK 0x03u
+#define NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define NOR_CTL_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB06_MSK
+
+/* NOR_SCK */
+#define NOR_SCK__0__INTTYPE CYREG_PICU3_INTTYPE7
+#define NOR_SCK__0__MASK 0x80u
+#define NOR_SCK__0__PC CYREG_PRT3_PC7
+#define NOR_SCK__0__PORT 3u
+#define NOR_SCK__0__SHIFT 7u
+#define NOR_SCK__AG CYREG_PRT3_AG
+#define NOR_SCK__AMUX CYREG_PRT3_AMUX
+#define NOR_SCK__BIE CYREG_PRT3_BIE
+#define NOR_SCK__BIT_MASK CYREG_PRT3_BIT_MASK
+#define NOR_SCK__BYP CYREG_PRT3_BYP
+#define NOR_SCK__CTL CYREG_PRT3_CTL
+#define NOR_SCK__DM0 CYREG_PRT3_DM0
+#define NOR_SCK__DM1 CYREG_PRT3_DM1
+#define NOR_SCK__DM2 CYREG_PRT3_DM2
+#define NOR_SCK__DR CYREG_PRT3_DR
+#define NOR_SCK__INP_DIS CYREG_PRT3_INP_DIS
+#define NOR_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
+#define NOR_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define NOR_SCK__LCD_EN CYREG_PRT3_LCD_EN
+#define NOR_SCK__MASK 0x80u
+#define NOR_SCK__PORT 3u
+#define NOR_SCK__PRT CYREG_PRT3_PRT
+#define NOR_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define NOR_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define NOR_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define NOR_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define NOR_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define NOR_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define NOR_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define NOR_SCK__PS CYREG_PRT3_PS
+#define NOR_SCK__SHIFT 7u
+#define NOR_SCK__SLW CYREG_PRT3_SLW
+
+/* NOR_SPI */
+#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
+#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
+#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB08_CTL
+#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB08_CTL
+#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB08_MSK
+#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
+#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB08_MSK
+#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB08_ST
+#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
+#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
+#define NOR_SPI_BSPIM_RxStsReg__4__MASK 0x10u
+#define NOR_SPI_BSPIM_RxStsReg__4__POS 4
+#define NOR_SPI_BSPIM_RxStsReg__5__MASK 0x20u
+#define NOR_SPI_BSPIM_RxStsReg__5__POS 5
+#define NOR_SPI_BSPIM_RxStsReg__6__MASK 0x40u
+#define NOR_SPI_BSPIM_RxStsReg__6__POS 6
+#define NOR_SPI_BSPIM_RxStsReg__MASK 0x70u
+#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK
+#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
+#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0
+#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0
+#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0
+#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1
+#define NOR_SPI_BSPIM_TxStsReg__0__MASK 0x01u
+#define NOR_SPI_BSPIM_TxStsReg__0__POS 0
+#define NOR_SPI_BSPIM_TxStsReg__1__MASK 0x02u
+#define NOR_SPI_BSPIM_TxStsReg__1__POS 1
+#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
+#define NOR_SPI_BSPIM_TxStsReg__2__MASK 0x04u
+#define NOR_SPI_BSPIM_TxStsReg__2__POS 2
+#define NOR_SPI_BSPIM_TxStsReg__3__MASK 0x08u
+#define NOR_SPI_BSPIM_TxStsReg__3__POS 3
+#define NOR_SPI_BSPIM_TxStsReg__4__MASK 0x10u
+#define NOR_SPI_BSPIM_TxStsReg__4__POS 4
+#define NOR_SPI_BSPIM_TxStsReg__MASK 0x1Fu
+#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
+#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
+
 /* SCSI_In */
 #define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1
 #define SCSI_In__0__MASK 0x02u
 #define TERM_EN__SHIFT 3u
 #define TERM_EN__SLW CYREG_PRT15_SLW
 
+/* nNOR_CS */
+#define nNOR_CS__0__INTTYPE CYREG_PICU3_INTTYPE4
+#define nNOR_CS__0__MASK 0x10u
+#define nNOR_CS__0__PC CYREG_PRT3_PC4
+#define nNOR_CS__0__PORT 3u
+#define nNOR_CS__0__SHIFT 4u
+#define nNOR_CS__AG CYREG_PRT3_AG
+#define nNOR_CS__AMUX CYREG_PRT3_AMUX
+#define nNOR_CS__BIE CYREG_PRT3_BIE
+#define nNOR_CS__BIT_MASK CYREG_PRT3_BIT_MASK
+#define nNOR_CS__BYP CYREG_PRT3_BYP
+#define nNOR_CS__CTL CYREG_PRT3_CTL
+#define nNOR_CS__DM0 CYREG_PRT3_DM0
+#define nNOR_CS__DM1 CYREG_PRT3_DM1
+#define nNOR_CS__DM2 CYREG_PRT3_DM2
+#define nNOR_CS__DR CYREG_PRT3_DR
+#define nNOR_CS__INP_DIS CYREG_PRT3_INP_DIS
+#define nNOR_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
+#define nNOR_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define nNOR_CS__LCD_EN CYREG_PRT3_LCD_EN
+#define nNOR_CS__MASK 0x10u
+#define nNOR_CS__PORT 3u
+#define nNOR_CS__PRT CYREG_PRT3_PRT
+#define nNOR_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define nNOR_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define nNOR_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define nNOR_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define nNOR_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define nNOR_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define nNOR_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define nNOR_CS__PS CYREG_PRT3_PS
+#define nNOR_CS__SHIFT 4u
+#define nNOR_CS__SLW CYREG_PRT3_SLW
+
+/* nNOR_WP */
+#define nNOR_WP__0__INTTYPE CYREG_PICU3_INTTYPE5
+#define nNOR_WP__0__MASK 0x20u
+#define nNOR_WP__0__PC CYREG_PRT3_PC5
+#define nNOR_WP__0__PORT 3u
+#define nNOR_WP__0__SHIFT 5u
+#define nNOR_WP__AG CYREG_PRT3_AG
+#define nNOR_WP__AMUX CYREG_PRT3_AMUX
+#define nNOR_WP__BIE CYREG_PRT3_BIE
+#define nNOR_WP__BIT_MASK CYREG_PRT3_BIT_MASK
+#define nNOR_WP__BYP CYREG_PRT3_BYP
+#define nNOR_WP__CTL CYREG_PRT3_CTL
+#define nNOR_WP__DM0 CYREG_PRT3_DM0
+#define nNOR_WP__DM1 CYREG_PRT3_DM1
+#define nNOR_WP__DM2 CYREG_PRT3_DM2
+#define nNOR_WP__DR CYREG_PRT3_DR
+#define nNOR_WP__INP_DIS CYREG_PRT3_INP_DIS
+#define nNOR_WP__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
+#define nNOR_WP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define nNOR_WP__LCD_EN CYREG_PRT3_LCD_EN
+#define nNOR_WP__MASK 0x20u
+#define nNOR_WP__PORT 3u
+#define nNOR_WP__PRT CYREG_PRT3_PRT
+#define nNOR_WP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define nNOR_WP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define nNOR_WP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define nNOR_WP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define nNOR_WP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define nNOR_WP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define nNOR_WP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define nNOR_WP__PS CYREG_PRT3_PS
+#define nNOR_WP__SHIFT 5u
+#define nNOR_WP__SLW CYREG_PRT3_SLW
+
 /* SCSI_CLK */
-#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
-#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
-#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG2_CFG0
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG2_CFG1
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG2_CFG2
 #define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
-#define SCSI_CLK__INDEX 0x01u
+#define SCSI_CLK__INDEX 0x02u
 #define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define SCSI_CLK__PM_ACT_MSK 0x02u
+#define SCSI_CLK__PM_ACT_MSK 0x04u
 #define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define SCSI_CLK__PM_STBY_MSK 0x02u
+#define SCSI_CLK__PM_STBY_MSK 0x04u
 
 /* SCSI_Out */
 #define SCSI_Out__0__AG CYREG_PRT6_AG
 #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
 #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL
 #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
 #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
 #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
 #define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
 #define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
 #define SCSI_Out_DBx__DB7__SHIFT 5u
 #define SCSI_Out_DBx__DB7__SLW CYREG_PRT15_SLW
 
+/* NOR_Clock */
+#define NOR_Clock__CFG0 CYREG_CLKDIST_DCFG0_CFG0
+#define NOR_Clock__CFG1 CYREG_CLKDIST_DCFG0_CFG1
+#define NOR_Clock__CFG2 CYREG_CLKDIST_DCFG0_CFG2
+#define NOR_Clock__CFG2_SRC_SEL_MASK 0x07u
+#define NOR_Clock__INDEX 0x00u
+#define NOR_Clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define NOR_Clock__PM_ACT_MSK 0x01u
+#define NOR_Clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define NOR_Clock__PM_STBY_MSK 0x01u
+
 /* SD_RX_DMA */
 #define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
 #define SD_RX_DMA__DRQ_NUMBER 2u
 #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
+/* nNOR_HOLD */
+#define nNOR_HOLD__0__INTTYPE CYREG_PICU12_INTTYPE1
+#define nNOR_HOLD__0__MASK 0x02u
+#define nNOR_HOLD__0__PC CYREG_PRT12_PC1
+#define nNOR_HOLD__0__PORT 12u
+#define nNOR_HOLD__0__SHIFT 1u
+#define nNOR_HOLD__AG CYREG_PRT12_AG
+#define nNOR_HOLD__BIE CYREG_PRT12_BIE
+#define nNOR_HOLD__BIT_MASK CYREG_PRT12_BIT_MASK
+#define nNOR_HOLD__BYP CYREG_PRT12_BYP
+#define nNOR_HOLD__DM0 CYREG_PRT12_DM0
+#define nNOR_HOLD__DM1 CYREG_PRT12_DM1
+#define nNOR_HOLD__DM2 CYREG_PRT12_DM2
+#define nNOR_HOLD__DR CYREG_PRT12_DR
+#define nNOR_HOLD__INP_DIS CYREG_PRT12_INP_DIS
+#define nNOR_HOLD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
+#define nNOR_HOLD__MASK 0x02u
+#define nNOR_HOLD__PORT 12u
+#define nNOR_HOLD__PRT CYREG_PRT12_PRT
+#define nNOR_HOLD__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define nNOR_HOLD__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define nNOR_HOLD__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define nNOR_HOLD__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define nNOR_HOLD__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define nNOR_HOLD__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define nNOR_HOLD__PS CYREG_PRT12_PS
+#define nNOR_HOLD__SHIFT 1u
+#define nNOR_HOLD__SIO_CFG CYREG_PRT12_SIO_CFG
+#define nNOR_HOLD__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define nNOR_HOLD__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define nNOR_HOLD__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define nNOR_HOLD__SLW CYREG_PRT12_SLW
+
 /* SCSI_Noise */
 #define SCSI_Noise__0__AG CYREG_PRT4_AG
 #define SCSI_Noise__0__AMUX CYREG_PRT4_AMUX
 #define scsiTarget_StatusReg__0__POS 0
 #define scsiTarget_StatusReg__1__MASK 0x02u
 #define scsiTarget_StatusReg__1__POS 1
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
 #define scsiTarget_StatusReg__2__MASK 0x04u
 #define scsiTarget_StatusReg__2__POS 2
 #define scsiTarget_StatusReg__3__MASK 0x08u
 #define scsiTarget_StatusReg__4__MASK 0x10u
 #define scsiTarget_StatusReg__4__POS 4
 #define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB15_ST_CTL
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB15_ST_CTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST
 
 /* Debug_Timer */
 #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
 #define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
 /* SD_Data_Clk */
-#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
-#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
-#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2
+#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG1_CFG0
+#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG1_CFG1
+#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG1_CFG2
 #define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u
-#define SD_Data_Clk__INDEX 0x00u
+#define SD_Data_Clk__INDEX 0x01u
 #define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define SD_Data_Clk__PM_ACT_MSK 0x01u
+#define SD_Data_Clk__PM_ACT_MSK 0x02u
 #define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define SD_Data_Clk__PM_STBY_MSK 0x01u
-
-/* SPI_Pullups */
-#define SPI_Pullups__0__INTTYPE CYREG_PICU3_INTTYPE4
-#define SPI_Pullups__0__MASK 0x10u
-#define SPI_Pullups__0__PC CYREG_PRT3_PC4
-#define SPI_Pullups__0__PORT 3u
-#define SPI_Pullups__0__SHIFT 4u
-#define SPI_Pullups__1__INTTYPE CYREG_PICU3_INTTYPE5
-#define SPI_Pullups__1__MASK 0x20u
-#define SPI_Pullups__1__PC CYREG_PRT3_PC5
-#define SPI_Pullups__1__PORT 3u
-#define SPI_Pullups__1__SHIFT 5u
-#define SPI_Pullups__2__INTTYPE CYREG_PICU3_INTTYPE6
-#define SPI_Pullups__2__MASK 0x40u
-#define SPI_Pullups__2__PC CYREG_PRT3_PC6
-#define SPI_Pullups__2__PORT 3u
-#define SPI_Pullups__2__SHIFT 6u
-#define SPI_Pullups__3__INTTYPE CYREG_PICU3_INTTYPE7
-#define SPI_Pullups__3__MASK 0x80u
-#define SPI_Pullups__3__PC CYREG_PRT3_PC7
-#define SPI_Pullups__3__PORT 3u
-#define SPI_Pullups__3__SHIFT 7u
-#define SPI_Pullups__AG CYREG_PRT3_AG
-#define SPI_Pullups__AMUX CYREG_PRT3_AMUX
-#define SPI_Pullups__BIE CYREG_PRT3_BIE
-#define SPI_Pullups__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SPI_Pullups__BYP CYREG_PRT3_BYP
-#define SPI_Pullups__CTL CYREG_PRT3_CTL
-#define SPI_Pullups__DM0 CYREG_PRT3_DM0
-#define SPI_Pullups__DM1 CYREG_PRT3_DM1
-#define SPI_Pullups__DM2 CYREG_PRT3_DM2
-#define SPI_Pullups__DR CYREG_PRT3_DR
-#define SPI_Pullups__INP_DIS CYREG_PRT3_INP_DIS
-#define SPI_Pullups__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
-#define SPI_Pullups__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SPI_Pullups__LCD_EN CYREG_PRT3_LCD_EN
-#define SPI_Pullups__MASK 0xF0u
-#define SPI_Pullups__PORT 3u
-#define SPI_Pullups__PRT CYREG_PRT3_PRT
-#define SPI_Pullups__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SPI_Pullups__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SPI_Pullups__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SPI_Pullups__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SPI_Pullups__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SPI_Pullups__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SPI_Pullups__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SPI_Pullups__PS CYREG_PRT3_PS
-#define SPI_Pullups__SHIFT 4u
-#define SPI_Pullups__SLW CYREG_PRT3_SLW
-#define SPI_Pullups_1__0__INTTYPE CYREG_PICU12_INTTYPE0
-#define SPI_Pullups_1__0__MASK 0x01u
-#define SPI_Pullups_1__0__PC CYREG_PRT12_PC0
-#define SPI_Pullups_1__0__PORT 12u
-#define SPI_Pullups_1__0__SHIFT 0u
-#define SPI_Pullups_1__1__INTTYPE CYREG_PICU12_INTTYPE1
-#define SPI_Pullups_1__1__MASK 0x02u
-#define SPI_Pullups_1__1__PC CYREG_PRT12_PC1
-#define SPI_Pullups_1__1__PORT 12u
-#define SPI_Pullups_1__1__SHIFT 1u
-#define SPI_Pullups_1__AG CYREG_PRT12_AG
-#define SPI_Pullups_1__BIE CYREG_PRT12_BIE
-#define SPI_Pullups_1__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SPI_Pullups_1__BYP CYREG_PRT12_BYP
-#define SPI_Pullups_1__DM0 CYREG_PRT12_DM0
-#define SPI_Pullups_1__DM1 CYREG_PRT12_DM1
-#define SPI_Pullups_1__DM2 CYREG_PRT12_DM2
-#define SPI_Pullups_1__DR CYREG_PRT12_DR
-#define SPI_Pullups_1__INP_DIS CYREG_PRT12_INP_DIS
-#define SPI_Pullups_1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
-#define SPI_Pullups_1__MASK 0x03u
-#define SPI_Pullups_1__PORT 12u
-#define SPI_Pullups_1__PRT CYREG_PRT12_PRT
-#define SPI_Pullups_1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SPI_Pullups_1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SPI_Pullups_1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SPI_Pullups_1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SPI_Pullups_1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SPI_Pullups_1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SPI_Pullups_1__PS CYREG_PRT12_PS
-#define SPI_Pullups_1__SHIFT 0u
-#define SPI_Pullups_1__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SPI_Pullups_1__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SPI_Pullups_1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SPI_Pullups_1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SPI_Pullups_1__SLW CYREG_PRT12_SLW
+#define SD_Data_Clk__PM_STBY_MSK 0x02u
 
 /* timer_clock */
-#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
-#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
-#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2
+#define timer_clock__CFG0 CYREG_CLKDIST_DCFG3_CFG0
+#define timer_clock__CFG1 CYREG_CLKDIST_DCFG3_CFG1
+#define timer_clock__CFG2 CYREG_CLKDIST_DCFG3_CFG2
 #define timer_clock__CFG2_SRC_SEL_MASK 0x07u
-#define timer_clock__INDEX 0x02u
+#define timer_clock__INDEX 0x03u
 #define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define timer_clock__PM_ACT_MSK 0x04u
+#define timer_clock__PM_ACT_MSK 0x08u
 #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define timer_clock__PM_STBY_MSK 0x04u
+#define timer_clock__PM_STBY_MSK 0x08u
 
 /* SCSI_RST_ISR */
 #define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
 #define SCSI_Filtered_sts_sts_reg__0__POS 0
 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
 #define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
 #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
 #define SCSI_Filtered_sts_sts_reg__2__POS 2
 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
 #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
 #define SCSI_Filtered_sts_sts_reg__4__POS 4
 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB15_MSK
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB15_ST
 
 /* SCSI_CTL_PHASE */
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
 
 /* SCSI_Glitch_Ctl */
 #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
 #define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
 
 /* SCSI_Parity_Error */
 #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
 #define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
 #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB14_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB14_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
 
 /* Miscellaneous */
 #define BCLK__BUS_CLK__HZ 50000000U