Add second SPI master for 5.2 board
[SCSI2SD.git] / software / SCSI2SD / v5.2 / SCSI2SD.cydsn / Generated_Source / PSoC5 / cyfittergnu.inc
index d6a1b5c..043d4f7 100644 (file)
 .set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
 .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
 
+/* NOR_SI */
+.set NOR_SI__0__INTTYPE, CYREG_PICU3_INTTYPE6
+.set NOR_SI__0__MASK, 0x40
+.set NOR_SI__0__PC, CYREG_PRT3_PC6
+.set NOR_SI__0__PORT, 3
+.set NOR_SI__0__SHIFT, 6
+.set NOR_SI__AG, CYREG_PRT3_AG
+.set NOR_SI__AMUX, CYREG_PRT3_AMUX
+.set NOR_SI__BIE, CYREG_PRT3_BIE
+.set NOR_SI__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set NOR_SI__BYP, CYREG_PRT3_BYP
+.set NOR_SI__CTL, CYREG_PRT3_CTL
+.set NOR_SI__DM0, CYREG_PRT3_DM0
+.set NOR_SI__DM1, CYREG_PRT3_DM1
+.set NOR_SI__DM2, CYREG_PRT3_DM2
+.set NOR_SI__DR, CYREG_PRT3_DR
+.set NOR_SI__INP_DIS, CYREG_PRT3_INP_DIS
+.set NOR_SI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
+.set NOR_SI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set NOR_SI__LCD_EN, CYREG_PRT3_LCD_EN
+.set NOR_SI__MASK, 0x40
+.set NOR_SI__PORT, 3
+.set NOR_SI__PRT, CYREG_PRT3_PRT
+.set NOR_SI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set NOR_SI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set NOR_SI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set NOR_SI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set NOR_SI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set NOR_SI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set NOR_SI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set NOR_SI__PS, CYREG_PRT3_PS
+.set NOR_SI__SHIFT, 6
+.set NOR_SI__SLW, CYREG_PRT3_SLW
+
+/* NOR_SO */
+.set NOR_SO__0__INTTYPE, CYREG_PICU15_INTTYPE2
+.set NOR_SO__0__MASK, 0x04
+.set NOR_SO__0__PC, CYREG_IO_PC_PRT15_PC2
+.set NOR_SO__0__PORT, 15
+.set NOR_SO__0__SHIFT, 2
+.set NOR_SO__AG, CYREG_PRT15_AG
+.set NOR_SO__AMUX, CYREG_PRT15_AMUX
+.set NOR_SO__BIE, CYREG_PRT15_BIE
+.set NOR_SO__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set NOR_SO__BYP, CYREG_PRT15_BYP
+.set NOR_SO__CTL, CYREG_PRT15_CTL
+.set NOR_SO__DM0, CYREG_PRT15_DM0
+.set NOR_SO__DM1, CYREG_PRT15_DM1
+.set NOR_SO__DM2, CYREG_PRT15_DM2
+.set NOR_SO__DR, CYREG_PRT15_DR
+.set NOR_SO__INP_DIS, CYREG_PRT15_INP_DIS
+.set NOR_SO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
+.set NOR_SO__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set NOR_SO__LCD_EN, CYREG_PRT15_LCD_EN
+.set NOR_SO__MASK, 0x04
+.set NOR_SO__PORT, 15
+.set NOR_SO__PRT, CYREG_PRT15_PRT
+.set NOR_SO__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set NOR_SO__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set NOR_SO__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set NOR_SO__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set NOR_SO__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set NOR_SO__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set NOR_SO__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set NOR_SO__PS, CYREG_PRT15_PS
+.set NOR_SO__SHIFT, 2
+.set NOR_SO__SLW, CYREG_PRT15_SLW
+
 /* SDCard */
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST
 .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
 .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_RxStsReg__6__POS, 6
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70
 .set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
+.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
 .set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
 .set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
 .set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
 .set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
 .set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
 .set SDCard_BSPIM_TxStsReg__0__POS, 0
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
 .set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
 .set SDCard_BSPIM_TxStsReg__2__POS, 2
 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_TxStsReg__4__POS, 4
 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB06_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB06_ST
 
 /* SD_SCK */
 .set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE1
 .set SD_SCK__SHIFT, 1
 .set SD_SCK__SLW, CYREG_PRT3_SLW
 
+/* NOR_CTL */
+.set NOR_CTL_Sync_ctrl_reg__0__MASK, 0x01
+.set NOR_CTL_Sync_ctrl_reg__0__POS, 0
+.set NOR_CTL_Sync_ctrl_reg__1__MASK, 0x02
+.set NOR_CTL_Sync_ctrl_reg__1__POS, 1
+.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
+.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
+.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
+.set NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
+.set NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
+.set NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
+.set NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
+.set NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
+.set NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
+.set NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
+.set NOR_CTL_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB06_CTL
+.set NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
+.set NOR_CTL_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB06_CTL
+.set NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
+.set NOR_CTL_Sync_ctrl_reg__MASK, 0x03
+.set NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set NOR_CTL_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB06_MSK
+
+/* NOR_SCK */
+.set NOR_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE7
+.set NOR_SCK__0__MASK, 0x80
+.set NOR_SCK__0__PC, CYREG_PRT3_PC7
+.set NOR_SCK__0__PORT, 3
+.set NOR_SCK__0__SHIFT, 7
+.set NOR_SCK__AG, CYREG_PRT3_AG
+.set NOR_SCK__AMUX, CYREG_PRT3_AMUX
+.set NOR_SCK__BIE, CYREG_PRT3_BIE
+.set NOR_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set NOR_SCK__BYP, CYREG_PRT3_BYP
+.set NOR_SCK__CTL, CYREG_PRT3_CTL
+.set NOR_SCK__DM0, CYREG_PRT3_DM0
+.set NOR_SCK__DM1, CYREG_PRT3_DM1
+.set NOR_SCK__DM2, CYREG_PRT3_DM2
+.set NOR_SCK__DR, CYREG_PRT3_DR
+.set NOR_SCK__INP_DIS, CYREG_PRT3_INP_DIS
+.set NOR_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
+.set NOR_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set NOR_SCK__LCD_EN, CYREG_PRT3_LCD_EN
+.set NOR_SCK__MASK, 0x80
+.set NOR_SCK__PORT, 3
+.set NOR_SCK__PRT, CYREG_PRT3_PRT
+.set NOR_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set NOR_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set NOR_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set NOR_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set NOR_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set NOR_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set NOR_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set NOR_SCK__PS, CYREG_PRT3_PS
+.set NOR_SCK__SHIFT, 7
+.set NOR_SCK__SLW, CYREG_PRT3_SLW
+
+/* NOR_SPI */
+.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB08_CTL
+.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB08_CTL
+.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB08_MSK
+.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
+.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB08_MSK
+.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
+.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
+.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB08_ST
+.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
+.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
+.set NOR_SPI_BSPIM_RxStsReg__4__MASK, 0x10
+.set NOR_SPI_BSPIM_RxStsReg__4__POS, 4
+.set NOR_SPI_BSPIM_RxStsReg__5__MASK, 0x20
+.set NOR_SPI_BSPIM_RxStsReg__5__POS, 5
+.set NOR_SPI_BSPIM_RxStsReg__6__MASK, 0x40
+.set NOR_SPI_BSPIM_RxStsReg__6__POS, 6
+.set NOR_SPI_BSPIM_RxStsReg__MASK, 0x70
+.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK
+.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
+.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0
+.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0
+.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0
+.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1
+.set NOR_SPI_BSPIM_TxStsReg__0__MASK, 0x01
+.set NOR_SPI_BSPIM_TxStsReg__0__POS, 0
+.set NOR_SPI_BSPIM_TxStsReg__1__MASK, 0x02
+.set NOR_SPI_BSPIM_TxStsReg__1__POS, 1
+.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
+.set NOR_SPI_BSPIM_TxStsReg__2__MASK, 0x04
+.set NOR_SPI_BSPIM_TxStsReg__2__POS, 2
+.set NOR_SPI_BSPIM_TxStsReg__3__MASK, 0x08
+.set NOR_SPI_BSPIM_TxStsReg__3__POS, 3
+.set NOR_SPI_BSPIM_TxStsReg__4__MASK, 0x10
+.set NOR_SPI_BSPIM_TxStsReg__4__POS, 4
+.set NOR_SPI_BSPIM_TxStsReg__MASK, 0x1F
+.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
+.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
+
 /* SCSI_In */
 .set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1
 .set SCSI_In__0__MASK, 0x02
 .set TERM_EN__SHIFT, 3
 .set TERM_EN__SLW, CYREG_PRT15_SLW
 
+/* nNOR_CS */
+.set nNOR_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4
+.set nNOR_CS__0__MASK, 0x10
+.set nNOR_CS__0__PC, CYREG_PRT3_PC4
+.set nNOR_CS__0__PORT, 3
+.set nNOR_CS__0__SHIFT, 4
+.set nNOR_CS__AG, CYREG_PRT3_AG
+.set nNOR_CS__AMUX, CYREG_PRT3_AMUX
+.set nNOR_CS__BIE, CYREG_PRT3_BIE
+.set nNOR_CS__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set nNOR_CS__BYP, CYREG_PRT3_BYP
+.set nNOR_CS__CTL, CYREG_PRT3_CTL
+.set nNOR_CS__DM0, CYREG_PRT3_DM0
+.set nNOR_CS__DM1, CYREG_PRT3_DM1
+.set nNOR_CS__DM2, CYREG_PRT3_DM2
+.set nNOR_CS__DR, CYREG_PRT3_DR
+.set nNOR_CS__INP_DIS, CYREG_PRT3_INP_DIS
+.set nNOR_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
+.set nNOR_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set nNOR_CS__LCD_EN, CYREG_PRT3_LCD_EN
+.set nNOR_CS__MASK, 0x10
+.set nNOR_CS__PORT, 3
+.set nNOR_CS__PRT, CYREG_PRT3_PRT
+.set nNOR_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set nNOR_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set nNOR_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set nNOR_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set nNOR_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set nNOR_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set nNOR_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set nNOR_CS__PS, CYREG_PRT3_PS
+.set nNOR_CS__SHIFT, 4
+.set nNOR_CS__SLW, CYREG_PRT3_SLW
+
+/* nNOR_WP */
+.set nNOR_WP__0__INTTYPE, CYREG_PICU3_INTTYPE5
+.set nNOR_WP__0__MASK, 0x20
+.set nNOR_WP__0__PC, CYREG_PRT3_PC5
+.set nNOR_WP__0__PORT, 3
+.set nNOR_WP__0__SHIFT, 5
+.set nNOR_WP__AG, CYREG_PRT3_AG
+.set nNOR_WP__AMUX, CYREG_PRT3_AMUX
+.set nNOR_WP__BIE, CYREG_PRT3_BIE
+.set nNOR_WP__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set nNOR_WP__BYP, CYREG_PRT3_BYP
+.set nNOR_WP__CTL, CYREG_PRT3_CTL
+.set nNOR_WP__DM0, CYREG_PRT3_DM0
+.set nNOR_WP__DM1, CYREG_PRT3_DM1
+.set nNOR_WP__DM2, CYREG_PRT3_DM2
+.set nNOR_WP__DR, CYREG_PRT3_DR
+.set nNOR_WP__INP_DIS, CYREG_PRT3_INP_DIS
+.set nNOR_WP__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
+.set nNOR_WP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set nNOR_WP__LCD_EN, CYREG_PRT3_LCD_EN
+.set nNOR_WP__MASK, 0x20
+.set nNOR_WP__PORT, 3
+.set nNOR_WP__PRT, CYREG_PRT3_PRT
+.set nNOR_WP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set nNOR_WP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set nNOR_WP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set nNOR_WP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set nNOR_WP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set nNOR_WP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set nNOR_WP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set nNOR_WP__PS, CYREG_PRT3_PS
+.set nNOR_WP__SHIFT, 5
+.set nNOR_WP__SLW, CYREG_PRT3_SLW
+
 /* SCSI_CLK */
-.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
-.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
-.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
+.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG2_CFG0
+.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG2_CFG1
+.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG2_CFG2
 .set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
-.set SCSI_CLK__INDEX, 0x01
+.set SCSI_CLK__INDEX, 0x02
 .set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set SCSI_CLK__PM_ACT_MSK, 0x02
+.set SCSI_CLK__PM_ACT_MSK, 0x04
 .set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set SCSI_CLK__PM_STBY_MSK, 0x02
+.set SCSI_CLK__PM_STBY_MSK, 0x04
 
 /* SCSI_Out */
 .set SCSI_Out__0__AG, CYREG_PRT6_AG
 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
 .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB09_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB09_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL
 .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB09_MSK
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
 .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
 .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
 .set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX
 .set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE
 .set SCSI_Out_DBx__DB7__SHIFT, 5
 .set SCSI_Out_DBx__DB7__SLW, CYREG_PRT15_SLW
 
+/* NOR_Clock */
+.set NOR_Clock__CFG0, CYREG_CLKDIST_DCFG0_CFG0
+.set NOR_Clock__CFG1, CYREG_CLKDIST_DCFG0_CFG1
+.set NOR_Clock__CFG2, CYREG_CLKDIST_DCFG0_CFG2
+.set NOR_Clock__CFG2_SRC_SEL_MASK, 0x07
+.set NOR_Clock__INDEX, 0x00
+.set NOR_Clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set NOR_Clock__PM_ACT_MSK, 0x01
+.set NOR_Clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set NOR_Clock__PM_STBY_MSK, 0x01
+
 /* SD_RX_DMA */
 .set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
 .set SD_RX_DMA__DRQ_NUMBER, 2
 .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
+/* nNOR_HOLD */
+.set nNOR_HOLD__0__INTTYPE, CYREG_PICU12_INTTYPE1
+.set nNOR_HOLD__0__MASK, 0x02
+.set nNOR_HOLD__0__PC, CYREG_PRT12_PC1
+.set nNOR_HOLD__0__PORT, 12
+.set nNOR_HOLD__0__SHIFT, 1
+.set nNOR_HOLD__AG, CYREG_PRT12_AG
+.set nNOR_HOLD__BIE, CYREG_PRT12_BIE
+.set nNOR_HOLD__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set nNOR_HOLD__BYP, CYREG_PRT12_BYP
+.set nNOR_HOLD__DM0, CYREG_PRT12_DM0
+.set nNOR_HOLD__DM1, CYREG_PRT12_DM1
+.set nNOR_HOLD__DM2, CYREG_PRT12_DM2
+.set nNOR_HOLD__DR, CYREG_PRT12_DR
+.set nNOR_HOLD__INP_DIS, CYREG_PRT12_INP_DIS
+.set nNOR_HOLD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU12_BASE
+.set nNOR_HOLD__MASK, 0x02
+.set nNOR_HOLD__PORT, 12
+.set nNOR_HOLD__PRT, CYREG_PRT12_PRT
+.set nNOR_HOLD__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set nNOR_HOLD__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set nNOR_HOLD__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set nNOR_HOLD__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set nNOR_HOLD__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set nNOR_HOLD__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set nNOR_HOLD__PS, CYREG_PRT12_PS
+.set nNOR_HOLD__SHIFT, 1
+.set nNOR_HOLD__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set nNOR_HOLD__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set nNOR_HOLD__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set nNOR_HOLD__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set nNOR_HOLD__SLW, CYREG_PRT12_SLW
+
 /* SCSI_Noise */
 .set SCSI_Noise__0__AG, CYREG_PRT4_AG
 .set SCSI_Noise__0__AMUX, CYREG_PRT4_AMUX
 .set scsiTarget_StatusReg__0__POS, 0
 .set scsiTarget_StatusReg__1__MASK, 0x02
 .set scsiTarget_StatusReg__1__POS, 1
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
 .set scsiTarget_StatusReg__2__MASK, 0x04
 .set scsiTarget_StatusReg__2__POS, 2
 .set scsiTarget_StatusReg__3__MASK, 0x08
 .set scsiTarget_StatusReg__4__MASK, 0x10
 .set scsiTarget_StatusReg__4__POS, 4
 .set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK
-.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
-.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
-.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB15_ST_CTL
-.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB15_ST_CTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST
 
 /* Debug_Timer */
 .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 .set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
 /* SD_Data_Clk */
-.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0
-.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1
-.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2
+.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG1_CFG0
+.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG1_CFG1
+.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG1_CFG2
 .set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07
-.set SD_Data_Clk__INDEX, 0x00
+.set SD_Data_Clk__INDEX, 0x01
 .set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set SD_Data_Clk__PM_ACT_MSK, 0x01
+.set SD_Data_Clk__PM_ACT_MSK, 0x02
 .set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set SD_Data_Clk__PM_STBY_MSK, 0x01
-
-/* SPI_Pullups */
-.set SPI_Pullups__0__INTTYPE, CYREG_PICU3_INTTYPE4
-.set SPI_Pullups__0__MASK, 0x10
-.set SPI_Pullups__0__PC, CYREG_PRT3_PC4
-.set SPI_Pullups__0__PORT, 3
-.set SPI_Pullups__0__SHIFT, 4
-.set SPI_Pullups__1__INTTYPE, CYREG_PICU3_INTTYPE5
-.set SPI_Pullups__1__MASK, 0x20
-.set SPI_Pullups__1__PC, CYREG_PRT3_PC5
-.set SPI_Pullups__1__PORT, 3
-.set SPI_Pullups__1__SHIFT, 5
-.set SPI_Pullups__2__INTTYPE, CYREG_PICU3_INTTYPE6
-.set SPI_Pullups__2__MASK, 0x40
-.set SPI_Pullups__2__PC, CYREG_PRT3_PC6
-.set SPI_Pullups__2__PORT, 3
-.set SPI_Pullups__2__SHIFT, 6
-.set SPI_Pullups__3__INTTYPE, CYREG_PICU3_INTTYPE7
-.set SPI_Pullups__3__MASK, 0x80
-.set SPI_Pullups__3__PC, CYREG_PRT3_PC7
-.set SPI_Pullups__3__PORT, 3
-.set SPI_Pullups__3__SHIFT, 7
-.set SPI_Pullups__AG, CYREG_PRT3_AG
-.set SPI_Pullups__AMUX, CYREG_PRT3_AMUX
-.set SPI_Pullups__BIE, CYREG_PRT3_BIE
-.set SPI_Pullups__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SPI_Pullups__BYP, CYREG_PRT3_BYP
-.set SPI_Pullups__CTL, CYREG_PRT3_CTL
-.set SPI_Pullups__DM0, CYREG_PRT3_DM0
-.set SPI_Pullups__DM1, CYREG_PRT3_DM1
-.set SPI_Pullups__DM2, CYREG_PRT3_DM2
-.set SPI_Pullups__DR, CYREG_PRT3_DR
-.set SPI_Pullups__INP_DIS, CYREG_PRT3_INP_DIS
-.set SPI_Pullups__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
-.set SPI_Pullups__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SPI_Pullups__LCD_EN, CYREG_PRT3_LCD_EN
-.set SPI_Pullups__MASK, 0xF0
-.set SPI_Pullups__PORT, 3
-.set SPI_Pullups__PRT, CYREG_PRT3_PRT
-.set SPI_Pullups__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SPI_Pullups__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SPI_Pullups__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SPI_Pullups__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SPI_Pullups__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SPI_Pullups__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SPI_Pullups__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SPI_Pullups__PS, CYREG_PRT3_PS
-.set SPI_Pullups__SHIFT, 4
-.set SPI_Pullups__SLW, CYREG_PRT3_SLW
-.set SPI_Pullups_1__0__INTTYPE, CYREG_PICU12_INTTYPE0
-.set SPI_Pullups_1__0__MASK, 0x01
-.set SPI_Pullups_1__0__PC, CYREG_PRT12_PC0
-.set SPI_Pullups_1__0__PORT, 12
-.set SPI_Pullups_1__0__SHIFT, 0
-.set SPI_Pullups_1__1__INTTYPE, CYREG_PICU12_INTTYPE1
-.set SPI_Pullups_1__1__MASK, 0x02
-.set SPI_Pullups_1__1__PC, CYREG_PRT12_PC1
-.set SPI_Pullups_1__1__PORT, 12
-.set SPI_Pullups_1__1__SHIFT, 1
-.set SPI_Pullups_1__AG, CYREG_PRT12_AG
-.set SPI_Pullups_1__BIE, CYREG_PRT12_BIE
-.set SPI_Pullups_1__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SPI_Pullups_1__BYP, CYREG_PRT12_BYP
-.set SPI_Pullups_1__DM0, CYREG_PRT12_DM0
-.set SPI_Pullups_1__DM1, CYREG_PRT12_DM1
-.set SPI_Pullups_1__DM2, CYREG_PRT12_DM2
-.set SPI_Pullups_1__DR, CYREG_PRT12_DR
-.set SPI_Pullups_1__INP_DIS, CYREG_PRT12_INP_DIS
-.set SPI_Pullups_1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU12_BASE
-.set SPI_Pullups_1__MASK, 0x03
-.set SPI_Pullups_1__PORT, 12
-.set SPI_Pullups_1__PRT, CYREG_PRT12_PRT
-.set SPI_Pullups_1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SPI_Pullups_1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SPI_Pullups_1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SPI_Pullups_1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SPI_Pullups_1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SPI_Pullups_1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SPI_Pullups_1__PS, CYREG_PRT12_PS
-.set SPI_Pullups_1__SHIFT, 0
-.set SPI_Pullups_1__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SPI_Pullups_1__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SPI_Pullups_1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SPI_Pullups_1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SPI_Pullups_1__SLW, CYREG_PRT12_SLW
+.set SD_Data_Clk__PM_STBY_MSK, 0x02
 
 /* timer_clock */
-.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0
-.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1
-.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2
+.set timer_clock__CFG0, CYREG_CLKDIST_DCFG3_CFG0
+.set timer_clock__CFG1, CYREG_CLKDIST_DCFG3_CFG1
+.set timer_clock__CFG2, CYREG_CLKDIST_DCFG3_CFG2
 .set timer_clock__CFG2_SRC_SEL_MASK, 0x07
-.set timer_clock__INDEX, 0x02
+.set timer_clock__INDEX, 0x03
 .set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set timer_clock__PM_ACT_MSK, 0x04
+.set timer_clock__PM_ACT_MSK, 0x08
 .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set timer_clock__PM_STBY_MSK, 0x04
+.set timer_clock__PM_STBY_MSK, 0x08
 
 /* SCSI_RST_ISR */
 .set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 .set SCSI_Filtered_sts_sts_reg__0__POS, 0
 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
 .set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
 .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
 .set SCSI_Filtered_sts_sts_reg__2__POS, 2
 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
 .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
 .set SCSI_Filtered_sts_sts_reg__4__POS, 4
 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB15_MSK
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB15_ST
 
 /* SCSI_CTL_PHASE */
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
 
 /* SCSI_Glitch_Ctl */
 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK
 
 /* SCSI_Parity_Error */
 .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
 .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB14_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB14_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
 
 /* Miscellaneous */
 .set BCLK__BUS_CLK__HZ, 50000000