Add second SPI master for 5.2 board
[SCSI2SD.git] / software / SCSI2SD / v5.2 / SCSI2SD.cydsn / Generated_Source / PSoC5 / cyfitterrv.inc
index cd3a5eb..5ddb795 100644 (file)
@@ -354,33 +354,101 @@ USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
 USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
 
+; NOR_SI
+NOR_SI__0__INTTYPE EQU CYREG_PICU3_INTTYPE6
+NOR_SI__0__MASK EQU 0x40
+NOR_SI__0__PC EQU CYREG_PRT3_PC6
+NOR_SI__0__PORT EQU 3
+NOR_SI__0__SHIFT EQU 6
+NOR_SI__AG EQU CYREG_PRT3_AG
+NOR_SI__AMUX EQU CYREG_PRT3_AMUX
+NOR_SI__BIE EQU CYREG_PRT3_BIE
+NOR_SI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+NOR_SI__BYP EQU CYREG_PRT3_BYP
+NOR_SI__CTL EQU CYREG_PRT3_CTL
+NOR_SI__DM0 EQU CYREG_PRT3_DM0
+NOR_SI__DM1 EQU CYREG_PRT3_DM1
+NOR_SI__DM2 EQU CYREG_PRT3_DM2
+NOR_SI__DR EQU CYREG_PRT3_DR
+NOR_SI__INP_DIS EQU CYREG_PRT3_INP_DIS
+NOR_SI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
+NOR_SI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+NOR_SI__LCD_EN EQU CYREG_PRT3_LCD_EN
+NOR_SI__MASK EQU 0x40
+NOR_SI__PORT EQU 3
+NOR_SI__PRT EQU CYREG_PRT3_PRT
+NOR_SI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+NOR_SI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+NOR_SI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+NOR_SI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+NOR_SI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+NOR_SI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+NOR_SI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+NOR_SI__PS EQU CYREG_PRT3_PS
+NOR_SI__SHIFT EQU 6
+NOR_SI__SLW EQU CYREG_PRT3_SLW
+
+; NOR_SO
+NOR_SO__0__INTTYPE EQU CYREG_PICU15_INTTYPE2
+NOR_SO__0__MASK EQU 0x04
+NOR_SO__0__PC EQU CYREG_IO_PC_PRT15_PC2
+NOR_SO__0__PORT EQU 15
+NOR_SO__0__SHIFT EQU 2
+NOR_SO__AG EQU CYREG_PRT15_AG
+NOR_SO__AMUX EQU CYREG_PRT15_AMUX
+NOR_SO__BIE EQU CYREG_PRT15_BIE
+NOR_SO__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+NOR_SO__BYP EQU CYREG_PRT15_BYP
+NOR_SO__CTL EQU CYREG_PRT15_CTL
+NOR_SO__DM0 EQU CYREG_PRT15_DM0
+NOR_SO__DM1 EQU CYREG_PRT15_DM1
+NOR_SO__DM2 EQU CYREG_PRT15_DM2
+NOR_SO__DR EQU CYREG_PRT15_DR
+NOR_SO__INP_DIS EQU CYREG_PRT15_INP_DIS
+NOR_SO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
+NOR_SO__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+NOR_SO__LCD_EN EQU CYREG_PRT15_LCD_EN
+NOR_SO__MASK EQU 0x04
+NOR_SO__PORT EQU 15
+NOR_SO__PRT EQU CYREG_PRT15_PRT
+NOR_SO__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+NOR_SO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+NOR_SO__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+NOR_SO__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+NOR_SO__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+NOR_SO__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+NOR_SO__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+NOR_SO__PS EQU CYREG_PRT15_PS
+NOR_SO__SHIFT EQU 2
+NOR_SO__SLW EQU CYREG_PRT15_SLW
+
 ; SDCard
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
 SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
 SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
@@ -391,7 +459,11 @@ SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
 SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
 SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
 SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
@@ -410,14 +482,12 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
 SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
 SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
 SDCard_BSPIM_TxStsReg__2__POS EQU 2
 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@@ -425,9 +495,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_TxStsReg__4__POS EQU 4
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST
 
 ; SD_SCK
 SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
@@ -463,6 +533,137 @@ SD_SCK__PS EQU CYREG_PRT3_PS
 SD_SCK__SHIFT EQU 1
 SD_SCK__SLW EQU CYREG_PRT3_SLW
 
+; NOR_CTL
+NOR_CTL_Sync_ctrl_reg__0__MASK EQU 0x01
+NOR_CTL_Sync_ctrl_reg__0__POS EQU 0
+NOR_CTL_Sync_ctrl_reg__1__MASK EQU 0x02
+NOR_CTL_Sync_ctrl_reg__1__POS EQU 1
+NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+NOR_CTL_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB06_CTL
+NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+NOR_CTL_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB06_CTL
+NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+NOR_CTL_Sync_ctrl_reg__MASK EQU 0x03
+NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+NOR_CTL_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB06_MSK
+
+; NOR_SCK
+NOR_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE7
+NOR_SCK__0__MASK EQU 0x80
+NOR_SCK__0__PC EQU CYREG_PRT3_PC7
+NOR_SCK__0__PORT EQU 3
+NOR_SCK__0__SHIFT EQU 7
+NOR_SCK__AG EQU CYREG_PRT3_AG
+NOR_SCK__AMUX EQU CYREG_PRT3_AMUX
+NOR_SCK__BIE EQU CYREG_PRT3_BIE
+NOR_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+NOR_SCK__BYP EQU CYREG_PRT3_BYP
+NOR_SCK__CTL EQU CYREG_PRT3_CTL
+NOR_SCK__DM0 EQU CYREG_PRT3_DM0
+NOR_SCK__DM1 EQU CYREG_PRT3_DM1
+NOR_SCK__DM2 EQU CYREG_PRT3_DM2
+NOR_SCK__DR EQU CYREG_PRT3_DR
+NOR_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
+NOR_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
+NOR_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+NOR_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
+NOR_SCK__MASK EQU 0x80
+NOR_SCK__PORT EQU 3
+NOR_SCK__PRT EQU CYREG_PRT3_PRT
+NOR_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+NOR_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+NOR_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+NOR_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+NOR_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+NOR_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+NOR_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+NOR_SCK__PS EQU CYREG_PRT3_PS
+NOR_SCK__SHIFT EQU 7
+NOR_SCK__SLW EQU CYREG_PRT3_SLW
+
+; NOR_SPI
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL
+NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
+NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK
+NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST
+NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
+NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10
+NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4
+NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20
+NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5
+NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40
+NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6
+NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70
+NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
+NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
+NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
+NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
+NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0
+NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1
+NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
+NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0
+NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1
+NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
+NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0
+NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1
+NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01
+NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0
+NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02
+NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1
+NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04
+NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2
+NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08
+NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3
+NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10
+NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4
+NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F
+NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
+
 ; SCSI_In
 SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
 SCSI_In__0__MASK EQU 0x02
@@ -1050,16 +1251,84 @@ TERM_EN__PS EQU CYREG_PRT15_PS
 TERM_EN__SHIFT EQU 3
 TERM_EN__SLW EQU CYREG_PRT15_SLW
 
+; nNOR_CS
+nNOR_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4
+nNOR_CS__0__MASK EQU 0x10
+nNOR_CS__0__PC EQU CYREG_PRT3_PC4
+nNOR_CS__0__PORT EQU 3
+nNOR_CS__0__SHIFT EQU 4
+nNOR_CS__AG EQU CYREG_PRT3_AG
+nNOR_CS__AMUX EQU CYREG_PRT3_AMUX
+nNOR_CS__BIE EQU CYREG_PRT3_BIE
+nNOR_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+nNOR_CS__BYP EQU CYREG_PRT3_BYP
+nNOR_CS__CTL EQU CYREG_PRT3_CTL
+nNOR_CS__DM0 EQU CYREG_PRT3_DM0
+nNOR_CS__DM1 EQU CYREG_PRT3_DM1
+nNOR_CS__DM2 EQU CYREG_PRT3_DM2
+nNOR_CS__DR EQU CYREG_PRT3_DR
+nNOR_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
+nNOR_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
+nNOR_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+nNOR_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
+nNOR_CS__MASK EQU 0x10
+nNOR_CS__PORT EQU 3
+nNOR_CS__PRT EQU CYREG_PRT3_PRT
+nNOR_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+nNOR_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+nNOR_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+nNOR_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+nNOR_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+nNOR_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+nNOR_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+nNOR_CS__PS EQU CYREG_PRT3_PS
+nNOR_CS__SHIFT EQU 4
+nNOR_CS__SLW EQU CYREG_PRT3_SLW
+
+; nNOR_WP
+nNOR_WP__0__INTTYPE EQU CYREG_PICU3_INTTYPE5
+nNOR_WP__0__MASK EQU 0x20
+nNOR_WP__0__PC EQU CYREG_PRT3_PC5
+nNOR_WP__0__PORT EQU 3
+nNOR_WP__0__SHIFT EQU 5
+nNOR_WP__AG EQU CYREG_PRT3_AG
+nNOR_WP__AMUX EQU CYREG_PRT3_AMUX
+nNOR_WP__BIE EQU CYREG_PRT3_BIE
+nNOR_WP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+nNOR_WP__BYP EQU CYREG_PRT3_BYP
+nNOR_WP__CTL EQU CYREG_PRT3_CTL
+nNOR_WP__DM0 EQU CYREG_PRT3_DM0
+nNOR_WP__DM1 EQU CYREG_PRT3_DM1
+nNOR_WP__DM2 EQU CYREG_PRT3_DM2
+nNOR_WP__DR EQU CYREG_PRT3_DR
+nNOR_WP__INP_DIS EQU CYREG_PRT3_INP_DIS
+nNOR_WP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
+nNOR_WP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+nNOR_WP__LCD_EN EQU CYREG_PRT3_LCD_EN
+nNOR_WP__MASK EQU 0x20
+nNOR_WP__PORT EQU 3
+nNOR_WP__PRT EQU CYREG_PRT3_PRT
+nNOR_WP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+nNOR_WP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+nNOR_WP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+nNOR_WP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+nNOR_WP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+nNOR_WP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+nNOR_WP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+nNOR_WP__PS EQU CYREG_PRT3_PS
+nNOR_WP__SHIFT EQU 5
+nNOR_WP__SLW EQU CYREG_PRT3_SLW
+
 ; SCSI_CLK
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
 SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
-SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__INDEX EQU 0x02
 SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_ACT_MSK EQU 0x04
 SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SCSI_CLK__PM_STBY_MSK EQU 0x02
+SCSI_CLK__PM_STBY_MSK EQU 0x04
 
 ; SCSI_Out
 SCSI_Out__0__AG EQU CYREG_PRT6_AG
@@ -1514,15 +1783,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1535,35 +1804,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
 SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
 SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
 SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
 SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
@@ -2011,6 +2280,17 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS
 SCSI_Out_DBx__DB7__SHIFT EQU 5
 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW
 
+; NOR_Clock
+NOR_Clock__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
+NOR_Clock__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
+NOR_Clock__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
+NOR_Clock__CFG2_SRC_SEL_MASK EQU 0x07
+NOR_Clock__INDEX EQU 0x00
+NOR_Clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+NOR_Clock__PM_ACT_MSK EQU 0x01
+NOR_Clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+NOR_Clock__PM_STBY_MSK EQU 0x01
+
 ; SD_RX_DMA
 SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
 SD_RX_DMA__DRQ_NUMBER EQU 2
@@ -2051,6 +2331,39 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
+; nNOR_HOLD
+nNOR_HOLD__0__INTTYPE EQU CYREG_PICU12_INTTYPE1
+nNOR_HOLD__0__MASK EQU 0x02
+nNOR_HOLD__0__PC EQU CYREG_PRT12_PC1
+nNOR_HOLD__0__PORT EQU 12
+nNOR_HOLD__0__SHIFT EQU 1
+nNOR_HOLD__AG EQU CYREG_PRT12_AG
+nNOR_HOLD__BIE EQU CYREG_PRT12_BIE
+nNOR_HOLD__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+nNOR_HOLD__BYP EQU CYREG_PRT12_BYP
+nNOR_HOLD__DM0 EQU CYREG_PRT12_DM0
+nNOR_HOLD__DM1 EQU CYREG_PRT12_DM1
+nNOR_HOLD__DM2 EQU CYREG_PRT12_DM2
+nNOR_HOLD__DR EQU CYREG_PRT12_DR
+nNOR_HOLD__INP_DIS EQU CYREG_PRT12_INP_DIS
+nNOR_HOLD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE
+nNOR_HOLD__MASK EQU 0x02
+nNOR_HOLD__PORT EQU 12
+nNOR_HOLD__PRT EQU CYREG_PRT12_PRT
+nNOR_HOLD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+nNOR_HOLD__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+nNOR_HOLD__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+nNOR_HOLD__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+nNOR_HOLD__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+nNOR_HOLD__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+nNOR_HOLD__PS EQU CYREG_PRT12_PS
+nNOR_HOLD__SHIFT EQU 1
+nNOR_HOLD__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+nNOR_HOLD__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+nNOR_HOLD__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+nNOR_HOLD__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+nNOR_HOLD__SLW EQU CYREG_PRT12_SLW
+
 ; SCSI_Noise
 SCSI_Noise__0__AG EQU CYREG_PRT4_AG
 SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX
@@ -2383,6 +2696,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0
 scsiTarget_StatusReg__1__MASK EQU 0x02
 scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
 scsiTarget_StatusReg__2__MASK EQU 0x04
 scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2390,13 +2705,13 @@ scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__4__MASK EQU 0x10
 scsiTarget_StatusReg__4__POS EQU 4
 scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
 
 ; Debug_Timer
 Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2465,111 +2780,26 @@ SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 ; SD_Data_Clk
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
 SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
-SD_Data_Clk__INDEX EQU 0x00
+SD_Data_Clk__INDEX EQU 0x01
 SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SD_Data_Clk__PM_ACT_MSK EQU 0x01
+SD_Data_Clk__PM_ACT_MSK EQU 0x02
 SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SD_Data_Clk__PM_STBY_MSK EQU 0x01
-
-; SPI_Pullups
-SPI_Pullups__0__INTTYPE EQU CYREG_PICU3_INTTYPE4
-SPI_Pullups__0__MASK EQU 0x10
-SPI_Pullups__0__PC EQU CYREG_PRT3_PC4
-SPI_Pullups__0__PORT EQU 3
-SPI_Pullups__0__SHIFT EQU 4
-SPI_Pullups__1__INTTYPE EQU CYREG_PICU3_INTTYPE5
-SPI_Pullups__1__MASK EQU 0x20
-SPI_Pullups__1__PC EQU CYREG_PRT3_PC5
-SPI_Pullups__1__PORT EQU 3
-SPI_Pullups__1__SHIFT EQU 5
-SPI_Pullups__2__INTTYPE EQU CYREG_PICU3_INTTYPE6
-SPI_Pullups__2__MASK EQU 0x40
-SPI_Pullups__2__PC EQU CYREG_PRT3_PC6
-SPI_Pullups__2__PORT EQU 3
-SPI_Pullups__2__SHIFT EQU 6
-SPI_Pullups__3__INTTYPE EQU CYREG_PICU3_INTTYPE7
-SPI_Pullups__3__MASK EQU 0x80
-SPI_Pullups__3__PC EQU CYREG_PRT3_PC7
-SPI_Pullups__3__PORT EQU 3
-SPI_Pullups__3__SHIFT EQU 7
-SPI_Pullups__AG EQU CYREG_PRT3_AG
-SPI_Pullups__AMUX EQU CYREG_PRT3_AMUX
-SPI_Pullups__BIE EQU CYREG_PRT3_BIE
-SPI_Pullups__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SPI_Pullups__BYP EQU CYREG_PRT3_BYP
-SPI_Pullups__CTL EQU CYREG_PRT3_CTL
-SPI_Pullups__DM0 EQU CYREG_PRT3_DM0
-SPI_Pullups__DM1 EQU CYREG_PRT3_DM1
-SPI_Pullups__DM2 EQU CYREG_PRT3_DM2
-SPI_Pullups__DR EQU CYREG_PRT3_DR
-SPI_Pullups__INP_DIS EQU CYREG_PRT3_INP_DIS
-SPI_Pullups__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
-SPI_Pullups__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SPI_Pullups__LCD_EN EQU CYREG_PRT3_LCD_EN
-SPI_Pullups__MASK EQU 0xF0
-SPI_Pullups__PORT EQU 3
-SPI_Pullups__PRT EQU CYREG_PRT3_PRT
-SPI_Pullups__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SPI_Pullups__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SPI_Pullups__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SPI_Pullups__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SPI_Pullups__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SPI_Pullups__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SPI_Pullups__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SPI_Pullups__PS EQU CYREG_PRT3_PS
-SPI_Pullups__SHIFT EQU 4
-SPI_Pullups__SLW EQU CYREG_PRT3_SLW
-SPI_Pullups_1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0
-SPI_Pullups_1__0__MASK EQU 0x01
-SPI_Pullups_1__0__PC EQU CYREG_PRT12_PC0
-SPI_Pullups_1__0__PORT EQU 12
-SPI_Pullups_1__0__SHIFT EQU 0
-SPI_Pullups_1__1__INTTYPE EQU CYREG_PICU12_INTTYPE1
-SPI_Pullups_1__1__MASK EQU 0x02
-SPI_Pullups_1__1__PC EQU CYREG_PRT12_PC1
-SPI_Pullups_1__1__PORT EQU 12
-SPI_Pullups_1__1__SHIFT EQU 1
-SPI_Pullups_1__AG EQU CYREG_PRT12_AG
-SPI_Pullups_1__BIE EQU CYREG_PRT12_BIE
-SPI_Pullups_1__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SPI_Pullups_1__BYP EQU CYREG_PRT12_BYP
-SPI_Pullups_1__DM0 EQU CYREG_PRT12_DM0
-SPI_Pullups_1__DM1 EQU CYREG_PRT12_DM1
-SPI_Pullups_1__DM2 EQU CYREG_PRT12_DM2
-SPI_Pullups_1__DR EQU CYREG_PRT12_DR
-SPI_Pullups_1__INP_DIS EQU CYREG_PRT12_INP_DIS
-SPI_Pullups_1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE
-SPI_Pullups_1__MASK EQU 0x03
-SPI_Pullups_1__PORT EQU 12
-SPI_Pullups_1__PRT EQU CYREG_PRT12_PRT
-SPI_Pullups_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SPI_Pullups_1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SPI_Pullups_1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SPI_Pullups_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SPI_Pullups_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SPI_Pullups_1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SPI_Pullups_1__PS EQU CYREG_PRT12_PS
-SPI_Pullups_1__SHIFT EQU 0
-SPI_Pullups_1__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SPI_Pullups_1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SPI_Pullups_1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SPI_Pullups_1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SPI_Pullups_1__SLW EQU CYREG_PRT12_SLW
+SD_Data_Clk__PM_STBY_MSK EQU 0x02
 
 ; timer_clock
-timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
-timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
-timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2
 timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
-timer_clock__INDEX EQU 0x02
+timer_clock__INDEX EQU 0x03
 timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-timer_clock__PM_ACT_MSK EQU 0x04
+timer_clock__PM_ACT_MSK EQU 0x08
 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-timer_clock__PM_STBY_MSK EQU 0x04
+timer_clock__PM_STBY_MSK EQU 0x08
 
 ; SCSI_RST_ISR
 SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2596,8 +2826,6 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2605,58 +2833,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST
 
 ; SCSI_CTL_PHASE
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
 
 ; SCSI_Glitch_Ctl
 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
 SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
 
 ; SCSI_Parity_Error
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB14_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB14_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
 
 ; Miscellaneous
 BCLK__BUS_CLK__HZ EQU 50000000