Add second SPI master for 5.2 board
[SCSI2SD.git] / software / SCSI2SD / v5.2 / SCSI2SD.cydsn / SCSI2SD.svd
index 510c132..9c0eed5 100644 (file)
@@ -7,7 +7,7 @@
   <width>32</width>
   <peripherals>
     <peripheral>
-      <name>SCSI_Filtered</name>
+      <name>SCSI_Glitch_Ctl</name>
       <description>No description available</description>
       <baseAddress>0x0</baseAddress>
       <addressBlock>
       </addressBlock>
       <registers>
         <register>
-          <name>SCSI_Filtered_STATUS_REG</name>
+          <name>SCSI_Glitch_Ctl_CONTROL_REG</name>
+          <description>No description available</description>
+          <addressOffset>0x4000647D</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SCSI_Parity_Error</name>
+      <description>No description available</description>
+      <baseAddress>0x0</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SCSI_Parity_Error_STATUS_REG</name>
           <description>No description available</description>
-          <addressOffset>0x40006467</addressOffset>
+          <addressOffset>0x4000646B</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
         </register>
         <register>
-          <name>SCSI_Filtered_MASK_REG</name>
+          <name>SCSI_Parity_Error_MASK_REG</name>
           <description>No description available</description>
-          <addressOffset>0x40006487</addressOffset>
+          <addressOffset>0x4000648B</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
         </register>
         <register>
-          <name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
+          <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
           <description>No description available</description>
-          <addressOffset>0x40006497</addressOffset>
+          <addressOffset>0x4000649B</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
       </registers>
     </peripheral>
     <peripheral>
-      <name>SCSI_Parity_Error</name>
+      <name>SCSI_Filtered</name>
       <description>No description available</description>
       <baseAddress>0x0</baseAddress>
       <addressBlock>
       </addressBlock>
       <registers>
         <register>
-          <name>SCSI_Parity_Error_STATUS_REG</name>
+          <name>SCSI_Filtered_STATUS_REG</name>
           <description>No description available</description>
-          <addressOffset>0x4000646E</addressOffset>
+          <addressOffset>0x4000646F</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
         </register>
         <register>
-          <name>SCSI_Parity_Error_MASK_REG</name>
+          <name>SCSI_Filtered_MASK_REG</name>
           <description>No description available</description>
-          <addressOffset>0x4000648E</addressOffset>
+          <addressOffset>0x4000648F</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
         </register>
         <register>
-          <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
+          <name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
           <description>No description available</description>
-          <addressOffset>0x4000649E</addressOffset>
+          <addressOffset>0x4000649F</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
       </registers>
     </peripheral>
     <peripheral>
-      <name>SCSI_Glitch_Ctl</name>
+      <name>NOR_CTL</name>
       <description>No description available</description>
       <baseAddress>0x0</baseAddress>
       <addressBlock>
       </addressBlock>
       <registers>
         <register>
-          <name>SCSI_Glitch_Ctl_CONTROL_REG</name>
+          <name>NOR_CTL_CONTROL_REG</name>
           <description>No description available</description>
-          <addressOffset>0x40006473</addressOffset>
+          <addressOffset>0x40006576</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
         <register>
           <name>SCSI_CTL_PHASE_CONTROL_REG</name>
           <description>No description available</description>
-          <addressOffset>0x4000647F</addressOffset>
+          <addressOffset>0x4000647C</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
       </registers>
     </peripheral>
     <peripheral>
-      <name>Debug_Timer</name>
-      <description>No description available</description>
+      <name>USBFS</name>
+      <description>USBFS</description>
       <baseAddress>0x0</baseAddress>
       <addressBlock>
         <offset>0</offset>
       </addressBlock>
       <registers>
         <register>
-          <name>Debug_Timer_GLOBAL_ENABLE</name>
-          <description>PM.ACT.CFG</description>
-          <addressOffset>0x400043A3</addressOffset>
+          <name>CR0</name>
+          <description>USB Control 0 Register</description>
+          <addressOffset>0x40006008</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
           <fields>
             <field>
-              <name>en_timer</name>
-              <description>Enable timer/counters.</description>
+              <name>DEVICE_ADDRESS</name>
+              <description>These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware.</description>
               <lsb>0</lsb>
-              <msb>3</msb>
+              <msb>6</msb>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_ENABLE</name>
+              <description>This bit enables the device to respond to USB traffic.</description>
+              <lsb>7</lsb>
+              <msb>7</msb>
               <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disabled</name>
+                  <description>Block responds to USB traffic.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enabled</name>
+                  <description>Block does not respond to USB traffic.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
             </field>
           </fields>
         </register>
         <register>
-          <name>Debug_Timer_CONTROL</name>
-          <description>TMRx.CFG0</description>
-          <addressOffset>0x40004F00</addressOffset>
+          <name>CR1</name>
+          <description>USB Control 1 Register</description>
+          <addressOffset>0x40006009</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
           <fields>
             <field>
-              <name>EN</name>
-              <description>Enables timer/comparator.</description>
+              <name>REG_ENABLE</name>
+              <description>This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply.</description>
               <lsb>0</lsb>
               <msb>0</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>MODE</name>
-              <description>Mode. (0 = Timer; 1 = Comparator)</description>
-              <lsb>1</lsb>
-              <msb>1</msb>
-              <access>read-write</access>
+              <access>read-only</access>
               <enumeratedValues>
                 <enumeratedValue>
-                  <name>Timer</name>
-                  <description>Timer mode. CNT/CMP register holds timer count value.</description>
+                  <name>Disabled</name>
+                  <description>Regulator for 5V is disabled.</description>
                   <value>0</value>
                 </enumeratedValue>
                 <enumeratedValue>
-                  <name>Comparator</name>
-                  <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
+                  <name>Enabled</name>
+                  <description>Regulator for 5V is enabled.</description>
                   <value>1</value>
                 </enumeratedValue>
               </enumeratedValues>
             </field>
             <field>
-              <name>ONESHOT</name>
-              <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
+              <name>ENABLE_LOCK</name>
+              <description>This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic.  Unless an external clock is being provided this bit should remain set for proper USB operation.</description>
+              <lsb>1</lsb>
+              <msb>1</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUS_ACTIVITY</name>
+              <description>The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it.</description>
               <lsb>2</lsb>
               <msb>2</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>CMP_BUFF</name>
-              <description>Buffer compare register. Compare register updates only on timer terminal count.</description>
+              <name>TRIM_OFFSET_MSB</name>
+              <description>This bit enables trim bit[7].</description>
+              <lsb>3</lsb>
+              <msb>3</msb>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIE_EP_INT_EN</name>
+          <description>USB SIE Data Endpoints Interrupt Enable Register</description>
+          <addressOffset>0x4000600A</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>EP1_INTR_EN</name>
+              <description>Enables interrupt for EP1.</description>
+              <lsb>0</lsb>
+              <msb>0</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EP2_INTR_EN</name>
+              <description>Enables interrupt for EP2.</description>
+              <lsb>1</lsb>
+              <msb>1</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EP3_INTR_EN</name>
+              <description>Enables interrupt for EP3.</description>
+              <lsb>2</lsb>
+              <msb>2</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EP4_INTR_EN</name>
+              <description>Enables interrupt for EP4.</description>
               <lsb>3</lsb>
               <msb>3</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>INV</name>
-              <description>Invert sense of TIMEREN signal</description>
+              <name>EP5_INTR_EN</name>
+              <description>Enables interrupt for EP5.</description>
               <lsb>4</lsb>
               <msb>4</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>DB</name>
-              <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
+              <name>EP6_INTR_EN</name>
+              <description>Enables interrupt for EP6.</description>
               <lsb>5</lsb>
               <msb>5</msb>
               <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Timer</name>
-                  <description>CMP and TC are output.</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Deadband</name>
-                  <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
             </field>
             <field>
-              <name>DEADBAND_PERIOD</name>
-              <description>Deadband Period</description>
+              <name>EP7_INTR_EN</name>
+              <description>Enables interrupt for EP7.</description>
               <lsb>6</lsb>
+              <msb>6</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EP8_INTR_EN</name>
+              <description>Enables interrupt for EP8.</description>
+              <lsb>7</lsb>
               <msb>7</msb>
               <access>read-write</access>
             </field>
           </fields>
         </register>
         <register>
-          <name>Debug_Timer_CONTROL2</name>
-          <description>TMRx.CFG1</description>
-          <addressOffset>0x40004F01</addressOffset>
+          <name>SIE_EP_INT_SR</name>
+          <description>SIE Data Endpoint Interrupt Status Register</description>
+          <addressOffset>0x4000600B</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
           <fields>
             <field>
-              <name>IRQ_SEL</name>
-              <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
+              <name>EP1_INTR</name>
+              <description>Interrupt status for EP1.</description>
               <lsb>0</lsb>
               <msb>0</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>FTC</name>
-              <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
+              <name>EP2_INTR</name>
+              <description>Interrupt status for EP2.</description>
               <lsb>1</lsb>
               <msb>1</msb>
               <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Disable_FTC</name>
-                  <description>Disable the single cycle pulse, which signifies the timer is starting.</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Enable_FTC</name>
-                  <description>Enable the single cycle pulse, which signifies the timer is starting.</description>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
             </field>
             <field>
-              <name>DCOR</name>
-              <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
+              <name>EP3_INTR</name>
+              <description>Interrupt status for EP3.</description>
               <lsb>2</lsb>
               <msb>2</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>DBMODE</name>
-              <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
+              <name>EP4_INTR</name>
+              <description>Interrupt status for EP4.</description>
               <lsb>3</lsb>
               <msb>3</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>CLK_BUS_EN_SEL</name>
-              <description>Digital Global Clock selection.</description>
+              <name>EP5_INTR</name>
+              <description>Interrupt status for EP5.</description>
               <lsb>4</lsb>
+              <msb>4</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EP6_INTR</name>
+              <description>Interrupt status for EP6.</description>
+              <lsb>5</lsb>
+              <msb>5</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EP7_INTR</name>
+              <description>Interrupt status for EP7.</description>
+              <lsb>6</lsb>
               <msb>6</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>BUS_CLK_SEL</name>
-              <description>Bus Clock selection.</description>
+              <name>EP8_INTR</name>
+              <description>Interrupt status for EP8.</description>
               <lsb>7</lsb>
               <msb>7</msb>
               <access>read-write</access>
           </fields>
         </register>
         <register>
-          <name>Debug_Timer_CONTROL3_</name>
-          <description>TMRx.CFG2</description>
-          <addressOffset>0x40004F02</addressOffset>
+          <name>SIE_EP1_CNT0</name>
+          <description>SIE Endpoint 1 Count0 Register</description>
+          <addressOffset>0x4000600C</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
           <fields>
             <field>
-              <name>TMR_CFG</name>
-              <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
+              <name>DATA_COUNT_MSB</name>
+              <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
               <lsb>0</lsb>
-              <msb>1</msb>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Continuous</name>
-                  <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Pulsewidth</name>
-                  <description>Timer runs from positive to negative edge of TIMEREN.</description>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Period</name>
-                  <description>Timer runs from positive to positive edge of TIMEREN.</description>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Irq</name>
-                  <description>Timer runs until IRQ.</description>
-                  <value>3</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>COD</name>
-              <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
-              <lsb>2</lsb>
-              <msb>2</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>ROD</name>
-              <description>Reset On Disable (ROD). Resets internal state of output logic</description>
-              <lsb>3</lsb>
-              <msb>3</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>CMP_CFG</name>
-              <description>Comparator configurations</description>
-              <lsb>4</lsb>
-              <msb>6</msb>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Equal</name>
-                  <description>Compare Equal </description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Less_than</name>
-                  <description>Compare Less Than </description>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Less_than_or_equal</name>
-                  <description>Compare Less Than or Equal .</description>
-                  <value>2</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Greater</name>
-                  <description>Compare Greater Than .</description>
-                  <value>3</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Greater_than_or_equal</name>
-                  <description>Compare Greater Than or Equal </description>
-                  <value>4</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>HW_EN</name>
-              <description>When set Timer Enable controls counting.</description>
-              <lsb>7</lsb>
-              <msb>7</msb>
-              <access>read-write</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>Debug_Timer_PERIOD</name>
-          <description>TMRx.PER0 - Assigned Period</description>
-          <addressOffset>0x40004F04</addressOffset>
-          <size>16</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-        </register>
-        <register>
-          <name>Debug_Timer_COUNTER</name>
-          <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
-          <addressOffset>0x40004F06</addressOffset>
-          <size>16</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-        </register>
-      </registers>
-    </peripheral>
-    <peripheral>
-      <name>SCSI_Out_Ctl</name>
-      <description>No description available</description>
-      <baseAddress>0x0</baseAddress>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x0</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <registers>
-        <register>
-          <name>SCSI_Out_Ctl_CONTROL_REG</name>
-          <description>No description available</description>
-          <addressOffset>0x40006476</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-        </register>
-      </registers>
-    </peripheral>
-    <peripheral>
-      <name>SCSI_Out_Bits</name>
-      <description>No description available</description>
-      <baseAddress>0x0</baseAddress>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x0</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <registers>
-        <register>
-          <name>SCSI_Out_Bits_CONTROL_REG</name>
-          <description>No description available</description>
-          <addressOffset>0x4000647D</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-        </register>
-      </registers>
-    </peripheral>
-    <peripheral>
-      <name>USBFS</name>
-      <description>USBFS</description>
-      <baseAddress>0x0</baseAddress>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x0</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <registers>
-        <register>
-          <name>CR0</name>
-          <description>USB Control 0 Register</description>
-          <addressOffset>0x40006008</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-          <fields>
-            <field>
-              <name>DEVICE_ADDRESS</name>
-              <description>These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware.</description>
-              <lsb>0</lsb>
-              <msb>6</msb>
-              <access>read-only</access>
-            </field>
-            <field>
-              <name>USB_ENABLE</name>
-              <description>This bit enables the device to respond to USB traffic.</description>
-              <lsb>7</lsb>
-              <msb>7</msb>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Disabled</name>
-                  <description>Block responds to USB traffic.</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Enabled</name>
-                  <description>Block does not respond to USB traffic.</description>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>CR1</name>
-          <description>USB Control 1 Register</description>
-          <addressOffset>0x40006009</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-          <fields>
-            <field>
-              <name>REG_ENABLE</name>
-              <description>This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply.</description>
-              <lsb>0</lsb>
-              <msb>0</msb>
-              <access>read-only</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>Disabled</name>
-                  <description>Regulator for 5V is disabled.</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>Enabled</name>
-                  <description>Regulator for 5V is enabled.</description>
-                  <value>1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>ENABLE_LOCK</name>
-              <description>This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic.  Unless an external clock is being provided this bit should remain set for proper USB operation.</description>
-              <lsb>1</lsb>
-              <msb>1</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>BUS_ACTIVITY</name>
-              <description>The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it.</description>
-              <lsb>2</lsb>
-              <msb>2</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>TRIM_OFFSET_MSB</name>
-              <description>This bit enables trim bit[7].</description>
-              <lsb>3</lsb>
-              <msb>3</msb>
-              <access>read-write</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>SIE_EP_INT_EN</name>
-          <description>USB SIE Data Endpoints Interrupt Enable Register</description>
-          <addressOffset>0x4000600A</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-          <fields>
-            <field>
-              <name>EP1_INTR_EN</name>
-              <description>Enables interrupt for EP1.</description>
-              <lsb>0</lsb>
-              <msb>0</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP2_INTR_EN</name>
-              <description>Enables interrupt for EP2.</description>
-              <lsb>1</lsb>
-              <msb>1</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP3_INTR_EN</name>
-              <description>Enables interrupt for EP3.</description>
-              <lsb>2</lsb>
-              <msb>2</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP4_INTR_EN</name>
-              <description>Enables interrupt for EP4.</description>
-              <lsb>3</lsb>
-              <msb>3</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP5_INTR_EN</name>
-              <description>Enables interrupt for EP5.</description>
-              <lsb>4</lsb>
-              <msb>4</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP6_INTR_EN</name>
-              <description>Enables interrupt for EP6.</description>
-              <lsb>5</lsb>
-              <msb>5</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP7_INTR_EN</name>
-              <description>Enables interrupt for EP7.</description>
-              <lsb>6</lsb>
-              <msb>6</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP8_INTR_EN</name>
-              <description>Enables interrupt for EP8.</description>
-              <lsb>7</lsb>
-              <msb>7</msb>
-              <access>read-write</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>SIE_EP_INT_SR</name>
-          <description>SIE Data Endpoint Interrupt Status Register</description>
-          <addressOffset>0x4000600B</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-          <fields>
-            <field>
-              <name>EP1_INTR</name>
-              <description>Interrupt status for EP1.</description>
-              <lsb>0</lsb>
-              <msb>0</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP2_INTR</name>
-              <description>Interrupt status for EP2.</description>
-              <lsb>1</lsb>
-              <msb>1</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP3_INTR</name>
-              <description>Interrupt status for EP3.</description>
-              <lsb>2</lsb>
-              <msb>2</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP4_INTR</name>
-              <description>Interrupt status for EP4.</description>
-              <lsb>3</lsb>
-              <msb>3</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP5_INTR</name>
-              <description>Interrupt status for EP5.</description>
-              <lsb>4</lsb>
-              <msb>4</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP6_INTR</name>
-              <description>Interrupt status for EP6.</description>
-              <lsb>5</lsb>
-              <msb>5</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP7_INTR</name>
-              <description>Interrupt status for EP7.</description>
-              <lsb>6</lsb>
-              <msb>6</msb>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>EP8_INTR</name>
-              <description>Interrupt status for EP8.</description>
-              <lsb>7</lsb>
-              <msb>7</msb>
-              <access>read-write</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>SIE_EP1_CNT0</name>
-          <description>SIE Endpoint 1 Count0 Register</description>
-          <addressOffset>0x4000600C</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-          <fields>
-            <field>
-              <name>DATA_COUNT_MSB</name>
-              <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
-              <lsb>0</lsb>
-              <msb>2</msb>
+              <msb>2</msb>
               <access>read-write</access>
             </field>
             <field>
           </fields>
         </register>
         <register>
-          <name>ARB_EP4_INT_EN</name>
-          <description>Arbiter Endpoint 1 Interrupt Enable Register</description>
-          <addressOffset>0x400060B1</addressOffset>
+          <name>ARB_EP4_INT_EN</name>
+          <description>Arbiter Endpoint 1 Interrupt Enable Register</description>
+          <addressOffset>0x400060B1</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>IN_BUF_FULL_EN</name>
+              <description>IN Endpoint Local Buffer Full</description>
+              <lsb>0</lsb>
+              <msb>0</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_GNT_EN</name>
+              <description>Endpoint DMA Grant</description>
+              <lsb>1</lsb>
+              <msb>1</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUF_OVER_EN</name>
+              <description>Endpoint Buffer Overflow</description>
+              <lsb>2</lsb>
+              <msb>2</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUF_UNDER_EN</name>
+              <description>Endpoint Buffer Underflow</description>
+              <lsb>3</lsb>
+              <msb>3</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_INT_EN</name>
+              <description>Endpoint Error in Transaction Interrupt</description>
+              <lsb>4</lsb>
+              <msb>4</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TERMIN_EN</name>
+              <description>Endpoint DMA Terminated Enable</description>
+              <lsb>5</lsb>
+              <msb>5</msb>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_EP4_INT_SR</name>
+          <description>Arbiter Endpoint 1 Interrupt Status Register</description>
+          <addressOffset>0x400060B2</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>IN_BUF_FULL_EN</name>
+              <description>IN Endpoint Local Buffer Full</description>
+              <lsb>0</lsb>
+              <msb>0</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_GNT_EN</name>
+              <description>Endpoint DMA Grant</description>
+              <lsb>1</lsb>
+              <msb>1</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUF_OVER_EN</name>
+              <description>Endpoint Buffer Overflow</description>
+              <lsb>2</lsb>
+              <msb>2</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUF_UNDER_EN</name>
+              <description>Endpoint Buffer Underflow</description>
+              <lsb>3</lsb>
+              <msb>3</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_INT_EN</name>
+              <description>Endpoint Error in Transaction Interrupt</description>
+              <lsb>4</lsb>
+              <msb>4</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TERMIN_EN</name>
+              <description>Endpoint DMA Terminated Enable</description>
+              <lsb>5</lsb>
+              <msb>5</msb>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_RW4_WA</name>
+          <description>Arbiter Endpoint 1 Write Address LSB Register</description>
+          <addressOffset>0x400060B4</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>WA8</name>
+              <description>Write Address for EP.</description>
+              <lsb>0</lsb>
+              <msb>7</msb>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_RW4_WA_MSB</name>
+          <description>Arbiter Endpoint 1 Write Address MSB Register</description>
+          <addressOffset>0x400060B5</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>WA9</name>
+              <description>Write Address for EP MSB.</description>
+              <lsb>0</lsb>
+              <msb>0</msb>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_RW4_RA</name>
+          <description>Arbiter Endpoint 1 Read Address LSB Register</description>
+          <addressOffset>0x400060B6</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>RA8</name>
+              <description>Read Address for EP MSB.</description>
+              <lsb>0</lsb>
+              <msb>7</msb>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_RW4_RA_MSB</name>
+          <description>Arbiter Endpoint 1 Read Address MSB Register</description>
+          <addressOffset>0x400060B7</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>RA9</name>
+              <description>Read Address for EP MSB.</description>
+              <lsb>0</lsb>
+              <msb>0</msb>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SCSI_Out_Ctl</name>
+      <description>No description available</description>
+      <baseAddress>0x0</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SCSI_Out_Ctl_CONTROL_REG</name>
+          <description>No description available</description>
+          <addressOffset>0x40006473</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>Debug_Timer</name>
+      <description>No description available</description>
+      <baseAddress>0x0</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>Debug_Timer_GLOBAL_ENABLE</name>
+          <description>PM.ACT.CFG</description>
+          <addressOffset>0x400043A3</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>en_timer</name>
+              <description>Enable timer/counters.</description>
+              <lsb>0</lsb>
+              <msb>3</msb>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Debug_Timer_CONTROL</name>
+          <description>TMRx.CFG0</description>
+          <addressOffset>0x40004F00</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
           <fields>
             <field>
-              <name>IN_BUF_FULL_EN</name>
-              <description>IN Endpoint Local Buffer Full</description>
+              <name>EN</name>
+              <description>Enables timer/comparator.</description>
               <lsb>0</lsb>
               <msb>0</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>DMA_GNT_EN</name>
-              <description>Endpoint DMA Grant</description>
+              <name>MODE</name>
+              <description>Mode. (0 = Timer; 1 = Comparator)</description>
               <lsb>1</lsb>
               <msb>1</msb>
               <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Timer</name>
+                  <description>Timer mode. CNT/CMP register holds timer count value.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Comparator</name>
+                  <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
             </field>
             <field>
-              <name>BUF_OVER_EN</name>
-              <description>Endpoint Buffer Overflow</description>
+              <name>ONESHOT</name>
+              <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
               <lsb>2</lsb>
               <msb>2</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>BUF_UNDER_EN</name>
-              <description>Endpoint Buffer Underflow</description>
+              <name>CMP_BUFF</name>
+              <description>Buffer compare register. Compare register updates only on timer terminal count.</description>
               <lsb>3</lsb>
               <msb>3</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>ERR_INT_EN</name>
-              <description>Endpoint Error in Transaction Interrupt</description>
+              <name>INV</name>
+              <description>Invert sense of TIMEREN signal</description>
               <lsb>4</lsb>
               <msb>4</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>DMA_TERMIN_EN</name>
-              <description>Endpoint DMA Terminated Enable</description>
+              <name>DB</name>
+              <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
               <lsb>5</lsb>
               <msb>5</msb>
               <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Timer</name>
+                  <description>CMP and TC are output.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Deadband</name>
+                  <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DEADBAND_PERIOD</name>
+              <description>Deadband Period</description>
+              <lsb>6</lsb>
+              <msb>7</msb>
+              <access>read-write</access>
             </field>
           </fields>
         </register>
         <register>
-          <name>ARB_EP4_INT_SR</name>
-          <description>Arbiter Endpoint 1 Interrupt Status Register</description>
-          <addressOffset>0x400060B2</addressOffset>
+          <name>Debug_Timer_CONTROL2</name>
+          <description>TMRx.CFG1</description>
+          <addressOffset>0x40004F01</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
           <fields>
             <field>
-              <name>IN_BUF_FULL_EN</name>
-              <description>IN Endpoint Local Buffer Full</description>
+              <name>IRQ_SEL</name>
+              <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
               <lsb>0</lsb>
               <msb>0</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>DMA_GNT_EN</name>
-              <description>Endpoint DMA Grant</description>
+              <name>FTC</name>
+              <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
               <lsb>1</lsb>
               <msb>1</msb>
               <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable_FTC</name>
+                  <description>Disable the single cycle pulse, which signifies the timer is starting.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable_FTC</name>
+                  <description>Enable the single cycle pulse, which signifies the timer is starting.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
             </field>
             <field>
-              <name>BUF_OVER_EN</name>
-              <description>Endpoint Buffer Overflow</description>
+              <name>DCOR</name>
+              <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
               <lsb>2</lsb>
               <msb>2</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>BUF_UNDER_EN</name>
-              <description>Endpoint Buffer Underflow</description>
+              <name>DBMODE</name>
+              <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
               <lsb>3</lsb>
               <msb>3</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>ERR_INT_EN</name>
-              <description>Endpoint Error in Transaction Interrupt</description>
+              <name>CLK_BUS_EN_SEL</name>
+              <description>Digital Global Clock selection.</description>
               <lsb>4</lsb>
-              <msb>4</msb>
+              <msb>6</msb>
               <access>read-write</access>
             </field>
             <field>
-              <name>DMA_TERMIN_EN</name>
-              <description>Endpoint DMA Terminated Enable</description>
-              <lsb>5</lsb>
-              <msb>5</msb>
+              <name>BUS_CLK_SEL</name>
+              <description>Bus Clock selection.</description>
+              <lsb>7</lsb>
+              <msb>7</msb>
               <access>read-write</access>
             </field>
           </fields>
         </register>
         <register>
-          <name>ARB_RW4_WA</name>
-          <description>Arbiter Endpoint 1 Write Address LSB Register</description>
-          <addressOffset>0x400060B4</addressOffset>
+          <name>Debug_Timer_CONTROL3_</name>
+          <description>TMRx.CFG2</description>
+          <addressOffset>0x40004F02</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
           <fields>
             <field>
-              <name>WA8</name>
-              <description>Write Address for EP.</description>
+              <name>TMR_CFG</name>
+              <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
               <lsb>0</lsb>
+              <msb>1</msb>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Continuous</name>
+                  <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Pulsewidth</name>
+                  <description>Timer runs from positive to negative edge of TIMEREN.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Period</name>
+                  <description>Timer runs from positive to positive edge of TIMEREN.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Irq</name>
+                  <description>Timer runs until IRQ.</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>COD</name>
+              <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
+              <lsb>2</lsb>
+              <msb>2</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROD</name>
+              <description>Reset On Disable (ROD). Resets internal state of output logic</description>
+              <lsb>3</lsb>
+              <msb>3</msb>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMP_CFG</name>
+              <description>Comparator configurations</description>
+              <lsb>4</lsb>
+              <msb>6</msb>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Equal</name>
+                  <description>Compare Equal </description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Less_than</name>
+                  <description>Compare Less Than </description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Less_than_or_equal</name>
+                  <description>Compare Less Than or Equal .</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Greater</name>
+                  <description>Compare Greater Than .</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Greater_than_or_equal</name>
+                  <description>Compare Greater Than or Equal </description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HW_EN</name>
+              <description>When set Timer Enable controls counting.</description>
+              <lsb>7</lsb>
               <msb>7</msb>
               <access>read-write</access>
             </field>
           </fields>
         </register>
         <register>
-          <name>ARB_RW4_WA_MSB</name>
-          <description>Arbiter Endpoint 1 Write Address MSB Register</description>
-          <addressOffset>0x400060B5</addressOffset>
-          <size>8</size>
+          <name>Debug_Timer_PERIOD</name>
+          <description>TMRx.PER0 - Assigned Period</description>
+          <addressOffset>0x40004F04</addressOffset>
+          <size>16</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
-          <fields>
-            <field>
-              <name>WA9</name>
-              <description>Write Address for EP MSB.</description>
-              <lsb>0</lsb>
-              <msb>0</msb>
-              <access>read-write</access>
-            </field>
-          </fields>
         </register>
         <register>
-          <name>ARB_RW4_RA</name>
-          <description>Arbiter Endpoint 1 Read Address LSB Register</description>
-          <addressOffset>0x400060B6</addressOffset>
-          <size>8</size>
+          <name>Debug_Timer_COUNTER</name>
+          <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
+          <addressOffset>0x40004F06</addressOffset>
+          <size>16</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
-          <fields>
-            <field>
-              <name>RA8</name>
-              <description>Read Address for EP MSB.</description>
-              <lsb>0</lsb>
-              <msb>7</msb>
-              <access>read-write</access>
-            </field>
-          </fields>
         </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SCSI_Out_Bits</name>
+      <description>No description available</description>
+      <baseAddress>0x0</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
         <register>
-          <name>ARB_RW4_RA_MSB</name>
-          <description>Arbiter Endpoint 1 Read Address MSB Register</description>
-          <addressOffset>0x400060B7</addressOffset>
+          <name>SCSI_Out_Bits_CONTROL_REG</name>
+          <description>No description available</description>
+          <addressOffset>0x40006479</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
           <resetMask>0</resetMask>
-          <fields>
-            <field>
-              <name>RA9</name>
-              <description>Read Address for EP MSB.</description>
-              <lsb>0</lsb>
-              <msb>0</msb>
-              <access>read-write</access>
-            </field>
-          </fields>
         </register>
       </registers>
     </peripheral>