+2018XXXX 4.8
+ - Fix Unit Serial Number inquiry page to use return configured serial number
+ - Apple mode pages now only sent when in Apple mode.
+ - Added quirks selection to scsi2sd-util. Apple users should manually fix
+ their settings to use the Apple mode.
+ - Added specific support for XEBEC controllers.
+ - Added a speed selection to scsi2sd-util. Users with older SASI or SCSI1
+ controllers should select the lower speed for stability.
+ - Support for v5.1 hardware boards.
+
20170501 4.7.1
- Fix scsi2sd-util size and sector-size inputs
- Fix crash when configured scsi disk starting sector is less than
//\r
// You should have received a copy of the GNU General Public License\r
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
-#pragma GCC push_options\r
-#pragma GCC optimize("-flto")\r
\r
#include "bits.h"\r
\r
return i;\r
}\r
\r
-#pragma GCC pop_options\r
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
-#pragma GCC push_options
-#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
return commandHandled;
}
-#pragma GCC pop_options
//\r
// You should have received a copy of the GNU General Public License\r
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
-#pragma GCC push_options\r
-#pragma GCC optimize("-flto")\r
\r
#include "device.h"\r
#include "config.h"\r
\r
#include <string.h>\r
\r
-static const uint16_t FIRMWARE_VERSION = 0x0471;\r
+static const uint16_t FIRMWARE_VERSION = 0x0480;\r
\r
// 1 flash row\r
static const uint8_t DEFAULT_CONFIG[256] =\r
uint8_t flashArray = cmd[257];\r
uint8_t flashRow = cmd[258];\r
\r
+ // Be very careful not to overwrite the bootloader or other\r\r
+ // code. Bootloader updates no longer supported. Use v5.1 board\r
+ // instead.\r
+ if ((flashArray != SCSI_CONFIG_ARRAY) ||\r
+ (flashRow < SCSI_CONFIG_4_ROW) ||\r
+ (flashRow >= SCSI_CONFIG_3_ROW + SCSI_CONFIG_ROWS))\r
+ {\r
+ uint8_t response[] = { CONFIG_STATUS_ERR };\r
+ hidPacket_send(response, sizeof(response));\r
+ }\r
+\r
CySetTemp();\r
int status = CyWriteRowData(flashArray, flashRow, cmd + 1);\r
\r
return NULL;\r
\r
}\r
-\r
-#pragma GCC pop_options\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
-#pragma GCC push_options\r
-#pragma GCC optimize("-flto")\r
-\r
#include "device.h"\r
#include "scsi.h"\r
#include "diagnostic.h"\r
}\r
\r
\r
-#pragma GCC pop_options\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
-#pragma GCC push_options\r
-#pragma GCC optimize("-flto")\r
-\r
#include "device.h"\r
#include "scsi.h"\r
#include "scsiPhy.h"\r
#endif\r
}\r
\r
-#pragma GCC pop_options\r
+\r
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
-#pragma GCC push_options
-#pragma GCC optimize("-flto")
-
#include "device.h"
#include "scsi.h"
#include "config.h"
{
memcpy(scsiDev.data, UnitSerialNumber, sizeof(UnitSerialNumber));
scsiDev.dataLen = sizeof(UnitSerialNumber);
+ const TargetConfig* config = scsiDev.target->cfg;
memcpy(&scsiDev.data[4], config->serial, sizeof(config->serial));
scsiDev.phase = DATA_IN;
}
}
}
-#pragma GCC pop_options
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
-#pragma GCC push_options
-#pragma GCC optimize("-flto")
#include "led.h"
void ledOff()
{
- LED1_Write(1);
+ LED1_Write(0xff);
#ifdef HAVE_EXTLED
EXTLED_Write(0);
#endif
}
-#pragma GCC pop_options
//\r
// You should have received a copy of the GNU General Public License\r
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
-#pragma GCC push_options\r
-#pragma GCC optimize("-flto")\r
-\r
#include "device.h"\r
#include "scsi.h"\r
#include "scsiPhy.h"\r
#include "time.h"\r
#include "trace.h"\r
\r
-const char* Notice = "Copyright (C) 2015 Michael McMaster <michael@codesrc.com>";\r
+const char* Notice = "Copyright (C) 2015-2018 Michael McMaster <michael@codesrc.com>";\r
\r
int main()\r
{\r
return 0;\r
}\r
\r
-#pragma GCC pop_options\r
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
-#pragma GCC push_options
-#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
return commandHandled;
}
-#pragma GCC pop_options
//\r
// You should have received a copy of the GNU General Public License\r
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
-#pragma GCC push_options\r
-#pragma GCC optimize("-flto")\r
-\r
#include "device.h"\r
#include "scsi.h"\r
#include "mode.h"\r
}\r
\r
if ((\r
- (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_APPLE) ||\r
- (idx + sizeof(AppleVendorPage) <= allocLength)\r
+ (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_APPLE)\r
) &&\r
(pageCode == 0x30 || pageCode == 0x3F))\r
{\r
\r
return commandHandled;\r
}\r
-\r
-#pragma GCC pop_options\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
-#pragma GCC push_options\r
-#pragma GCC optimize("-flto")\r
\r
#include "device.h"\r
#include "scsi.h"\r
// OMTI non-standard LINK control\r
if (control & 0x01)\r
{\r
- scsiDev.phase = COMMAND; return;\r
+ scsiDev.phase = COMMAND;\r
+ return;\r
}\r
}\r
\r
- if ((scsiDev.status == GOOD) && (control & 0x01))\r
+ if ((scsiDev.status == GOOD) && (control & 0x01) &&\r
+ scsiDev.target->cfg->quirks != CONFIG_QUIRKS_XEBEC)\r
{\r
// Linked command.\r
scsiDev.status = INTERMEDIATE;\r
}\r
\r
\r
- if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_OMTI)\r
+ if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_XEBEC)\r
+ {\r
+ // More non-standardness. Expects 2 status bytes (really status + msg)\r
+ // 00 d 000 err 0\r
+ // d == disk number\r
+ // ERR = 1 if error.\r
+ if (scsiDev.status == GOOD)\r
+ {\r
+ scsiWriteByte(scsiDev.cdb[1] & 0x20);\r
+ }\r
+ else\r
+ {\r
+ scsiWriteByte((scsiDev.cdb[1] & 0x20) | 0x2);\r
+ }\r
+ CyDelayUs(10); // Seems to need a delay before changing phase bits.\r
+ }\r
+ else if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_OMTI)\r
{\r
scsiDev.status |= (scsiDev.target->targetId & 0x03) << 5;\r
+ scsiWriteByte(scsiDev.status);\r
+ }\r
+ else\r
+ {\r
+ scsiWriteByte(scsiDev.status);\r
}\r
-\r
- scsiWriteByte(scsiDev.status);\r
\r
scsiDev.lastStatus = scsiDev.status;\r
scsiDev.lastSense = scsiDev.target->sense.code;\r
// Prefer LUN's set by IDENTIFY messages for newer hosts.\r
if (scsiDev.lun < 0)\r
{\r
- scsiDev.lun = scsiDev.cdb[1] >> 5;\r
+ if (command == 0xE0 || command == 0xE4) // XEBEC s1410\r
+ {\r
+ scsiDev.lun = 0;\r
+ }\r
+ else\r
+ {\r
+ scsiDev.lun = scsiDev.cdb[1] >> 5;\r
+ }\r
}\r
\r
// For Philips P2000C with Xebec S1410 SASI/MFM adapter\r
scsiDev.target->sense.asc = SCSI_PARITY_ERROR;\r
enter_Status(CHECK_CONDITION);\r
}\r
- else if ((control & 0x02) && ((control & 0x01) == 0))\r
+ else if ((control & 0x02) && ((control & 0x01) == 0) &&\r
+ // used for head step options on xebec.\r
+ likely(scsiDev.target->cfg->quirks != CONFIG_QUIRKS_XEBEC))\r
{\r
// FLAG set without LINK flag.\r
scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
// REQUEST SENSE\r
uint32 allocLength = scsiDev.cdb[4];\r
\r
+ if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_XEBEC)\r
+ {\r
+ // Completely non-standard\r
+ allocLength = 4;\r
+ if (scsiDev.target->sense.code == NO_SENSE)\r
+ scsiDev.data[0] = 0;\r
+ else if (scsiDev.target->sense.code == ILLEGAL_REQUEST)\r
+ scsiDev.data[0] = 0x20; // Illegal command\r
+ else if (scsiDev.target->sense.code == NOT_READY)\r
+ scsiDev.data[0] = 0x04; // Drive not ready\r
+ else\r
+ scsiDev.data[0] = 0x11; // Uncorrectable data error\r
+\r
+ scsiDev.data[1] = (scsiDev.cdb[1] & 0x20) | ((transfer.lba >> 16) & 0x1F);\r
+ scsiDev.data[2] = transfer.lba >> 8;\r
+ scsiDev.data[3] = transfer.lba;\r
+\r
+ }\r
+ else\r
+ {\r
// As specified by the SASI and SCSI1 standard.\r
// Newer initiators won't be specifying 0 anyway.\r
if (allocLength == 0) allocLength = 4;\r
scsiDev.data[7] = 10; // additional length\r
scsiDev.data[12] = scsiDev.target->sense.asc >> 8;\r
scsiDev.data[13] = scsiDev.target->sense.asc;\r
+ }\r
\r
// Silently truncate results. SCSI-2 spec 8.2.14.\r
enter_DataIn(allocLength);\r
// The Mac Plus boot-time (ie. rom code) selection abort time\r
// is < 1ms and must have no delay (standard suggests 250ms abort time)\r
// Most newer SCSI2 hosts don't care either way.\r
- if (scsiDev.boardCfg.selectionDelay == 255) // auto\r
+ if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_XEBEC)\r
+ {\r
+ CyDelay(1); // Simply won't work if set to 0.\r
+ }\r
+ else if (scsiDev.boardCfg.selectionDelay == 255) // auto\r
{\r
if (scsiDev.compatMode < COMPAT_SCSI2)\r
{\r
int sel = (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL);\r
\r
int bsy = SCSI_ReadFilt(SCSI_Filt_BSY);\r
+#ifdef SCSI_In_IO\r
int io = SCSI_ReadPin(SCSI_In_IO);\r
+#else\r
+ int io = 0;\r
+#endif\r
\r
// Only read these pins AFTER SEL and BSY - we don't want to catch them\r
// during a transition period.\r
}\r
sel &= (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL);\r
bsy |= SCSI_ReadFilt(SCSI_Filt_BSY);\r
+#ifdef SCSI_In_IO\r
io |= SCSI_ReadPin(SCSI_In_IO);\r
+#endif\r
if (!bsy && !io && sel &&\r
target &&\r
(goodParity || !(scsiDev.boardCfg.flags & CONFIG_ENABLE_PARITY) || !atnFlag) &&\r
}\r
\r
// Wait until the end of the selection phase.\r
+ uint32_t selTimerBegin = getTime_ms();\r
while (likely(!scsiDev.resetFlag))\r
{\r
if (!SCSI_ReadFilt(SCSI_Filt_SEL))\r
{\r
break;\r
}\r
+ else if (elapsedTime_ms(selTimerBegin) >= 250)\r
+ {\r
+ SCSI_ClearPin(SCSI_Out_BSY);\r
+ scsiDev.resetFlag = 1;\r
+ break;\r
+ }\r
}\r
\r
scsiDev.phase = COMMAND;\r
{\r
scsiDev.phase = BUS_BUSY;\r
}\r
- \r
+\r
scsiDev.selFlag = 0;\r
}\r
\r
return reconnected;\r
}\r
\r
-#pragma GCC pop_options\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
-#pragma GCC push_options\r
-#pragma GCC optimize("-flto")\r
-\r
#include "device.h"\r
#include "scsi.h"\r
#include "scsiPhy.h"\r
{\r
// ANSI INCITS 362-2002 SPI-3 10.7.1:\r
// Phase changes are not allowed while REQ or ACK is asserted.\r
- while (likely(!scsiDev.resetFlag) &&\r
- (SCSI_ReadPin(SCSI_In_REQ) || SCSI_ReadFilt(SCSI_Filt_ACK))\r
- ) {}\r
+ while (likely(!scsiDev.resetFlag) && SCSI_ReadFilt(SCSI_Filt_ACK))\r
+ {}\r
\r
int newPhase = phase > 0 ? phase : 0;\r
if (newPhase != SCSI_CTL_PHASE_Read())\r
\r
if (scsiDev.compatMode < COMPAT_SCSI2)\r
{\r
- CyDelayUs(100);\r
+ // XEBEC S1410 manual (old SASI controller) gives 10uSec delay\r
+ // between phase bits and REQ.\r
+ CyDelayUs(10);\r
}\r
}\r
}\r
SCSI_SetPin(SCSI_Out_RST);\r
\r
SCSI_CTL_PHASE_Write(0);\r
+ #ifdef SCSI_Out_ATN\r
SCSI_ClearPin(SCSI_Out_ATN);\r
+ #endif\r
SCSI_ClearPin(SCSI_Out_BSY);\r
+ #ifdef SCSI_Out_ACK\r
SCSI_ClearPin(SCSI_Out_ACK);\r
+ #endif\r
SCSI_ClearPin(SCSI_Out_RST);\r
SCSI_ClearPin(SCSI_Out_SEL);\r
SCSI_ClearPin(SCSI_Out_REQ);\r
if (scsiDev.boardCfg.flags & CONFIG_DISABLE_GLITCH)\r
{\r
SCSI_Glitch_Ctl_Write(1);\r
+\r
+ // Reduce deskew time to 1. (deskew init + 0)\r
CY_SET_REG8(scsiTarget_datapath__D0_REG, 0);\r
}\r
+ if ((scsiDev.target->cfg->quirks == CONFIG_QUIRKS_XEBEC) ||\r
+ (scsiDev.boardCfg.scsiSpeed == CONFIG_SPEED_ASYNC_15))\r
+ {\r
+ // 125ns to 250ns deskew time = 3.125 clocks\r
+ // - 1 (valid during DESKEW INIT)\r
+ // = 2.125. Default is 1.\r
+ // Round down because it's going to be doubled anyway due to clock\r
+ // divider change below.\r
+ CY_SET_REG8(scsiTarget_datapath__D0_REG, 2);\r
+\r
+ // Half the SCSI clock as a way to extend the glitch filter.\r
+ // This also helps meet the 250ns delays between ACK and reading\r
+ // data, or release ack and reassert req.\r
+\r
+ // The register contains (divider - 1)\r
+ uint16_t clkDiv25MHz = SCSI_CLK_GetDividerRegister();\r
+ SCSI_CLK_SetDivider(((clkDiv25MHz + 1) * 2) - 1);\r
+ // Wait for the clock to settle.\r
+ CyDelayUs(1);\r
+ }\r
+\r
+ #ifdef TERM_EN_0\r
+ TERM_EN_Write((scsiDev.boardCfg.flags6 & S2S_CFG_ENABLE_TERMINATOR) ? 0 : 1);\r
+ #endif\r
}\r
\r
// 1 = DBx error\r
SCSI_Out_Ctl_Write(0); // Write bits normally.\r
\r
// TEST MSG, CD, IO\r
+ #ifdef SCSI_In_MSG\r
for (i = 0; i < 8; ++i)\r
{\r
SCSI_CTL_PHASE_Write(i);\r
result |= 16;\r
}\r
}\r
+ #endif\r
SCSI_CTL_PHASE_Write(0);\r
\r
- uint32_t signalsOut[] = { SCSI_Out_ATN, SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL };\r
- uint32_t signalsIn[] = { SCSI_Filt_ATN, SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL };\r
+ uint32_t signalsOut[] = { SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL };\r
+ uint32_t signalsIn[] = { SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL };\r
\r
- for (i = 0; i < 4; ++i)\r
+ for (i = 0; i < 3; ++i)\r
{\r
SCSI_SetPin(signalsOut[i]);\r
scsiDeskewDelay();\r
\r
int j;\r
- for (j = 0; j < 4; ++j)\r
+ for (j = 0; j < 3; ++j)\r
{\r
if (i == j)\r
{\r
}\r
\r
\r
-#pragma GCC pop_options\r
#define scsiPhyTx(val) CY_SET_REG8(scsiTarget_datapath__F0_REG, (val))
#define scsiPhyRx() CY_GET_REG8(scsiTarget_datapath__F1_REG)
+#ifdef TERM_EN_0
+ // V5.1 is active-low
+#define SCSI_SetPin(pin) \
+ CyPins_ClearPin((pin));
+
+#define SCSI_ClearPin(pin) \
+ CyPins_SetPin((pin));
+#else
+ // <= V5.0 is active-high
#define SCSI_SetPin(pin) \
CyPins_SetPin((pin));
#define SCSI_ClearPin(pin) \
- CyPins_ClearPin((pin));
+ CyPins_ClearPin((pin));
+#endif
// Active low: we interpret a 0 as "true", and non-zero as "false"
#define SCSI_ReadPin(pin) \
//\r
// You should have received a copy of the GNU General Public License\r
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
-#pragma GCC push_options\r
-#pragma GCC optimize("-flto")\r
\r
#include "device.h"\r
#include "scsi.h"\r
firstCheck = 0;\r
}\r
\r
-#pragma GCC pop_options\r
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
-#pragma GCC push_options
-#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
return 0;
}
-
-#pragma GCC pop_options
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
-#pragma GCC push_options
-#pragma GCC optimize("-flto")
#include "time.h"
#include "limits.h"
}
}
-#pragma GCC pop_options
scsiDev.phase = DATA_OUT;
scsiDev.postDataOutHook = doAssignDiskParameters;
}
+ else if (command == 0x0C)
+ {
+ // Initialize Drive Characteristics
+ // XEBEC S1410 controller
+ // http://bitsavers.informatik.uni-stuttgart.de/pdf/xebec/104524C_S1410Man_Aug83.pdf
+ scsiDev.dataLen = 8;
+ scsiDev.phase = DATA_OUT;
+ }
+ else if (command == 0xE0)
+ {
+ // RAM Diagnostic
+ // XEBEC S1410 controller
+ // http://bitsavers.informatik.uni-stuttgart.de/pdf/xebec/104524C_S1410Man_Aug83.pdf
+ // Stub, return success
+ }
+ else if (command == 0xE4)
+ {
+ // Drive Diagnostic
+ // XEBEC S1410 controller
+ // Stub, return success
+ }
else
{
commandHandled = 0;
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK\r
+#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__2__POS 2\r
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
\r
/* SD_SCK */\r
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB08_09_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB08_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB08_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB08_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB08_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB08_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB08_MSK\r
\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
#define scsiTarget_StatusReg__0__POS 0\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST\r
\r
/* Debug_Timer_Interrupt */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
/* SCSI_Glitch_Ctl */\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK\r
\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 41u\r
+#define CY_CFG_BASE_ADDR_COUNT 40u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
static const uint32 CYCODE cy_cfg_addr_table[] = {\r
0x40004501u, /* Base address: 0x40004500 Count: 1 */\r
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
- 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */\r
+ 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x40010040u, /* Base address: 0x40010000 Count: 64 */\r
- 0x4001013Bu, /* Base address: 0x40010100 Count: 59 */\r
- 0x4001024Au, /* Base address: 0x40010200 Count: 74 */\r
- 0x40010354u, /* Base address: 0x40010300 Count: 84 */\r
- 0x40010441u, /* Base address: 0x40010400 Count: 65 */\r
- 0x4001054Cu, /* Base address: 0x40010500 Count: 76 */\r
- 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */\r
- 0x40010753u, /* Base address: 0x40010700 Count: 83 */\r
- 0x4001091Du, /* Base address: 0x40010900 Count: 29 */\r
- 0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */\r
- 0x40010B54u, /* Base address: 0x40010B00 Count: 84 */\r
- 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */\r
- 0x40010D4Bu, /* Base address: 0x40010D00 Count: 75 */\r
- 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */\r
- 0x40010F38u, /* Base address: 0x40010F00 Count: 56 */\r
- 0x4001145Eu, /* Base address: 0x40011400 Count: 94 */\r
- 0x40011555u, /* Base address: 0x40011500 Count: 85 */\r
- 0x40011658u, /* Base address: 0x40011600 Count: 88 */\r
- 0x4001174Bu, /* Base address: 0x40011700 Count: 75 */\r
- 0x40011850u, /* Base address: 0x40011800 Count: 80 */\r
- 0x40011948u, /* Base address: 0x40011900 Count: 72 */\r
- 0x40011B0Au, /* Base address: 0x40011B00 Count: 10 */\r
- 0x4001401Au, /* Base address: 0x40014000 Count: 26 */\r
- 0x4001411Fu, /* Base address: 0x40014100 Count: 31 */\r
- 0x40014217u, /* Base address: 0x40014200 Count: 23 */\r
- 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */\r
- 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */\r
+ 0x4001004Au, /* Base address: 0x40010000 Count: 74 */\r
+ 0x40010142u, /* Base address: 0x40010100 Count: 66 */\r
+ 0x40010248u, /* Base address: 0x40010200 Count: 72 */\r
+ 0x40010355u, /* Base address: 0x40010300 Count: 85 */\r
+ 0x4001045Du, /* Base address: 0x40010400 Count: 93 */\r
+ 0x4001055Au, /* Base address: 0x40010500 Count: 90 */\r
+ 0x40010657u, /* Base address: 0x40010600 Count: 87 */\r
+ 0x4001075Au, /* Base address: 0x40010700 Count: 90 */\r
+ 0x40010851u, /* Base address: 0x40010800 Count: 81 */\r
+ 0x40010953u, /* Base address: 0x40010900 Count: 83 */\r
+ 0x40010A4Au, /* Base address: 0x40010A00 Count: 74 */\r
+ 0x40010B45u, /* Base address: 0x40010B00 Count: 69 */\r
+ 0x40010D13u, /* Base address: 0x40010D00 Count: 19 */\r
+ 0x40010F06u, /* Base address: 0x40010F00 Count: 6 */\r
+ 0x4001141Au, /* Base address: 0x40011400 Count: 26 */\r
+ 0x40011550u, /* Base address: 0x40011500 Count: 80 */\r
+ 0x4001164Fu, /* Base address: 0x40011600 Count: 79 */\r
+ 0x40011758u, /* Base address: 0x40011700 Count: 88 */\r
+ 0x40011849u, /* Base address: 0x40011800 Count: 73 */\r
+ 0x40011955u, /* Base address: 0x40011900 Count: 85 */\r
+ 0x40011B09u, /* Base address: 0x40011B00 Count: 9 */\r
+ 0x4001401Cu, /* Base address: 0x40014000 Count: 28 */\r
+ 0x4001411Du, /* Base address: 0x40014100 Count: 29 */\r
+ 0x40014214u, /* Base address: 0x40014200 Count: 20 */\r
+ 0x40014309u, /* Base address: 0x40014300 Count: 9 */\r
+ 0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
0x40014515u, /* Base address: 0x40014500 Count: 21 */\r
- 0x40014610u, /* Base address: 0x40014600 Count: 16 */\r
- 0x40014716u, /* Base address: 0x40014700 Count: 22 */\r
- 0x4001480Bu, /* Base address: 0x40014800 Count: 11 */\r
- 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
- 0x40014C08u, /* Base address: 0x40014C00 Count: 8 */\r
- 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */\r
- 0x40015005u, /* Base address: 0x40015000 Count: 5 */\r
+ 0x40014613u, /* Base address: 0x40014600 Count: 19 */\r
+ 0x40014711u, /* Base address: 0x40014700 Count: 17 */\r
+ 0x40014808u, /* Base address: 0x40014800 Count: 8 */\r
+ 0x4001490Au, /* Base address: 0x40014900 Count: 10 */\r
+ 0x40014C06u, /* Base address: 0x40014C00 Count: 6 */\r
+ 0x40014D06u, /* Base address: 0x40014D00 Count: 6 */\r
+ 0x40015006u, /* Base address: 0x40015000 Count: 6 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
{0x0Au, 0x4Bu},\r
- {0x00u, 0x12u},\r
+ {0x00u, 0x11u},\r
{0x01u, 0x03u},\r
- {0x18u, 0x04u},\r
+ {0x18u, 0x08u},\r
+ {0x19u, 0x04u},\r
{0x1Cu, 0x71u},\r
- {0x20u, 0xC0u},\r
- {0x21u, 0x58u},\r
+ {0x20u, 0xA0u},\r
+ {0x21u, 0x98u},\r
{0x2Cu, 0x0Eu},\r
- {0x30u, 0x09u},\r
- {0x31u, 0x0Au},\r
+ {0x30u, 0x05u},\r
+ {0x31u, 0x09u},\r
{0x34u, 0x80u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x01u},\r
- {0x86u, 0x0Fu},\r
- {0x01u, 0x33u},\r
- {0x03u, 0xCCu},\r
- {0x04u, 0x3Fu},\r
- {0x08u, 0x04u},\r
- {0x0Au, 0x08u},\r
- {0x0Bu, 0xFFu},\r
- {0x0Eu, 0x3Fu},\r
+ {0x84u, 0x0Fu},\r
+ {0x01u, 0x69u},\r
+ {0x02u, 0x03u},\r
+ {0x03u, 0x96u},\r
+ {0x05u, 0xFFu},\r
+ {0x06u, 0x18u},\r
+ {0x09u, 0x55u},\r
+ {0x0Au, 0x24u},\r
+ {0x0Bu, 0xAAu},\r
{0x0Fu, 0xFFu},\r
- {0x10u, 0x10u},\r
- {0x12u, 0x20u},\r
- {0x14u, 0x01u},\r
- {0x15u, 0xFFu},\r
- {0x16u, 0x02u},\r
- {0x18u, 0x3Fu},\r
+ {0x10u, 0x24u},\r
+ {0x11u, 0x0Fu},\r
+ {0x12u, 0x09u},\r
+ {0x13u, 0xF0u},\r
+ {0x17u, 0xFFu},\r
+ {0x18u, 0x24u},\r
{0x19u, 0xFFu},\r
- {0x1Cu, 0x01u},\r
- {0x1Du, 0x0Fu},\r
- {0x1Eu, 0x02u},\r
- {0x1Fu, 0xF0u},\r
- {0x20u, 0x10u},\r
- {0x21u, 0x69u},\r
+ {0x1Au, 0x12u},\r
{0x22u, 0x20u},\r
- {0x23u, 0x96u},\r
- {0x24u, 0x04u},\r
- {0x25u, 0x55u},\r
- {0x26u, 0x08u},\r
- {0x27u, 0xAAu},\r
- {0x2Au, 0x3Fu},\r
- {0x2Eu, 0x3Fu},\r
- {0x2Fu, 0xFFu},\r
- {0x30u, 0x30u},\r
- {0x32u, 0x03u},\r
- {0x34u, 0x0Cu},\r
- {0x37u, 0xFFu},\r
- {0x3Au, 0x2Au},\r
- {0x3Bu, 0x80u},\r
- {0x40u, 0x52u},\r
+ {0x25u, 0x33u},\r
+ {0x26u, 0x04u},\r
+ {0x27u, 0xCCu},\r
+ {0x2Bu, 0xFFu},\r
+ {0x30u, 0x07u},\r
+ {0x33u, 0xFFu},\r
+ {0x34u, 0x38u},\r
+ {0x39u, 0x80u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Fu, 0x40u},\r
+ {0x40u, 0x32u},\r
{0x41u, 0x06u},\r
- {0x42u, 0x30u},\r
- {0x45u, 0xDCu},\r
- {0x46u, 0xE2u},\r
- {0x47u, 0x0Fu},\r
- {0x48u, 0x1Fu},\r
+ {0x42u, 0x10u},\r
+ {0x45u, 0x0Du},\r
+ {0x46u, 0x2Eu},\r
+ {0x47u, 0xCFu},\r
+ {0x48u, 0x3Du},\r
{0x49u, 0xFFu},\r
{0x4Au, 0xFFu},\r
{0x4Bu, 0xFFu},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0xD6u, 0x08u},\r
+ {0x81u, 0x33u},\r
+ {0x83u, 0xCCu},\r
+ {0x85u, 0xFFu},\r
+ {0x8Bu, 0xFFu},\r
+ {0x8Du, 0x0Fu},\r
+ {0x8Fu, 0xF0u},\r
+ {0x91u, 0x55u},\r
+ {0x93u, 0xAAu},\r
+ {0x97u, 0xFFu},\r
+ {0x99u, 0xFFu},\r
+ {0xABu, 0xFFu},\r
+ {0xADu, 0x96u},\r
+ {0xAFu, 0x69u},\r
+ {0xB7u, 0xFFu},\r
+ {0xBBu, 0x80u},\r
+ {0xD4u, 0x01u},\r
+ {0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDDu, 0x90u},\r
- {0x01u, 0x80u},\r
- {0x02u, 0x08u},\r
- {0x03u, 0x10u},\r
- {0x08u, 0x81u},\r
- {0x0Au, 0x18u},\r
- {0x10u, 0x40u},\r
- {0x12u, 0x22u},\r
- {0x13u, 0x10u},\r
- {0x19u, 0x04u},\r
- {0x1Au, 0x90u},\r
- {0x1Bu, 0x10u},\r
- {0x20u, 0x02u},\r
- {0x21u, 0x80u},\r
- {0x28u, 0x80u},\r
- {0x29u, 0x80u},\r
+ {0xDCu, 0x10u},\r
+ {0xDDu, 0x10u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x02u},\r
+ {0x03u, 0x04u},\r
+ {0x09u, 0x22u},\r
+ {0x10u, 0x80u},\r
+ {0x13u, 0x08u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x02u},\r
+ {0x23u, 0x22u},\r
+ {0x25u, 0x40u},\r
+ {0x29u, 0x20u},\r
{0x2Au, 0x04u},\r
- {0x31u, 0x80u},\r
- {0x32u, 0x04u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x10u},\r
+ {0x2Du, 0x60u},\r
+ {0x31u, 0x10u},\r
+ {0x33u, 0x05u},\r
+ {0x34u, 0x02u},\r
{0x35u, 0x10u},\r
- {0x39u, 0x80u},\r
- {0x3Bu, 0x12u},\r
- {0x43u, 0x14u},\r
- {0x48u, 0x40u},\r
- {0x49u, 0x80u},\r
- {0x4Bu, 0x18u},\r
- {0x53u, 0x58u},\r
- {0x58u, 0x40u},\r
- {0x59u, 0x24u},\r
- {0x5Au, 0x82u},\r
- {0x5Fu, 0x80u},\r
- {0x61u, 0x22u},\r
- {0x62u, 0x88u},\r
- {0x63u, 0x20u},\r
- {0x64u, 0x01u},\r
- {0x67u, 0x02u},\r
- {0x68u, 0x94u},\r
- {0x69u, 0x40u},\r
- {0x71u, 0x10u},\r
- {0x72u, 0x82u},\r
- {0x73u, 0x20u},\r
- {0x83u, 0x80u},\r
- {0x85u, 0x04u},\r
- {0x88u, 0x44u},\r
- {0x8Du, 0x40u},\r
- {0xC0u, 0x07u},\r
- {0xC2u, 0x0Fu},\r
- {0xC4u, 0x0Fu},\r
- {0xCAu, 0x0Bu},\r
- {0xCCu, 0x0Eu},\r
- {0xCEu, 0x0Du},\r
- {0xD0u, 0x06u},\r
- {0xD2u, 0x0Cu},\r
+ {0x37u, 0x04u},\r
+ {0x3Au, 0x99u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Cu, 0x20u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Eu, 0x08u},\r
+ {0x3Fu, 0x02u},\r
+ {0x41u, 0x20u},\r
+ {0x42u, 0x08u},\r
+ {0x43u, 0x84u},\r
+ {0x49u, 0x20u},\r
+ {0x4Au, 0x04u},\r
+ {0x4Bu, 0x08u},\r
+ {0x51u, 0x44u},\r
+ {0x52u, 0x02u},\r
+ {0x53u, 0x10u},\r
+ {0x5Au, 0xAAu},\r
+ {0x5Eu, 0x80u},\r
+ {0x61u, 0x08u},\r
+ {0x62u, 0x40u},\r
+ {0x63u, 0x44u},\r
+ {0x69u, 0x24u},\r
+ {0x6Au, 0x40u},\r
+ {0x6Bu, 0x40u},\r
+ {0x70u, 0x8Au},\r
+ {0x73u, 0x08u},\r
+ {0x80u, 0x04u},\r
+ {0x81u, 0x40u},\r
+ {0x83u, 0x40u},\r
+ {0x86u, 0x40u},\r
+ {0x87u, 0x10u},\r
+ {0x88u, 0x10u},\r
+ {0x89u, 0x10u},\r
+ {0x8Bu, 0x40u},\r
+ {0x8Fu, 0x40u},\r
+ {0xC0u, 0x0Eu},\r
+ {0xC2u, 0x0Au},\r
+ {0xC4u, 0x0Cu},\r
+ {0xCAu, 0x36u},\r
+ {0xCCu, 0xE7u},\r
+ {0xCEu, 0xFFu},\r
+ {0xD0u, 0x0Eu},\r
+ {0xD2u, 0x04u},\r
{0xD6u, 0x1Fu},\r
- {0xD8u, 0x1Fu},\r
- {0xE2u, 0x01u},\r
- {0xE4u, 0x02u},\r
- {0xE6u, 0x40u},\r
- {0x05u, 0x20u},\r
- {0x07u, 0x40u},\r
- {0x09u, 0x64u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x02u},\r
- {0x11u, 0x20u},\r
- {0x13u, 0x40u},\r
- {0x15u, 0x03u},\r
- {0x17u, 0x1Cu},\r
- {0x19u, 0x69u},\r
- {0x1Au, 0x01u},\r
- {0x1Bu, 0x12u},\r
- {0x23u, 0x01u},\r
- {0x27u, 0x67u},\r
- {0x28u, 0x01u},\r
- {0x29u, 0x08u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x77u},\r
- {0x2Du, 0x0Bu},\r
- {0x2Fu, 0x74u},\r
- {0x31u, 0x60u},\r
- {0x34u, 0x03u},\r
- {0x35u, 0x1Fu},\r
- {0x3Bu, 0x22u},\r
- {0x3Eu, 0x10u},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE0u, 0x04u},\r
+ {0xE2u, 0x10u},\r
+ {0xE4u, 0x01u},\r
+ {0xE6u, 0x44u},\r
+ {0x01u, 0x40u},\r
+ {0x03u, 0x80u},\r
+ {0x05u, 0x01u},\r
+ {0x0Du, 0x0Bu},\r
+ {0x0Fu, 0xF4u},\r
+ {0x11u, 0x06u},\r
+ {0x15u, 0x11u},\r
+ {0x17u, 0xECu},\r
+ {0x19u, 0xE0u},\r
+ {0x21u, 0xCAu},\r
+ {0x22u, 0x01u},\r
+ {0x23u, 0x15u},\r
+ {0x25u, 0x40u},\r
+ {0x27u, 0x80u},\r
+ {0x2Bu, 0x10u},\r
+ {0x2Fu, 0xFFu},\r
+ {0x32u, 0x01u},\r
+ {0x33u, 0xC0u},\r
+ {0x35u, 0x3Fu},\r
+ {0x3Bu, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
{0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x01u},\r
- {0x83u, 0x02u},\r
- {0x84u, 0xFFu},\r
- {0x85u, 0x3Fu},\r
- {0x8Bu, 0x3Fu},\r
- {0x8Eu, 0xFFu},\r
- {0x8Fu, 0x3Fu},\r
- {0x90u, 0x0Fu},\r
- {0x92u, 0xF0u},\r
- {0x94u, 0x55u},\r
- {0x95u, 0x3Fu},\r
- {0x96u, 0xAAu},\r
- {0x98u, 0xFFu},\r
- {0x99u, 0x10u},\r
- {0x9Bu, 0x20u},\r
- {0x9Cu, 0x96u},\r
- {0x9Du, 0x04u},\r
- {0x9Eu, 0x69u},\r
- {0x9Fu, 0x08u},\r
- {0xA1u, 0x04u},\r
- {0xA3u, 0x08u},\r
- {0xA4u, 0x33u},\r
+ {0x81u, 0x03u},\r
+ {0x82u, 0x02u},\r
+ {0x83u, 0x0Cu},\r
+ {0x85u, 0x02u},\r
+ {0x86u, 0x0Du},\r
+ {0x8Au, 0x90u},\r
+ {0x8Bu, 0x01u},\r
+ {0x8Du, 0xF4u},\r
+ {0x8Eu, 0x60u},\r
+ {0x90u, 0x01u},\r
+ {0x91u, 0x08u},\r
+ {0x92u, 0x02u},\r
+ {0x93u, 0xF7u},\r
+ {0x95u, 0x0Bu},\r
+ {0x97u, 0xF4u},\r
+ {0x98u, 0x90u},\r
+ {0x99u, 0x40u},\r
+ {0x9Au, 0x48u},\r
+ {0x9Bu, 0x80u},\r
+ {0x9Cu, 0x90u},\r
+ {0x9Du, 0xFDu},\r
+ {0x9Eu, 0x24u},\r
+ {0x9Fu, 0x02u},\r
+ {0xA1u, 0x10u},\r
+ {0xA3u, 0x20u},\r
{0xA5u, 0x10u},\r
- {0xA6u, 0xCCu},\r
{0xA7u, 0x20u},\r
- {0xA9u, 0x01u},\r
- {0xAAu, 0xFFu},\r
- {0xABu, 0x02u},\r
- {0xAEu, 0xFFu},\r
- {0xAFu, 0x3Fu},\r
- {0xB0u, 0xFFu},\r
- {0xB1u, 0x03u},\r
- {0xB5u, 0x30u},\r
- {0xB7u, 0x0Cu},\r
- {0xB8u, 0x08u},\r
- {0xBAu, 0x02u},\r
- {0xBBu, 0xA2u},\r
- {0xBEu, 0x04u},\r
+ {0xA9u, 0x40u},\r
+ {0xAAu, 0x80u},\r
+ {0xABu, 0x80u},\r
+ {0xAEu, 0x10u},\r
+ {0xAFu, 0xF7u},\r
+ {0xB0u, 0xE0u},\r
+ {0xB3u, 0x30u},\r
+ {0xB4u, 0x1Cu},\r
+ {0xB5u, 0xC0u},\r
+ {0xB6u, 0x03u},\r
+ {0xB7u, 0x0Fu},\r
+ {0xBBu, 0xA8u},\r
+ {0xBEu, 0x40u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDCu, 0x11u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x80u},\r
- {0x03u, 0x10u},\r
- {0x06u, 0x01u},\r
- {0x08u, 0x08u},\r
- {0x09u, 0x80u},\r
- {0x0Au, 0x88u},\r
- {0x0Eu, 0x04u},\r
- {0x12u, 0x22u},\r
- {0x13u, 0x10u},\r
- {0x17u, 0x20u},\r
- {0x18u, 0x20u},\r
- {0x1Au, 0x80u},\r
- {0x1Fu, 0x20u},\r
- {0x21u, 0x21u},\r
- {0x22u, 0x81u},\r
- {0x25u, 0x02u},\r
- {0x26u, 0x01u},\r
- {0x27u, 0x08u},\r
- {0x28u, 0x40u},\r
- {0x29u, 0x90u},\r
+ {0x00u, 0x02u},\r
+ {0x03u, 0x26u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x80u},\r
+ {0x08u, 0x81u},\r
+ {0x09u, 0x10u},\r
+ {0x10u, 0x0Au},\r
+ {0x16u, 0x40u},\r
+ {0x1Bu, 0x62u},\r
+ {0x1Eu, 0x20u},\r
+ {0x22u, 0x14u},\r
+ {0x23u, 0x01u},\r
+ {0x25u, 0x38u},\r
+ {0x2Au, 0x91u},\r
{0x2Bu, 0x10u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x80u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x40u},\r
- {0x31u, 0x20u},\r
- {0x32u, 0x84u},\r
- {0x36u, 0x01u},\r
- {0x37u, 0x18u},\r
- {0x38u, 0x04u},\r
- {0x39u, 0x82u},\r
- {0x3Au, 0x20u},\r
- {0x3Bu, 0x10u},\r
- {0x3Cu, 0xA0u},\r
- {0x3Fu, 0x08u},\r
- {0x59u, 0x04u},\r
+ {0x2Cu, 0x90u},\r
+ {0x2Eu, 0x80u},\r
+ {0x2Fu, 0x04u},\r
+ {0x30u, 0x80u},\r
+ {0x31u, 0x02u},\r
+ {0x32u, 0x10u},\r
+ {0x33u, 0x04u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0x02u},\r
+ {0x37u, 0x04u},\r
+ {0x38u, 0x80u},\r
+ {0x3Bu, 0x29u},\r
+ {0x3Du, 0x08u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x02u},\r
+ {0x40u, 0x80u},\r
+ {0x41u, 0x02u},\r
+ {0x42u, 0x40u},\r
+ {0x44u, 0x10u},\r
+ {0x45u, 0x08u},\r
+ {0x4Eu, 0x04u},\r
+ {0x4Fu, 0x20u},\r
+ {0x58u, 0x44u},\r
{0x5Au, 0x11u},\r
- {0x5Bu, 0x40u},\r
- {0x60u, 0x88u},\r
+ {0x5Du, 0x9Au},\r
+ {0x60u, 0x02u},\r
{0x61u, 0x80u},\r
- {0x62u, 0x04u},\r
- {0x63u, 0x08u},\r
- {0x80u, 0x10u},\r
- {0x82u, 0x02u},\r
+ {0x62u, 0x15u},\r
+ {0x67u, 0x02u},\r
+ {0x81u, 0x08u},\r
+ {0x83u, 0x01u},\r
+ {0x84u, 0x01u},\r
{0x85u, 0x80u},\r
- {0x89u, 0x04u},\r
- {0x8Bu, 0x10u},\r
- {0x8Cu, 0x04u},\r
- {0x8Du, 0x04u},\r
- {0x8Eu, 0x10u},\r
- {0x8Fu, 0x10u},\r
- {0x93u, 0x88u},\r
- {0x95u, 0x84u},\r
- {0x96u, 0x0Au},\r
- {0x97u, 0x10u},\r
- {0x98u, 0x10u},\r
- {0x9Au, 0x82u},\r
- {0x9Cu, 0x80u},\r
- {0x9Du, 0xA2u},\r
- {0x9Eu, 0x04u},\r
- {0x9Fu, 0x14u},\r
- {0xA0u, 0xC1u},\r
- {0xA5u, 0x22u},\r
- {0xA6u, 0xA2u},\r
- {0xA9u, 0x80u},\r
- {0xACu, 0x10u},\r
- {0xAFu, 0x34u},\r
+ {0x88u, 0x80u},\r
+ {0x89u, 0x20u},\r
+ {0x8Fu, 0x20u},\r
+ {0x91u, 0x8Cu},\r
+ {0x93u, 0x28u},\r
+ {0x95u, 0x40u},\r
+ {0x96u, 0xAAu},\r
+ {0x97u, 0x54u},\r
+ {0x98u, 0x04u},\r
+ {0x9Au, 0x80u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Eu, 0x15u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA0u, 0x0Au},\r
+ {0xA1u, 0x40u},\r
+ {0xA2u, 0x02u},\r
+ {0xA4u, 0x10u},\r
+ {0xA5u, 0x2Au},\r
+ {0xA6u, 0x44u},\r
+ {0xA7u, 0xC1u},\r
+ {0xADu, 0x04u},\r
+ {0xAFu, 0x23u},\r
+ {0xB0u, 0x04u},\r
{0xB5u, 0x02u},\r
- {0xB7u, 0x08u},\r
- {0xC0u, 0x85u},\r
- {0xC2u, 0x4Fu},\r
- {0xC4u, 0x47u},\r
+ {0xB6u, 0x40u},\r
+ {0xC0u, 0x0Fu},\r
+ {0xC2u, 0x0Bu},\r
+ {0xC4u, 0x13u},\r
{0xCAu, 0xFFu},\r
- {0xCCu, 0xEEu},\r
- {0xCEu, 0x7Fu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x0Fu},\r
- {0xE0u, 0x08u},\r
- {0xE2u, 0x20u},\r
- {0xE4u, 0x04u},\r
- {0xE6u, 0x21u},\r
- {0xE8u, 0x0Eu},\r
- {0xEAu, 0x10u},\r
- {0xECu, 0x0Au},\r
- {0x02u, 0x1Cu},\r
- {0x04u, 0x28u},\r
+ {0xCCu, 0xEFu},\r
+ {0xCEu, 0xDFu},\r
+ {0xD6u, 0xFFu},\r
+ {0xD8u, 0x1Fu},\r
+ {0xE2u, 0x08u},\r
+ {0xE6u, 0x0Du},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x04u},\r
+ {0x02u, 0x08u},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0x08u},\r
{0x05u, 0x10u},\r
- {0x06u, 0x14u},\r
- {0x07u, 0x08u},\r
- {0x0Cu, 0x10u},\r
- {0x0Du, 0x01u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x02u},\r
- {0x11u, 0x10u},\r
- {0x13u, 0x08u},\r
- {0x19u, 0x08u},\r
- {0x1Bu, 0x11u},\r
- {0x1Du, 0x10u},\r
+ {0x06u, 0x37u},\r
+ {0x07u, 0x20u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x40u},\r
+ {0x0Bu, 0x02u},\r
+ {0x0Du, 0x40u},\r
+ {0x0Fu, 0x3Fu},\r
+ {0x10u, 0x10u},\r
+ {0x12u, 0x20u},\r
+ {0x13u, 0x40u},\r
+ {0x14u, 0x01u},\r
+ {0x15u, 0x40u},\r
+ {0x16u, 0x02u},\r
+ {0x17u, 0x3Fu},\r
+ {0x18u, 0x33u},\r
+ {0x19u, 0x7Fu},\r
+ {0x1Au, 0x04u},\r
+ {0x1Cu, 0x01u},\r
+ {0x1Du, 0x01u},\r
{0x1Eu, 0x02u},\r
- {0x1Fu, 0x0Eu},\r
- {0x22u, 0x20u},\r
- {0x28u, 0x24u},\r
- {0x2Au, 0x08u},\r
- {0x2Du, 0x10u},\r
- {0x2Eu, 0x01u},\r
- {0x2Fu, 0x08u},\r
- {0x30u, 0x02u},\r
- {0x31u, 0x04u},\r
+ {0x1Fu, 0x02u},\r
+ {0x20u, 0x33u},\r
+ {0x21u, 0x10u},\r
+ {0x22u, 0x04u},\r
+ {0x23u, 0x20u},\r
+ {0x25u, 0x04u},\r
+ {0x26u, 0x37u},\r
+ {0x27u, 0x08u},\r
+ {0x28u, 0x10u},\r
+ {0x29u, 0x3Fu},\r
+ {0x2Au, 0x20u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Eu, 0x37u},\r
+ {0x2Fu, 0x3Fu},\r
+ {0x30u, 0x30u},\r
+ {0x31u, 0x0Cu},\r
+ {0x32u, 0x03u},\r
{0x33u, 0x03u},\r
- {0x34u, 0x01u},\r
- {0x35u, 0x18u},\r
- {0x36u, 0x3Cu},\r
- {0x3Bu, 0x20u},\r
- {0x3Fu, 0x04u},\r
+ {0x34u, 0x40u},\r
+ {0x35u, 0x30u},\r
+ {0x36u, 0x0Cu},\r
+ {0x37u, 0x40u},\r
+ {0x3Au, 0x8Au},\r
+ {0x3Bu, 0x2Au},\r
+ {0x3Fu, 0x40u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x01u},\r
- {0x84u, 0x04u},\r
- {0x86u, 0x43u},\r
- {0x8Cu, 0x21u},\r
- {0x8Eu, 0x02u},\r
- {0x8Fu, 0x01u},\r
- {0x92u, 0x01u},\r
- {0x96u, 0xECu},\r
- {0x98u, 0x88u},\r
- {0x9Au, 0x03u},\r
- {0x9Cu, 0xE0u},\r
- {0x9Du, 0x01u},\r
- {0xA5u, 0x01u},\r
- {0xA6u, 0x12u},\r
- {0xA9u, 0x01u},\r
- {0xAFu, 0x01u},\r
- {0xB0u, 0x10u},\r
- {0xB2u, 0x0Fu},\r
- {0xB4u, 0xE0u},\r
- {0xB5u, 0x01u},\r
- {0xBEu, 0x10u},\r
- {0xBFu, 0x10u},\r
- {0xD4u, 0x40u},\r
- {0xD6u, 0x04u},\r
+ {0x80u, 0x01u},\r
+ {0x81u, 0x81u},\r
+ {0x82u, 0x02u},\r
+ {0x83u, 0x2Eu},\r
+ {0x87u, 0x80u},\r
+ {0x8Bu, 0x1Fu},\r
+ {0x93u, 0x60u},\r
+ {0x94u, 0x02u},\r
+ {0x95u, 0x03u},\r
+ {0x96u, 0x01u},\r
+ {0x97u, 0x94u},\r
+ {0x98u, 0x02u},\r
+ {0x9Au, 0x11u},\r
+ {0x9Bu, 0x01u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Eu, 0x09u},\r
+ {0xA0u, 0x02u},\r
+ {0xA1u, 0x98u},\r
+ {0xA2u, 0x05u},\r
+ {0xA3u, 0x43u},\r
+ {0xA7u, 0x08u},\r
+ {0xA9u, 0x02u},\r
+ {0xADu, 0x04u},\r
+ {0xB0u, 0x03u},\r
+ {0xB2u, 0x10u},\r
+ {0xB4u, 0x08u},\r
+ {0xB5u, 0x1Fu},\r
+ {0xB6u, 0x04u},\r
+ {0xB7u, 0xE0u},\r
+ {0xBAu, 0x02u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x80u},\r
- {0x03u, 0x90u},\r
- {0x04u, 0x44u},\r
- {0x0Au, 0x02u},\r
- {0x0Eu, 0xA8u},\r
- {0x0Fu, 0x01u},\r
- {0x10u, 0x81u},\r
- {0x13u, 0x10u},\r
+ {0x02u, 0x28u},\r
+ {0x03u, 0x80u},\r
+ {0x05u, 0x01u},\r
+ {0x09u, 0x80u},\r
+ {0x0Au, 0xA8u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Du, 0x0Au},\r
+ {0x0Eu, 0x06u},\r
+ {0x10u, 0x82u},\r
+ {0x12u, 0x04u},\r
+ {0x13u, 0x08u},\r
+ {0x14u, 0x20u},\r
{0x15u, 0x08u},\r
- {0x18u, 0x08u},\r
- {0x1Bu, 0xC1u},\r
- {0x1Eu, 0xA0u},\r
- {0x1Fu, 0x10u},\r
- {0x20u, 0x20u},\r
- {0x22u, 0x1Du},\r
- {0x25u, 0x20u},\r
- {0x28u, 0x01u},\r
- {0x2Bu, 0x01u},\r
- {0x2Cu, 0x08u},\r
- {0x2Fu, 0x21u},\r
- {0x32u, 0x91u},\r
- {0x37u, 0x40u},\r
- {0x38u, 0x08u},\r
- {0x39u, 0x40u},\r
- {0x3Eu, 0x42u},\r
- {0x45u, 0x20u},\r
- {0x46u, 0x08u},\r
- {0x58u, 0x80u},\r
- {0x5Bu, 0x28u},\r
- {0x61u, 0x14u},\r
- {0x62u, 0x80u},\r
- {0x63u, 0x20u},\r
- {0x66u, 0x18u},\r
- {0x67u, 0x42u},\r
- {0x69u, 0x40u},\r
- {0x6Du, 0x94u},\r
- {0x80u, 0x08u},\r
- {0x85u, 0x50u},\r
- {0x88u, 0x80u},\r
- {0x8Eu, 0x10u},\r
- {0x8Fu, 0x41u},\r
- {0x91u, 0x80u},\r
- {0x92u, 0x80u},\r
- {0x93u, 0x88u},\r
- {0x95u, 0x04u},\r
- {0x96u, 0x0Cu},\r
- {0x97u, 0x10u},\r
- {0x98u, 0x10u},\r
- {0x9Au, 0x84u},\r
- {0x9Cu, 0x40u},\r
- {0x9Du, 0xB2u},\r
- {0x9Eu, 0x01u},\r
- {0x9Fu, 0x14u},\r
- {0xA0u, 0xC1u},\r
- {0xA1u, 0x01u},\r
+ {0x17u, 0x02u},\r
+ {0x1Au, 0xA0u},\r
+ {0x1Bu, 0xA8u},\r
+ {0x1Cu, 0x80u},\r
+ {0x1Du, 0x09u},\r
+ {0x1Eu, 0x06u},\r
+ {0x1Fu, 0x01u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0x81u},\r
+ {0x23u, 0x14u},\r
+ {0x26u, 0x20u},\r
+ {0x27u, 0x05u},\r
+ {0x28u, 0x10u},\r
+ {0x29u, 0x92u},\r
+ {0x2Cu, 0x80u},\r
+ {0x2Eu, 0x40u},\r
+ {0x2Fu, 0x14u},\r
+ {0x30u, 0x40u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x02u},\r
+ {0x33u, 0x06u},\r
+ {0x37u, 0x15u},\r
+ {0x39u, 0x02u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Bu, 0x14u},\r
+ {0x3Cu, 0x20u},\r
+ {0x3Du, 0x06u},\r
+ {0x45u, 0x01u},\r
+ {0x46u, 0x80u},\r
+ {0x5Bu, 0x40u},\r
+ {0x63u, 0x02u},\r
+ {0x6Cu, 0x09u},\r
+ {0x6Du, 0x08u},\r
+ {0x6Fu, 0x10u},\r
+ {0x81u, 0x02u},\r
+ {0x83u, 0x04u},\r
+ {0x84u, 0x50u},\r
+ {0x88u, 0x08u},\r
+ {0x8Du, 0x40u},\r
+ {0x8Eu, 0x01u},\r
+ {0x91u, 0x8Cu},\r
+ {0x93u, 0x28u},\r
+ {0x94u, 0x80u},\r
+ {0x95u, 0x50u},\r
+ {0x96u, 0x82u},\r
+ {0x97u, 0x16u},\r
+ {0x9Au, 0x04u},\r
+ {0x9Bu, 0x60u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA0u, 0x80u},\r
+ {0xA1u, 0xF0u},\r
+ {0xA2u, 0x12u},\r
{0xA4u, 0x10u},\r
- {0xA6u, 0x20u},\r
- {0xA7u, 0x10u},\r
- {0xA8u, 0x20u},\r
- {0xA9u, 0x40u},\r
- {0xAAu, 0x02u},\r
- {0xABu, 0x60u},\r
+ {0xA5u, 0x06u},\r
+ {0xA6u, 0x44u},\r
+ {0xA7u, 0x89u},\r
+ {0xAAu, 0x10u},\r
+ {0xABu, 0x40u},\r
+ {0xACu, 0x41u},\r
+ {0xAFu, 0x4Au},\r
{0xB2u, 0x01u},\r
- {0xB5u, 0x01u},\r
- {0xB7u, 0x28u},\r
- {0xC0u, 0xADu},\r
- {0xC2u, 0xF1u},\r
- {0xC4u, 0x2Bu},\r
- {0xCAu, 0x78u},\r
- {0xCCu, 0x1Du},\r
- {0xCEu, 0x9Au},\r
- {0xD6u, 0x0Eu},\r
- {0xD8u, 0xFEu},\r
- {0xE6u, 0x04u},\r
- {0xEAu, 0x01u},\r
- {0xEEu, 0x49u},\r
- {0x02u, 0x10u},\r
- {0x04u, 0x01u},\r
- {0x05u, 0x0Au},\r
- {0x07u, 0x55u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x8Bu},\r
- {0x0Bu, 0x74u},\r
- {0x0Cu, 0x01u},\r
- {0x0Fu, 0x10u},\r
- {0x12u, 0x01u},\r
- {0x14u, 0x12u},\r
- {0x15u, 0x20u},\r
- {0x16u, 0x04u},\r
- {0x17u, 0x40u},\r
- {0x19u, 0x40u},\r
- {0x1Au, 0x0Eu},\r
- {0x1Bu, 0x80u},\r
- {0x1Cu, 0x08u},\r
- {0x1Eu, 0x10u},\r
- {0x23u, 0x7Fu},\r
- {0x25u, 0x01u},\r
- {0x28u, 0x14u},\r
- {0x29u, 0x06u},\r
- {0x2Au, 0x0Au},\r
- {0x2Cu, 0x01u},\r
- {0x2Du, 0x91u},\r
- {0x2Fu, 0x6Cu},\r
- {0x32u, 0x01u},\r
- {0x33u, 0x3Fu},\r
- {0x34u, 0x1Eu},\r
- {0x35u, 0xC0u},\r
- {0x36u, 0x01u},\r
- {0x3Bu, 0x20u},\r
- {0x3Eu, 0x44u},\r
+ {0xB5u, 0x04u},\r
+ {0xC0u, 0x1Eu},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0x1Fu},\r
+ {0xCAu, 0xFFu},\r
+ {0xCCu, 0xEFu},\r
+ {0xCEu, 0xEFu},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE0u, 0x01u},\r
+ {0xE6u, 0x6Eu},\r
+ {0xE8u, 0x08u},\r
+ {0xEAu, 0x03u},\r
+ {0xEEu, 0x4Du},\r
+ {0x01u, 0x80u},\r
+ {0x05u, 0x0Fu},\r
+ {0x06u, 0xFFu},\r
+ {0x08u, 0x60u},\r
+ {0x09u, 0x20u},\r
+ {0x0Au, 0x90u},\r
+ {0x0Bu, 0x4Fu},\r
+ {0x0Cu, 0x05u},\r
+ {0x0Du, 0x06u},\r
+ {0x0Eu, 0x0Au},\r
+ {0x0Fu, 0x09u},\r
+ {0x10u, 0x50u},\r
+ {0x11u, 0x80u},\r
+ {0x12u, 0xA0u},\r
+ {0x14u, 0x30u},\r
+ {0x15u, 0x40u},\r
+ {0x16u, 0xC0u},\r
+ {0x17u, 0x1Fu},\r
+ {0x19u, 0x03u},\r
+ {0x1Au, 0xFFu},\r
+ {0x1Bu, 0x0Cu},\r
+ {0x1Cu, 0xFFu},\r
+ {0x1Fu, 0x70u},\r
+ {0x20u, 0x06u},\r
+ {0x21u, 0x80u},\r
+ {0x22u, 0x09u},\r
+ {0x24u, 0x0Fu},\r
+ {0x25u, 0x80u},\r
+ {0x26u, 0xF0u},\r
+ {0x28u, 0x03u},\r
+ {0x29u, 0x05u},\r
+ {0x2Au, 0x0Cu},\r
+ {0x2Bu, 0x0Au},\r
+ {0x2Du, 0x10u},\r
+ {0x2Fu, 0x2Fu},\r
+ {0x33u, 0x80u},\r
+ {0x36u, 0xFFu},\r
+ {0x37u, 0x7Fu},\r
+ {0x39u, 0x08u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Cu, 0x11u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x7Fu},\r
- {0x84u, 0x78u},\r
- {0x86u, 0x03u},\r
- {0x88u, 0x20u},\r
- {0x8Au, 0x40u},\r
- {0x8Bu, 0xFFu},\r
- {0x8Cu, 0x02u},\r
- {0x8Fu, 0xFFu},\r
- {0x91u, 0x0Fu},\r
- {0x92u, 0x08u},\r
- {0x93u, 0xF0u},\r
- {0x94u, 0x01u},\r
- {0x95u, 0xFFu},\r
- {0x96u, 0x6Eu},\r
- {0x98u, 0x64u},\r
- {0x99u, 0xFFu},\r
- {0x9Cu, 0x03u},\r
- {0x9Eu, 0x74u},\r
- {0xA1u, 0x55u},\r
- {0xA3u, 0xAAu},\r
- {0xA5u, 0x69u},\r
- {0xA6u, 0x01u},\r
- {0xA7u, 0x96u},\r
- {0xA8u, 0x20u},\r
- {0xA9u, 0x33u},\r
- {0xAAu, 0x40u},\r
- {0xABu, 0xCCu},\r
- {0xAFu, 0xFFu},\r
- {0xB1u, 0xFFu},\r
- {0xB4u, 0x60u},\r
- {0xB6u, 0x1Fu},\r
- {0xBAu, 0x20u},\r
- {0xBBu, 0x02u},\r
- {0xD6u, 0x08u},\r
+ {0x81u, 0xD6u},\r
+ {0x84u, 0x01u},\r
+ {0x85u, 0x17u},\r
+ {0x86u, 0x06u},\r
+ {0x87u, 0x28u},\r
+ {0x89u, 0xD0u},\r
+ {0x8Bu, 0x06u},\r
+ {0x8Eu, 0x08u},\r
+ {0x90u, 0x05u},\r
+ {0x91u, 0xD6u},\r
+ {0x92u, 0x02u},\r
+ {0x95u, 0x20u},\r
+ {0x97u, 0xD0u},\r
+ {0x99u, 0x29u},\r
+ {0x9Bu, 0x46u},\r
+ {0x9Cu, 0x04u},\r
+ {0x9Du, 0xD6u},\r
+ {0x9Eu, 0x03u},\r
+ {0xA1u, 0x21u},\r
+ {0xA2u, 0x10u},\r
+ {0xA3u, 0x8Eu},\r
+ {0xA4u, 0x03u},\r
+ {0xA5u, 0xD2u},\r
+ {0xA6u, 0x04u},\r
+ {0xA7u, 0x04u},\r
+ {0xA9u, 0x02u},\r
+ {0xACu, 0x08u},\r
+ {0xADu, 0x04u},\r
+ {0xAEu, 0x10u},\r
+ {0xB0u, 0x18u},\r
+ {0xB3u, 0xF0u},\r
+ {0xB4u, 0x18u},\r
+ {0xB5u, 0x0Fu},\r
+ {0xB6u, 0x07u},\r
+ {0xB9u, 0x20u},\r
+ {0xBAu, 0x80u},\r
+ {0xBBu, 0x08u},\r
+ {0xBEu, 0x11u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
- {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x80u},\r
- {0x01u, 0x20u},\r
- {0x02u, 0x40u},\r
- {0x03u, 0x10u},\r
- {0x04u, 0xA8u},\r
- {0x06u, 0x80u},\r
- {0x0Au, 0x09u},\r
- {0x0Bu, 0x90u},\r
- {0x0Eu, 0x45u},\r
- {0x0Fu, 0x10u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x04u},\r
- {0x16u, 0x02u},\r
- {0x17u, 0x10u},\r
- {0x19u, 0xA0u},\r
- {0x1Au, 0x01u},\r
- {0x1Eu, 0x06u},\r
- {0x1Fu, 0x08u},\r
- {0x22u, 0x02u},\r
- {0x25u, 0x04u},\r
- {0x26u, 0x10u},\r
- {0x27u, 0x14u},\r
- {0x28u, 0x40u},\r
- {0x29u, 0x94u},\r
- {0x2Du, 0x84u},\r
- {0x2Fu, 0x84u},\r
- {0x32u, 0x06u},\r
- {0x33u, 0x10u},\r
- {0x36u, 0x18u},\r
- {0x39u, 0x80u},\r
- {0x3Au, 0x40u},\r
- {0x3Bu, 0x10u},\r
- {0x3Cu, 0x80u},\r
- {0x3Du, 0x08u},\r
- {0x3Fu, 0x10u},\r
+ {0x00u, 0x84u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x04u},\r
+ {0x07u, 0x10u},\r
+ {0x0Au, 0x82u},\r
+ {0x0Du, 0x01u},\r
+ {0x0Eu, 0x04u},\r
+ {0x0Fu, 0x22u},\r
+ {0x11u, 0x40u},\r
+ {0x12u, 0x20u},\r
+ {0x13u, 0x03u},\r
+ {0x14u, 0x80u},\r
+ {0x15u, 0x20u},\r
+ {0x16u, 0x10u},\r
+ {0x18u, 0x80u},\r
+ {0x19u, 0x10u},\r
+ {0x1Au, 0x4Au},\r
+ {0x1Bu, 0x40u},\r
+ {0x1Fu, 0x40u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x20u},\r
+ {0x24u, 0x10u},\r
+ {0x26u, 0x40u},\r
+ {0x29u, 0x01u},\r
+ {0x2Au, 0x08u},\r
+ {0x2Bu, 0x06u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Eu, 0xA0u},\r
+ {0x2Fu, 0x40u},\r
+ {0x31u, 0x88u},\r
+ {0x32u, 0x20u},\r
+ {0x33u, 0x01u},\r
+ {0x35u, 0x02u},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0x24u},\r
+ {0x38u, 0x04u},\r
+ {0x39u, 0x11u},\r
+ {0x3Du, 0xA8u},\r
+ {0x3Eu, 0x05u},\r
{0x41u, 0x40u},\r
- {0x43u, 0x80u},\r
- {0x58u, 0x80u},\r
- {0x5Bu, 0x20u},\r
- {0x62u, 0x20u},\r
- {0x63u, 0x02u},\r
- {0x78u, 0x40u},\r
- {0x7Bu, 0x01u},\r
- {0x83u, 0x20u},\r
+ {0x43u, 0x40u},\r
+ {0x58u, 0x26u},\r
+ {0x5Bu, 0x40u},\r
+ {0x62u, 0x80u},\r
+ {0x69u, 0x40u},\r
+ {0x7Fu, 0x0Cu},\r
+ {0x82u, 0x04u},\r
+ {0x83u, 0x10u},\r
{0x84u, 0x80u},\r
+ {0x88u, 0x40u},\r
+ {0x8Au, 0x10u},\r
+ {0x8Bu, 0x01u},\r
+ {0x8Cu, 0x10u},\r
+ {0x8Du, 0x02u},\r
{0x8Fu, 0x10u},\r
- {0x91u, 0x85u},\r
- {0x92u, 0x88u},\r
- {0x93u, 0x88u},\r
- {0x94u, 0x44u},\r
- {0x95u, 0x08u},\r
- {0x96u, 0x44u},\r
- {0x97u, 0x12u},\r
- {0x98u, 0x18u},\r
- {0x99u, 0x14u},\r
- {0x9Au, 0x85u},\r
- {0x9Cu, 0x40u},\r
- {0x9Du, 0xA2u},\r
- {0x9Eu, 0x12u},\r
- {0x9Fu, 0x54u},\r
- {0xA0u, 0x41u},\r
- {0xA1u, 0x01u},\r
- {0xA2u, 0x08u},\r
- {0xA4u, 0x08u},\r
- {0xA6u, 0x24u},\r
- {0xA7u, 0x20u},\r
- {0xAAu, 0x01u},\r
- {0xABu, 0x20u},\r
- {0xAFu, 0x18u},\r
- {0xB1u, 0x03u},\r
- {0xB3u, 0x40u},\r
- {0xC0u, 0xFFu},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0xC6u},\r
+ {0x91u, 0xA0u},\r
+ {0x93u, 0x08u},\r
+ {0x94u, 0x80u},\r
+ {0x96u, 0x48u},\r
+ {0x98u, 0x24u},\r
+ {0x9Bu, 0x24u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Eu, 0x41u},\r
+ {0x9Fu, 0x0Au},\r
+ {0xA0u, 0xC0u},\r
+ {0xA1u, 0x54u},\r
+ {0xA2u, 0x90u},\r
+ {0xA3u, 0x20u},\r
+ {0xA4u, 0x10u},\r
+ {0xA5u, 0x03u},\r
+ {0xA6u, 0x4Cu},\r
+ {0xA8u, 0x01u},\r
+ {0xADu, 0x90u},\r
+ {0xAFu, 0x09u},\r
+ {0xB0u, 0x04u},\r
+ {0xB1u, 0x10u},\r
+ {0xB3u, 0x02u},\r
+ {0xC0u, 0xE5u},\r
+ {0xC2u, 0xF9u},\r
+ {0xC4u, 0x7Du},\r
{0xCAu, 0xFFu},\r
- {0xCCu, 0x67u},\r
- {0xCEu, 0x7Cu},\r
- {0xD6u, 0x0Cu},\r
- {0xD8u, 0x0Cu},\r
- {0xE2u, 0x01u},\r
- {0xE6u, 0x06u},\r
- {0xEAu, 0x2Fu},\r
- {0xEEu, 0x20u},\r
- {0x65u, 0x08u},\r
- {0x66u, 0x08u},\r
- {0x81u, 0x01u},\r
- {0x82u, 0x04u},\r
- {0x89u, 0x40u},\r
- {0x8Du, 0x04u},\r
- {0x8Eu, 0x21u},\r
- {0x91u, 0x60u},\r
- {0x94u, 0x30u},\r
- {0x95u, 0x92u},\r
- {0x98u, 0x0Cu},\r
- {0x9Au, 0x04u},\r
- {0x9Bu, 0x42u},\r
- {0x9Du, 0x48u},\r
- {0x9Eu, 0x1Au},\r
- {0xA0u, 0x30u},\r
- {0xA2u, 0x04u},\r
- {0xA3u, 0x08u},\r
- {0xA5u, 0x40u},\r
- {0xA9u, 0x01u},\r
- {0xB2u, 0x20u},\r
- {0xB3u, 0x04u},\r
- {0xE0u, 0x04u},\r
- {0xE2u, 0x01u},\r
- {0xE4u, 0x40u},\r
- {0xE6u, 0x02u},\r
- {0xE8u, 0x80u},\r
- {0xEAu, 0x0Bu},\r
- {0xEEu, 0xA0u},\r
- {0x00u, 0xFFu},\r
- {0x03u, 0x02u},\r
- {0x04u, 0x03u},\r
- {0x06u, 0x0Cu},\r
- {0x07u, 0x04u},\r
- {0x08u, 0x09u},\r
- {0x0Au, 0x06u},\r
- {0x0Du, 0x02u},\r
- {0x0Fu, 0x04u},\r
+ {0xCCu, 0xFFu},\r
+ {0xCEu, 0xF7u},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x11u},\r
+ {0xE6u, 0x03u},\r
+ {0xE8u, 0x02u},\r
+ {0xEAu, 0x20u},\r
+ {0xEEu, 0x01u},\r
+ {0x01u, 0x08u},\r
+ {0x03u, 0x05u},\r
+ {0x04u, 0x55u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0xAAu},\r
+ {0x07u, 0x10u},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Bu, 0x30u},\r
+ {0x0Cu, 0xFFu},\r
+ {0x0Fu, 0x40u},\r
{0x10u, 0x0Fu},\r
+ {0x11u, 0x08u},\r
{0x12u, 0xF0u},\r
+ {0x13u, 0x06u},\r
+ {0x15u, 0x04u},\r
{0x16u, 0xFFu},\r
- {0x18u, 0xFFu},\r
- {0x20u, 0x05u},\r
- {0x22u, 0x0Au},\r
- {0x24u, 0x30u},\r
- {0x26u, 0xC0u},\r
- {0x28u, 0x50u},\r
- {0x2Au, 0xA0u},\r
- {0x2Cu, 0x90u},\r
- {0x2Eu, 0x60u},\r
- {0x2Fu, 0x01u},\r
+ {0x17u, 0x08u},\r
+ {0x19u, 0x08u},\r
+ {0x1Au, 0xFFu},\r
+ {0x1Bu, 0x04u},\r
+ {0x1Cu, 0x69u},\r
+ {0x1Eu, 0x96u},\r
+ {0x21u, 0x40u},\r
+ {0x23u, 0x20u},\r
+ {0x24u, 0xFFu},\r
+ {0x25u, 0x08u},\r
+ {0x27u, 0x04u},\r
+ {0x28u, 0x33u},\r
+ {0x2Au, 0xCCu},\r
+ {0x2Bu, 0x40u},\r
{0x30u, 0xFFu},\r
- {0x33u, 0x06u},\r
- {0x35u, 0x01u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x04u},\r
+ {0x31u, 0x01u},\r
+ {0x33u, 0x0Cu},\r
+ {0x35u, 0x70u},\r
+ {0x37u, 0x02u},\r
+ {0x3Au, 0x02u},\r
+ {0x3Bu, 0x08u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x10u},\r
+ {0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x40u},\r
- {0x81u, 0x08u},\r
- {0x82u, 0x20u},\r
- {0x83u, 0x10u},\r
- {0x84u, 0x01u},\r
- {0x86u, 0x02u},\r
- {0x88u, 0x08u},\r
- {0x8Au, 0x10u},\r
- {0x8Bu, 0x10u},\r
- {0x8Du, 0x01u},\r
- {0x8Fu, 0x66u},\r
- {0x91u, 0x04u},\r
- {0x93u, 0x03u},\r
- {0x94u, 0x06u},\r
- {0x97u, 0x20u},\r
- {0x98u, 0x10u},\r
- {0x9Au, 0x08u},\r
+ {0x80u, 0xFFu},\r
+ {0x84u, 0x30u},\r
+ {0x86u, 0xC0u},\r
+ {0x87u, 0x01u},\r
+ {0x88u, 0x50u},\r
+ {0x8Au, 0xA0u},\r
+ {0x8Bu, 0x20u},\r
+ {0x8Cu, 0x90u},\r
+ {0x8Eu, 0x60u},\r
+ {0x90u, 0x03u},\r
+ {0x92u, 0x0Cu},\r
+ {0x93u, 0x04u},\r
+ {0x94u, 0xFFu},\r
+ {0x97u, 0x10u},\r
+ {0x98u, 0x05u},\r
+ {0x9Au, 0x0Au},\r
{0x9Bu, 0x08u},\r
- {0x9Cu, 0x18u},\r
- {0x9Eu, 0x60u},\r
- {0xA0u, 0x20u},\r
- {0xA1u, 0xC5u},\r
- {0xA2u, 0x40u},\r
+ {0xA2u, 0xFFu},\r
{0xA3u, 0x02u},\r
- {0xA8u, 0x01u},\r
- {0xA9u, 0x03u},\r
- {0xAAu, 0x04u},\r
- {0xABu, 0xA4u},\r
- {0xACu, 0x02u},\r
- {0xAEu, 0x01u},\r
- {0xB2u, 0x07u},\r
- {0xB3u, 0xE0u},\r
- {0xB5u, 0x18u},\r
- {0xB6u, 0x78u},\r
- {0xB7u, 0x07u},\r
- {0xB8u, 0x08u},\r
- {0xBBu, 0x80u},\r
+ {0xA8u, 0x09u},\r
+ {0xAAu, 0x06u},\r
+ {0xACu, 0x0Fu},\r
+ {0xADu, 0x15u},\r
+ {0xAEu, 0xF0u},\r
+ {0xAFu, 0x2Au},\r
+ {0xB1u, 0x03u},\r
+ {0xB3u, 0x0Cu},\r
+ {0xB5u, 0x30u},\r
+ {0xB6u, 0xFFu},\r
{0xBEu, 0x40u},\r
- {0xBFu, 0x10u},\r
+ {0xBFu, 0x15u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x08u},\r
- {0x02u, 0x04u},\r
- {0x03u, 0x80u},\r
- {0x04u, 0x20u},\r
- {0x06u, 0x10u},\r
- {0x07u, 0x40u},\r
- {0x0Bu, 0xA8u},\r
- {0x0Du, 0x70u},\r
- {0x0Eu, 0x10u},\r
- {0x0Fu, 0x02u},\r
- {0x10u, 0x28u},\r
- {0x11u, 0x41u},\r
- {0x15u, 0x10u},\r
- {0x16u, 0x02u},\r
- {0x17u, 0x02u},\r
- {0x19u, 0x02u},\r
- {0x1Eu, 0x10u},\r
- {0x1Fu, 0x80u},\r
- {0x23u, 0x14u},\r
- {0x24u, 0x02u},\r
- {0x26u, 0x14u},\r
- {0x27u, 0x01u},\r
- {0x28u, 0x02u},\r
- {0x2Du, 0x10u},\r
- {0x2Eu, 0x02u},\r
- {0x36u, 0x24u},\r
- {0x37u, 0x01u},\r
- {0x38u, 0x08u},\r
- {0x39u, 0x83u},\r
- {0x3Bu, 0x80u},\r
- {0x3Du, 0x80u},\r
- {0x3Eu, 0x20u},\r
- {0x3Fu, 0x02u},\r
- {0x59u, 0x40u},\r
- {0x60u, 0x02u},\r
- {0x6Cu, 0x2Cu},\r
- {0x6Du, 0x40u},\r
- {0x6Eu, 0x40u},\r
- {0x6Fu, 0x46u},\r
- {0x74u, 0x10u},\r
- {0x75u, 0x01u},\r
- {0x76u, 0x20u},\r
- {0x77u, 0x02u},\r
- {0x80u, 0x01u},\r
- {0x8Bu, 0x10u},\r
- {0x8Du, 0x20u},\r
- {0x8Eu, 0x10u},\r
- {0x8Fu, 0x01u},\r
- {0x93u, 0x20u},\r
- {0x94u, 0x10u},\r
- {0x95u, 0x83u},\r
- {0x96u, 0x40u},\r
- {0x97u, 0x0Eu},\r
- {0x98u, 0x0Cu},\r
- {0x9Au, 0x04u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0x0Au},\r
- {0x9Eu, 0x08u},\r
- {0x9Fu, 0x04u},\r
- {0xA2u, 0x20u},\r
- {0xA3u, 0x08u},\r
- {0xA4u, 0x28u},\r
- {0xA6u, 0x10u},\r
- {0xA7u, 0x82u},\r
- {0xABu, 0x21u},\r
- {0xAEu, 0x10u},\r
- {0xB1u, 0x04u},\r
- {0xB3u, 0x40u},\r
- {0xB5u, 0x40u},\r
- {0xB6u, 0x22u},\r
- {0xC0u, 0x7Eu},\r
- {0xC2u, 0xEEu},\r
- {0xC4u, 0xDFu},\r
- {0xCAu, 0xA8u},\r
- {0xCCu, 0xE0u},\r
- {0xCEu, 0xBBu},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x08u},\r
- {0xE0u, 0x40u},\r
- {0xE2u, 0x20u},\r
- {0xE4u, 0x40u},\r
- {0xE6u, 0x10u},\r
- {0xEAu, 0x10u},\r
- {0xEEu, 0x91u},\r
- {0x01u, 0x04u},\r
- {0x03u, 0x03u},\r
- {0x07u, 0x38u},\r
+ {0x01u, 0x10u},\r
+ {0x02u, 0x23u},\r
+ {0x03u, 0x88u},\r
+ {0x05u, 0x80u},\r
+ {0x06u, 0x20u},\r
+ {0x07u, 0x04u},\r
+ {0x08u, 0x01u},\r
{0x09u, 0x04u},\r
- {0x0Bu, 0x02u},\r
- {0x0Du, 0x02u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x02u},\r
- {0x11u, 0x04u},\r
- {0x13u, 0x82u},\r
- {0x15u, 0x20u},\r
- {0x17u, 0x40u},\r
- {0x19u, 0x04u},\r
+ {0x0Au, 0x08u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Cu, 0x68u},\r
+ {0x0Eu, 0x40u},\r
+ {0x0Fu, 0x08u},\r
+ {0x11u, 0xA0u},\r
+ {0x13u, 0x02u},\r
+ {0x16u, 0x08u},\r
+ {0x17u, 0x08u},\r
+ {0x18u, 0x02u},\r
+ {0x1Eu, 0x40u},\r
+ {0x20u, 0x80u},\r
+ {0x21u, 0x08u},\r
+ {0x23u, 0x04u},\r
+ {0x24u, 0x04u},\r
+ {0x25u, 0x10u},\r
+ {0x26u, 0x85u},\r
+ {0x2Au, 0x01u},\r
+ {0x2Bu, 0x02u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Fu, 0x60u},\r
+ {0x30u, 0x01u},\r
+ {0x32u, 0x24u},\r
+ {0x36u, 0x15u},\r
+ {0x38u, 0x04u},\r
+ {0x39u, 0x14u},\r
+ {0x3Du, 0x20u},\r
+ {0x3Fu, 0x8Au},\r
+ {0x5Au, 0x80u},\r
+ {0x5Eu, 0x80u},\r
+ {0x63u, 0x02u},\r
+ {0x64u, 0x02u},\r
+ {0x6Du, 0x80u},\r
+ {0x6Fu, 0x03u},\r
+ {0x82u, 0x22u},\r
+ {0x85u, 0x0Cu},\r
+ {0x8Au, 0x40u},\r
+ {0x8Bu, 0x81u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Du, 0x04u},\r
+ {0x90u, 0x20u},\r
+ {0x92u, 0x18u},\r
+ {0x93u, 0xA0u},\r
+ {0x95u, 0x01u},\r
+ {0x97u, 0x44u},\r
+ {0x98u, 0x41u},\r
+ {0x9Au, 0x28u},\r
+ {0x9Bu, 0x18u},\r
+ {0x9Du, 0x25u},\r
+ {0x9Eu, 0x10u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA0u, 0x08u},\r
+ {0xA2u, 0x10u},\r
+ {0xA3u, 0x40u},\r
+ {0xA4u, 0x65u},\r
+ {0xA6u, 0x84u},\r
+ {0xA8u, 0x40u},\r
+ {0xAAu, 0x40u},\r
+ {0xACu, 0x01u},\r
+ {0xAFu, 0x10u},\r
+ {0xB0u, 0x05u},\r
+ {0xB7u, 0x02u},\r
+ {0xC0u, 0xEFu},\r
+ {0xC2u, 0xFEu},\r
+ {0xC4u, 0x6Bu},\r
+ {0xCAu, 0xE9u},\r
+ {0xCCu, 0xE7u},\r
+ {0xCEu, 0xF6u},\r
+ {0xD6u, 0x18u},\r
+ {0xD8u, 0x18u},\r
+ {0xE0u, 0x02u},\r
+ {0xE2u, 0xC0u},\r
+ {0xE6u, 0x60u},\r
+ {0xEAu, 0xACu},\r
+ {0xEEu, 0x05u},\r
+ {0x01u, 0x02u},\r
+ {0x02u, 0x02u},\r
+ {0x03u, 0x01u},\r
+ {0x0Cu, 0x01u},\r
+ {0x0Eu, 0x02u},\r
+ {0x10u, 0x90u},\r
+ {0x12u, 0x48u},\r
+ {0x15u, 0x02u},\r
+ {0x16u, 0x61u},\r
+ {0x17u, 0x09u},\r
+ {0x19u, 0x01u},\r
+ {0x1Au, 0x0Cu},\r
{0x1Bu, 0x02u},\r
- {0x21u, 0x48u},\r
- {0x23u, 0x10u},\r
- {0x28u, 0x01u},\r
- {0x29u, 0x50u},\r
- {0x2Bu, 0x28u},\r
- {0x2Fu, 0x40u},\r
- {0x30u, 0x02u},\r
- {0x31u, 0x06u},\r
- {0x33u, 0x80u},\r
- {0x34u, 0x01u},\r
- {0x35u, 0x78u},\r
- {0x37u, 0x01u},\r
- {0x3Bu, 0x02u},\r
+ {0x1Du, 0x02u},\r
+ {0x1Eu, 0x10u},\r
+ {0x1Fu, 0x11u},\r
+ {0x22u, 0x80u},\r
+ {0x24u, 0x90u},\r
+ {0x26u, 0x24u},\r
+ {0x2Au, 0x90u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Fu, 0x05u},\r
+ {0x30u, 0x03u},\r
+ {0x31u, 0x10u},\r
+ {0x32u, 0xE0u},\r
+ {0x33u, 0x04u},\r
+ {0x34u, 0x1Cu},\r
+ {0x35u, 0x03u},\r
+ {0x37u, 0x08u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Eu, 0x01u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x19u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0xFFu},\r
- {0x84u, 0x03u},\r
- {0x85u, 0x04u},\r
- {0x86u, 0x0Cu},\r
- {0x87u, 0x12u},\r
- {0x88u, 0x50u},\r
- {0x89u, 0x04u},\r
- {0x8Au, 0xA0u},\r
- {0x8Bu, 0x02u},\r
- {0x8Du, 0x02u},\r
- {0x8Fu, 0x04u},\r
- {0x90u, 0x60u},\r
- {0x92u, 0x90u},\r
- {0x95u, 0x01u},\r
- {0x96u, 0xFFu},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0xFFu},\r
- {0x9Bu, 0x0Au},\r
- {0x9Du, 0x01u},\r
- {0xA0u, 0x05u},\r
- {0xA1u, 0x01u},\r
- {0xA2u, 0x0Au},\r
- {0xA4u, 0x30u},\r
- {0xA6u, 0xC0u},\r
- {0xA8u, 0x06u},\r
- {0xA9u, 0x01u},\r
- {0xAAu, 0x09u},\r
- {0xACu, 0x0Fu},\r
- {0xADu, 0x04u},\r
- {0xAEu, 0xF0u},\r
- {0xAFu, 0x02u},\r
+ {0x80u, 0x30u},\r
+ {0x82u, 0xC0u},\r
+ {0x84u, 0x50u},\r
+ {0x86u, 0xA0u},\r
+ {0x87u, 0x08u},\r
+ {0x88u, 0x60u},\r
+ {0x8Au, 0x90u},\r
+ {0x8Cu, 0x0Fu},\r
+ {0x8Eu, 0xF0u},\r
+ {0x8Fu, 0x01u},\r
+ {0x91u, 0x0Au},\r
+ {0x93u, 0x14u},\r
+ {0x97u, 0x04u},\r
+ {0x98u, 0x06u},\r
+ {0x9Au, 0x09u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Fu, 0x20u},\r
+ {0xA4u, 0x05u},\r
+ {0xA6u, 0x0Au},\r
+ {0xABu, 0x10u},\r
+ {0xACu, 0x03u},\r
+ {0xAEu, 0x0Cu},\r
{0xB1u, 0x06u},\r
- {0xB3u, 0x08u},\r
+ {0xB3u, 0x01u},\r
{0xB4u, 0xFFu},\r
- {0xB5u, 0x10u},\r
- {0xB7u, 0x01u},\r
- {0xB9u, 0x80u},\r
- {0xBBu, 0x02u},\r
+ {0xB5u, 0x20u},\r
+ {0xB7u, 0x18u},\r
{0xBEu, 0x10u},\r
- {0xBFu, 0x40u},\r
+ {0xBFu, 0x41u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDCu, 0x10u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x08u},\r
- {0x03u, 0x84u},\r
- {0x0Au, 0x40u},\r
- {0x0Bu, 0x28u},\r
- {0x0Fu, 0x40u},\r
- {0x10u, 0x20u},\r
- {0x11u, 0x01u},\r
- {0x12u, 0x06u},\r
- {0x17u, 0x20u},\r
- {0x19u, 0x10u},\r
- {0x1Du, 0x01u},\r
- {0x1Eu, 0x04u},\r
- {0x21u, 0xA0u},\r
- {0x23u, 0x50u},\r
- {0x24u, 0x44u},\r
- {0x25u, 0x08u},\r
- {0x26u, 0x20u},\r
- {0x27u, 0x11u},\r
+ {0x01u, 0x01u},\r
+ {0x03u, 0x01u},\r
+ {0x05u, 0x2Bu},\r
+ {0x06u, 0x10u},\r
+ {0x07u, 0x01u},\r
+ {0x09u, 0x40u},\r
+ {0x0Au, 0x14u},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Fu, 0x08u},\r
+ {0x10u, 0x28u},\r
+ {0x11u, 0x02u},\r
+ {0x14u, 0x20u},\r
+ {0x15u, 0x48u},\r
+ {0x1Au, 0x1Cu},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Fu, 0x10u},\r
+ {0x21u, 0x29u},\r
+ {0x22u, 0x40u},\r
+ {0x24u, 0x02u},\r
+ {0x26u, 0x11u},\r
+ {0x27u, 0x10u},\r
{0x28u, 0x02u},\r
- {0x29u, 0x12u},\r
- {0x2Cu, 0x01u},\r
- {0x2Eu, 0x21u},\r
- {0x31u, 0x20u},\r
- {0x32u, 0x84u},\r
- {0x36u, 0x08u},\r
- {0x37u, 0x11u},\r
- {0x3Bu, 0x54u},\r
- {0x3Cu, 0x44u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x02u},\r
- {0x58u, 0x40u},\r
- {0x5Cu, 0x50u},\r
- {0x5Du, 0x04u},\r
- {0x5Fu, 0x01u},\r
- {0x63u, 0x02u},\r
- {0x67u, 0x02u},\r
+ {0x2Du, 0x20u},\r
+ {0x31u, 0x28u},\r
+ {0x32u, 0x40u},\r
+ {0x34u, 0x20u},\r
+ {0x35u, 0x08u},\r
+ {0x36u, 0x80u},\r
+ {0x37u, 0x01u},\r
+ {0x39u, 0x02u},\r
+ {0x3Fu, 0x48u},\r
+ {0x5Au, 0x40u},\r
+ {0x5Cu, 0x44u},\r
+ {0x5Fu, 0x12u},\r
+ {0x60u, 0x02u},\r
+ {0x64u, 0x40u},\r
+ {0x66u, 0x2Au},\r
+ {0x67u, 0x0Au},\r
{0x80u, 0x08u},\r
- {0x81u, 0x80u},\r
- {0x84u, 0x40u},\r
+ {0x82u, 0x02u},\r
{0x86u, 0x08u},\r
- {0x8Au, 0x05u},\r
- {0x8Bu, 0x08u},\r
- {0x8Eu, 0x20u},\r
- {0x92u, 0x18u},\r
- {0x93u, 0x20u},\r
- {0x95u, 0x82u},\r
- {0x96u, 0x40u},\r
- {0x98u, 0x05u},\r
- {0x9Au, 0x04u},\r
- {0x9Bu, 0x20u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x28u},\r
- {0x9Fu, 0x0Cu},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0x08u},\r
- {0xA4u, 0x28u},\r
- {0xA5u, 0x08u},\r
- {0xA7u, 0x82u},\r
- {0xABu, 0x10u},\r
- {0xACu, 0x4Du},\r
- {0xAFu, 0x40u},\r
- {0xB5u, 0x60u},\r
- {0xB7u, 0x04u},\r
- {0xC0u, 0x0Eu},\r
- {0xC2u, 0x1Eu},\r
- {0xC4u, 0x4Fu},\r
- {0xCAu, 0xBDu},\r
- {0xCCu, 0xEEu},\r
- {0xCEu, 0xFEu},\r
+ {0x87u, 0x04u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Fu, 0x03u},\r
+ {0x90u, 0x24u},\r
+ {0x91u, 0x48u},\r
+ {0x93u, 0x80u},\r
+ {0x94u, 0x02u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Du, 0x06u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA1u, 0x41u},\r
+ {0xA3u, 0x44u},\r
+ {0xA4u, 0x40u},\r
+ {0xA5u, 0x20u},\r
+ {0xA6u, 0x05u},\r
+ {0xADu, 0x04u},\r
+ {0xAFu, 0x01u},\r
+ {0xC0u, 0xF9u},\r
+ {0xC2u, 0x4Fu},\r
+ {0xC4u, 0xAEu},\r
+ {0xCAu, 0x28u},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0x51u},\r
{0xD6u, 0xF8u},\r
- {0xD8u, 0x18u},\r
+ {0xD8u, 0xF8u},\r
+ {0xE2u, 0x40u},\r
+ {0xEAu, 0x01u},\r
+ {0xEEu, 0x8Du},\r
+ {0x80u, 0x04u},\r
+ {0x81u, 0x04u},\r
+ {0x82u, 0x04u},\r
+ {0x85u, 0x22u},\r
+ {0x88u, 0x40u},\r
+ {0x8Bu, 0x48u},\r
+ {0x8Du, 0x40u},\r
+ {0x90u, 0x20u},\r
+ {0x94u, 0x02u},\r
+ {0xA1u, 0x41u},\r
+ {0xA3u, 0x44u},\r
+ {0xA6u, 0x01u},\r
+ {0xB7u, 0x44u},\r
+ {0xE0u, 0x40u},\r
+ {0xE2u, 0x04u},\r
+ {0xE4u, 0x80u},\r
+ {0xE8u, 0x40u},\r
+ {0xECu, 0x40u},\r
+ {0xEEu, 0x80u},\r
+ {0x80u, 0x11u},\r
+ {0x81u, 0x01u},\r
+ {0x89u, 0x40u},\r
+ {0x8Eu, 0x01u},\r
{0xE2u, 0x10u},\r
- {0xE4u, 0xC0u},\r
- {0xE6u, 0x38u},\r
- {0xE8u, 0x50u},\r
+ {0xE4u, 0x20u},\r
+ {0x82u, 0x02u},\r
+ {0x83u, 0x07u},\r
+ {0x88u, 0x11u},\r
+ {0x8Au, 0x22u},\r
+ {0x8Cu, 0x28u},\r
+ {0x8Eu, 0x13u},\r
+ {0x91u, 0x34u},\r
+ {0x95u, 0x07u},\r
+ {0x96u, 0x01u},\r
+ {0x98u, 0x60u},\r
+ {0x9Bu, 0x2Au},\r
+ {0x9Eu, 0x0Cu},\r
+ {0x9Fu, 0x08u},\r
+ {0xA4u, 0x14u},\r
+ {0xA6u, 0x43u},\r
+ {0xA9u, 0x01u},\r
+ {0xABu, 0x18u},\r
+ {0xB1u, 0x38u},\r
+ {0xB4u, 0x70u},\r
+ {0xB6u, 0x0Fu},\r
+ {0xB7u, 0x07u},\r
+ {0xB8u, 0x20u},\r
+ {0xBFu, 0x40u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x01u},\r
+ {0x03u, 0x01u},\r
+ {0x04u, 0x40u},\r
+ {0x05u, 0x20u},\r
+ {0x06u, 0x40u},\r
+ {0x09u, 0x80u},\r
+ {0x0Au, 0x94u},\r
+ {0x0Eu, 0x2Au},\r
+ {0x0Fu, 0x01u},\r
+ {0x11u, 0x10u},\r
+ {0x12u, 0x21u},\r
+ {0x13u, 0x08u},\r
+ {0x17u, 0x08u},\r
+ {0x18u, 0x44u},\r
+ {0x19u, 0x29u},\r
+ {0x1Au, 0x90u},\r
+ {0x1Bu, 0x04u},\r
+ {0x1Eu, 0x0Au},\r
+ {0x22u, 0x02u},\r
+ {0x27u, 0x82u},\r
+ {0x29u, 0x29u},\r
+ {0x2Au, 0x40u},\r
+ {0x2Du, 0x20u},\r
+ {0x31u, 0x10u},\r
+ {0x32u, 0x20u},\r
+ {0x33u, 0x49u},\r
+ {0x35u, 0x01u},\r
+ {0x36u, 0x24u},\r
+ {0x37u, 0x80u},\r
+ {0x38u, 0x80u},\r
+ {0x39u, 0x18u},\r
+ {0x3Fu, 0x01u},\r
+ {0x40u, 0x64u},\r
+ {0x49u, 0x14u},\r
+ {0x4Bu, 0x40u},\r
+ {0x50u, 0x20u},\r
+ {0x52u, 0x41u},\r
+ {0x53u, 0x06u},\r
+ {0x63u, 0x80u},\r
+ {0x69u, 0x19u},\r
+ {0x6Au, 0x04u},\r
+ {0x6Bu, 0x61u},\r
+ {0x70u, 0x40u},\r
+ {0x71u, 0x80u},\r
+ {0x80u, 0x20u},\r
+ {0x87u, 0x02u},\r
+ {0x8Bu, 0x80u},\r
+ {0x93u, 0x40u},\r
+ {0x94u, 0x84u},\r
+ {0x95u, 0x19u},\r
+ {0x96u, 0x90u},\r
+ {0x97u, 0x08u},\r
+ {0x9Du, 0x05u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x61u},\r
+ {0xA2u, 0x30u},\r
+ {0xA3u, 0x48u},\r
+ {0xA4u, 0x20u},\r
+ {0xA5u, 0x80u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x06u},\r
+ {0xA8u, 0x08u},\r
+ {0xAEu, 0x60u},\r
+ {0xB1u, 0x04u},\r
+ {0xB2u, 0x08u},\r
+ {0xB3u, 0x20u},\r
+ {0xB4u, 0x01u},\r
+ {0xC0u, 0xDDu},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0x27u},\r
+ {0xCAu, 0x2Fu},\r
+ {0xCCu, 0xFFu},\r
+ {0xCEu, 0x8Eu},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x0Cu},\r
+ {0xD8u, 0x01u},\r
+ {0xE6u, 0x20u},\r
+ {0xEAu, 0x09u},\r
+ {0xEEu, 0x02u},\r
{0x01u, 0x05u},\r
- {0x02u, 0xFFu},\r
- {0x03u, 0x0Au},\r
- {0x05u, 0x03u},\r
- {0x07u, 0x0Cu},\r
- {0x08u, 0x50u},\r
- {0x0Au, 0xA0u},\r
- {0x0Bu, 0xFFu},\r
- {0x0Cu, 0xFFu},\r
- {0x0Du, 0x0Fu},\r
- {0x0Fu, 0xF0u},\r
- {0x10u, 0x60u},\r
- {0x11u, 0x90u},\r
- {0x12u, 0x90u},\r
- {0x13u, 0x60u},\r
- {0x15u, 0x50u},\r
- {0x16u, 0xFFu},\r
- {0x17u, 0xA0u},\r
- {0x18u, 0x30u},\r
- {0x19u, 0x30u},\r
- {0x1Au, 0xC0u},\r
- {0x1Bu, 0xC0u},\r
- {0x20u, 0x0Fu},\r
- {0x22u, 0xF0u},\r
- {0x23u, 0xFFu},\r
- {0x24u, 0x03u},\r
- {0x25u, 0x09u},\r
- {0x26u, 0x0Cu},\r
- {0x27u, 0x06u},\r
- {0x28u, 0x06u},\r
- {0x2Au, 0x09u},\r
- {0x2Bu, 0xFFu},\r
- {0x2Cu, 0x05u},\r
- {0x2Eu, 0x0Au},\r
- {0x34u, 0xFFu},\r
- {0x37u, 0xFFu},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x40u},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0x0Fu},\r
+ {0x06u, 0xF0u},\r
+ {0x07u, 0x01u},\r
+ {0x08u, 0x60u},\r
+ {0x0Au, 0x90u},\r
+ {0x0Cu, 0x05u},\r
+ {0x0Eu, 0x0Au},\r
+ {0x0Fu, 0x08u},\r
+ {0x10u, 0x50u},\r
+ {0x12u, 0xA0u},\r
+ {0x14u, 0x30u},\r
+ {0x15u, 0x01u},\r
+ {0x16u, 0xC0u},\r
+ {0x17u, 0x08u},\r
+ {0x18u, 0x03u},\r
+ {0x1Au, 0x0Cu},\r
+ {0x1Eu, 0xFFu},\r
+ {0x20u, 0x06u},\r
+ {0x21u, 0x04u},\r
+ {0x22u, 0x09u},\r
+ {0x23u, 0x08u},\r
+ {0x26u, 0xFFu},\r
+ {0x28u, 0xFFu},\r
+ {0x2Du, 0x02u},\r
+ {0x31u, 0x0Fu},\r
+ {0x33u, 0x0Fu},\r
+ {0x36u, 0xFFu},\r
+ {0x39u, 0x0Au},\r
+ {0x3Eu, 0x40u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
+ {0x5Cu, 0x10u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x02u},\r
- {0x83u, 0x05u},\r
- {0x84u, 0x1Au},\r
- {0x86u, 0x05u},\r
- {0x89u, 0x02u},\r
- {0x8Au, 0x08u},\r
- {0x8Bu, 0x01u},\r
- {0x8Eu, 0x40u},\r
- {0x91u, 0x02u},\r
- {0x93u, 0x01u},\r
- {0x96u, 0x20u},\r
- {0x99u, 0x01u},\r
- {0x9Au, 0x07u},\r
- {0x9Bu, 0x02u},\r
- {0x9Eu, 0x10u},\r
- {0xA1u, 0x02u},\r
- {0xA3u, 0x09u},\r
- {0xA4u, 0x19u},\r
- {0xA6u, 0x02u},\r
- {0xA8u, 0x14u},\r
- {0xAAu, 0x08u},\r
- {0xB0u, 0x10u},\r
- {0xB2u, 0x20u},\r
- {0xB3u, 0x03u},\r
- {0xB4u, 0x0Fu},\r
- {0xB5u, 0x08u},\r
- {0xB6u, 0x40u},\r
- {0xB7u, 0x04u},\r
- {0xBBu, 0x08u},\r
- {0xBEu, 0x01u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
- {0xDFu, 0x01u},\r
- {0x01u, 0x40u},\r
- {0x03u, 0x84u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x20u},\r
- {0x07u, 0x01u},\r
- {0x08u, 0x10u},\r
- {0x0Au, 0x40u},\r
- {0x0Bu, 0x20u},\r
- {0x0Cu, 0x40u},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x08u},\r
- {0x12u, 0x45u},\r
- {0x13u, 0x04u},\r
- {0x17u, 0x18u},\r
- {0x1Au, 0x08u},\r
- {0x1Eu, 0x18u},\r
- {0x1Fu, 0x61u},\r
- {0x22u, 0x80u},\r
- {0x25u, 0x10u},\r
- {0x27u, 0x21u},\r
- {0x2Au, 0x04u},\r
- {0x2Bu, 0xA4u},\r
- {0x2Fu, 0x40u},\r
- {0x30u, 0x38u},\r
- {0x33u, 0x02u},\r
- {0x37u, 0x21u},\r
- {0x39u, 0x82u},\r
- {0x3Au, 0x49u},\r
- {0x3Bu, 0x24u},\r
- {0x3Du, 0x20u},\r
- {0x3Fu, 0x01u},\r
- {0x44u, 0x02u},\r
- {0x45u, 0x40u},\r
- {0x5Au, 0x80u},\r
- {0x5Cu, 0x0Au},\r
- {0x5Du, 0x20u},\r
- {0x5Fu, 0x40u},\r
- {0x63u, 0x01u},\r
- {0x67u, 0x02u},\r
- {0x82u, 0x40u},\r
- {0x87u, 0x10u},\r
- {0x89u, 0x40u},\r
- {0x8Bu, 0x08u},\r
- {0x8Du, 0x11u},\r
- {0xC0u, 0xEBu},\r
- {0xC2u, 0xEEu},\r
- {0xC4u, 0x6Fu},\r
- {0xCAu, 0x87u},\r
- {0xCCu, 0xA7u},\r
- {0xCEu, 0xAFu},\r
- {0xD6u, 0xF8u},\r
- {0xD8u, 0x18u},\r
- {0xE0u, 0x60u},\r
- {0xE2u, 0x01u},\r
- {0xE4u, 0x20u},\r
- {0xE6u, 0x41u},\r
- {0x00u, 0x03u},\r
- {0x02u, 0x0Cu},\r
- {0x04u, 0x20u},\r
- {0x06u, 0x4Fu},\r
- {0x0Cu, 0x40u},\r
- {0x0Eu, 0x1Fu},\r
- {0x10u, 0x06u},\r
- {0x12u, 0x09u},\r
- {0x16u, 0x70u},\r
- {0x1Eu, 0x80u},\r
- {0x24u, 0x0Fu},\r
- {0x28u, 0x10u},\r
- {0x2Au, 0x2Fu},\r
- {0x2Cu, 0x05u},\r
- {0x2Eu, 0x0Au},\r
- {0x30u, 0x80u},\r
- {0x32u, 0x7Fu},\r
- {0x40u, 0x26u},\r
- {0x41u, 0x04u},\r
- {0x42u, 0x30u},\r
- {0x44u, 0x05u},\r
- {0x45u, 0xCEu},\r
- {0x46u, 0xF0u},\r
- {0x47u, 0xDBu},\r
- {0x48u, 0x3Bu},\r
- {0x49u, 0xFFu},\r
- {0x4Au, 0xFFu},\r
- {0x4Bu, 0xFFu},\r
- {0x4Cu, 0x22u},\r
- {0x4Eu, 0xF0u},\r
- {0x4Fu, 0x08u},\r
- {0x50u, 0x04u},\r
- {0x58u, 0x04u},\r
- {0x5Au, 0x04u},\r
- {0x5Cu, 0x01u},\r
- {0x5Fu, 0x01u},\r
- {0x62u, 0xC0u},\r
- {0x64u, 0x40u},\r
- {0x65u, 0x01u},\r
- {0x66u, 0x10u},\r
- {0x67u, 0x11u},\r
- {0x68u, 0xC0u},\r
- {0x69u, 0x01u},\r
- {0x6Bu, 0x11u},\r
- {0x6Cu, 0x40u},\r
- {0x6Du, 0x01u},\r
- {0x6Eu, 0x40u},\r
- {0x6Fu, 0x01u},\r
- {0x80u, 0x40u},\r
- {0x84u, 0x88u},\r
- {0x86u, 0x21u},\r
- {0x87u, 0xFFu},\r
- {0x88u, 0x01u},\r
- {0x89u, 0x80u},\r
+ {0x80u, 0x10u},\r
+ {0x84u, 0x87u},\r
+ {0x85u, 0x03u},\r
+ {0x86u, 0x18u},\r
+ {0x88u, 0x04u},\r
+ {0x89u, 0x03u},\r
{0x8Cu, 0x01u},\r
- {0x8Du, 0x1Fu},\r
- {0x8Fu, 0x20u},\r
- {0x90u, 0x87u},\r
- {0x91u, 0xC0u},\r
- {0x92u, 0x18u},\r
- {0x93u, 0x01u},\r
+ {0x8Du, 0x03u},\r
+ {0x90u, 0xA2u},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0x03u},\r
{0x94u, 0x01u},\r
- {0x97u, 0x9Fu},\r
- {0x98u, 0xA2u},\r
- {0x99u, 0x7Fu},\r
- {0x9Au, 0x08u},\r
- {0x9Bu, 0x80u},\r
- {0x9Cu, 0x04u},\r
- {0x9Du, 0xC0u},\r
- {0x9Fu, 0x02u},\r
+ {0x97u, 0x04u},\r
+ {0x98u, 0x40u},\r
+ {0x9Bu, 0x01u},\r
+ {0x9Cu, 0x01u},\r
+ {0x9Du, 0x03u},\r
{0xA0u, 0x01u},\r
- {0xA3u, 0x60u},\r
- {0xA4u, 0x10u},\r
- {0xA5u, 0xC0u},\r
- {0xA7u, 0x04u},\r
- {0xA8u, 0x40u},\r
- {0xA9u, 0xC0u},\r
+ {0xA4u, 0x88u},\r
+ {0xA6u, 0x21u},\r
+ {0xA8u, 0x01u},\r
{0xABu, 0x08u},\r
- {0xACu, 0x01u},\r
- {0xADu, 0x90u},\r
- {0xAFu, 0x40u},\r
- {0xB0u, 0x3Fu},\r
- {0xB2u, 0x80u},\r
- {0xB3u, 0xFFu},\r
- {0xB6u, 0x40u},\r
- {0xB8u, 0x82u},\r
- {0xBEu, 0x05u},\r
- {0xBFu, 0x04u},\r
+ {0xACu, 0x40u},\r
+ {0xB0u, 0x80u},\r
+ {0xB1u, 0x02u},\r
+ {0xB2u, 0x40u},\r
+ {0xB3u, 0x08u},\r
+ {0xB4u, 0x3Fu},\r
+ {0xB5u, 0x04u},\r
+ {0xB6u, 0x08u},\r
+ {0xB7u, 0x01u},\r
+ {0xB8u, 0x28u},\r
+ {0xBEu, 0x51u},\r
+ {0xBFu, 0x41u},\r
{0xD4u, 0x09u},\r
{0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x02u},\r
- {0x01u, 0x80u},\r
- {0x03u, 0x10u},\r
- {0x04u, 0x24u},\r
- {0x05u, 0x01u},\r
- {0x07u, 0x01u},\r
- {0x08u, 0x80u},\r
- {0x0Au, 0xA0u},\r
- {0x0Du, 0x0Au},\r
- {0x0Eu, 0x09u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x02u},\r
- {0x13u, 0x10u},\r
- {0x15u, 0x08u},\r
- {0x17u, 0x62u},\r
- {0x18u, 0x80u},\r
- {0x19u, 0x08u},\r
- {0x1Au, 0x20u},\r
- {0x1Du, 0x05u},\r
- {0x1Eu, 0x01u},\r
- {0x27u, 0x20u},\r
- {0x2Cu, 0x08u},\r
- {0x2Eu, 0x41u},\r
- {0x2Fu, 0x20u},\r
- {0x35u, 0x10u},\r
- {0x36u, 0x08u},\r
- {0x37u, 0x42u},\r
- {0x3Cu, 0xA4u},\r
- {0x40u, 0x04u},\r
- {0x41u, 0x02u},\r
- {0x43u, 0x08u},\r
- {0x48u, 0x82u},\r
- {0x49u, 0x12u},\r
- {0x4Bu, 0x04u},\r
- {0x51u, 0x04u},\r
- {0x52u, 0x18u},\r
- {0x53u, 0x01u},\r
- {0x5Du, 0x10u},\r
- {0x5Eu, 0x82u},\r
- {0x5Fu, 0x04u},\r
- {0x64u, 0x02u},\r
- {0x67u, 0x40u},\r
- {0x80u, 0x40u},\r
- {0x84u, 0x02u},\r
- {0x85u, 0x48u},\r
- {0x89u, 0x12u},\r
- {0x8Bu, 0x40u},\r
- {0x8Cu, 0x02u},\r
- {0x8Du, 0x04u},\r
- {0x90u, 0x24u},\r
- {0x91u, 0x04u},\r
- {0x92u, 0xC0u},\r
- {0x93u, 0x10u},\r
- {0x95u, 0x08u},\r
- {0x97u, 0x02u},\r
- {0x98u, 0x80u},\r
- {0x99u, 0x90u},\r
- {0x9Bu, 0x53u},\r
- {0x9Du, 0x40u},\r
- {0x9Eu, 0x10u},\r
- {0xA0u, 0x59u},\r
- {0xA1u, 0x0Au},\r
- {0xA2u, 0x47u},\r
- {0xA3u, 0x28u},\r
- {0xA4u, 0x80u},\r
- {0xA8u, 0x80u},\r
- {0xABu, 0x01u},\r
- {0xAEu, 0x10u},\r
- {0xB3u, 0x10u},\r
- {0xB5u, 0x10u},\r
- {0xC0u, 0xFDu},\r
- {0xC2u, 0xFDu},\r
- {0xC4u, 0xF7u},\r
- {0xCAu, 0xF0u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0x70u},\r
- {0xD0u, 0x07u},\r
- {0xD2u, 0x0Cu},\r
- {0xD6u, 0xF0u},\r
- {0xD8u, 0x90u},\r
- {0xE0u, 0x01u},\r
- {0xE2u, 0x20u},\r
- {0xEAu, 0x01u},\r
- {0xECu, 0x08u},\r
- {0xEEu, 0x01u},\r
- {0x00u, 0x6Cu},\r
- {0x01u, 0xD6u},\r
- {0x04u, 0x40u},\r
- {0x05u, 0x29u},\r
- {0x06u, 0x2Cu},\r
- {0x07u, 0x46u},\r
- {0x08u, 0x64u},\r
- {0x09u, 0x02u},\r
- {0x0Au, 0x08u},\r
- {0x0Cu, 0x2Cu},\r
- {0x0Du, 0xD6u},\r
- {0x0Eu, 0x40u},\r
- {0x10u, 0x71u},\r
- {0x12u, 0x82u},\r
- {0x14u, 0xA4u},\r
- {0x15u, 0x21u},\r
- {0x16u, 0x40u},\r
- {0x17u, 0x8Eu},\r
- {0x18u, 0xC0u},\r
- {0x19u, 0x20u},\r
- {0x1Au, 0x2Fu},\r
- {0x1Bu, 0xD0u},\r
- {0x1Cu, 0x08u},\r
- {0x1Du, 0xD6u},\r
- {0x1Eu, 0x10u},\r
- {0x20u, 0x6Cu},\r
- {0x21u, 0x04u},\r
- {0x24u, 0x91u},\r
- {0x25u, 0xD2u},\r
- {0x26u, 0x4Eu},\r
- {0x27u, 0x04u},\r
- {0x29u, 0xD0u},\r
- {0x2Bu, 0x06u},\r
- {0x2Du, 0x17u},\r
- {0x2Fu, 0x28u},\r
- {0x30u, 0x0Fu},\r
- {0x32u, 0xC0u},\r
- {0x33u, 0xF0u},\r
- {0x34u, 0x31u},\r
- {0x35u, 0x0Fu},\r
- {0x37u, 0x08u},\r
- {0x39u, 0x20u},\r
- {0x3Au, 0x38u},\r
- {0x3Bu, 0x08u},\r
- {0x3Fu, 0x40u},\r
- {0x56u, 0x02u},\r
- {0x57u, 0x24u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Fu, 0x01u},\r
- {0x80u, 0x06u},\r
- {0x82u, 0x09u},\r
- {0x87u, 0x01u},\r
- {0x88u, 0x60u},\r
- {0x89u, 0x95u},\r
- {0x8Au, 0x90u},\r
- {0x8Bu, 0x28u},\r
- {0x8Cu, 0x30u},\r
- {0x8Du, 0x02u},\r
- {0x8Eu, 0xC0u},\r
- {0x90u, 0x05u},\r
- {0x92u, 0x0Au},\r
- {0x97u, 0x08u},\r
- {0x98u, 0x03u},\r
- {0x99u, 0xA4u},\r
- {0x9Au, 0x0Cu},\r
- {0x9Bu, 0x58u},\r
- {0x9Cu, 0x0Fu},\r
- {0x9Eu, 0xF0u},\r
- {0x9Fu, 0x70u},\r
- {0xA0u, 0x50u},\r
- {0xA2u, 0xA0u},\r
- {0xA7u, 0x80u},\r
- {0xADu, 0x41u},\r
- {0xAFu, 0x88u},\r
- {0xB0u, 0xFFu},\r
- {0xB3u, 0x0Fu},\r
- {0xB7u, 0xF0u},\r
- {0xB9u, 0x08u},\r
- {0xBEu, 0x01u},\r
- {0xD4u, 0x01u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
{0xDCu, 0x10u},\r
- {0xDDu, 0x10u},\r
- {0xDFu, 0x01u},\r
- {0x02u, 0x89u},\r
- {0x04u, 0x28u},\r
- {0x07u, 0x41u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x04u},\r
- {0x0Bu, 0x01u},\r
- {0x0Cu, 0x80u},\r
- {0x0Du, 0x0Au},\r
- {0x0Eu, 0x08u},\r
- {0x11u, 0x01u},\r
- {0x17u, 0x0Au},\r
- {0x19u, 0x02u},\r
- {0x1Cu, 0xE0u},\r
- {0x1Du, 0x1Au},\r
- {0x1Eu, 0x08u},\r
- {0x1Fu, 0x02u},\r
- {0x22u, 0x80u},\r
- {0x23u, 0x10u},\r
- {0x24u, 0x04u},\r
- {0x26u, 0x50u},\r
- {0x27u, 0x28u},\r
- {0x28u, 0x10u},\r
- {0x29u, 0x80u},\r
- {0x2Cu, 0x88u},\r
- {0x2Fu, 0x22u},\r
- {0x32u, 0x84u},\r
- {0x33u, 0x10u},\r
- {0x36u, 0x04u},\r
- {0x37u, 0x60u},\r
- {0x39u, 0x84u},\r
- {0x3Bu, 0x10u},\r
- {0x3Cu, 0x24u},\r
- {0x3Eu, 0x42u},\r
- {0x59u, 0x40u},\r
- {0x64u, 0x08u},\r
- {0x6Cu, 0x5Cu},\r
- {0x6Eu, 0x40u},\r
- {0x6Fu, 0x61u},\r
- {0x76u, 0x02u},\r
- {0x77u, 0x02u},\r
- {0x86u, 0x88u},\r
- {0x88u, 0x40u},\r
- {0x91u, 0x85u},\r
- {0x92u, 0x8Cu},\r
- {0x94u, 0xECu},\r
- {0x95u, 0x08u},\r
- {0x96u, 0x40u},\r
- {0x97u, 0x12u},\r
- {0x98u, 0x18u},\r
- {0x99u, 0x80u},\r
- {0x9Au, 0x01u},\r
- {0x9Bu, 0x10u},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0x12u},\r
- {0x9Fu, 0x40u},\r
- {0xA0u, 0x01u},\r
- {0xA1u, 0x01u},\r
- {0xA2u, 0x03u},\r
- {0xA3u, 0x08u},\r
- {0xA4u, 0x08u},\r
- {0xA6u, 0x04u},\r
- {0xA7u, 0x20u},\r
- {0xB1u, 0x80u},\r
- {0xC0u, 0xFBu},\r
- {0xC2u, 0xFBu},\r
- {0xC4u, 0x38u},\r
- {0xCAu, 0xFAu},\r
- {0xCCu, 0x7Eu},\r
- {0xCEu, 0xFEu},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x20u},\r
- {0xE2u, 0x8Au},\r
- {0xE4u, 0x08u},\r
- {0xEAu, 0x02u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x04u},\r
+ {0x02u, 0x40u},\r
+ {0x03u, 0x09u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x14u},\r
+ {0x09u, 0x80u},\r
+ {0x0Au, 0x98u},\r
+ {0x0Cu, 0x40u},\r
+ {0x0Du, 0x11u},\r
+ {0x0Fu, 0x20u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0x22u},\r
+ {0x13u, 0x20u},\r
+ {0x14u, 0x80u},\r
+ {0x15u, 0x04u},\r
+ {0x17u, 0x10u},\r
+ {0x19u, 0x80u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Bu, 0x09u},\r
+ {0x1Eu, 0x01u},\r
+ {0x20u, 0x09u},\r
+ {0x22u, 0x09u},\r
+ {0x23u, 0x40u},\r
+ {0x25u, 0x03u},\r
+ {0x26u, 0x04u},\r
+ {0x28u, 0x02u},\r
+ {0x2Au, 0x20u},\r
+ {0x2Bu, 0x02u},\r
+ {0x2Cu, 0x82u},\r
+ {0x30u, 0x28u},\r
+ {0x32u, 0x10u},\r
+ {0x33u, 0x41u},\r
+ {0x37u, 0x04u},\r
+ {0x38u, 0x80u},\r
+ {0x39u, 0x18u},\r
+ {0x3Au, 0x08u},\r
+ {0x3Du, 0x0Eu},\r
+ {0x3Eu, 0x40u},\r
+ {0x58u, 0x10u},\r
+ {0x59u, 0x84u},\r
+ {0x5Au, 0x02u},\r
+ {0x5Eu, 0x80u},\r
+ {0x62u, 0x01u},\r
+ {0x63u, 0x02u},\r
+ {0x67u, 0x01u},\r
+ {0x84u, 0x12u},\r
+ {0x88u, 0x16u},\r
+ {0x8Bu, 0x0Cu},\r
+ {0x8Eu, 0x10u},\r
+ {0x91u, 0x22u},\r
+ {0x92u, 0x40u},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0x11u},\r
+ {0x96u, 0x81u},\r
+ {0x97u, 0x01u},\r
+ {0x98u, 0xC0u},\r
+ {0x99u, 0x40u},\r
+ {0x9Au, 0x14u},\r
+ {0x9Bu, 0x14u},\r
+ {0x9Du, 0x01u},\r
+ {0x9Eu, 0x49u},\r
+ {0x9Fu, 0x09u},\r
+ {0xA0u, 0x80u},\r
+ {0xA1u, 0x04u},\r
+ {0xA2u, 0x30u},\r
+ {0xA3u, 0x70u},\r
+ {0xA4u, 0x10u},\r
+ {0xA5u, 0x83u},\r
+ {0xA6u, 0x0Cu},\r
+ {0xA7u, 0x06u},\r
+ {0xA8u, 0x22u},\r
+ {0xAAu, 0x40u},\r
+ {0xABu, 0x08u},\r
+ {0xB1u, 0x43u},\r
+ {0xB2u, 0x80u},\r
+ {0xB6u, 0x20u},\r
+ {0xC0u, 0xEFu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0x7Fu},\r
+ {0xCAu, 0x94u},\r
+ {0xCCu, 0x4Fu},\r
+ {0xCEu, 0xDEu},\r
+ {0xD6u, 0x1Fu},\r
+ {0xD8u, 0x19u},\r
+ {0xE6u, 0x44u},\r
+ {0xE8u, 0x04u},\r
+ {0xEAu, 0x03u},\r
{0xEEu, 0x08u},\r
- {0x02u, 0x08u},\r
+ {0x01u, 0x01u},\r
{0x03u, 0x02u},\r
- {0x06u, 0x10u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x28u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x14u},\r
- {0x0Du, 0x01u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x02u},\r
- {0x10u, 0x14u},\r
- {0x12u, 0x28u},\r
- {0x14u, 0x02u},\r
- {0x16u, 0x01u},\r
- {0x17u, 0x20u},\r
- {0x1Bu, 0x1Cu},\r
- {0x1Cu, 0x02u},\r
- {0x1Eu, 0x01u},\r
- {0x1Fu, 0x01u},\r
- {0x20u, 0x02u},\r
+ {0x05u, 0x02u},\r
+ {0x07u, 0x01u},\r
+ {0x08u, 0x08u},\r
+ {0x09u, 0x02u},\r
+ {0x0Au, 0x12u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Cu, 0x1Au},\r
+ {0x0Du, 0x10u},\r
+ {0x0Eu, 0x64u},\r
+ {0x0Fu, 0x08u},\r
+ {0x11u, 0x02u},\r
+ {0x13u, 0x21u},\r
+ {0x14u, 0x10u},\r
+ {0x15u, 0x08u},\r
+ {0x16u, 0x08u},\r
+ {0x17u, 0x10u},\r
+ {0x18u, 0x80u},\r
+ {0x19u, 0x10u},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Cu, 0x20u},\r
+ {0x1Eu, 0x44u},\r
+ {0x20u, 0x40u},\r
{0x21u, 0x10u},\r
- {0x22u, 0x41u},\r
- {0x23u, 0x20u},\r
- {0x24u, 0x02u},\r
- {0x26u, 0x01u},\r
- {0x2Au, 0x04u},\r
- {0x2Bu, 0x40u},\r
- {0x2Du, 0x24u},\r
- {0x2Fu, 0x08u},\r
- {0x30u, 0x0Cu},\r
- {0x32u, 0x03u},\r
- {0x33u, 0x3Cu},\r
- {0x34u, 0x30u},\r
- {0x35u, 0x40u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x03u},\r
- {0x3Au, 0x08u},\r
- {0x3Eu, 0x11u},\r
- {0x3Fu, 0x40u},\r
+ {0x22u, 0x20u},\r
+ {0x23u, 0x0Cu},\r
+ {0x24u, 0x01u},\r
+ {0x25u, 0x10u},\r
+ {0x27u, 0x08u},\r
+ {0x29u, 0x02u},\r
+ {0x2Bu, 0x01u},\r
+ {0x30u, 0x80u},\r
+ {0x31u, 0x03u},\r
+ {0x32u, 0x01u},\r
+ {0x33u, 0x20u},\r
+ {0x34u, 0x06u},\r
+ {0x35u, 0x18u},\r
+ {0x36u, 0x78u},\r
+