Many bug fixes, including selection fixes.
authorMichael McMaster <michael@codesrc.com>
Fri, 14 Feb 2014 20:58:27 +0000 (06:58 +1000)
committerMichael McMaster <michael@codesrc.com>
Fri, 14 Feb 2014 20:58:27 +0000 (06:58 +1000)
- Better selection support for SCSI1 initiators
- Support select-with-atn

25 files changed:
CHANGELOG
readme.txt
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd
software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
software/SCSI2SD/SCSI2SD.cydsn/blinky.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/blinky.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/config.c
software/SCSI2SD/SCSI2SD.cydsn/disk.c
software/SCSI2SD/SCSI2SD.cydsn/inquiry.c
software/SCSI2SD/SCSI2SD.cydsn/main.c
software/SCSI2SD/SCSI2SD.cydsn/mode.c
software/SCSI2SD/SCSI2SD.cydsn/scsi.c
software/SCSI2SD/SCSI2SD.cydsn/scsi.h
software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c
software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v

index b74f36f..5a4eb9f 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,13 @@
+20140214               3.2
+       - Remove hacks around ATN handling, and implement proper select-with-atn
+       support.  This fix is essential for communicating with some SCSI hosts.
+       All SCSI2SD users are urged to upgrade to this firmware version.
+       - More fixes to support Apple HD SC Setup (thanks to Doug Brown!)
+       - Fixes to support SCSI1 initiators
+               * Support non-arbitrating initiators.
+               * Support single-initiator option.
+               * Set CCS response format flag in INQUIRY response.
+
 20131227               3.1
        - Fixes for better SCSI reset handling
        - Fix for reading the last sector of the SD card.
index 0931201..9eea4c0 100644 (file)
@@ -55,6 +55,13 @@ Tested with a 16GB class 10 SD card, via the commands:
 
 Compatibility
 
-Tested with Linux (current), Apple Macintosh System 7.5.3 on LC-III, and LC-475
-hardware. 
+Tested with Linux (current), Apple Macintosh System 7.5.3 on LC-III, and LC-475 hardware.
+
+Users have reported success on these systems:
+
+    Mac II running System 6.0.8
+    Mac SE/30
+    Roland JS-30 Sampler
+    Akai S3200 Sampler
+    EMU Emulator E4X with EOS 3.00b 
 
index bc90348..af7277c 100755 (executable)
 #define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
-/* SCSI_ATN_ISR */\r
-#define SCSI_ATN_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_ATN_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_ATN_ISR__INTC_MASK 0x800u\r
-#define SCSI_ATN_ISR__INTC_NUMBER 11u\r
-#define SCSI_ATN_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_ATN_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_11\r
-#define SCSI_ATN_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_ATN_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
 /* SCSI_Out_DBx */\r
 #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
 #define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX\r
 #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 /* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB07_ST\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_RxStsReg__4__POS 4\r
 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
 #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
 #define SDCard_BSPIM_RxStsReg__6__POS 6\r
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB06_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB06_ST\r
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
 #define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
 #define SDCard_BSPIM_TxStsReg__1__POS 1\r
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_TxStsReg__4__POS 4\r
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
 \r
 /* USBFS_dp_int */\r
 #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 /* SCSI_CTL_IO */\r
 #define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL\r
 #define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
 \r
 /* SCSI_In_DBx */\r
 #define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
 /* scsiTarget */\r
 #define scsiTarget_StatusReg__0__MASK 0x01u\r
 #define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
 #define scsiTarget_StatusReg__1__MASK 0x02u\r
 #define scsiTarget_StatusReg__1__POS 1\r
 #define scsiTarget_StatusReg__2__MASK 0x04u\r
 #define scsiTarget_StatusReg__3__MASK 0x08u\r
 #define scsiTarget_StatusReg__3__POS 3\r
 #define scsiTarget_StatusReg__MASK 0x0Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB00_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB00_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST\r
 #define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
 #define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
 #define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK\r
 /* SD_Clk_Ctl */\r
 #define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
 #define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
 \r
 /* USBFS_ep_0 */\r
 #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define SCSI_ATN__DM2 CYREG_PRT12_DM2\r
 #define SCSI_ATN__DR CYREG_PRT12_DR\r
 #define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_ATN__INTSTAT CYREG_PICU12_INTSTAT\r
 #define SCSI_ATN__INT__MASK 0x20u\r
 #define SCSI_ATN__INT__PC CYREG_PRT12_PC5\r
 #define SCSI_ATN__INT__PORT 12u\r
 #define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
 #define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
 #define SCSI_ATN__SLW CYREG_PRT12_SLW\r
-#define SCSI_ATN__SNAP CYREG_PICU12_SNAP\r
 \r
 /* SCSI_Out */\r
 #define SCSI_Out__0__AG CYREG_PRT4_AG\r
 #define CYDEV_CHIP_FAMILY_PSOC5 3u\r
 #define CYDEV_CHIP_DIE_PSOC5LP 4u\r
 #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP\r
-#define BCLK__BUS_CLK__HZ 64000000U\r
-#define BCLK__BUS_CLK__KHZ 64000U\r
-#define BCLK__BUS_CLK__MHZ 64U\r
+#define BCLK__BUS_CLK__HZ 60000000U\r
+#define BCLK__BUS_CLK__KHZ 60000U\r
+#define BCLK__BUS_CLK__MHZ 60U\r
 #define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT\r
 #define CYDEV_CHIP_DIE_LEOPARD 1u\r
 #define CYDEV_CHIP_DIE_PANTHER 3u\r
index 6c7544e..fae8663 100755 (executable)
@@ -200,7 +200,7 @@ static void ClockSetup(void)
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));\r
 \r
        /* Configure PLL based on settings from Clock DWR */\r
-       CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u);\r
+       CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0919u);\r
        CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);\r
        /* Wait up to 250us for the PLL to lock */\r
        pllLock = 0u;\r
@@ -362,37 +362,37 @@ void cyfitter_cfg(void)
 \r
        {\r
                static const uint32 CYCODE cy_cfg_addr_table[] = {\r
-                       0x40004503u, /* Base address: 0x40004500 Count: 3 */\r
-                       0x40005209u, /* Base address: 0x40005200 Count: 9 */\r
-                       0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
-                       0x40010044u, /* Base address: 0x40010000 Count: 68 */\r
-                       0x40010135u, /* Base address: 0x40010100 Count: 53 */\r
-                       0x4001023Eu, /* Base address: 0x40010200 Count: 62 */\r
-                       0x40010350u, /* Base address: 0x40010300 Count: 80 */\r
-                       0x4001044Bu, /* Base address: 0x40010400 Count: 75 */\r
-                       0x40010554u, /* Base address: 0x40010500 Count: 84 */\r
-                       0x40010605u, /* Base address: 0x40010600 Count: 5 */\r
-                       0x4001074Bu, /* Base address: 0x40010700 Count: 75 */\r
-                       0x40010911u, /* Base address: 0x40010900 Count: 17 */\r
-                       0x40010A37u, /* Base address: 0x40010A00 Count: 55 */\r
-                       0x40010B35u, /* Base address: 0x40010B00 Count: 53 */\r
-                       0x40010D0Fu, /* Base address: 0x40010D00 Count: 15 */\r
-                       0x40010F02u, /* Base address: 0x40010F00 Count: 2 */\r
-                       0x40011504u, /* Base address: 0x40011500 Count: 4 */\r
-                       0x40011642u, /* Base address: 0x40011600 Count: 66 */\r
-                       0x40011747u, /* Base address: 0x40011700 Count: 71 */\r
-                       0x40011908u, /* Base address: 0x40011900 Count: 8 */\r
-                       0x40011B05u, /* Base address: 0x40011B00 Count: 5 */\r
-                       0x4001400Fu, /* Base address: 0x40014000 Count: 15 */\r
-                       0x4001410Du, /* Base address: 0x40014100 Count: 13 */\r
-                       0x40014206u, /* Base address: 0x40014200 Count: 6 */\r
+                       0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
+                       0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
+                       0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
+                       0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
+                       0x40010043u, /* Base address: 0x40010000 Count: 67 */\r
+                       0x40010130u, /* Base address: 0x40010100 Count: 48 */\r
+                       0x4001023Au, /* Base address: 0x40010200 Count: 58 */\r
+                       0x4001034Cu, /* Base address: 0x40010300 Count: 76 */\r
+                       0x40010447u, /* Base address: 0x40010400 Count: 71 */\r
+                       0x4001054Du, /* Base address: 0x40010500 Count: 77 */\r
+                       0x40010649u, /* Base address: 0x40010600 Count: 73 */\r
+                       0x40010746u, /* Base address: 0x40010700 Count: 70 */\r
+                       0x4001090Du, /* Base address: 0x40010900 Count: 13 */\r
+                       0x40010A33u, /* Base address: 0x40010A00 Count: 51 */\r
+                       0x40010B38u, /* Base address: 0x40010B00 Count: 56 */\r
+                       0x40010D06u, /* Base address: 0x40010D00 Count: 6 */\r
+                       0x40010F03u, /* Base address: 0x40010F00 Count: 3 */\r
+                       0x40011503u, /* Base address: 0x40011500 Count: 3 */\r
+                       0x40011736u, /* Base address: 0x40011700 Count: 54 */\r
+                       0x40011902u, /* Base address: 0x40011900 Count: 2 */\r
+                       0x40011B02u, /* Base address: 0x40011B00 Count: 2 */\r
+                       0x4001400Du, /* Base address: 0x40014000 Count: 13 */\r
+                       0x4001410Fu, /* Base address: 0x40014100 Count: 15 */\r
+                       0x4001420Au, /* Base address: 0x40014200 Count: 10 */\r
                        0x40014308u, /* Base address: 0x40014300 Count: 8 */\r
-                       0x4001440Au, /* Base address: 0x40014400 Count: 10 */\r
-                       0x40014514u, /* Base address: 0x40014500 Count: 20 */\r
-                       0x40014609u, /* Base address: 0x40014600 Count: 9 */\r
-                       0x40014709u, /* Base address: 0x40014700 Count: 9 */\r
-                       0x4001480Bu, /* Base address: 0x40014800 Count: 11 */\r
-                       0x40014907u, /* Base address: 0x40014900 Count: 7 */\r
+                       0x4001440Bu, /* Base address: 0x40014400 Count: 11 */\r
+                       0x40014512u, /* Base address: 0x40014500 Count: 18 */\r
+                       0x4001460Cu, /* Base address: 0x40014600 Count: 12 */\r
+                       0x40014706u, /* Base address: 0x40014700 Count: 6 */\r
+                       0x4001480Au, /* Base address: 0x40014800 Count: 10 */\r
+                       0x40014909u, /* Base address: 0x40014900 Count: 9 */\r
                        0x40014C02u, /* Base address: 0x40014C00 Count: 2 */\r
                        0x40015006u, /* Base address: 0x40015000 Count: 6 */\r
                        0x40015101u, /* Base address: 0x40015100 Count: 1 */\r
@@ -400,185 +400,175 @@ void cyfitter_cfg(void)
 \r
                static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
                        {0x36u, 0x02u},\r
-                       {0x65u, 0x02u},\r
                        {0x7Eu, 0x02u},\r
+                       {0x00u, 0x01u},\r
                        {0x01u, 0x01u},\r
-                       {0x18u, 0x0Cu},\r
+                       {0x18u, 0x08u},\r
                        {0x19u, 0x04u},\r
                        {0x1Cu, 0x61u},\r
-                       {0x20u, 0x50u},\r
-                       {0x21u, 0x98u},\r
-                       {0x30u, 0x05u},\r
-                       {0x31u, 0x09u},\r
+                       {0x20u, 0x98u},\r
+                       {0x21u, 0x50u},\r
+                       {0x30u, 0x03u},\r
+                       {0x31u, 0x06u},\r
                        {0x7Cu, 0x40u},\r
                        {0x33u, 0x03u},\r
-                       {0x87u, 0x0Fu},\r
-                       {0x00u, 0x0Du},\r
-                       {0x03u, 0x04u},\r
-                       {0x04u, 0x01u},\r
-                       {0x06u, 0x32u},\r
-                       {0x07u, 0x24u},\r
-                       {0x08u, 0x02u},\r
-                       {0x09u, 0x24u},\r
-                       {0x0Au, 0x54u},\r
-                       {0x0Bu, 0x12u},\r
-                       {0x0Du, 0x24u},\r
-                       {0x0Eu, 0x10u},\r
-                       {0x0Fu, 0x09u},\r
-                       {0x14u, 0x62u},\r
-                       {0x16u, 0x08u},\r
-                       {0x1Bu, 0x03u},\r
-                       {0x1Cu, 0x02u},\r
-                       {0x1Eu, 0x0Du},\r
-                       {0x1Fu, 0x18u},\r
-                       {0x20u, 0x0Du},\r
-                       {0x23u, 0x20u},\r
-                       {0x24u, 0x0Du},\r
-                       {0x28u, 0x0Du},\r
-                       {0x29u, 0x40u},\r
-                       {0x2Cu, 0x0Du},\r
-                       {0x30u, 0x70u},\r
-                       {0x33u, 0x40u},\r
-                       {0x35u, 0x07u},\r
-                       {0x36u, 0x0Fu},\r
-                       {0x37u, 0x38u},\r
-                       {0x3Au, 0x80u},\r
-                       {0x3Fu, 0x04u},\r
-                       {0x58u, 0x0Bu},\r
+                       {0x86u, 0x0Fu},\r
+                       {0x06u, 0x44u},\r
+                       {0x07u, 0x03u},\r
+                       {0x09u, 0x10u},\r
+                       {0x10u, 0x44u},\r
+                       {0x12u, 0x22u},\r
+                       {0x16u, 0x03u},\r
+                       {0x17u, 0x04u},\r
+                       {0x19u, 0x04u},\r
+                       {0x1Au, 0x30u},\r
+                       {0x1Bu, 0x01u},\r
+                       {0x1Du, 0x08u},\r
+                       {0x1Eu, 0x40u},\r
+                       {0x21u, 0x04u},\r
+                       {0x23u, 0x02u},\r
+                       {0x24u, 0x08u},\r
+                       {0x28u, 0x44u},\r
+                       {0x2Au, 0x11u},\r
+                       {0x2Bu, 0x04u},\r
+                       {0x2Eu, 0x04u},\r
+                       {0x31u, 0x10u},\r
+                       {0x32u, 0x07u},\r
+                       {0x33u, 0x07u},\r
+                       {0x34u, 0x70u},\r
+                       {0x35u, 0x08u},\r
+                       {0x36u, 0x08u},\r
+                       {0x3Eu, 0x40u},\r
+                       {0x3Fu, 0x11u},\r
+                       {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
                        {0x5Cu, 0x99u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x24u},\r
-                       {0x82u, 0x09u},\r
-                       {0x85u, 0x08u},\r
+                       {0x84u, 0x18u},\r
+                       {0x86u, 0x60u},\r
                        {0x87u, 0x04u},\r
-                       {0x8Au, 0x18u},\r
-                       {0x8Bu, 0x09u},\r
-                       {0x8Eu, 0x03u},\r
-                       {0x96u, 0x24u},\r
-                       {0x98u, 0x24u},\r
-                       {0x9Au, 0x12u},\r
-                       {0x9Eu, 0x20u},\r
-                       {0x9Fu, 0x06u},\r
-                       {0xA1u, 0x08u},\r
-                       {0xA2u, 0x80u},\r
-                       {0xA3u, 0x03u},\r
-                       {0xA6u, 0x04u},\r
-                       {0xAAu, 0x40u},\r
-                       {0xACu, 0x40u},\r
-                       {0xAEu, 0x80u},\r
-                       {0xAFu, 0x08u},\r
-                       {0xB0u, 0xC0u},\r
-                       {0xB1u, 0x0Eu},\r
-                       {0xB4u, 0x38u},\r
-                       {0xB5u, 0x01u},\r
-                       {0xB6u, 0x07u},\r
-                       {0xBEu, 0x01u},\r
-                       {0xBFu, 0x10u},\r
+                       {0x88u, 0x07u},\r
+                       {0x8Bu, 0x08u},\r
+                       {0x8Du, 0x08u},\r
+                       {0x8Fu, 0x10u},\r
+                       {0x90u, 0x28u},\r
+                       {0x92u, 0x50u},\r
+                       {0x93u, 0x03u},\r
+                       {0x98u, 0x04u},\r
+                       {0x9Bu, 0x04u},\r
+                       {0xA0u, 0x30u},\r
+                       {0xA2u, 0x48u},\r
+                       {0xA3u, 0x10u},\r
+                       {0xA5u, 0x04u},\r
+                       {0xA6u, 0x02u},\r
+                       {0xA7u, 0x01u},\r
+                       {0xA8u, 0x01u},\r
+                       {0xADu, 0x04u},\r
+                       {0xAEu, 0x07u},\r
+                       {0xAFu, 0x02u},\r
+                       {0xB1u, 0x18u},\r
+                       {0xB2u, 0x78u},\r
+                       {0xB4u, 0x07u},\r
+                       {0xB7u, 0x07u},\r
+                       {0xBEu, 0x14u},\r
+                       {0xBFu, 0x01u},\r
+                       {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x99u},\r
+                       {0xDCu, 0x90u},\r
+                       {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x60u},\r
-                       {0x03u, 0x60u},\r
-                       {0x05u, 0x50u},\r
-                       {0x06u, 0x40u},\r
-                       {0x07u, 0x04u},\r
-                       {0x0Au, 0x22u},\r
-                       {0x0Du, 0x14u},\r
-                       {0x0Eu, 0x01u},\r
-                       {0x11u, 0x14u},\r
-                       {0x13u, 0x41u},\r
-                       {0x15u, 0x40u},\r
-                       {0x16u, 0xA4u},\r
-                       {0x18u, 0x40u},\r
-                       {0x1Au, 0x02u},\r
-                       {0x1Du, 0x50u},\r
-                       {0x1Eu, 0x40u},\r
-                       {0x21u, 0x20u},\r
-                       {0x22u, 0x84u},\r
-                       {0x23u, 0x08u},\r
-                       {0x25u, 0x10u},\r
-                       {0x27u, 0x80u},\r
-                       {0x29u, 0x01u},\r
-                       {0x2Bu, 0x04u},\r
-                       {0x2Cu, 0x02u},\r
-                       {0x2Fu, 0x40u},\r
-                       {0x31u, 0x20u},\r
-                       {0x32u, 0x80u},\r
-                       {0x37u, 0x80u},\r
-                       {0x39u, 0x28u},\r
-                       {0x3Au, 0x42u},\r
-                       {0x3Bu, 0x80u},\r
-                       {0x3Cu, 0x10u},\r
+                       {0x00u, 0x04u},\r
+                       {0x05u, 0x08u},\r
+                       {0x06u, 0x08u},\r
+                       {0x09u, 0x80u},\r
+                       {0x0Au, 0x54u},\r
+                       {0x0Cu, 0x02u},\r
+                       {0x0Eu, 0x08u},\r
+                       {0x12u, 0x08u},\r
+                       {0x13u, 0x48u},\r
+                       {0x14u, 0x08u},\r
+                       {0x16u, 0x01u},\r
+                       {0x17u, 0x05u},\r
+                       {0x19u, 0x08u},\r
+                       {0x1Au, 0x16u},\r
+                       {0x1Bu, 0x10u},\r
+                       {0x1Du, 0x18u},\r
+                       {0x21u, 0x04u},\r
+                       {0x22u, 0x12u},\r
+                       {0x24u, 0x40u},\r
+                       {0x27u, 0x01u},\r
+                       {0x29u, 0x21u},\r
+                       {0x2Du, 0x02u},\r
+                       {0x2Eu, 0x40u},\r
+                       {0x2Fu, 0x20u},\r
+                       {0x30u, 0x40u},\r
+                       {0x31u, 0x24u},\r
+                       {0x33u, 0x20u},\r
+                       {0x35u, 0x20u},\r
+                       {0x37u, 0x01u},\r
+                       {0x39u, 0x08u},\r
+                       {0x3Bu, 0x10u},\r
+                       {0x3Du, 0x80u},\r
+                       {0x3Eu, 0x20u},\r
                        {0x3Fu, 0x04u},\r
-                       {0x58u, 0x84u},\r
-                       {0x59u, 0x02u},\r
-                       {0x5Bu, 0x10u},\r
-                       {0x6Du, 0x40u},\r
-                       {0x78u, 0x02u},\r
-                       {0x7Cu, 0x80u},\r
-                       {0x7Fu, 0x01u},\r
-                       {0x80u, 0x40u},\r
-                       {0x81u, 0x20u},\r
-                       {0x86u, 0x80u},\r
-                       {0xC0u, 0xDFu},\r
-                       {0xC2u, 0xE5u},\r
-                       {0xC4u, 0xFFu},\r
-                       {0xCAu, 0x95u},\r
-                       {0xCCu, 0x1Cu},\r
-                       {0xCEu, 0x6Fu},\r
-                       {0xD6u, 0x0Fu},\r
-                       {0xDEu, 0x01u},\r
-                       {0xE0u, 0x04u},\r
-                       {0xE4u, 0x08u},\r
-                       {0x0Cu, 0x01u},\r
-                       {0x14u, 0x01u},\r
-                       {0x18u, 0x02u},\r
-                       {0x2Eu, 0x01u},\r
-                       {0x36u, 0x03u},\r
-                       {0x3Au, 0xC0u},\r
-                       {0x58u, 0x04u},\r
-                       {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x09u},\r
-                       {0x5Fu, 0x01u},\r
-                       {0x84u, 0x96u},\r
+                       {0x5Cu, 0x40u},\r
+                       {0x67u, 0x02u},\r
+                       {0x69u, 0x80u},\r
+                       {0x82u, 0x10u},\r
+                       {0x83u, 0x01u},\r
+                       {0xC0u, 0x64u},\r
+                       {0xC2u, 0x5Fu},\r
+                       {0xC4u, 0xF7u},\r
+                       {0xCAu, 0xD5u},\r
+                       {0xCCu, 0xAEu},\r
+                       {0xCEu, 0x76u},\r
+                       {0xD6u, 0x10u},\r
+                       {0xD8u, 0x10u},\r
+                       {0xE4u, 0x04u},\r
+                       {0x82u, 0x40u},\r
+                       {0x83u, 0x06u},\r
+                       {0x84u, 0x16u},\r
                        {0x85u, 0x10u},\r
-                       {0x86u, 0x69u},\r
-                       {0x87u, 0x2Du},\r
-                       {0x89u, 0x67u},\r
-                       {0x8Au, 0xFFu},\r
-                       {0x8Bu, 0x18u},\r
-                       {0x8Cu, 0x33u},\r
-                       {0x8Du, 0x02u},\r
-                       {0x8Eu, 0xCCu},\r
-                       {0x94u, 0x55u},\r
-                       {0x96u, 0xAAu},\r
-                       {0x9Bu, 0x40u},\r
-                       {0xA0u, 0x0Fu},\r
-                       {0xA1u, 0x02u},\r
-                       {0xA2u, 0xF0u},\r
-                       {0xA4u, 0xFFu},\r
-                       {0xA5u, 0x01u},\r
-                       {0xA7u, 0x02u},\r
-                       {0xADu, 0x16u},\r
-                       {0xAEu, 0xFFu},\r
-                       {0xAFu, 0x48u},\r
-                       {0xB1u, 0x08u},\r
-                       {0xB3u, 0x70u},\r
-                       {0xB5u, 0x07u},\r
-                       {0xB6u, 0xFFu},\r
-                       {0xBEu, 0x40u},\r
-                       {0xBFu, 0x01u},\r
-                       {0xC0u, 0x32u},\r
-                       {0xC1u, 0x05u},\r
-                       {0xC2u, 0x40u},\r
-                       {0xC5u, 0xD2u},\r
-                       {0xC6u, 0x0Cu},\r
-                       {0xC7u, 0xEFu},\r
-                       {0xC8u, 0x37u},\r
+                       {0x86u, 0x48u},\r
+                       {0x8Bu, 0x08u},\r
+                       {0x8Cu, 0x02u},\r
+                       {0x8Fu, 0x20u},\r
+                       {0x90u, 0x67u},\r
+                       {0x92u, 0x18u},\r
+                       {0x94u, 0x01u},\r
+                       {0x96u, 0x02u},\r
+                       {0x98u, 0x10u},\r
+                       {0x99u, 0x28u},\r
+                       {0x9Au, 0x2Du},\r
+                       {0x9Bu, 0x02u},\r
+                       {0x9Du, 0x01u},\r
+                       {0xA0u, 0x80u},\r
+                       {0xA1u, 0x48u},\r
+                       {0xA3u, 0x04u},\r
+                       {0xA4u, 0x02u},\r
+                       {0xA9u, 0x20u},\r
+                       {0xABu, 0x08u},\r
+                       {0xB0u, 0x07u},\r
+                       {0xB1u, 0x0Eu},\r
+                       {0xB2u, 0x80u},\r
+                       {0xB3u, 0x10u},\r
+                       {0xB4u, 0x70u},\r
+                       {0xB5u, 0x60u},\r
+                       {0xB6u, 0x08u},\r
+                       {0xB7u, 0x01u},\r
+                       {0xBBu, 0x30u},\r
+                       {0xBEu, 0x44u},\r
+                       {0xBFu, 0x44u},\r
+                       {0xC0u, 0x24u},\r
+                       {0xC1u, 0x06u},\r
+                       {0xC2u, 0x50u},\r
+                       {0xC5u, 0xCFu},\r
+                       {0xC6u, 0xD2u},\r
+                       {0xC7u, 0x0Eu},\r
+                       {0xC8u, 0x1Fu},\r
                        {0xC9u, 0xFFu},\r
                        {0xCAu, 0xFFu},\r
                        {0xCBu, 0xFFu},\r
@@ -588,7 +578,7 @@ void cyfitter_cfg(void)
                        {0xD9u, 0x04u},\r
                        {0xDAu, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x90u},\r
+                       {0xDCu, 0x99u},\r
                        {0xDDu, 0x09u},\r
                        {0xDFu, 0x01u},\r
                        {0xE2u, 0xC0u},\r
@@ -596,729 +586,675 @@ void cyfitter_cfg(void)
                        {0xE8u, 0x40u},\r
                        {0xE9u, 0x40u},\r
                        {0xEEu, 0x08u},\r
-                       {0x01u, 0x80u},\r
-                       {0x02u, 0x10u},\r
-                       {0x03u, 0x04u},\r
-                       {0x04u, 0x08u},\r
-                       {0x05u, 0x40u},\r
-                       {0x07u, 0x10u},\r
-                       {0x0Au, 0x10u},\r
-                       {0x0Fu, 0x14u},\r
-                       {0x11u, 0x40u},\r
-                       {0x13u, 0x0Au},\r
-                       {0x15u, 0x40u},\r
-                       {0x1Bu, 0x80u},\r
-                       {0x1Du, 0x40u},\r
-                       {0x1Eu, 0x02u},\r
-                       {0x1Fu, 0x40u},\r
-                       {0x20u, 0x50u},\r
-                       {0x21u, 0x14u},\r
-                       {0x23u, 0x14u},\r
-                       {0x29u, 0x42u},\r
-                       {0x2Au, 0x08u},\r
-                       {0x30u, 0x20u},\r
-                       {0x38u, 0x80u},\r
-                       {0x39u, 0x28u},\r
-                       {0x40u, 0x50u},\r
-                       {0x41u, 0x10u},\r
-                       {0x48u, 0x20u},\r
-                       {0x49u, 0x02u},\r
-                       {0x4Au, 0x01u},\r
-                       {0x50u, 0x44u},\r
-                       {0x52u, 0x40u},\r
-                       {0x53u, 0x01u},\r
-                       {0x58u, 0x50u},\r
-                       {0x5Au, 0x0Au},\r
-                       {0x60u, 0x08u},\r
-                       {0x61u, 0x08u},\r
-                       {0x63u, 0x82u},\r
-                       {0x68u, 0x06u},\r
-                       {0x6Au, 0x01u},\r
-                       {0x6Bu, 0x20u},\r
-                       {0x6Du, 0x40u},\r
-                       {0x71u, 0x21u},\r
-                       {0x72u, 0x22u},\r
-                       {0x81u, 0x40u},\r
-                       {0x82u, 0x80u},\r
-                       {0x83u, 0x42u},\r
-                       {0x86u, 0x08u},\r
-                       {0x89u, 0x08u},\r
-                       {0x8Au, 0x01u},\r
-                       {0x8Fu, 0x08u},\r
-                       {0x92u, 0x48u},\r
-                       {0x94u, 0x10u},\r
-                       {0x95u, 0x3Cu},\r
-                       {0x96u, 0x21u},\r
-                       {0x97u, 0xC7u},\r
-                       {0x9Bu, 0x8Cu},\r
-                       {0x9Cu, 0x06u},\r
-                       {0x9Du, 0x03u},\r
-                       {0x9Eu, 0xA6u},\r
-                       {0x9Fu, 0x50u},\r
-                       {0xA1u, 0x10u},\r
-                       {0xA4u, 0x12u},\r
-                       {0xA7u, 0x20u},\r
-                       {0xABu, 0x04u},\r
-                       {0xADu, 0x40u},\r
-                       {0xB5u, 0x10u},\r
-                       {0xC0u, 0x87u},\r
-                       {0xC2u, 0x64u},\r
-                       {0xC4u, 0x8Du},\r
-                       {0xCAu, 0x0Bu},\r
-                       {0xCCu, 0x04u},\r
-                       {0xCEu, 0x0Eu},\r
-                       {0xD0u, 0x07u},\r
-                       {0xD2u, 0x08u},\r
+                       {0x00u, 0x88u},\r
+                       {0x02u, 0x80u},\r
+                       {0x09u, 0x04u},\r
+                       {0x0Au, 0x44u},\r
+                       {0x11u, 0x02u},\r
+                       {0x12u, 0x10u},\r
+                       {0x18u, 0x14u},\r
+                       {0x19u, 0xA1u},\r
+                       {0x1Au, 0x44u},\r
+                       {0x1Bu, 0x02u},\r
+                       {0x20u, 0x08u},\r
+                       {0x21u, 0x21u},\r
+                       {0x22u, 0x04u},\r
+                       {0x23u, 0x01u},\r
+                       {0x29u, 0x21u},\r
+                       {0x31u, 0x20u},\r
+                       {0x33u, 0x40u},\r
+                       {0x39u, 0xA2u},\r
+                       {0x3Bu, 0x08u},\r
+                       {0x40u, 0x04u},\r
+                       {0x42u, 0x40u},\r
+                       {0x48u, 0x54u},\r
+                       {0x49u, 0x80u},\r
+                       {0x4Au, 0x08u},\r
+                       {0x52u, 0x94u},\r
+                       {0x53u, 0x10u},\r
+                       {0x58u, 0x80u},\r
+                       {0x5Au, 0x2Au},\r
+                       {0x60u, 0x10u},\r
+                       {0x62u, 0x02u},\r
+                       {0x63u, 0x09u},\r
+                       {0x68u, 0x80u},\r
+                       {0x69u, 0x24u},\r
+                       {0x6Au, 0x80u},\r
+                       {0x71u, 0x84u},\r
+                       {0x73u, 0x44u},\r
+                       {0x81u, 0x05u},\r
+                       {0x82u, 0x04u},\r
+                       {0x87u, 0x1Cu},\r
+                       {0x8Du, 0x10u},\r
+                       {0x91u, 0x80u},\r
+                       {0x92u, 0x22u},\r
+                       {0x93u, 0x02u},\r
+                       {0x94u, 0x04u},\r
+                       {0x96u, 0x40u},\r
+                       {0x97u, 0x54u},\r
+                       {0x99u, 0x10u},\r
+                       {0x9Cu, 0x48u},\r
+                       {0x9Du, 0x25u},\r
+                       {0x9Eu, 0x29u},\r
+                       {0x9Fu, 0x0Cu},\r
+                       {0xA1u, 0x08u},\r
+                       {0xA2u, 0x02u},\r
+                       {0xA3u, 0x10u},\r
+                       {0xA5u, 0xE0u},\r
+                       {0xA6u, 0x0Cu},\r
+                       {0xABu, 0x10u},\r
+                       {0xACu, 0x02u},\r
+                       {0xADu, 0x04u},\r
+                       {0xAFu, 0x01u},\r
+                       {0xB5u, 0x02u},\r
+                       {0xC0u, 0x0Du},\r
+                       {0xC2u, 0x0Eu},\r
+                       {0xC4u, 0x0Cu},\r
+                       {0xCAu, 0x05u},\r
+                       {0xCCu, 0x0Cu},\r
+                       {0xCEu, 0x0Fu},\r
+                       {0xD0u, 0x05u},\r
+                       {0xD2u, 0x0Cu},\r
                        {0xD6u, 0x0Fu},\r
                        {0xD8u, 0x0Fu},\r
-                       {0xE2u, 0x14u},\r
-                       {0xE4u, 0x01u},\r
-                       {0xE6u, 0x02u},\r
-                       {0xECu, 0x08u},\r
-                       {0xEEu, 0x04u},\r
-                       {0x00u, 0x40u},\r
-                       {0x03u, 0x04u},\r
-                       {0x06u, 0x04u},\r
-                       {0x07u, 0x30u},\r
-                       {0x09u, 0x41u},\r
-                       {0x0Eu, 0x03u},\r
-                       {0x0Fu, 0x41u},\r
-                       {0x11u, 0x23u},\r
-                       {0x12u, 0x18u},\r
-                       {0x13u, 0x0Cu},\r
-                       {0x14u, 0x40u},\r
-                       {0x15u, 0x02u},\r
-                       {0x17u, 0x01u},\r
-                       {0x19u, 0x41u},\r
-                       {0x1Au, 0x20u},\r
-                       {0x1Cu, 0x40u},\r
-                       {0x1Du, 0x41u},\r
-                       {0x20u, 0x24u},\r
-                       {0x21u, 0x41u},\r
-                       {0x22u, 0x09u},\r
-                       {0x24u, 0x24u},\r
-                       {0x25u, 0x12u},\r
-                       {0x26u, 0x12u},\r
-                       {0x27u, 0x0Du},\r
-                       {0x29u, 0x05u},\r
-                       {0x2Au, 0x24u},\r
-                       {0x2Bu, 0x0Au},\r
-                       {0x2Cu, 0x40u},\r
-                       {0x2Fu, 0x08u},\r
-                       {0x30u, 0x38u},\r
-                       {0x31u, 0x40u},\r
-                       {0x32u, 0x40u},\r
-                       {0x33u, 0x03u},\r
-                       {0x35u, 0x3Cu},\r
-                       {0x36u, 0x07u},\r
-                       {0x38u, 0x08u},\r
-                       {0x3Bu, 0x08u},\r
-                       {0x3Eu, 0x04u},\r
-                       {0x3Fu, 0x01u},\r
+                       {0xE0u, 0x01u},\r
+                       {0xE2u, 0x4Cu},\r
+                       {0xE4u, 0x02u},\r
+                       {0xE6u, 0x09u},\r
+                       {0xE8u, 0x40u},\r
+                       {0x04u, 0x24u},\r
+                       {0x06u, 0x49u},\r
+                       {0x0Cu, 0x24u},\r
+                       {0x0Eu, 0x12u},\r
+                       {0x0Fu, 0xFFu},\r
+                       {0x11u, 0xFFu},\r
+                       {0x12u, 0x04u},\r
+                       {0x15u, 0x96u},\r
+                       {0x16u, 0x03u},\r
+                       {0x17u, 0x69u},\r
+                       {0x19u, 0x55u},\r
+                       {0x1Au, 0x64u},\r
+                       {0x1Bu, 0xAAu},\r
+                       {0x1Du, 0x33u},\r
+                       {0x1Eu, 0x18u},\r
+                       {0x1Fu, 0xCCu},\r
+                       {0x21u, 0x0Fu},\r
+                       {0x22u, 0x20u},\r
+                       {0x23u, 0xF0u},\r
+                       {0x27u, 0xFFu},\r
+                       {0x32u, 0x07u},\r
+                       {0x34u, 0x40u},\r
+                       {0x35u, 0xFFu},\r
+                       {0x36u, 0x38u},\r
+                       {0x3Eu, 0x10u},\r
+                       {0x3Fu, 0x10u},\r
                        {0x58u, 0x04u},\r
-                       {0x59u, 0x0Bu},\r
+                       {0x59u, 0x04u},\r
+                       {0x5Cu, 0x09u},\r
+                       {0x5Fu, 0x01u},\r
+                       {0x82u, 0x20u},\r
+                       {0x84u, 0x11u},\r
+                       {0x85u, 0x06u},\r
+                       {0x86u, 0x22u},\r
+                       {0x89u, 0x20u},\r
+                       {0x8Au, 0x10u},\r
+                       {0x8Bu, 0x18u},\r
+                       {0x8Eu, 0xC0u},\r
+                       {0x90u, 0x02u},\r
+                       {0x92u, 0x0Du},\r
+                       {0x94u, 0x0Du},\r
+                       {0x95u, 0x49u},\r
+                       {0x97u, 0x32u},\r
+                       {0x98u, 0x82u},\r
+                       {0x99u, 0x59u},\r
+                       {0x9Au, 0x38u},\r
+                       {0x9Bu, 0x24u},\r
+                       {0x9Cu, 0x0Du},\r
+                       {0xA0u, 0x0Du},\r
+                       {0xA4u, 0x42u},\r
+                       {0xA5u, 0x6Au},\r
+                       {0xA6u, 0x34u},\r
+                       {0xA7u, 0x11u},\r
+                       {0xA8u, 0x0Du},\r
+                       {0xACu, 0x0Du},\r
+                       {0xB0u, 0x0Fu},\r
+                       {0xB3u, 0x07u},\r
+                       {0xB5u, 0x38u},\r
+                       {0xB6u, 0xF0u},\r
+                       {0xB7u, 0x40u},\r
+                       {0xB9u, 0x08u},\r
+                       {0xBAu, 0x02u},\r
+                       {0xBBu, 0x20u},\r
+                       {0xBFu, 0x40u},\r
+                       {0xD4u, 0x09u},\r
+                       {0xD8u, 0x08u},\r
+                       {0xD9u, 0x08u},\r
+                       {0xDBu, 0x08u},\r
+                       {0xDCu, 0x99u},\r
+                       {0xDDu, 0x90u},\r
+                       {0xDFu, 0x01u},\r
+                       {0x00u, 0x08u},\r
+                       {0x03u, 0x02u},\r
+                       {0x05u, 0x54u},\r
+                       {0x06u, 0x81u},\r
+                       {0x0Au, 0xA6u},\r
+                       {0x0Du, 0x02u},\r
+                       {0x0Eu, 0x19u},\r
+                       {0x10u, 0x80u},\r
+                       {0x12u, 0x10u},\r
+                       {0x13u, 0x08u},\r
+                       {0x16u, 0x06u},\r
+                       {0x17u, 0x05u},\r
+                       {0x18u, 0x08u},\r
+                       {0x1Au, 0x22u},\r
+                       {0x1Du, 0x42u},\r
+                       {0x21u, 0x20u},\r
+                       {0x24u, 0x02u},\r
+                       {0x25u, 0x14u},\r
+                       {0x27u, 0x08u},\r
+                       {0x29u, 0x02u},\r
+                       {0x2Bu, 0x10u},\r
+                       {0x2Cu, 0x20u},\r
+                       {0x31u, 0x08u},\r
+                       {0x32u, 0x91u},\r
+                       {0x34u, 0x08u},\r
+                       {0x35u, 0x04u},\r
+                       {0x36u, 0x20u},\r
+                       {0x39u, 0x80u},\r
+                       {0x3Du, 0x28u},\r
+                       {0x3Eu, 0x08u},\r
+                       {0x4Cu, 0x01u},\r
+                       {0x4Du, 0x80u},\r
+                       {0x5Cu, 0x40u},\r
+                       {0x5Du, 0x08u},\r
+                       {0x5Eu, 0x02u},\r
+                       {0x5Fu, 0x20u},\r
+                       {0x65u, 0x80u},\r
+                       {0x6Du, 0x80u},\r
+                       {0x79u, 0x02u},\r
+                       {0x7Au, 0x80u},\r
+                       {0x7Fu, 0x01u},\r
+                       {0x81u, 0x62u},\r
+                       {0x88u, 0x41u},\r
+                       {0x89u, 0x01u},\r
+                       {0x8Eu, 0x30u},\r
+                       {0x8Fu, 0x10u},\r
+                       {0x91u, 0x86u},\r
+                       {0x92u, 0x84u},\r
+                       {0x93u, 0x02u},\r
+                       {0x9Cu, 0x88u},\r
+                       {0x9Eu, 0x29u},\r
+                       {0x9Fu, 0x04u},\r
+                       {0xA0u, 0xC4u},\r
+                       {0xA1u, 0x08u},\r
+                       {0xA3u, 0x12u},\r
+                       {0xA5u, 0x40u},\r
+                       {0xA6u, 0x04u},\r
+                       {0xA7u, 0x04u},\r
+                       {0xA9u, 0x40u},\r
+                       {0xABu, 0x40u},\r
+                       {0xACu, 0x40u},\r
+                       {0xAFu, 0x10u},\r
+                       {0xB0u, 0x10u},\r
+                       {0xC0u, 0xF5u},\r
+                       {0xC2u, 0xFFu},\r
+                       {0xC4u, 0xF8u},\r
+                       {0xCAu, 0x43u},\r
+                       {0xCCu, 0x6Fu},\r
+                       {0xCEu, 0x68u},\r
+                       {0xD6u, 0xF0u},\r
+                       {0xD8u, 0x10u},\r
+                       {0xDEu, 0x10u},\r
+                       {0xE0u, 0x05u},\r
+                       {0xE4u, 0x44u},\r
+                       {0xE6u, 0x02u},\r
+                       {0xEAu, 0x08u},\r
+                       {0xEEu, 0x09u},\r
+                       {0x00u, 0x01u},\r
+                       {0x01u, 0x86u},\r
+                       {0x04u, 0x07u},\r
+                       {0x05u, 0x04u},\r
+                       {0x06u, 0x18u},\r
+                       {0x07u, 0x40u},\r
+                       {0x08u, 0x01u},\r
+                       {0x0Bu, 0x86u},\r
+                       {0x0Cu, 0x04u},\r
+                       {0x0Du, 0x86u},\r
+                       {0x10u, 0x10u},\r
+                       {0x11u, 0x82u},\r
+                       {0x12u, 0x40u},\r
+                       {0x15u, 0x69u},\r
+                       {0x17u, 0x06u},\r
+                       {0x18u, 0x22u},\r
+                       {0x19u, 0x82u},\r
+                       {0x1Au, 0x08u},\r
+                       {0x1Bu, 0x04u},\r
+                       {0x1Cu, 0x01u},\r
+                       {0x1Du, 0x10u},\r
+                       {0x20u, 0x01u},\r
+                       {0x21u, 0x10u},\r
+                       {0x24u, 0x08u},\r
+                       {0x25u, 0x01u},\r
+                       {0x26u, 0x21u},\r
+                       {0x27u, 0xAEu},\r
+                       {0x29u, 0xE7u},\r
+                       {0x2Bu, 0x08u},\r
+                       {0x2Cu, 0x01u},\r
+                       {0x2Du, 0x86u},\r
+                       {0x30u, 0x08u},\r
+                       {0x31u, 0x10u},\r
+                       {0x33u, 0xE0u},\r
+                       {0x34u, 0x40u},\r
+                       {0x35u, 0x0Fu},\r
+                       {0x36u, 0x3Fu},\r
+                       {0x38u, 0x80u},\r
+                       {0x39u, 0x22u},\r
+                       {0x3Bu, 0x0Cu},\r
+                       {0x3Eu, 0x41u},\r
+                       {0x54u, 0x40u},\r
+                       {0x58u, 0x08u},\r
+                       {0x59u, 0x08u},\r
+                       {0x5Bu, 0x08u},\r
                        {0x5Cu, 0x99u},\r
+                       {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x82u, 0xFFu},\r
-                       {0x84u, 0x96u},\r
-                       {0x85u, 0xFFu},\r
-                       {0x86u, 0x69u},\r
-                       {0x88u, 0xFFu},\r
-                       {0x8Cu, 0x0Fu},\r
-                       {0x8Du, 0x33u},\r
-                       {0x8Eu, 0xF0u},\r
-                       {0x8Fu, 0xCCu},\r
-                       {0x90u, 0x33u},\r
-                       {0x91u, 0x0Fu},\r
-                       {0x92u, 0xCCu},\r
-                       {0x93u, 0xF0u},\r
-                       {0x95u, 0xFFu},\r
-                       {0x99u, 0x69u},\r
-                       {0x9Bu, 0x96u},\r
-                       {0x9Du, 0x55u},\r
-                       {0x9Fu, 0xAAu},\r
-                       {0xA6u, 0xFFu},\r
-                       {0xACu, 0x55u},\r
-                       {0xAEu, 0xAAu},\r
-                       {0xAFu, 0xFFu},\r
-                       {0xB6u, 0xFFu},\r
+                       {0x82u, 0x03u},\r
+                       {0x84u, 0x04u},\r
+                       {0x86u, 0x01u},\r
+                       {0x8Cu, 0x04u},\r
+                       {0x8Eu, 0x02u},\r
+                       {0x8Fu, 0xFFu},\r
+                       {0x93u, 0xFFu},\r
+                       {0x95u, 0x69u},\r
+                       {0x97u, 0x96u},\r
+                       {0x99u, 0x55u},\r
+                       {0x9Au, 0x04u},\r
+                       {0x9Bu, 0xAAu},\r
+                       {0x9Du, 0x33u},\r
+                       {0x9Fu, 0xCCu},\r
+                       {0xA1u, 0x0Fu},\r
+                       {0xA3u, 0xF0u},\r
+                       {0xA6u, 0x04u},\r
+                       {0xA7u, 0xFFu},\r
+                       {0xB0u, 0x07u},\r
                        {0xB7u, 0xFFu},\r
-                       {0xBEu, 0x40u},\r
                        {0xBFu, 0x40u},\r
-                       {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
-                       {0xDBu, 0x04u},\r
-                       {0xDDu, 0x90u},\r
+                       {0xDCu, 0x09u},\r
                        {0xDFu, 0x01u},\r
                        {0x00u, 0x08u},\r
-                       {0x01u, 0x80u},\r
-                       {0x03u, 0x80u},\r
-                       {0x04u, 0x02u},\r
-                       {0x05u, 0x40u},\r
-                       {0x06u, 0x18u},\r
-                       {0x07u, 0x16u},\r
-                       {0x09u, 0x24u},\r
-                       {0x0Au, 0x81u},\r
+                       {0x01u, 0x02u},\r
+                       {0x03u, 0x02u},\r
+                       {0x04u, 0xA0u},\r
+                       {0x05u, 0x05u},\r
+                       {0x06u, 0x04u},\r
+                       {0x0Au, 0x04u},\r
+                       {0x0Cu, 0x20u},\r
+                       {0x0Eu, 0x09u},\r
                        {0x0Fu, 0x80u},\r
-                       {0x11u, 0x81u},\r
-                       {0x13u, 0x14u},\r
-                       {0x17u, 0x88u},\r
-                       {0x19u, 0x80u},\r
-                       {0x1Au, 0x80u},\r
-                       {0x1Bu, 0x48u},\r
-                       {0x1Eu, 0x01u},\r
-                       {0x20u, 0x04u},\r
-                       {0x22u, 0x0Bu},\r
-                       {0x25u, 0x40u},\r
-                       {0x28u, 0x20u},\r
-                       {0x29u, 0x10u},\r
-                       {0x2Au, 0x02u},\r
-                       {0x2Bu, 0x02u},\r
-                       {0x2Du, 0x40u},\r
-                       {0x30u, 0x20u},\r
-                       {0x32u, 0x08u},\r
-                       {0x33u, 0x41u},\r
-                       {0x37u, 0x9Au},\r
-                       {0x38u, 0x04u},\r
-                       {0x39u, 0x92u},\r
-                       {0x3Bu, 0x40u},\r
-                       {0x3Eu, 0x08u},\r
-                       {0x3Fu, 0x80u},\r
-                       {0x4Eu, 0x08u},\r
-                       {0x4Fu, 0x20u},\r
-                       {0x5Du, 0x01u},\r
-                       {0x5Eu, 0x42u},\r
-                       {0x64u, 0x02u},\r
-                       {0x66u, 0x80u},\r
-                       {0x78u, 0x02u},\r
-                       {0x80u, 0x0Cu},\r
-                       {0x8Au, 0x80u},\r
-                       {0x8Cu, 0x01u},\r
-                       {0x8Du, 0x40u},\r
-                       {0x8Eu, 0x40u},\r
-                       {0x91u, 0x68u},\r
-                       {0x92u, 0x40u},\r
-                       {0x93u, 0x14u},\r
-                       {0x95u, 0x14u},\r
-                       {0x96u, 0x20u},\r
-                       {0x97u, 0x41u},\r
-                       {0x9Au, 0x01u},\r
-                       {0x9Bu, 0xACu},\r
-                       {0x9Cu, 0x0Au},\r
-                       {0x9Du, 0x80u},\r
-                       {0x9Eu, 0x14u},\r
-                       {0x9Fu, 0x42u},\r
+                       {0x11u, 0x04u},\r
+                       {0x16u, 0x02u},\r
+                       {0x17u, 0x05u},\r
+                       {0x19u, 0x02u},\r
+                       {0x1Cu, 0x40u},\r
+                       {0x1Du, 0x10u},\r
+                       {0x1Fu, 0x40u},\r
+                       {0x20u, 0x02u},\r
+                       {0x24u, 0x80u},\r
+                       {0x25u, 0x20u},\r
+                       {0x26u, 0x2Eu},\r
+                       {0x27u, 0x04u},\r
+                       {0x29u, 0x02u},\r
+                       {0x2Bu, 0x10u},\r
+                       {0x2Cu, 0x20u},\r
+                       {0x2Du, 0x80u},\r
+                       {0x2Fu, 0x48u},\r
+                       {0x31u, 0x08u},\r
+                       {0x32u, 0x91u},\r
+                       {0x35u, 0x01u},\r
+                       {0x37u, 0x54u},\r
+                       {0x39u, 0x80u},\r
+                       {0x3Du, 0x80u},\r
+                       {0x3Eu, 0x19u},\r
+                       {0x46u, 0x08u},\r
+                       {0x47u, 0x20u},\r
+                       {0x66u, 0x20u},\r
+                       {0x67u, 0x21u},\r
+                       {0x7Fu, 0x01u},\r
+                       {0x8Eu, 0x24u},\r
+                       {0x91u, 0x84u},\r
+                       {0x92u, 0x26u},\r
+                       {0x93u, 0x02u},\r
+                       {0x94u, 0x40u},\r
+                       {0x96u, 0x11u},\r
+                       {0x9Au, 0x10u},\r
+                       {0x9Du, 0x1Eu},\r
+                       {0x9Eu, 0x86u},\r
+                       {0x9Fu, 0x25u},\r
                        {0xA0u, 0x04u},\r
-                       {0xA1u, 0x20u},\r
-                       {0xA2u, 0x01u},\r
-                       {0xA3u, 0x80u},\r
-                       {0xA4u, 0x10u},\r
-                       {0xA7u, 0x29u},\r
-                       {0xAAu, 0x10u},\r
-                       {0xABu, 0x80u},\r
-                       {0xACu, 0x54u},\r
-                       {0xAEu, 0x40u},\r
-                       {0xB5u, 0x10u},\r
-                       {0xB6u, 0x01u},\r
+                       {0xA1u, 0x08u},\r
+                       {0xA2u, 0x80u},\r
+                       {0xA3u, 0x12u},\r
+                       {0xA4u, 0x21u},\r
+                       {0xA6u, 0x25u},\r
+                       {0xA8u, 0x04u},\r
+                       {0xABu, 0x04u},\r
+                       {0xACu, 0x80u},\r
+                       {0xB1u, 0x08u},\r
+                       {0xB2u, 0x01u},\r
                        {0xC0u, 0xFDu},\r
-                       {0xC2u, 0x1Fu},\r
-                       {0xC4u, 0xAFu},\r
-                       {0xCAu, 0x1Fu},\r
+                       {0xC2u, 0xD2u},\r
+                       {0xC4u, 0xB4u},\r
+                       {0xCAu, 0xF3u},\r
                        {0xCCu, 0xFFu},\r
-                       {0xCEu, 0x5Fu},\r
-                       {0xD6u, 0x10u},\r
-                       {0xD8u, 0x10u},\r
-                       {0xDEu, 0x01u},\r
-                       {0xE0u, 0x04u},\r
-                       {0xE2u, 0x10u},\r
-                       {0xE6u, 0x04u},\r
-                       {0xE8u, 0x01u},\r
-                       {0xEEu, 0x1Au},\r
-                       {0x2Cu, 0x01u},\r
-                       {0x36u, 0x01u},\r
-                       {0x3Eu, 0x40u},\r
-                       {0x58u, 0x04u},\r
-                       {0x5Fu, 0x01u},\r
-                       {0x01u, 0x70u},\r
-                       {0x03u, 0x60u},\r
-                       {0x08u, 0x01u},\r
-                       {0x0Au, 0x80u},\r
-                       {0x0Bu, 0x14u},\r
-                       {0x0Eu, 0x01u},\r
-                       {0x0Fu, 0x02u},\r
-                       {0x10u, 0x22u},\r
-                       {0x12u, 0x08u},\r
-                       {0x13u, 0x02u},\r
-                       {0x16u, 0x01u},\r
-                       {0x19u, 0x01u},\r
-                       {0x1Eu, 0x01u},\r
-                       {0x21u, 0x09u},\r
-                       {0x22u, 0x40u},\r
-                       {0x28u, 0x01u},\r
-                       {0x29u, 0x11u},\r
-                       {0x2Bu, 0x10u},\r
-                       {0x30u, 0x22u},\r
-                       {0x31u, 0x08u},\r
-                       {0x33u, 0x40u},\r
-                       {0x39u, 0x40u},\r
-                       {0x3Au, 0x02u},\r
-                       {0x3Bu, 0x14u},\r
-                       {0x40u, 0xB0u},\r
-                       {0x41u, 0x20u},\r
-                       {0x45u, 0x40u},\r
-                       {0x47u, 0x40u},\r
-                       {0x49u, 0x14u},\r
-                       {0x4Au, 0x02u},\r
-                       {0x4Bu, 0x02u},\r
-                       {0x50u, 0x02u},\r
-                       {0x52u, 0x50u},\r
-                       {0x53u, 0x02u},\r
-                       {0x62u, 0x80u},\r
-                       {0x68u, 0x20u},\r
-                       {0x69u, 0xD4u},\r
-                       {0x6Bu, 0x48u},\r
-                       {0x72u, 0x02u},\r
-                       {0x73u, 0x03u},\r
-                       {0x78u, 0x02u},\r
-                       {0x80u, 0x80u},\r
-                       {0x8Eu, 0x40u},\r
-                       {0x91u, 0x28u},\r
-                       {0x92u, 0x02u},\r
-                       {0x95u, 0x96u},\r
-                       {0x96u, 0x20u},\r
-                       {0x97u, 0x01u},\r
-                       {0x98u, 0x02u},\r
-                       {0x9Au, 0x01u},\r
-                       {0x9Bu, 0x20u},\r
-                       {0x9Cu, 0x20u},\r
-                       {0x9Du, 0x50u},\r
-                       {0x9Eu, 0x02u},\r
-                       {0x9Fu, 0x41u},\r
-                       {0xA2u, 0x8Bu},\r
-                       {0xA3u, 0x10u},\r
-                       {0xA4u, 0x30u},\r
-                       {0xA7u, 0x23u},\r
-                       {0xA9u, 0x04u},\r
-                       {0xAAu, 0x04u},\r
-                       {0xADu, 0x80u},\r
-                       {0xB2u, 0x90u},\r
-                       {0xC0u, 0x0Fu},\r
-                       {0xC2u, 0x0Eu},\r
-                       {0xC4u, 0x8Fu},\r
-                       {0xCAu, 0x0Fu},\r
-                       {0xCCu, 0x0Fu},\r
-                       {0xCEu, 0x0Fu},\r
-                       {0xD0u, 0x07u},\r
-                       {0xD2u, 0x0Cu},\r
-                       {0xD8u, 0x08u},\r
-                       {0xDEu, 0x01u},\r
-                       {0xE8u, 0x08u},\r
-                       {0xEAu, 0x04u},\r
-                       {0x8Fu, 0x40u},\r
-                       {0x90u, 0x20u},\r
-                       {0x96u, 0x04u},\r
-                       {0x97u, 0x80u},\r
-                       {0x9Cu, 0x40u},\r
-                       {0x9Du, 0x08u},\r
-                       {0xA7u, 0x40u},\r
-                       {0xA9u, 0x09u},\r
-                       {0xADu, 0x01u},\r
-                       {0xAFu, 0x80u},\r
-                       {0xB1u, 0x22u},\r
-                       {0xB2u, 0x10u},\r
-                       {0xB4u, 0x04u},\r
-                       {0xE4u, 0x40u},\r
-                       {0xE8u, 0x08u},\r
-                       {0xEAu, 0x83u},\r
-                       {0xEEu, 0x20u},\r
-                       {0x00u, 0x33u},\r
-                       {0x02u, 0xCCu},\r
-                       {0x08u, 0x55u},\r
-                       {0x09u, 0x01u},\r
-                       {0x0Au, 0xAAu},\r
-                       {0x10u, 0x69u},\r
-                       {0x12u, 0x96u},\r
-                       {0x16u, 0xFFu},\r
+                       {0xCEu, 0xF8u},\r
+                       {0xD8u, 0x70u},\r
+                       {0xDEu, 0x10u},\r
+                       {0xEAu, 0x80u},\r
+                       {0xEEu, 0x06u},\r
+                       {0x8Du, 0x08u},\r
+                       {0x8Fu, 0x02u},\r
+                       {0x9Du, 0x28u},\r
+                       {0x9Fu, 0x02u},\r
+                       {0xA8u, 0x40u},\r
+                       {0xAEu, 0x28u},\r
+                       {0xB0u, 0x08u},\r
+                       {0xB2u, 0x18u},\r
+                       {0xB3u, 0x10u},\r
+                       {0xE0u, 0x50u},\r
+                       {0xE8u, 0x20u},\r
+                       {0xEAu, 0x88u},\r
+                       {0xECu, 0x20u},\r
+                       {0x08u, 0xFFu},\r
+                       {0x14u, 0xFFu},\r
+                       {0x15u, 0x02u},\r
                        {0x1Au, 0xFFu},\r
-                       {0x1Cu, 0x0Fu},\r
-                       {0x1Eu, 0xF0u},\r
-                       {0x26u, 0xFFu},\r
-                       {0x29u, 0x02u},\r
-                       {0x30u, 0xFFu},\r
+                       {0x1Cu, 0x33u},\r
+                       {0x1Eu, 0xCCu},\r
+                       {0x20u, 0x55u},\r
+                       {0x21u, 0x01u},\r
+                       {0x22u, 0xAAu},\r
+                       {0x28u, 0x69u},\r
+                       {0x2Au, 0x96u},\r
+                       {0x2Cu, 0x0Fu},\r
+                       {0x2Eu, 0xF0u},\r
                        {0x31u, 0x02u},\r
                        {0x35u, 0x01u},\r
-                       {0x3Eu, 0x01u},\r
+                       {0x36u, 0xFFu},\r
+                       {0x3Eu, 0x40u},\r
                        {0x3Fu, 0x11u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x05u},\r
-                       {0x82u, 0x0Au},\r
-                       {0x84u, 0x20u},\r
-                       {0x85u, 0x25u},\r
-                       {0x87u, 0x02u},\r
-                       {0x88u, 0x06u},\r
-                       {0x8Au, 0x09u},\r
-                       {0x8Cu, 0x03u},\r
-                       {0x8Du, 0x38u},\r
-                       {0x8Eu, 0x0Cu},\r
-                       {0x94u, 0x10u},\r
-                       {0x97u, 0x38u},\r
-                       {0x99u, 0x04u},\r
-                       {0x9Bu, 0x03u},\r
-                       {0x9Du, 0x40u},\r
-                       {0xA1u, 0x03u},\r
-                       {0xA3u, 0x14u},\r
-                       {0xA5u, 0x09u},\r
-                       {0xA7u, 0x06u},\r
-                       {0xACu, 0x40u},\r
-                       {0xB0u, 0x0Fu},\r
-                       {0xB2u, 0x40u},\r
-                       {0xB3u, 0x38u},\r
-                       {0xB4u, 0x20u},\r
-                       {0xB5u, 0x07u},\r
-                       {0xB6u, 0x10u},\r
-                       {0xB7u, 0x40u},\r
-                       {0xBBu, 0x20u},\r
-                       {0xBEu, 0x55u},\r
-                       {0xBFu, 0x44u},\r
-                       {0xD8u, 0x04u},\r
-                       {0xD9u, 0x08u},\r
-                       {0xDCu, 0x90u},\r
-                       {0xDFu, 0x01u},\r
-                       {0x01u, 0x01u},\r
-                       {0x02u, 0x04u},\r
-                       {0x04u, 0x18u},\r
-                       {0x05u, 0x42u},\r
-                       {0x08u, 0x68u},\r
-                       {0x09u, 0x02u},\r
-                       {0x0Du, 0x08u},\r
-                       {0x11u, 0x08u},\r
-                       {0x16u, 0x01u},\r
-                       {0x19u, 0x01u},\r
-                       {0x1Cu, 0x08u},\r
-                       {0x1Du, 0x02u},\r
-                       {0x1Fu, 0x84u},\r
-                       {0x21u, 0x21u},\r
-                       {0x24u, 0x20u},\r
-                       {0x26u, 0x10u},\r
-                       {0x27u, 0x01u},\r
-                       {0x29u, 0x20u},\r
-                       {0x2Du, 0x08u},\r
-                       {0x2Fu, 0x40u},\r
-                       {0x36u, 0x10u},\r
-                       {0x37u, 0x88u},\r
-                       {0x3Au, 0x10u},\r
-                       {0x3Eu, 0x04u},\r
-                       {0x3Fu, 0x80u},\r
-                       {0x7Eu, 0x02u},\r
-                       {0x83u, 0x88u},\r
-                       {0x8Au, 0x02u},\r
-                       {0x8Cu, 0x18u},\r
-                       {0x95u, 0x02u},\r
-                       {0x97u, 0x08u},\r
-                       {0x98u, 0x20u},\r
-                       {0x99u, 0x42u},\r
-                       {0x9Au, 0x15u},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA1u, 0x04u},\r
-                       {0xA4u, 0x04u},\r
-                       {0xA5u, 0x20u},\r
-                       {0xAAu, 0x04u},\r
-                       {0xACu, 0x04u},\r
-                       {0xAFu, 0x04u},\r
-                       {0xB2u, 0x10u},\r
-                       {0xC0u, 0xFAu},\r
-                       {0xC2u, 0x2Fu},\r
-                       {0xC4u, 0x84u},\r
-                       {0xCAu, 0xC4u},\r
-                       {0xCCu, 0x70u},\r
-                       {0xCEu, 0x54u},\r
-                       {0xDEu, 0x10u},\r
-                       {0xE0u, 0x50u},\r
-                       {0xE4u, 0x20u},\r
-                       {0xE8u, 0x01u},\r
-                       {0xEEu, 0x40u},\r
-                       {0x81u, 0x20u},\r
-                       {0x89u, 0x01u},\r
-                       {0x8Bu, 0x01u},\r
-                       {0x98u, 0x20u},\r
-                       {0x99u, 0x42u},\r
-                       {0x9Au, 0x01u},\r
-                       {0xA1u, 0x04u},\r
-                       {0xADu, 0x02u},\r
-                       {0xB4u, 0x20u},\r
-                       {0xB6u, 0x01u},\r
-                       {0xE2u, 0x20u},\r
-                       {0xE4u, 0x01u},\r
-                       {0xE6u, 0x22u},\r
-                       {0xE8u, 0x40u},\r
-                       {0xEEu, 0x04u},\r
-                       {0x81u, 0x04u},\r
-                       {0x85u, 0x40u},\r
-                       {0xACu, 0x21u},\r
-                       {0xB2u, 0x02u},\r
-                       {0xB3u, 0x14u},\r
-                       {0xB5u, 0x10u},\r
-                       {0x06u, 0x04u},\r
-                       {0x0Eu, 0x03u},\r
-                       {0x16u, 0x04u},\r
-                       {0x18u, 0x04u},\r
-                       {0x1Au, 0x02u},\r
-                       {0x1Cu, 0x04u},\r
-                       {0x1Eu, 0x01u},\r
-                       {0x36u, 0x07u},\r
-                       {0x54u, 0x40u},\r
-                       {0x58u, 0x04u},\r
-                       {0x5Bu, 0x0Bu},\r
-                       {0x5Cu, 0x09u},\r
-                       {0x5Du, 0x90u},\r
-                       {0x5Fu, 0x01u},\r
-                       {0x80u, 0x08u},\r
-                       {0x84u, 0x44u},\r
-                       {0x85u, 0x01u},\r
-                       {0x86u, 0x08u},\r
-                       {0x87u, 0x5Eu},\r
-                       {0x88u, 0x04u},\r
-                       {0x89u, 0x39u},\r
-                       {0x8Bu, 0x06u},\r
-                       {0x8Cu, 0x0Cu},\r
-                       {0x8Du, 0x46u},\r
-                       {0x8Eu, 0x40u},\r
-                       {0x90u, 0x30u},\r
-                       {0x94u, 0x01u},\r
-                       {0x95u, 0x42u},\r
-                       {0x96u, 0x2Eu},\r
-                       {0x98u, 0x01u},\r
-                       {0x99u, 0x42u},\r
-                       {0x9Au, 0x12u},\r
-                       {0x9Bu, 0x04u},\r
-                       {0x9Du, 0x46u},\r
-                       {0x9Eu, 0x40u},\r
-                       {0xA0u, 0x4Cu},\r
-                       {0xA1u, 0x46u},\r
-                       {0xA4u, 0x40u},\r
-                       {0xA5u, 0x77u},\r
-                       {0xA6u, 0x0Cu},\r
-                       {0xA7u, 0x08u},\r
-                       {0xA8u, 0x10u},\r
-                       {0xAAu, 0x0Fu},\r
-                       {0xABu, 0x46u},\r
-                       {0xACu, 0x4Cu},\r
-                       {0xADu, 0x04u},\r
-                       {0xAFu, 0x20u},\r
-                       {0xB0u, 0x31u},\r
-                       {0xB1u, 0x08u},\r
-                       {0xB2u, 0x40u},\r
-                       {0xB3u, 0x0Fu},\r
-                       {0xB4u, 0x0Fu},\r
-                       {0xB5u, 0x70u},\r
-                       {0xB7u, 0x01u},\r
+                       {0x84u, 0x06u},\r
+                       {0x85u, 0x0Fu},\r
+                       {0x87u, 0xF0u},\r
+                       {0x8Au, 0x03u},\r
+                       {0x8Bu, 0xFFu},\r
+                       {0x8Eu, 0x05u},\r
+                       {0x91u, 0xFFu},\r
+                       {0x95u, 0x55u},\r
+                       {0x96u, 0x01u},\r
+                       {0x97u, 0xAAu},\r
+                       {0x98u, 0x08u},\r
+                       {0x99u, 0x33u},\r
+                       {0x9Bu, 0xCCu},\r
+                       {0x9Cu, 0x08u},\r
+                       {0xA0u, 0x08u},\r
+                       {0xA4u, 0x08u},\r
+                       {0xA7u, 0xFFu},\r
+                       {0xA9u, 0x96u},\r
+                       {0xABu, 0x69u},\r
+                       {0xB0u, 0x08u},\r
+                       {0xB2u, 0x07u},\r
+                       {0xB5u, 0xFFu},\r
                        {0xB8u, 0x02u},\r
-                       {0xB9u, 0x08u},\r
-                       {0xBBu, 0x30u},\r
-                       {0xBEu, 0x04u},\r
-                       {0xBFu, 0x41u},\r
-                       {0xD4u, 0x09u},\r
+                       {0xBEu, 0x01u},\r
+                       {0xBFu, 0x10u},\r
                        {0xD8u, 0x0Bu},\r
-                       {0xD9u, 0x0Bu},\r
-                       {0xDBu, 0x0Bu},\r
-                       {0xDCu, 0x99u},\r
-                       {0xDDu, 0x90u},\r
+                       {0xD9u, 0x04u},\r
+                       {0xDBu, 0x04u},\r
+                       {0xDCu, 0x09u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x02u},\r
-                       {0x01u, 0x44u},\r
-                       {0x02u, 0x48u},\r
-                       {0x05u, 0x40u},\r
-                       {0x07u, 0x20u},\r
-                       {0x0Au, 0x44u},\r
-                       {0x0Bu, 0x12u},\r
-                       {0x0Du, 0x14u},\r
-                       {0x0Eu, 0x02u},\r
-                       {0x11u, 0x80u},\r
-                       {0x12u, 0x04u},\r
-                       {0x13u, 0x0Au},\r
-                       {0x19u, 0x18u},\r
-                       {0x1Au, 0x44u},\r
-                       {0x1Bu, 0x20u},\r
-                       {0x1Du, 0x40u},\r
-                       {0x20u, 0x30u},\r
-                       {0x21u, 0x20u},\r
-                       {0x22u, 0x90u},\r
-                       {0x23u, 0x94u},\r
-                       {0x29u, 0x20u},\r
-                       {0x2Au, 0x42u},\r
-                       {0x2Bu, 0x20u},\r
-                       {0x30u, 0x20u},\r
+                       {0x00u, 0x10u},\r
+                       {0x05u, 0x28u},\r
+                       {0x07u, 0x02u},\r
+                       {0x09u, 0x10u},\r
+                       {0x0Au, 0x02u},\r
+                       {0x0Bu, 0x20u},\r
+                       {0x0Du, 0x20u},\r
+                       {0x0Eu, 0x21u},\r
+                       {0x10u, 0x08u},\r
+                       {0x11u, 0x40u},\r
+                       {0x12u, 0x80u},\r
+                       {0x14u, 0x40u},\r
+                       {0x16u, 0x20u},\r
+                       {0x1Au, 0x01u},\r
+                       {0x1Eu, 0xA0u},\r
+                       {0x20u, 0x40u},\r
+                       {0x22u, 0x20u},\r
+                       {0x25u, 0x20u},\r
+                       {0x28u, 0x80u},\r
+                       {0x2Cu, 0x08u},\r
+                       {0x2Eu, 0x08u},\r
                        {0x32u, 0x08u},\r
-                       {0x33u, 0x40u},\r
-                       {0x36u, 0x02u},\r
-                       {0x37u, 0x01u},\r
-                       {0x39u, 0x40u},\r
-                       {0x3Au, 0x04u},\r
-                       {0x3Bu, 0x14u},\r
-                       {0x58u, 0x20u},\r
-                       {0x59u, 0x04u},\r
-                       {0x5Au, 0x02u},\r
-                       {0x5Bu, 0x80u},\r
-                       {0x62u, 0x80u},\r
-                       {0x65u, 0x08u},\r
+                       {0x34u, 0x18u},\r
+                       {0x36u, 0x01u},\r
+                       {0x3Du, 0x20u},\r
+                       {0x3Fu, 0x08u},\r
+                       {0x5Cu, 0x02u},\r
+                       {0x5Fu, 0x94u},\r
+                       {0x7Fu, 0x80u},\r
+                       {0x81u, 0x50u},\r
+                       {0x82u, 0x20u},\r
+                       {0x83u, 0x04u},\r
+                       {0x86u, 0x40u},\r
+                       {0x88u, 0x50u},\r
+                       {0x8Au, 0x01u},\r
+                       {0x8Bu, 0x04u},\r
+                       {0x8Cu, 0x18u},\r
+                       {0x8Eu, 0x81u},\r
+                       {0x93u, 0x10u},\r
+                       {0x98u, 0x82u},\r
+                       {0x9Bu, 0x80u},\r
+                       {0xA3u, 0x80u},\r
+                       {0xB3u, 0x10u},\r
+                       {0xC0u, 0xE2u},\r
+                       {0xC2u, 0xE7u},\r
+                       {0xC4u, 0x3Bu},\r
+                       {0xCAu, 0x61u},\r
+                       {0xCCu, 0xE2u},\r
+                       {0xCEu, 0x60u},\r
+                       {0xD6u, 0xF0u},\r
+                       {0xDEu, 0x80u},\r
+                       {0xE0u, 0xF0u},\r
+                       {0xE4u, 0x24u},\r
+                       {0xEAu, 0x08u},\r
+                       {0xECu, 0x80u},\r
+                       {0xEEu, 0x09u},\r
+                       {0x83u, 0x80u},\r
+                       {0x84u, 0x02u},\r
+                       {0x98u, 0x80u},\r
+                       {0xA3u, 0x80u},\r
+                       {0xE2u, 0x0Cu},\r
+                       {0xE6u, 0x09u},\r
+                       {0x83u, 0x80u},\r
+                       {0x84u, 0x80u},\r
+                       {0xE6u, 0x02u},\r
+                       {0x80u, 0x01u},\r
+                       {0x94u, 0x02u},\r
+                       {0xB5u, 0x04u},\r
+                       {0x05u, 0x05u},\r
+                       {0x06u, 0x0Au},\r
+                       {0x0Eu, 0x99u},\r
+                       {0x15u, 0x01u},\r
+                       {0x17u, 0x14u},\r
+                       {0x1Du, 0x8Du},\r
+                       {0x1Eu, 0x02u},\r
+                       {0x1Fu, 0x1Au},\r
+                       {0x27u, 0x40u},\r
+                       {0x2Eu, 0x02u},\r
+                       {0x2Fu, 0x0Au},\r
+                       {0x36u, 0x6Au},\r
+                       {0x3Eu, 0x15u},\r
+                       {0x3Fu, 0x80u},\r
+                       {0x45u, 0xA8u},\r
+                       {0x4Cu, 0x01u},\r
+                       {0x4Du, 0x09u},\r
+                       {0x4Eu, 0x08u},\r
+                       {0x4Fu, 0x01u},\r
+                       {0x56u, 0xA8u},\r
+                       {0x57u, 0x40u},\r
                        {0x66u, 0x10u},\r
-                       {0x67u, 0x02u},\r
-                       {0x78u, 0x02u},\r
-                       {0x7Cu, 0x02u},\r
-                       {0x89u, 0x40u},\r
-                       {0x91u, 0x6Cu},\r
-                       {0x92u, 0x02u},\r
+                       {0x6Cu, 0x10u},\r
+                       {0x6Du, 0x80u},\r
+                       {0x6Eu, 0x95u},\r
+                       {0x6Fu, 0x11u},\r
+                       {0x75u, 0x80u},\r
+                       {0x76u, 0x02u},\r
+                       {0x7Fu, 0x01u},\r
                        {0x93u, 0x02u},\r
-                       {0x94u, 0x10u},\r
-                       {0x96u, 0x60u},\r
-                       {0x97u, 0x14u},\r
-                       {0x98u, 0x02u},\r
-                       {0x99u, 0x24u},\r
-                       {0x9Au, 0x52u},\r
-                       {0x9Bu, 0x6Au},\r
-                       {0x9Du, 0x50u},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA0u, 0x20u},\r
-                       {0xA1u, 0x40u},\r
-                       {0xA2u, 0x09u},\r
-                       {0xA4u, 0x10u},\r
-                       {0xA5u, 0x20u},\r
-                       {0xA7u, 0x20u},\r
-                       {0xC0u, 0xAFu},\r
-                       {0xC2u, 0xEFu},\r
-                       {0xC4u, 0x0Fu},\r
-                       {0xCAu, 0x0Fu},\r
-                       {0xCCu, 0x0Eu},\r
-                       {0xCEu, 0x0Eu},\r
-                       {0xD6u, 0x0Fu},\r
-                       {0xD8u, 0x78u},\r
-                       {0xDEu, 0x81u},\r
-                       {0xEAu, 0x04u},\r
+                       {0x94u, 0x20u},\r
+                       {0x96u, 0x11u},\r
+                       {0x97u, 0x21u},\r
+                       {0x9Au, 0x10u},\r
+                       {0x9Bu, 0x04u},\r
+                       {0x9Du, 0x8Du},\r
+                       {0x9Eu, 0xAAu},\r
+                       {0x9Fu, 0x51u},\r
+                       {0xA1u, 0x20u},\r
+                       {0xA2u, 0x2Eu},\r
+                       {0xA5u, 0x40u},\r
+                       {0xA6u, 0x01u},\r
+                       {0xA7u, 0x48u},\r
+                       {0xC0u, 0xF0u},\r
+                       {0xC2u, 0xF0u},\r
+                       {0xC4u, 0x70u},\r
+                       {0xCAu, 0xB0u},\r
+                       {0xCCu, 0xF0u},\r
+                       {0xCEu, 0xF0u},\r
+                       {0xD0u, 0x70u},\r
+                       {0xD2u, 0x30u},\r
+                       {0xD8u, 0x20u},\r
+                       {0xDEu, 0x10u},\r
                        {0xEEu, 0x0Au},\r
-                       {0x88u, 0x40u},\r
-                       {0x96u, 0x04u},\r
-                       {0x97u, 0x80u},\r
-                       {0x9Cu, 0x40u},\r
-                       {0x9Du, 0x08u},\r
-                       {0xA8u, 0x10u},\r
-                       {0xE0u, 0x80u},\r
+                       {0x9Du, 0x20u},\r
                        {0xEEu, 0x0Au},\r
-                       {0xB2u, 0x04u},\r
-                       {0xB3u, 0x40u},\r
-                       {0xB5u, 0x08u},\r
-                       {0xE8u, 0x40u},\r
-                       {0xECu, 0xA0u},\r
+                       {0xB5u, 0x20u},\r
+                       {0xE8u, 0x10u},\r
                        {0x33u, 0x80u},\r
                        {0x36u, 0x40u},\r
-                       {0x5Au, 0x80u},\r
+                       {0x56u, 0x08u},\r
+                       {0x58u, 0x04u},\r
                        {0x5Eu, 0x02u},\r
-                       {0x62u, 0x01u},\r
-                       {0x63u, 0x02u},\r
-                       {0x67u, 0x08u},\r
-                       {0x82u, 0x03u},\r
-                       {0x87u, 0x04u},\r
+                       {0x62u, 0x02u},\r
+                       {0x66u, 0x04u},\r
+                       {0x82u, 0x04u},\r
                        {0xCCu, 0x30u},\r
-                       {0xD4u, 0x80u},\r
+                       {0xD4u, 0x40u},\r
                        {0xD6u, 0xC0u},\r
                        {0xD8u, 0xC0u},\r
-                       {0xE2u, 0x20u},\r
-                       {0xE6u, 0x30u},\r
-                       {0x51u, 0x08u},\r
-                       {0x53u, 0x01u},\r
-                       {0x83u, 0x05u},\r
-                       {0x8Eu, 0x40u},\r
-                       {0x96u, 0x80u},\r
-                       {0x9Au, 0x02u},\r
-                       {0xA6u, 0x41u},\r
+                       {0xE2u, 0x80u},\r
+                       {0x52u, 0x20u},\r
+                       {0x5Fu, 0x20u},\r
+                       {0x8Fu, 0x04u},\r
+                       {0x94u, 0x02u},\r
+                       {0x9Eu, 0x08u},\r
+                       {0xA6u, 0x40u},\r
                        {0xA7u, 0x80u},\r
-                       {0xAFu, 0x01u},\r
-                       {0xD4u, 0xA0u},\r
-                       {0xE0u, 0x80u},\r
-                       {0xE6u, 0x20u},\r
-                       {0xEEu, 0x10u},\r
-                       {0x8Eu, 0x01u},\r
-                       {0x9Au, 0x02u},\r
-                       {0x9Fu, 0x04u},\r
-                       {0xA6u, 0x41u},\r
+                       {0xAAu, 0x01u},\r
+                       {0xACu, 0x04u},\r
+                       {0xAEu, 0x02u},\r
+                       {0xB4u, 0x01u},\r
+                       {0xD4u, 0x20u},\r
+                       {0xD6u, 0x20u},\r
+                       {0xEAu, 0x50u},\r
+                       {0xEEu, 0x80u},\r
+                       {0x86u, 0x08u},\r
+                       {0x8Eu, 0x08u},\r
+                       {0x94u, 0x02u},\r
+                       {0x9Eu, 0x08u},\r
+                       {0xA3u, 0x04u},\r
+                       {0xA6u, 0x60u},\r
                        {0xA7u, 0x80u},\r
-                       {0xB5u, 0x08u},\r
-                       {0x81u, 0x04u},\r
-                       {0x9Au, 0x02u},\r
-                       {0x9Fu, 0x84u},\r
-                       {0xA6u, 0x40u},\r
+                       {0xABu, 0x20u},\r
+                       {0xE6u, 0x40u},\r
+                       {0xEAu, 0x80u},\r
+                       {0x94u, 0x02u},\r
+                       {0x98u, 0x20u},\r
+                       {0xA3u, 0x04u},\r
+                       {0xA6u, 0x48u},\r
                        {0xA7u, 0x80u},\r
-                       {0xABu, 0x80u},\r
-                       {0xE4u, 0x80u},\r
-                       {0xE8u, 0x80u},\r
-                       {0x0Eu, 0x80u},\r
-                       {0x10u, 0x80u},\r
-                       {0x50u, 0x04u},\r
-                       {0x54u, 0x10u},\r
-                       {0x5Au, 0x10u},\r
+                       {0xAAu, 0x20u},\r
+                       {0xB0u, 0x20u},\r
+                       {0xEEu, 0x80u},\r
+                       {0x0Cu, 0x02u},\r
+                       {0x12u, 0x20u},\r
+                       {0x53u, 0x80u},\r
+                       {0x55u, 0x80u},\r
+                       {0x58u, 0x80u},\r
                        {0x5Cu, 0x40u},\r
+                       {0x86u, 0x20u},\r
                        {0xC2u, 0x04u},\r
                        {0xC4u, 0x08u},\r
                        {0xD4u, 0x07u},\r
                        {0xD6u, 0x04u},\r
-                       {0x03u, 0x01u},\r
-                       {0x04u, 0x80u},\r
-                       {0x06u, 0x80u},\r
-                       {0x08u, 0x20u},\r
-                       {0x09u, 0x04u},\r
-                       {0x0Eu, 0x02u},\r
-                       {0x0Fu, 0x40u},\r
-                       {0x80u, 0x04u},\r
-                       {0x86u, 0x40u},\r
-                       {0x94u, 0x08u},\r
-                       {0x96u, 0x10u},\r
-                       {0x9Cu, 0x20u},\r
-                       {0xA2u, 0x40u},\r
-                       {0xA4u, 0x10u},\r
-                       {0xA8u, 0x20u},\r
-                       {0xB4u, 0xC0u},\r
+                       {0x01u, 0x20u},\r
+                       {0x06u, 0x40u},\r
+                       {0x07u, 0x08u},\r
+                       {0x08u, 0x02u},\r
+                       {0x0Bu, 0x08u},\r
+                       {0x0Du, 0x04u},\r
+                       {0x0Fu, 0x02u},\r
+                       {0x80u, 0x02u},\r
+                       {0x81u, 0x20u},\r
+                       {0x85u, 0x04u},\r
+                       {0x87u, 0x04u},\r
+                       {0x94u, 0x40u},\r
+                       {0x9Cu, 0x80u},\r
+                       {0xA0u, 0x02u},\r
+                       {0xA5u, 0x80u},\r
+                       {0xA7u, 0x80u},\r
                        {0xC0u, 0x07u},\r
                        {0xC2u, 0x0Fu},\r
-                       {0xE8u, 0x02u},\r
-                       {0xEEu, 0x02u},\r
-                       {0x90u, 0x80u},\r
-                       {0x93u, 0x40u},\r
-                       {0x9Bu, 0x01u},\r
-                       {0xA2u, 0x01u},\r
-                       {0xA4u, 0x10u},\r
-                       {0xAAu, 0x10u},\r
-                       {0xB2u, 0x80u},\r
-                       {0xB5u, 0x04u},\r
-                       {0xEEu, 0x06u},\r
+                       {0x80u, 0x40u},\r
+                       {0x88u, 0x80u},\r
+                       {0x8Fu, 0x80u},\r
+                       {0x94u, 0x40u},\r
+                       {0x9Bu, 0x08u},\r
+                       {0x9Cu, 0x80u},\r
+                       {0xA5u, 0x80u},\r
+                       {0xA7u, 0x80u},\r
+                       {0xA8u, 0x02u},\r
+                       {0xAEu, 0x40u},\r
+                       {0xAFu, 0x01u},\r
+                       {0xE0u, 0x06u},\r
                        {0x08u, 0x08u},\r
                        {0x0Fu, 0x40u},\r
-                       {0xA8u, 0x40u},\r
-                       {0xACu, 0x10u},\r
-                       {0xAFu, 0x01u},\r
-                       {0xB3u, 0x40u},\r
-                       {0xB6u, 0x01u},\r
+                       {0xAFu, 0x08u},\r
+                       {0xB1u, 0x80u},\r
                        {0xC2u, 0x0Cu},\r
-                       {0xEAu, 0x0Cu},\r
-                       {0x23u, 0x80u},\r
-                       {0x27u, 0x04u},\r
-                       {0x9Au, 0x22u},\r
-                       {0x9Du, 0x04u},\r
-                       {0x9Fu, 0x84u},\r
-                       {0xAAu, 0x20u},\r
+                       {0xE8u, 0x04u},\r
+                       {0x22u, 0x08u},\r
+                       {0x24u, 0x02u},\r
+                       {0x94u, 0x02u},\r
+                       {0x98u, 0x20u},\r
+                       {0xA3u, 0x04u},\r
+                       {0xA6u, 0x08u},\r
                        {0xAEu, 0x40u},\r
                        {0xAFu, 0x80u},\r
                        {0xC8u, 0x60u},\r
-                       {0xEAu, 0x20u},\r
                        {0xEEu, 0x50u},\r
-                       {0x05u, 0x04u},\r
-                       {0x56u, 0x22u},\r
-                       {0x9Au, 0x22u},\r
-                       {0x9Du, 0x04u},\r
+                       {0x05u, 0x02u},\r
+                       {0x57u, 0x04u},\r
+                       {0x58u, 0x20u},\r
+                       {0x81u, 0x02u},\r
+                       {0x98u, 0x20u},\r
+                       {0xA3u, 0x04u},\r
                        {0xC0u, 0x20u},\r
-                       {0xD4u, 0x40u},\r
-                       {0xD6u, 0x20u},\r
+                       {0xD4u, 0xC0u},\r
+                       {0xE4u, 0x20u},\r
                        {0xACu, 0x08u},\r
                        {0xAFu, 0x40u},\r
                        {0x01u, 0x01u},\r
@@ -1347,28 +1283,28 @@ void cyfitter_cfg(void)
                static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
                        /* address, size */\r
                        {(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
-                       {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1664u},\r
-                       {(void CYFAR *)(CYDEV_UCFG_B0_P3_ROUTE_BASE), 2304u},\r
-                       {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
+                       {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
+                       {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 512u},\r
+                       {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), 1408u},\r
                        {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
                        {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
                        {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},\r
                };\r
 \r
-               /* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */\r
-               static const uint8 CYCODE BS_UDB_1_2_0_CONFIG_VAL[] = {\r
-                       0xC0u, 0x01u, 0x02u, 0x00u, 0x1Fu, 0x22u, 0x20u, 0x08u, 0xC0u, 0x08u, 0x08u, 0x21u, 0x90u, 0x01u, 0x40u, 0x00u, \r
-                       0x00u, 0x10u, 0x60u, 0x80u, 0x00u, 0x40u, 0xFFu, 0x00u, 0x7Fu, 0x01u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, \r
-                       0xC0u, 0x40u, 0x01u, 0x00u, 0xC0u, 0x01u, 0x04u, 0x00u, 0x80u, 0x07u, 0x00u, 0x18u, 0x00u, 0x04u, 0x9Fu, 0x00u, \r
-                       0xFFu, 0x80u, 0x00u, 0x3Fu, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x88u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x04u, \r
-                       0x32u, 0x06u, 0x50u, 0x00u, 0x04u, 0xDEu, 0xFCu, 0xB0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
-                       0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, \r
+               /* UDB_1_1_1_CONFIG Address: CYDEV_UCFG_B1_P3_U0_BASE Size (bytes): 128 */\r
+               static const uint8 CYCODE BS_UDB_1_1_1_CONFIG_VAL[] = {\r
+                       0x24u, 0xC0u, 0x10u, 0x02u, 0x11u, 0xC0u, 0x22u, 0x04u, 0x08u, 0xC0u, 0x00u, 0x08u, 0xDCu, 0x00u, 0x00u, 0x9Fu, \r
+                       0x0Cu, 0x00u, 0xD0u, 0x60u, 0xD0u, 0x7Fu, 0x0Cu, 0x80u, 0x30u, 0x00u, 0x0Fu, 0xFFu, 0xDCu, 0x90u, 0x00u, 0x40u, \r
+                       0x00u, 0xC0u, 0x80u, 0x01u, 0x21u, 0x00u, 0x1Eu, 0x00u, 0xD4u, 0x1Fu, 0x08u, 0x20u, 0x00u, 0x80u, 0x00u, 0x00u, \r
+                       0x30u, 0xFFu, 0x0Fu, 0x00u, 0x80u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x50u, 0x01u, \r
+                       0x26u, 0x03u, 0x10u, 0x00u, 0x05u, 0xDEu, 0xFBu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+                       0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x08u, 0x04u, 0x08u, 0x08u, 0x09u, 0x99u, 0x00u, 0x01u, \r
                        0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
                        0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
 \r
                static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
                        /* dest, src, size */\r
-                       {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), BS_UDB_1_2_0_CONFIG_VAL, 128u},\r
+                       {(void CYFAR *)(CYDEV_UCFG_B1_P3_U0_BASE), BS_UDB_1_1_1_CONFIG_VAL, 128u},\r
                };\r
 \r
                uint8 CYDATA i;\r
index 1cdc92f..099248a 100755 (executable)
 .set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
-/* SCSI_ATN_ISR */\r
-.set SCSI_ATN_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_ATN_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_ATN_ISR__INTC_MASK, 0x800\r
-.set SCSI_ATN_ISR__INTC_NUMBER, 11\r
-.set SCSI_ATN_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_ATN_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_11\r
-.set SCSI_ATN_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_ATN_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
 /* SCSI_Out_DBx */\r
 .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
 .set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX\r
 .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB07_ST\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
 .set SDCard_BSPIM_RxStsReg__4__POS, 4\r
 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
 .set SDCard_BSPIM_RxStsReg__6__POS, 6\r
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB06_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB06_ST\r
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
 .set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
 .set SDCard_BSPIM_TxStsReg__1__POS, 1\r
 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
 .set SDCard_BSPIM_TxStsReg__4__POS, 4\r
 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB07_08_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB07_08_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB07_08_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB07_08_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB07_08_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB07_08_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB07_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB07_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB07_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB07_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB07_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB07_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB07_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB07_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB07_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
+.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB06_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB06_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB06_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB06_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB06_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB06_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
 \r
 /* USBFS_dp_int */\r
 .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 /* SCSI_CTL_IO */\r
 .set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL\r
 .set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
 \r
 /* SCSI_In_DBx */\r
 .set SCSI_In_DBx__0__AG, CYREG_PRT12_AG\r
 /* scsiTarget */\r
 .set scsiTarget_StatusReg__0__MASK, 0x01\r
 .set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
 .set scsiTarget_StatusReg__1__MASK, 0x02\r
 .set scsiTarget_StatusReg__1__POS, 1\r
 .set scsiTarget_StatusReg__2__MASK, 0x04\r
 .set scsiTarget_StatusReg__3__MASK, 0x08\r
 .set scsiTarget_StatusReg__3__POS, 3\r
 .set scsiTarget_StatusReg__MASK, 0x0F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB00_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB00_ST\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST\r
 .set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
 .set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
 .set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK\r
 /* SD_Clk_Ctl */\r
 .set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
 .set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
 \r
 /* USBFS_ep_0 */\r
 .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set SCSI_ATN__DM2, CYREG_PRT12_DM2\r
 .set SCSI_ATN__DR, CYREG_PRT12_DR\r
 .set SCSI_ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_ATN__INTSTAT, CYREG_PICU12_INTSTAT\r
 .set SCSI_ATN__INT__MASK, 0x20\r
 .set SCSI_ATN__INT__PC, CYREG_PRT12_PC5\r
 .set SCSI_ATN__INT__PORT, 12\r
 .set SCSI_ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
 .set SCSI_ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
 .set SCSI_ATN__SLW, CYREG_PRT12_SLW\r
-.set SCSI_ATN__SNAP, CYREG_PICU12_SNAP\r
 \r
 /* SCSI_Out */\r
 .set SCSI_Out__0__AG, CYREG_PRT4_AG\r
 .set CYDEV_CHIP_FAMILY_PSOC5, 3\r
 .set CYDEV_CHIP_DIE_PSOC5LP, 4\r
 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP\r
-.set BCLK__BUS_CLK__HZ, 64000000\r
-.set BCLK__BUS_CLK__KHZ, 64000\r
-.set BCLK__BUS_CLK__MHZ, 64\r
+.set BCLK__BUS_CLK__HZ, 60000000\r
+.set BCLK__BUS_CLK__KHZ, 60000\r
+.set BCLK__BUS_CLK__MHZ, 60\r
 .set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT\r
 .set CYDEV_CHIP_DIE_LEOPARD, 1\r
 .set CYDEV_CHIP_DIE_PANTHER, 3\r
index e4afa13..962465c 100755 (executable)
@@ -33,16 +33,6 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
 USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
 USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
 \r
-/* SCSI_ATN_ISR */\r
-SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_ATN_ISR__INTC_MASK EQU 0x800\r
-SCSI_ATN_ISR__INTC_NUMBER EQU 11\r
-SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11\r
-SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
 /* SCSI_Out_DBx */\r
 SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
 SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
@@ -488,34 +478,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
 \r
 /* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
@@ -523,13 +513,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
 SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
 SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
 SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
@@ -539,28 +529,32 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
 \r
 /* USBFS_dp_int */\r
 USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
@@ -575,24 +569,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 /* SCSI_CTL_IO */\r
 SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
 SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
 \r
 /* SCSI_In_DBx */\r
 SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
@@ -1051,8 +1045,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02
 /* scsiTarget */\r
 scsiTarget_StatusReg__0__MASK EQU 0x01\r
 scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
 scsiTarget_StatusReg__1__MASK EQU 0x02\r
 scsiTarget_StatusReg__1__POS EQU 1\r
 scsiTarget_StatusReg__2__MASK EQU 0x04\r
@@ -1060,9 +1054,9 @@ scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08\r
 scsiTarget_StatusReg__3__POS EQU 3\r
 scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
 scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
 scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
 scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
@@ -1112,24 +1106,24 @@ scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
 /* SD_Clk_Ctl */\r
 SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
 SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
 \r
 /* USBFS_ep_0 */\r
 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
@@ -1301,7 +1295,6 @@ SCSI_ATN__DM1 EQU CYREG_PRT12_DM1
 SCSI_ATN__DM2 EQU CYREG_PRT12_DM2\r
 SCSI_ATN__DR EQU CYREG_PRT12_DR\r
 SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_ATN__INTSTAT EQU CYREG_PICU12_INTSTAT\r
 SCSI_ATN__INT__MASK EQU 0x20\r
 SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5\r
 SCSI_ATN__INT__PORT EQU 12\r
@@ -1322,7 +1315,6 @@ SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
 SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
 SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
 SCSI_ATN__SLW EQU CYREG_PRT12_SLW\r
-SCSI_ATN__SNAP EQU CYREG_PICU12_SNAP\r
 \r
 /* SCSI_Out */\r
 SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
@@ -2671,9 +2663,9 @@ CYDEV_CHIP_MEMBER_5B EQU 4
 CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
 CYDEV_CHIP_DIE_PSOC5LP EQU 4\r
 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP\r
-BCLK__BUS_CLK__HZ EQU 64000000\r
-BCLK__BUS_CLK__KHZ EQU 64000\r
-BCLK__BUS_CLK__MHZ EQU 64\r
+BCLK__BUS_CLK__HZ EQU 60000000\r
+BCLK__BUS_CLK__KHZ EQU 60000\r
+BCLK__BUS_CLK__MHZ EQU 60\r
 CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
 CYDEV_CHIP_DIE_LEOPARD EQU 1\r
 CYDEV_CHIP_DIE_PANTHER EQU 3\r
index bb7ab3a..05b91a0 100755 (executable)
@@ -33,16 +33,6 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
 USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
 USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
 \r
-; SCSI_ATN_ISR\r
-SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_ATN_ISR__INTC_MASK EQU 0x800\r
-SCSI_ATN_ISR__INTC_NUMBER EQU 11\r
-SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11\r
-SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
 ; SCSI_Out_DBx\r
 SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
 SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
@@ -488,34 +478,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
 \r
 ; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
@@ -523,13 +513,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
 SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
 SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
 SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
@@ -539,28 +529,32 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
 \r
 ; USBFS_dp_int\r
 USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
@@ -575,24 +569,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 ; SCSI_CTL_IO\r
 SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
 SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
 \r
 ; SCSI_In_DBx\r
 SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
@@ -1051,8 +1045,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02
 ; scsiTarget\r
 scsiTarget_StatusReg__0__MASK EQU 0x01\r
 scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
 scsiTarget_StatusReg__1__MASK EQU 0x02\r
 scsiTarget_StatusReg__1__POS EQU 1\r
 scsiTarget_StatusReg__2__MASK EQU 0x04\r
@@ -1060,9 +1054,9 @@ scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08\r
 scsiTarget_StatusReg__3__POS EQU 3\r
 scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
 scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
 scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
 scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
@@ -1112,24 +1106,24 @@ scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
 ; SD_Clk_Ctl\r
 SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
 SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
 \r
 ; USBFS_ep_0\r
 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
@@ -1301,7 +1295,6 @@ SCSI_ATN__DM1 EQU CYREG_PRT12_DM1
 SCSI_ATN__DM2 EQU CYREG_PRT12_DM2\r
 SCSI_ATN__DR EQU CYREG_PRT12_DR\r
 SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_ATN__INTSTAT EQU CYREG_PICU12_INTSTAT\r
 SCSI_ATN__INT__MASK EQU 0x20\r
 SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5\r
 SCSI_ATN__INT__PORT EQU 12\r
@@ -1322,7 +1315,6 @@ SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
 SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
 SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
 SCSI_ATN__SLW EQU CYREG_PRT12_SLW\r
-SCSI_ATN__SNAP EQU CYREG_PICU12_SNAP\r
 \r
 ; SCSI_Out\r
 SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
@@ -2671,9 +2663,9 @@ CYDEV_CHIP_MEMBER_5B EQU 4
 CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
 CYDEV_CHIP_DIE_PSOC5LP EQU 4\r
 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP\r
-BCLK__BUS_CLK__HZ EQU 64000000\r
-BCLK__BUS_CLK__KHZ EQU 64000\r
-BCLK__BUS_CLK__MHZ EQU 64\r
+BCLK__BUS_CLK__HZ EQU 60000000\r
+BCLK__BUS_CLK__KHZ EQU 60000\r
+BCLK__BUS_CLK__MHZ EQU 60\r
 CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
 CYDEV_CHIP_DIE_LEOPARD EQU 1\r
 CYDEV_CHIP_DIE_PANTHER EQU 3\r
index 3b9f84b..92a14ac 100755 (executable)
@@ -45,7 +45,6 @@
 #include <SCSI_ATN_aliases.h>\r
 #include <SCSI_ATN.h>\r
 #include <SCSI_RST_ISR.h>\r
-#include <SCSI_ATN_ISR.h>\r
 #include <LED1_aliases.h>\r
 #include <LED1.h>\r
 #include <SDCard.h>\r
index 658cb56..b9aff61 100755 (executable)
@@ -1,12 +1,12 @@
 <?xml version="1.0" encoding="utf-8"?>\r
 <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
+  <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
     <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
@@ -87,6 +87,8 @@
     <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
   </block>\r
   <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
     <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
     <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
     <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
     <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   </block>\r
-  <block name="SCSI_ATN_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
-    <register name="SD_Clk_Ctl_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />\r
+    <register name="SD_Clk_Ctl_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" />\r
   </block>\r
+  <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_CTL_IO" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
-    <register name="SCSI_CTL_IO_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
+    <register name="SCSI_CTL_IO_CONTROL_REG" address="0x40006470" bitWidth="8" desc="" />\r
   </block>\r
 </blockRegMap>
\ No newline at end of file
index 7e702d8..821b57b 100755 (executable)
Binary files a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr and b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr differ
index c6d5f47..3c24266 100755 (executable)
Binary files a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit differ
index 9bcf221..63786d6 100755 (executable)
 <PropertyDeltas />\r
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="blinky.c" persistent=".\blinky.c">\r
-<Hidden v="False" />\r
-</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
-<build_action v="C_FILE" />\r
-<PropertyDeltas />\r
-</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
-<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="diagnostic.c" persistent=".\diagnostic.c">\r
 <Hidden v="False" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <PropertyDeltas />\r
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="blinky.h" persistent=".\blinky.h">\r
-<Hidden v="False" />\r
-</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
-<build_action v="NONE" />\r
-<PropertyDeltas />\r
-</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
-<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="bits.h" persistent=".\bits.h">\r
 <Hidden v="False" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_ATN_ISR" persistent="">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
 <dependencies>\r
 <CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_ATN_ISR.c" persistent=".\Generated_Source\PSoC5\SCSI_ATN_ISR.c">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <build_action v="ARM_C_FILE" />\r
 <PropertyDeltas />\r
 <CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_ATN_ISR.h" persistent=".\Generated_Source\PSoC5\SCSI_ATN_ISR.h">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <build_action v="NONE" />\r
 <PropertyDeltas />\r
index 9b19422..3770159 100755 (executable)
     <peripheral>\r
       <name>SD_Clk_Ctl</name>\r
       <description>No description available</description>\r
-      <baseAddress>0x40006471</baseAddress>\r
+      <baseAddress>0x40006475</baseAddress>\r
       <addressBlock>\r
         <offset>0</offset>\r
         <size>0x1</size>\r
     <peripheral>\r
       <name>SCSI_CTL_IO</name>\r
       <description>No description available</description>\r
-      <baseAddress>0x40006472</baseAddress>\r
+      <baseAddress>0x40006470</baseAddress>\r
       <addressBlock>\r
         <offset>0</offset>\r
         <size>0x1</size>\r
index 5eb78a5..430cf96 100755 (executable)
Binary files a/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/blinky.c b/software/SCSI2SD/SCSI2SD.cydsn/blinky.c
deleted file mode 100755 (executable)
index 4d9d7ae..0000000
+++ /dev/null
@@ -1,31 +0,0 @@
-//     Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
-//\r
-//     This file is part of SCSI2SD.\r
-//\r
-//     SCSI2SD is free software: you can redistribute it and/or modify\r
-//     it under the terms of the GNU General Public License as published by\r
-//     the Free Software Foundation, either version 3 of the License, or\r
-//     (at your option) any later version.\r
-//\r
-//     SCSI2SD is distributed in the hope that it will be useful,\r
-//     but WITHOUT ANY WARRANTY; without even the implied warranty of\r
-//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
-//     GNU General Public License for more details.\r
-//\r
-//     You should have received a copy of the GNU General Public License\r
-//     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
-\r
-#include "blinky.h"\r
-#include "device.h"\r
-\r
-void scsi2sd_test_blink(void)\r
-{\r
-       // Toggle LED.\r
-       while (1)\r
-       {\r
-               LED1_Write(0);\r
-               CyDelay(1000); // ms\r
-               LED1_Write(1);\r
-               CyDelay(250); // ms\r
-       }\r
-}\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/blinky.h b/software/SCSI2SD/SCSI2SD.cydsn/blinky.h
deleted file mode 100755 (executable)
index a8fde4b..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-//     Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
-//\r
-//     This file is part of SCSI2SD.\r
-//\r
-//     SCSI2SD is free software: you can redistribute it and/or modify\r
-//     it under the terms of the GNU General Public License as published by\r
-//     the Free Software Foundation, either version 3 of the License, or\r
-//     (at your option) any later version.\r
-//\r
-//     SCSI2SD is distributed in the hope that it will be useful,\r
-//     but WITHOUT ANY WARRANTY; without even the implied warranty of\r
-//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
-//     GNU General Public License for more details.\r
-//\r
-//     You should have received a copy of the GNU General Public License\r
-//     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
-\r
-#ifndef SCSI2SD_BLINKY_H\r
-#define SCSI2SD_BLINKY_H\r
-\r
-// Helloworld LED blink test.\r
-void scsi2sd_test_blink(void);\r
-\r
-\r
-#endif // SCSI2SD_POST_H\r
index 674d752..98578f9 100755 (executable)
@@ -1,4 +1,4 @@
-//     Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//     Copyright (C) 2014 Michael McMaster <michael@codesrc.com>\r
 //\r
 //     This file is part of SCSI2SD.\r
 //\r
@@ -20,6 +20,9 @@
 #include "USBFS.h"\r
 #include "led.h"\r
 \r
+#include "scsi.h"\r
+#include "scsiPhy.h"\r
+\r
 #include <string.h>\r
 \r
 // CYDEV_EEPROM_ROW_SIZE == 16.\r
@@ -31,7 +34,7 @@ static Config shadow =
        0, // SCSI ID\r
        " codesrc", // vendor  (68k Apple Drive Setup: Set to " SEAGATE")\r
        "         SCSI2SD", //prodId (68k Apple Drive Setup: Set to "          ST225N")\r
-       "2.0a", // revision (68k Apple Drive Setup: Set to "1.0 ")\r
+       " 3.2", // revision (68k Apple Drive Setup: Set to "1.0 ")\r
        1, // enable parity\r
        0, // disable unit attention,\r
        0 // Max blocks (0 == disabled)\r
@@ -94,7 +97,7 @@ void configInit()
 {\r
        int shadowRows, shadowBytes;\r
        uint8* eeprom = (uint8*)CYDEV_EE_BASE;\r
-       \r
+\r
        // We could map cfgPtr directly into the EEPROM memory,\r
        // but that would waste power. Copy it to RAM then turn off\r
        // the EEPROM.\r
@@ -137,21 +140,21 @@ void configPoll()
        {\r
                return;\r
        }\r
-       \r
+\r
        if (reset)\r
        {\r
                USBFS_EnableOutEP(USB_EP_OUT);\r
                usbInEpState = USB_IDLE;\r
-       }       \r
+       }\r
 \r
        if(USBFS_GetEPState(USB_EP_OUT) == USBFS_OUT_BUFFER_FULL)\r
        {\r
                int byteCount;\r
-               \r
+\r
                ledOn();\r
-               \r
+\r
                // The host sent us some data!\r
-                byteCount = USBFS_GetEPCount(USB_EP_OUT);\r
+               byteCount = USBFS_GetEPCount(USB_EP_OUT);\r
 \r
                // Assume that byteCount <= sizeof(shadow).\r
                // shadow should be padded out to 64bytes, which is the largest\r
@@ -162,20 +165,38 @@ void configPoll()
                CFG_EEPROM_Start();\r
                saveConfig(); // write to eeprom\r
                CFG_EEPROM_Stop();\r
-               \r
+\r
                // Send the updated data.\r
                usbInEpState = USB_IDLE;\r
 \r
                // Allow the host to send us another updated config.\r
                USBFS_EnableOutEP(USB_EP_OUT);\r
 \r
-               ledOff();               \r
+               ledOff();\r
        }\r
 \r
        switch (usbInEpState)\r
        {\r
        case USB_IDLE:\r
                shadow.maxBlocks = htonl(shadow.maxBlocks);\r
+               \r
+               #ifdef MM_DEBUG\r
+               memcpy(&shadow.reserved, &scsiDev.cdb, 12);\r
+               shadow.reserved[12] = scsiDev.msgIn;\r
+               shadow.reserved[13] = scsiDev.msgOut;\r
+               shadow.reserved[14] = scsiDev.lastStatus;\r
+               shadow.reserved[15] = scsiDev.lastSense;\r
+               shadow.reserved[16] = scsiDev.phase;\r
+               shadow.reserved[17] = SCSI_ReadPin(SCSI_In_BSY);\r
+               shadow.reserved[18] = SCSI_ReadPin(SCSI_In_SEL);\r
+               shadow.reserved[19] = SCSI_ReadPin(SCSI_ATN_INT);\r
+               shadow.reserved[20] = SCSI_ReadPin(SCSI_RST_INT);\r
+               shadow.reserved[21] = scsiDev.rstCount;\r
+               shadow.reserved[22] = scsiDev.selCount;\r
+               shadow.reserved[23] = scsiDev.msgCount;\r
+               shadow.reserved[24] = scsiDev.watchdogTick++;\r
+               #endif\r
+\r
                USBFS_LoadInEP(USB_EP_IN, (uint8 *)&shadow, sizeof(shadow));\r
                shadow.maxBlocks = ntohl(shadow.maxBlocks);\r
                usbInEpState = USB_DATA_SENT;\r
index c94aaa8..cfd5b9a 100755 (executable)
@@ -1,4 +1,5 @@
 //     Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//     Copyright (C) 2014 Doug Brown <doug@downtowndougbrown.com>\r
 //\r
 //     This file is part of SCSI2SD.\r
 //\r
@@ -118,7 +119,7 @@ static void doWrite(uint32 lba, uint32 blocks)
                scsiDev.phase = DATA_OUT;\r
                scsiDev.dataLen = SCSI_BLOCK_SIZE;\r
                scsiDev.dataPtr = SCSI_BLOCK_SIZE; // TODO FIX scsiDiskPoll()\r
-               \r
+\r
                // No need for single-block reads atm.  Overhead of the\r
                // multi-block read is minimal.\r
                transfer.multiBlock = 1;\r
@@ -144,20 +145,20 @@ static void doRead(uint32 lba, uint32 blocks)
                transfer.currentBlock = 0;\r
                scsiDev.phase = DATA_IN;\r
                scsiDev.dataLen = 0; // No data yet\r
-               \r
+\r
                if ((blocks == 1) ||\r
                        (((uint64) lba) + blocks == blockDev.capacity)\r
                        )\r
                {\r
                        // We get errors on reading the last sector using a multi-sector\r
                        // read :-(\r
-                       transfer.multiBlock = 0;        \r
+                       transfer.multiBlock = 0;\r
                }\r
                else\r
                {\r
                        transfer.multiBlock = 1;\r
                        sdPrepareRead();\r
-               }               \r
+               }\r
        }\r
 }\r
 \r
@@ -354,6 +355,26 @@ int scsiDiskCommand()
                // SYNCHRONIZE CACHE\r
                // We don't have a cache. do nothing.\r
        }\r
+       else if (command == 0x2F)\r
+       {\r
+               // VERIFY\r
+               // TODO: When they supply data to verify, we should read the data and\r
+               // verify it. If they don't supply any data, just say success.\r
+               if ((scsiDev.cdb[1] & 0x02) == 0)\r
+               {\r
+                       // They are asking us to do a medium verification with no data\r
+                       // comparison. Assume success, do nothing.\r
+               }\r
+               else\r
+               {\r
+                       // TODO. This means they are supplying data to verify against.\r
+                       // Technically we should probably grab the data and compare it.\r
+                       scsiDev.status = CHECK_CONDITION;\r
+                       scsiDev.sense.code = ILLEGAL_REQUEST;\r
+                       scsiDev.sense.asc = INVALID_FIELD_IN_CDB;\r
+                       scsiDev.phase = STATUS;\r
+               }\r
+       }\r
        else\r
        {\r
                commandHandled = 0;\r
@@ -406,7 +427,7 @@ void scsiDiskPoll()
                        scsiDev.dataLen = 0;\r
                        scsiDev.dataPtr = 0;\r
                        scsiDev.phase = STATUS;\r
-                       \r
+\r
                        scsiDiskReset();\r
 \r
                        if (writeOk)\r
index 9cc0f23..9cc8f8b 100755 (executable)
@@ -27,8 +27,8 @@ static uint8 StandardResponse[] =
 0x00, // "Direct-access device". AKA standard hard disk\r
 0x00, // device type qualifier\r
 0x02, // Complies with ANSI SCSI-2.\r
-0x02, // SCSI-2 Inquiry response\r
-31, // standard length\r
+0x01, // Response format is compatible with the old CCS format.\r
+0x1f, // standard length.\r
 0, 0, //Reserved\r
 0 // We don't support anything at all\r
 };\r
@@ -36,6 +36,19 @@ static uint8 StandardResponse[] =
 // prodId set by config'S','C','S','I','2','S','D',' ',' ',' ',' ',' ',' ',' ',' ',' ',\r
 // Revision set by config'2','.','0','a'\r
 \r
+/* For reference, here's a dump from an Apple branded 500Mb drive from 1994.\r
+$ sudo sg_inq -H /dev/sdd --len 255\r
+standard INQUIRY:\r
+ 00     00 00 02 01 31 00 00 18  51 55 41 4e 54 55 4d 20    ....1...QUANTUM \r
+ 10     4c 50 53 32 37 30 20 20  20 20 20 20 20 20 20 20    LPS270          \r
+ 20     30 39 30 30 00 00 00 d9  b0 27 34 01 04 b3 01 1b    0900.....'4.....\r
+ 30     07 00 a0 00 00 ff                                   ......\r
+ Vendor identification: QUANTUM \r
+ Product identification: LPS270          \r
+ Product revision level: 0900\r
+*/\r
+\r
+\r
 static const uint8 SupportedVitalPages[] =\r
 {\r
 0x00, // "Direct-access device". AKA standard hard disk\r
@@ -85,7 +98,7 @@ void scsiInquiry()
        uint8 lun = scsiDev.cdb[1] >> 5;\r
        uint32 allocationLength = scsiDev.cdb[4];\r
        if (allocationLength == 0) allocationLength = 256;\r
-\r
+       \r
        if (!evpd)\r
        {\r
                if (pageCode)\r
@@ -98,16 +111,14 @@ void scsiInquiry()
                }\r
                else\r
                {\r
-                       uint8* out;\r
                        memcpy(scsiDev.data, StandardResponse, sizeof(StandardResponse));\r
-                       out = scsiDev.data + sizeof(StandardResponse);\r
-                       memcpy(out, config->vendor, sizeof(config->vendor));\r
-                       out += sizeof(config->vendor);\r
-                       memcpy(out, config->prodId, sizeof(config->prodId));\r
-                       out += sizeof(config->prodId);\r
-                       memcpy(out, config->revision, sizeof(config->revision));\r
-                       out += sizeof(config->revision);                        \r
-                       scsiDev.dataLen = out - scsiDev.data;\r
+                       memcpy(&scsiDev.data[8], config->vendor, sizeof(config->vendor));\r
+                       memcpy(&scsiDev.data[16], config->prodId, sizeof(config->prodId));\r
+                       memcpy(&scsiDev.data[32], config->revision, sizeof(config->revision));\r
+                       scsiDev.dataLen = sizeof(StandardResponse) +\r
+                               sizeof(config->vendor) +\r
+                               sizeof(config->prodId) +\r
+                               sizeof(config->revision);\r
                        scsiDev.phase = DATA_IN;\r
                        \r
                        if (!lun) scsiDev.unitAttention = 0;\r
@@ -153,13 +164,23 @@ void scsiInquiry()
        }\r
 \r
 \r
-       if (scsiDev.phase == DATA_IN && scsiDev.dataLen > allocationLength)\r
+       if (scsiDev.phase == DATA_IN)\r
        {\r
-               // Spec 8.2.5 requires us to simply truncate the response.\r
+               // "real" hard drives send back exactly allocationLenth bytes, padded\r
+               // with zeroes. This only seems to happen for Inquiry responses, and not\r
+               // other commands that also supply an allocation length such as Mode Sense or\r
+               // Request Sense.\r
+               if (scsiDev.dataLen < allocationLength)\r
+               {\r
+                       memset(\r
+                               &scsiDev.data[scsiDev.dataLen],\r
+                               0,\r
+                               allocationLength - scsiDev.dataLen);\r
+               }\r
+               // Spec 8.2.5 requires us to simply truncate the response if it's too big.\r
                scsiDev.dataLen = allocationLength;\r
        }\r
 \r
-\r
        // Set the first byte to indicate LUN presence.\r
        if (lun) // We only support lun 0\r
        {\r
index 4ae3d96..c738428 100755 (executable)
@@ -1,4 +1,4 @@
-//     Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//     Copyright (C) 2014 Michael McMaster <michael@codesrc.com>\r
 //\r
 //     This file is part of SCSI2SD.\r
 //\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
 \r
 #include "device.h"\r
-#include "blinky.h"\r
 #include "scsi.h"\r
 #include "scsiPhy.h"\r
 #include "config.h"\r
 #include "disk.h"\r
 #include "led.h"\r
 \r
-const char* Notice = "Copyright (C) 2013 Michael McMaster <michael@codesrc.com>";\r
+const char* Notice = "Copyright (C) 2014 Michael McMaster <michael@codesrc.com>";\r
 \r
 int main()\r
 {\r
-       // scsi2sd_test_blink(); // Initial test. Will not return.\r
        ledOff();\r
 \r
        // Enable global interrupts.\r
@@ -36,19 +34,17 @@ int main()
 \r
        // Set interrupt handlers.\r
        scsiPhyInit();\r
-       \r
+\r
        configInit();\r
-       \r
+\r
        scsiInit();\r
        scsiDiskInit();\r
 \r
-       // Reading jumpers\r
-       // Is SD card detect asserted ?\r
-\r
-       // TODO POST ?\r
-\r
        while (1)\r
        {\r
+#ifdef MM_DEBUG\r
+               scsiDev.watchdogTick++;\r
+#endif\r
                scsiPoll();\r
                scsiDiskPoll();\r
                configPoll();\r
index 99e89b1..0f5b38c 100755 (executable)
@@ -1,4 +1,5 @@
 //     Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//  Copyright (C) 2014 Doug Brown <doug@downtowndougbrown.com>\r
 //\r
 //     This file is part of SCSI2SD.\r
 //\r
 \r
 #include <string.h>\r
 \r
+static const uint8 ReadWriteErrorRecoveryPage[] =\r
+{\r
+0x01, // Page code\r
+0x0A, // Page length\r
+0x00, // No error recovery options for now\r
+0x00, // Don't try recovery algorithm during reads\r
+0x00, // Correction span 0\r
+0x00, // Head offset count 0,\r
+0x00, // Data strobe offset count 0,\r
+0x00, // Reserved\r
+0x00, // Don't try recovery algorithm during writes\r
+0x00, // Reserved\r
+0x00, 0x00 // Recovery time limit 0 (use default)*/\r
+};\r
+\r
 static const uint8 DisconnectReconnectPage[] =\r
 {\r
 0x02, // Page code\r
@@ -117,13 +133,6 @@ static void pageIn(int pc, int dataIdx, const uint8* pageData, int pageLen)
 static void doModeSense(\r
        int sixByteCmd, int dbd, int pc, int pageCode, int allocLength)\r
 {\r
-       // TODO Apple HD SC Drive Setup requests Page 3 (FormatDevicePage) with an\r
-       // allocLength of 0x20. We need 0x24 if we include a block descriptor, and\r
-       // thus return CHECK CONDITION. A block descriptor is optional, so we\r
-       // chose to ignore it.\r
-       // TODO make configurable\r
-       dbd = 1;\r
-       \r
        if (pc == 0x03) // Saved Values not supported.\r
        {\r
                scsiDev.status = CHECK_CONDITION;\r
@@ -202,6 +211,11 @@ static void doModeSense(
                case 0x3F:\r
                        // EVERYTHING\r
 \r
+               case 0x01:\r
+                       pageIn(pc, idx, ReadWriteErrorRecoveryPage, sizeof(ReadWriteErrorRecoveryPage));\r
+                       idx += sizeof(ReadWriteErrorRecoveryPage);\r
+                       if (pageCode != 0x3f) break;\r
+\r
                case 0x02:\r
                        pageIn(pc, idx, DisconnectReconnectPage, sizeof(DisconnectReconnectPage));\r
                        idx += sizeof(DisconnectReconnectPage);\r
@@ -250,7 +264,7 @@ static void doModeSense(
                        pageIn(pc, idx, AppleVendorPage, sizeof(AppleVendorPage));\r
                        idx += sizeof(AppleVendorPage);\r
                        break;\r
-                       \r
+\r
                default:\r
                        // Unknown Page Code\r
                        pageFound = 0;\r
@@ -263,13 +277,11 @@ static void doModeSense(
 \r
                if (idx > allocLength)\r
                {\r
-                       // Initiator may not have space to receive results.\r
-                       scsiDev.status = CHECK_CONDITION;\r
-                       scsiDev.sense.code = ILLEGAL_REQUEST;\r
-                       scsiDev.sense.asc = INVALID_FIELD_IN_CDB;\r
-                       scsiDev.phase = STATUS;\r
+                       // Chop the reply off early if shorter length is requested\r
+                       idx = allocLength;\r
                }\r
-               else if (pageFound)\r
+\r
+               if (pageFound)\r
                {\r
                        // Go back and fill out the mode data length\r
                        if (sixByteCmd)\r
@@ -288,7 +300,7 @@ static void doModeSense(
                }\r
                else\r
                {\r
-                       // Initiator may not have space to receive results.\r
+                       // Page not found\r
                        scsiDev.status = CHECK_CONDITION;\r
                        scsiDev.sense.code = ILLEGAL_REQUEST;\r
                        scsiDev.sense.asc = INVALID_FIELD_IN_CDB;\r
index 245bf1d..59d9688 100755 (executable)
@@ -1,4 +1,4 @@
-//     Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//     Copyright (C) 2014 Michael McMaster <michael@codesrc.com>\r
 //\r
 //     This file is part of SCSI2SD.\r
 //\r
@@ -95,6 +95,11 @@ static void process_Status()
 {\r
        scsiEnterPhase(STATUS);\r
        scsiWriteByte(scsiDev.status);\r
+       \r
+       #ifdef MM_DEBUG\r
+       scsiDev.lastStatus = scsiDev.status;\r
+       scsiDev.lastSense = scsiDev.sense.code;\r
+       #endif\r
 \r
        // Command Complete occurs AFTER a valid status has been\r
        // sent. then we go bus-free.\r
@@ -323,6 +328,9 @@ static void doReserveRelease()
 \r
 static void scsiReset()\r
 {\r
+#ifdef MM_DEBUG\r
+       scsiDev.rstCount++;\r
+#endif\r
        ledOff();\r
        // done in verilog SCSI_Out_DBx_Write(0);\r
        SCSI_CTL_IO_Write(0);\r
@@ -364,7 +372,7 @@ static void enter_SelectionPhase()
 {\r
        // Ignore stale versions of this flag, but ensure we know the\r
        // current value if the flag is still set.\r
-       scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT);\r
+       scsiDev.atnFlag = 0;\r
        scsiDev.parityError = 0;\r
        scsiDev.dataPtr = 0;\r
        scsiDev.savedDataPtr = 0;\r
@@ -378,15 +386,24 @@ static void enter_SelectionPhase()
 \r
 static void process_SelectionPhase()\r
 {\r
+       int sel = SCSI_ReadPin(SCSI_In_SEL);\r
+       int bsy = SCSI_ReadPin(SCSI_In_BSY);\r
+\r
+       // Only read these pins AFTER SEL and BSY - we don't want to catch them\r
+       // during a transition period.\r
        uint8 mask = scsiReadDBxPins();\r
+       int maskBitCount = countBits(mask);\r
        int goodParity = (Lookup_OddParity[mask] == SCSI_ReadPin(SCSI_In_DBP));\r
 \r
-       int sel = SCSI_ReadPin(SCSI_In_SEL);\r
-       int bsy = SCSI_ReadPin(SCSI_In_BSY);\r
        if (!bsy && sel &&\r
                (mask & scsiDev.scsiIdMask) &&\r
-               (goodParity || !config->enableParity) && (countBits(mask) == 2))\r
+               (goodParity || !config->enableParity) && (maskBitCount <= 2))\r
        {\r
+               // Do we enter MESSAGE OUT immediately ? SCSI 1 and 2 standards says\r
+               // move to MESSAGE OUT if ATN is true before we release BSY.\r
+               // The initiate should assert ATN with SEL.\r
+               scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT);\r
+\r
                // We've been selected!\r
                // Assert BSY - Selection success!\r
                // must happen within 200us (Selection abort time) of seeing our\r
@@ -396,18 +413,29 @@ static void process_SelectionPhase()
                SCSI_SetPin(SCSI_Out_BSY);\r
                ledOn();\r
 \r
+               #ifdef MM_DEBUG\r
+               scsiDev.selCount++;\r
+               #endif\r
+\r
                // Wait until the end of the selection phase.\r
                while (!scsiDev.resetFlag)\r
                {\r
-                       scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
                        if (!SCSI_ReadPin(SCSI_In_SEL))\r
                        {\r
                                break;\r
                        }\r
                }\r
+               // Last chance for the ATN signal! The initiator should have set this\r
+               // previously, but we try and be a little tolerant. This is required\r
+               // for the LCIII to work. I assume ATN is being set before the\r
+               // initiator releases SEL.\r
+               scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT);\r
+\r
 \r
                // Save our initiator now that we're no longer in a time-critical\r
                // section.\r
+               // SCSI1/SASI initiators may not set their own ID.\r
+               if (maskBitCount == 2)\r
                {\r
                        int i;\r
                        uint8 initiatorMask = mask ^ scsiDev.scsiIdMask;\r
@@ -421,11 +449,12 @@ static void process_SelectionPhase()
                                }\r
                        }\r
                }\r
+               else\r
+               {\r
+                       scsiDev.initiatorId = -1;\r
+               }\r
 \r
                scsiDev.phase = COMMAND;\r
-               \r
-               CyDelayUs(2); // DODGY HACK\r
-               scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
        }\r
        else if (!sel)\r
        {\r
@@ -440,6 +469,9 @@ static void process_MessageOut()
        scsiDev.atnFlag = 0;\r
        scsiDev.parityError = 0;\r
        scsiDev.msgOut = scsiReadByte();\r
+#ifdef MM_DEBUG\r
+       scsiDev.msgCount++;\r
+#endif\r
 \r
        if (scsiDev.parityError)\r
        {\r
@@ -531,7 +563,7 @@ static void process_MessageOut()
        else if (scsiDev.msgOut == 0x01)\r
        {\r
                int i;\r
-               \r
+\r
                // Extended message.\r
                int msgLen = scsiReadByte();\r
                if (msgLen == 0) msgLen = 256;\r
@@ -554,31 +586,9 @@ static void process_MessageOut()
        {\r
                messageReject();\r
        }\r
-       \r
-       // Re-check the ATN flag. We won't get another interrupt if\r
-       // it stays asserted.\r
-       CyDelayUs(2); // DODGY HACK\r
-       scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
-}\r
-\r
 \r
-// TODO remove.\r
-// This is a hack until I work out why the ATN ISR isn't\r
-// running when it should.\r
-static int atnErrCount = 0;\r
-static int atnHitCount = 0;\r
-static void checkATN()\r
-{\r
-       int atn = SCSI_ReadPin(SCSI_ATN_INT);\r
-       if (atn && !scsiDev.atnFlag)\r
-       {\r
-               atnErrCount++;\r
-               scsiDev.atnFlag = 1;\r
-       }\r
-       else if (atn && scsiDev.atnFlag)\r
-       {\r
-               atnHitCount++;\r
-       }\r
+       // Re-check the ATN flag in case it stays asserted.\r
+       scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
 }\r
 \r
 void scsiPoll(void)\r
@@ -595,6 +605,14 @@ void scsiPoll(void)
                {\r
                        scsiDev.phase = BUS_BUSY;\r
                }\r
+               // The Arbitration phase is optional for SCSI1/SASI hosts if there is only\r
+               // one initiator in the chain. Support this by moving\r
+               // straight to selection if SEL is asserted.\r
+               // ie. the initiator won't assert BSY and it's own ID before moving to selection.\r
+               else if (SCSI_ReadPin(SCSI_In_SEL))\r
+               {\r
+                       enter_SelectionPhase();\r
+               }\r
        break;\r
 \r
        case BUS_BUSY:\r
@@ -623,7 +641,9 @@ void scsiPoll(void)
        break;\r
 \r
        case COMMAND:\r
-               checkATN();\r
+               // Do not check ATN here. SCSI 1 & 2 initiators must set ATN\r
+               // and SEL together upon entering the selection phase if they\r
+               // want to send a message (IDENTIFY) immediately.\r
                if (scsiDev.atnFlag)\r
                {\r
                        process_MessageOut();\r
@@ -635,7 +655,7 @@ void scsiPoll(void)
        break;\r
 \r
        case DATA_IN:\r
-               checkATN();\r
+               scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
                if (scsiDev.atnFlag)\r
                {\r
                        process_MessageOut();\r
@@ -647,7 +667,7 @@ void scsiPoll(void)
        break;\r
 \r
        case DATA_OUT:\r
-               checkATN();\r
+               scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
                if (scsiDev.atnFlag)\r
                {\r
                        process_MessageOut();\r
@@ -659,7 +679,7 @@ void scsiPoll(void)
        break;\r
 \r
        case STATUS:\r
-               checkATN();\r
+               scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
                if (scsiDev.atnFlag)\r
                {\r
                        process_MessageOut();\r
@@ -671,7 +691,7 @@ void scsiPoll(void)
        break;\r
 \r
        case MESSAGE_IN:\r
-               checkATN();\r
+               scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
                if (scsiDev.atnFlag)\r
                {\r
                        process_MessageOut();\r
index 68ec8bd..fe16954 100755 (executable)
 // Fixed 512 byte sector size.
 // 2TB limit, based on 32bit LBA (read16/write16 not supported)
 
+// Set this to true to log SCSI commands and status information via
+// USB HID packets.  The can be captured and viewed in wireshark.
+// For windows users, capture using USBPcap http://desowin.org/usbpcap/
+#define MM_DEBUG 0
+
 #include "geometry.h"
 #include "sense.h"
 
@@ -97,11 +102,20 @@ typedef struct
        uint8 status;
 
        ScsiSense sense;
-       
+
        uint16 unitAttention; // Set to the sense qualifier key to be returned.
 
        uint8 msgIn;
        uint8 msgOut;
+
+#ifdef MM_DEBUG
+       uint8 selCount;
+       uint8 rstCount;
+       uint8 msgCount;
+       uint8 watchdogTick;
+       uint8 lastStatus;
+       uint8 lastSense;
+#endif
 } ScsiDevice;
 
 extern ScsiDevice scsiDev;
index d6d1a91..f67f5f8 100755 (executable)
@@ -27,13 +27,6 @@ CY_ISR(scsiResetISR)
        SCSI_RST_ClearInterrupt();\r
 }\r
 \r
-CY_ISR_PROTO(scsiAttentionISR);\r
-CY_ISR(scsiAttentionISR)\r
-{\r
-       scsiDev.atnFlag = 1;\r
-       SCSI_ATN_ClearInterrupt();\r
-}\r
-\r
 uint8 scsiReadDBxPins()\r
 {\r
        return\r
@@ -149,10 +142,8 @@ void scsiEnterPhase(int phase)
 void scsiPhyInit()\r
 {\r
        SCSI_RST_ISR_StartEx(scsiResetISR);\r
-       SCSI_ATN_ISR_StartEx(scsiAttentionISR);\r
 \r
        // Interrupts may have already been directed to the (empty)\r
        // standard ISR generated by PSoC Creator.\r
        SCSI_RST_ClearInterrupt();\r
-       SCSI_ATN_ClearInterrupt();\r
 }\r
index 20f9cc6..e820cd3 100755 (executable)
@@ -133,7 +133,6 @@ reg[2:0] state;
 reg[7:0] data;\r
 \r
 // Set by the datapath zero detector (z1). High when A1 counts down to zero.\r
-// D1 set to constant by .d1_init_a(4) (55ns at 66MHz)\r
 wire deskewComplete;\r
 \r
 // Parallel input to the datapath SRCA.\r
@@ -185,8 +184,6 @@ always @(posedge op_clk) begin
                        else state <= STATE_DESKEW;\r
 \r
                STATE_READY:\r
-                       //if ((IO == IO_WRITE) & ~nACK) state <= STATE_IDLE;\r
-                       //else if ((IO == IO_READ) & ~nACK) state <= STATE_RX;\r
                        if (~nACK) state <= STATE_RX;\r
                        else state <= STATE_READY;\r
 \r
@@ -196,6 +193,10 @@ always @(posedge op_clk) begin
        endcase\r
 end\r
 \r
+// D1 is used for the deskew count.\r
+// The data output is valid during the DESKEW_INIT phase as well,\r
+// so we subtract 1.\r
+// D1 = [0.000000055 / (1 / clk)] - 1\r
 cy_psoc3_dp #(.d1_init(3), \r
 .cy_dpconfig(\r
 {\r
@@ -300,23 +301,3 @@ cy_psoc3_dp #(.d1_init(3),
 endmodule\r
 //`#start footer` -- edit after this line, do not edit this line\r
 //`#end` -- edit above this line, do not edit this line\r
-\r
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