Adding support for DB25 External board V5.5
authorMichael McMaster <michael@codesrc.com>
Wed, 31 Oct 2018 13:04:45 +0000 (23:04 +1000)
committerMichael McMaster <michael@codesrc.com>
Wed, 31 Oct 2018 13:04:45 +0000 (23:04 +1000)
200 files changed:
software/SCSI2SD/src/scsiPhy.h
software/SCSI2SD/v5.5/SCSI2SD.cydsn/.gitignore [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/.USBFS_boot.c.swp [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/BOOTLDR.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/BOOTLDR.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/BOOTLDR_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.c [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN_aliases.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE_PM.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl_PM.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits_PM.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl_PM.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.c [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_aliases.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cydmac.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_armcc.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_compiler.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_gcc.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmFunc.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmInstr.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cycodeshareexport.ld [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cycodeshareimport.ld [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cycodeshareimport.scat [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cydisabledsheets.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/eeprom.hex [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/exported_symbols.txt [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/protect.hex [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/renamed_symbols.txt [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/OddParityGen [new symlink]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/SCSI2SD.cycdx [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/SCSI2SD.cydwr [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/SCSI2SD.cyfit [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/SCSI2SD.cyprj [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/SCSI2SD.svd [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/TopDesign/TopDesign.cysch [new file with mode: 0755]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/device.h [new file with mode: 0644]
software/SCSI2SD/v5.5/SCSI2SD.cydsn/scsiTarget [new symlink]
software/scsi2sd-util/SCSI2SD_Bootloader.cc

index ec458c2..503bd84 100755 (executable)
@@ -37,8 +37,8 @@ typedef enum
 #define scsiPhyTx(val) CY_SET_REG8(scsiTarget_datapath__F0_REG, (val))
 #define scsiPhyRx() CY_GET_REG8(scsiTarget_datapath__F1_REG)
 
-#ifdef TERM_EN_0
-       // V5.1 is active-low
+#if defined(TERM_EN_0) || defined(BOOTLDR_0)
+       // V5.1 and v5.5 is active-low
 #define SCSI_SetPin(pin) \
        CyPins_ClearPin((pin));
 
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/.gitignore b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/.gitignore
new file mode 100644 (file)
index 0000000..0cf205e
--- /dev/null
@@ -0,0 +1,7 @@
+codegentemp
+CortexM3
+*.Micha_000
+*.rpt
+*.pdf
+*.html
+
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/.USBFS_boot.c.swp b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/.USBFS_boot.c.swp
new file mode 100644 (file)
index 0000000..dc66109
Binary files /dev/null and b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/.USBFS_boot.c.swp differ
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/BOOTLDR.c b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/BOOTLDR.c
new file mode 100755 (executable)
index 0000000..a38a767
--- /dev/null
@@ -0,0 +1,226 @@
+/*******************************************************************************
+* File Name: BOOTLDR.c  
+* Version 2.20
+*
+* Description:
+*  This file contains API to enable firmware control of a Pins component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "cytypes.h"
+#include "BOOTLDR.h"
+
+/* APIs are not generated for P15[7:6] on PSoC 5 */
+#if !(CY_PSOC5A &&\
+        BOOTLDR__PORT == 15 && ((BOOTLDR__MASK & 0xC0) != 0))
+
+
+/*******************************************************************************
+* Function Name: BOOTLDR_Write
+****************************************************************************//**
+*
+* \brief Writes the value to the physical port (data output register), masking
+*  and shifting the bits appropriately. 
+*
+* The data output register controls the signal applied to the physical pin in 
+* conjunction with the drive mode parameter. This function avoids changing 
+* other bits in the port by using the appropriate method (read-modify-write or
+* bit banding).
+*
+* <b>Note</b> This function should not be used on a hardware digital output pin 
+* as it is driven by the hardware signal attached to it.
+*
+* \param value
+*  Value to write to the component instance.
+*
+* \return 
+*  None 
+*
+* \sideeffect
+*  If you use read-modify-write operations that are not atomic; the Interrupt 
+*  Service Routines (ISR) can cause corruption of this function. An ISR that 
+*  interrupts this function and performs writes to the Pins component data 
+*  register can cause corrupted port data. To avoid this issue, you should 
+*  either use the Per-Pin APIs (primary method) or disable interrupts around 
+*  this function.
+*
+* \funcusage
+*  \snippet BOOTLDR_SUT.c usage_BOOTLDR_Write
+*******************************************************************************/
+void BOOTLDR_Write(uint8 value)
+{
+    uint8 staticBits = (BOOTLDR_DR & (uint8)(~BOOTLDR_MASK));
+    BOOTLDR_DR = staticBits | ((uint8)(value << BOOTLDR_SHIFT) & BOOTLDR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: BOOTLDR_SetDriveMode
+****************************************************************************//**
+*
+* \brief Sets the drive mode for each of the Pins component's pins.
+* 
+* <b>Note</b> This affects all pins in the Pins component instance. Use the
+* Per-Pin APIs if you wish to control individual pin's drive modes.
+*
+* \param mode
+*  Mode for the selected signals. Valid options are documented in 
+*  \ref driveMode.
+*
+* \return
+*  None
+*
+* \sideeffect
+*  If you use read-modify-write operations that are not atomic, the ISR can
+*  cause corruption of this function. An ISR that interrupts this function 
+*  and performs writes to the Pins component Drive Mode registers can cause 
+*  corrupted port data. To avoid this issue, you should either use the Per-Pin
+*  APIs (primary method) or disable interrupts around this function.
+*
+* \funcusage
+*  \snippet BOOTLDR_SUT.c usage_BOOTLDR_SetDriveMode
+*******************************************************************************/
+void BOOTLDR_SetDriveMode(uint8 mode)
+{
+       CyPins_SetPinDriveMode(BOOTLDR_0, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: BOOTLDR_Read
+****************************************************************************//**
+*
+* \brief Reads the associated physical port (pin status register) and masks 
+*  the required bits according to the width and bit position of the component
+*  instance. 
+*
+* The pin's status register returns the current logic level present on the 
+* physical pin.
+*
+* \return 
+*  The current value for the pins in the component as a right justified number.
+*
+* \funcusage
+*  \snippet BOOTLDR_SUT.c usage_BOOTLDR_Read  
+*******************************************************************************/
+uint8 BOOTLDR_Read(void)
+{
+    return (BOOTLDR_PS & BOOTLDR_MASK) >> BOOTLDR_SHIFT;
+}
+
+
+/*******************************************************************************
+* Function Name: BOOTLDR_ReadDataReg
+****************************************************************************//**
+*
+* \brief Reads the associated physical port's data output register and masks 
+*  the correct bits according to the width and bit position of the component 
+*  instance. 
+*
+* The data output register controls the signal applied to the physical pin in 
+* conjunction with the drive mode parameter. This is not the same as the 
+* preferred BOOTLDR_Read() API because the 
+* BOOTLDR_ReadDataReg() reads the data register instead of the status 
+* register. For output pins this is a useful function to determine the value 
+* just written to the pin.
+*
+* \return 
+*  The current value of the data register masked and shifted into a right 
+*  justified number for the component instance.
+*
+* \funcusage
+*  \snippet BOOTLDR_SUT.c usage_BOOTLDR_ReadDataReg 
+*******************************************************************************/
+uint8 BOOTLDR_ReadDataReg(void)
+{
+    return (BOOTLDR_DR & BOOTLDR_MASK) >> BOOTLDR_SHIFT;
+}
+
+
+/* If interrupt is connected for this Pins component */ 
+#if defined(BOOTLDR_INTSTAT) 
+
+    /*******************************************************************************
+    * Function Name: BOOTLDR_SetInterruptMode
+    ****************************************************************************//**
+    *
+    * \brief Configures the interrupt mode for each of the Pins component's
+    *  pins. Alternatively you may set the interrupt mode for all the pins
+    *  specified in the Pins component.
+    *
+    *  <b>Note</b> The interrupt is port-wide and therefore any enabled pin
+    *  interrupt may trigger it.
+    *
+    * \param position
+    *  The pin position as listed in the Pins component. You may OR these to be 
+    *  able to configure the interrupt mode of multiple pins within a Pins 
+    *  component. Or you may use BOOTLDR_INTR_ALL to configure the
+    *  interrupt mode of all the pins in the Pins component.       
+    *  - BOOTLDR_0_INTR       (First pin in the list)
+    *  - BOOTLDR_1_INTR       (Second pin in the list)
+    *  - ...
+    *  - BOOTLDR_INTR_ALL     (All pins in Pins component)
+    *
+    * \param mode
+    *  Interrupt mode for the selected pins. Valid options are documented in
+    *  \ref intrMode.
+    *
+    * \return 
+    *  None
+    *  
+    * \sideeffect
+    *  It is recommended that the interrupt be disabled before calling this 
+    *  function to avoid unintended interrupt requests. Note that the interrupt
+    *  type is port wide, and therefore will trigger for any enabled pin on the 
+    *  port.
+    *
+    * \funcusage
+    *  \snippet BOOTLDR_SUT.c usage_BOOTLDR_SetInterruptMode
+    *******************************************************************************/
+    void BOOTLDR_SetInterruptMode(uint16 position, uint16 mode)
+    {
+               if((position & BOOTLDR_0_INTR) != 0u) 
+               { 
+                        BOOTLDR_0_INTTYPE_REG = (uint8)mode; 
+               }
+    }
+    
+    
+    /*******************************************************************************
+    * Function Name: BOOTLDR_ClearInterrupt
+    ****************************************************************************//**
+    *
+    * \brief Clears any active interrupts attached with the component and returns 
+    *  the value of the interrupt status register allowing determination of which
+    *  pins generated an interrupt event.
+    *
+    * \return 
+    *  The right-shifted current value of the interrupt status register. Each pin 
+    *  has one bit set if it generated an interrupt event. For example, bit 0 is 
+    *  for pin 0 and bit 1 is for pin 1 of the Pins component.
+    *  
+    * \sideeffect
+    *  Clears all bits of the physical port's interrupt status register, not just
+    *  those associated with the Pins component.
+    *
+    * \funcusage
+    *  \snippet BOOTLDR_SUT.c usage_BOOTLDR_ClearInterrupt
+    *******************************************************************************/
+    uint8 BOOTLDR_ClearInterrupt(void)
+    {
+        return (BOOTLDR_INTSTAT & BOOTLDR_MASK) >> BOOTLDR_SHIFT;
+    }
+
+#endif /* If Interrupts Are Enabled for this Pins component */ 
+
+#endif /* CY_PSOC5A... */
+
+    
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/BOOTLDR.h b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/BOOTLDR.h
new file mode 100755 (executable)
index 0000000..f42e794
--- /dev/null
@@ -0,0 +1,165 @@
+/*******************************************************************************
+* File Name: BOOTLDR.h  
+* Version 2.20
+*
+* Description:
+*  This file contains Pin function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_BOOTLDR_H) /* Pins BOOTLDR_H */
+#define CY_PINS_BOOTLDR_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cypins.h"
+#include "BOOTLDR_aliases.h"
+
+/* APIs are not generated for P15[7:6] */
+#if !(CY_PSOC5A &&\
+        BOOTLDR__PORT == 15 && ((BOOTLDR__MASK & 0xC0) != 0))
+
+
+/***************************************
+*        Function Prototypes             
+***************************************/    
+
+/**
+* \addtogroup group_general
+* @{
+*/
+void    BOOTLDR_Write(uint8 value);
+void    BOOTLDR_SetDriveMode(uint8 mode);
+uint8   BOOTLDR_ReadDataReg(void);
+uint8   BOOTLDR_Read(void);
+void    BOOTLDR_SetInterruptMode(uint16 position, uint16 mode);
+uint8   BOOTLDR_ClearInterrupt(void);
+/** @} general */
+
+/***************************************
+*           API Constants        
+***************************************/
+/**
+* \addtogroup group_constants
+* @{
+*/
+    /** \addtogroup driveMode Drive mode constants
+     * \brief Constants to be passed as "mode" parameter in the BOOTLDR_SetDriveMode() function.
+     *  @{
+     */
+        #define BOOTLDR_DM_ALG_HIZ         PIN_DM_ALG_HIZ
+        #define BOOTLDR_DM_DIG_HIZ         PIN_DM_DIG_HIZ
+        #define BOOTLDR_DM_RES_UP          PIN_DM_RES_UP
+        #define BOOTLDR_DM_RES_DWN         PIN_DM_RES_DWN
+        #define BOOTLDR_DM_OD_LO           PIN_DM_OD_LO
+        #define BOOTLDR_DM_OD_HI           PIN_DM_OD_HI
+        #define BOOTLDR_DM_STRONG          PIN_DM_STRONG
+        #define BOOTLDR_DM_RES_UPDWN       PIN_DM_RES_UPDWN
+    /** @} driveMode */
+/** @} group_constants */
+    
+/* Digital Port Constants */
+#define BOOTLDR_MASK               BOOTLDR__MASK
+#define BOOTLDR_SHIFT              BOOTLDR__SHIFT
+#define BOOTLDR_WIDTH              1u
+
+/* Interrupt constants */
+#if defined(BOOTLDR__INTSTAT)
+/**
+* \addtogroup group_constants
+* @{
+*/
+    /** \addtogroup intrMode Interrupt constants
+     * \brief Constants to be passed as "mode" parameter in BOOTLDR_SetInterruptMode() function.
+     *  @{
+     */
+        #define BOOTLDR_INTR_NONE      (uint16)(0x0000u)
+        #define BOOTLDR_INTR_RISING    (uint16)(0x0001u)
+        #define BOOTLDR_INTR_FALLING   (uint16)(0x0002u)
+        #define BOOTLDR_INTR_BOTH      (uint16)(0x0003u) 
+    /** @} intrMode */
+/** @} group_constants */
+
+    #define BOOTLDR_INTR_MASK      (0x01u) 
+#endif /* (BOOTLDR__INTSTAT) */
+
+
+/***************************************
+*             Registers        
+***************************************/
+
+/* Main Port Registers */
+/* Pin State */
+#define BOOTLDR_PS                     (* (reg8 *) BOOTLDR__PS)
+/* Data Register */
+#define BOOTLDR_DR                     (* (reg8 *) BOOTLDR__DR)
+/* Port Number */
+#define BOOTLDR_PRT_NUM                (* (reg8 *) BOOTLDR__PRT) 
+/* Connect to Analog Globals */                                                  
+#define BOOTLDR_AG                     (* (reg8 *) BOOTLDR__AG)                       
+/* Analog MUX bux enable */
+#define BOOTLDR_AMUX                   (* (reg8 *) BOOTLDR__AMUX) 
+/* Bidirectional Enable */                                                        
+#define BOOTLDR_BIE                    (* (reg8 *) BOOTLDR__BIE)
+/* Bit-mask for Aliased Register Access */
+#define BOOTLDR_BIT_MASK               (* (reg8 *) BOOTLDR__BIT_MASK)
+/* Bypass Enable */
+#define BOOTLDR_BYP                    (* (reg8 *) BOOTLDR__BYP)
+/* Port wide control signals */                                                   
+#define BOOTLDR_CTL                    (* (reg8 *) BOOTLDR__CTL)
+/* Drive Modes */
+#define BOOTLDR_DM0                    (* (reg8 *) BOOTLDR__DM0) 
+#define BOOTLDR_DM1                    (* (reg8 *) BOOTLDR__DM1)
+#define BOOTLDR_DM2                    (* (reg8 *) BOOTLDR__DM2) 
+/* Input Buffer Disable Override */
+#define BOOTLDR_INP_DIS                (* (reg8 *) BOOTLDR__INP_DIS)
+/* LCD Common or Segment Drive */
+#define BOOTLDR_LCD_COM_SEG            (* (reg8 *) BOOTLDR__LCD_COM_SEG)
+/* Enable Segment LCD */
+#define BOOTLDR_LCD_EN                 (* (reg8 *) BOOTLDR__LCD_EN)
+/* Slew Rate Control */
+#define BOOTLDR_SLW                    (* (reg8 *) BOOTLDR__SLW)
+
+/* DSI Port Registers */
+/* Global DSI Select Register */
+#define BOOTLDR_PRTDSI__CAPS_SEL       (* (reg8 *) BOOTLDR__PRTDSI__CAPS_SEL) 
+/* Double Sync Enable */
+#define BOOTLDR_PRTDSI__DBL_SYNC_IN    (* (reg8 *) BOOTLDR__PRTDSI__DBL_SYNC_IN) 
+/* Output Enable Select Drive Strength */
+#define BOOTLDR_PRTDSI__OE_SEL0        (* (reg8 *) BOOTLDR__PRTDSI__OE_SEL0) 
+#define BOOTLDR_PRTDSI__OE_SEL1        (* (reg8 *) BOOTLDR__PRTDSI__OE_SEL1) 
+/* Port Pin Output Select Registers */
+#define BOOTLDR_PRTDSI__OUT_SEL0       (* (reg8 *) BOOTLDR__PRTDSI__OUT_SEL0) 
+#define BOOTLDR_PRTDSI__OUT_SEL1       (* (reg8 *) BOOTLDR__PRTDSI__OUT_SEL1) 
+/* Sync Output Enable Registers */
+#define BOOTLDR_PRTDSI__SYNC_OUT       (* (reg8 *) BOOTLDR__PRTDSI__SYNC_OUT) 
+
+/* SIO registers */
+#if defined(BOOTLDR__SIO_CFG)
+    #define BOOTLDR_SIO_HYST_EN        (* (reg8 *) BOOTLDR__SIO_HYST_EN)
+    #define BOOTLDR_SIO_REG_HIFREQ     (* (reg8 *) BOOTLDR__SIO_REG_HIFREQ)
+    #define BOOTLDR_SIO_CFG            (* (reg8 *) BOOTLDR__SIO_CFG)
+    #define BOOTLDR_SIO_DIFF           (* (reg8 *) BOOTLDR__SIO_DIFF)
+#endif /* (BOOTLDR__SIO_CFG) */
+
+/* Interrupt Registers */
+#if defined(BOOTLDR__INTSTAT)
+    #define BOOTLDR_INTSTAT            (* (reg8 *) BOOTLDR__INTSTAT)
+    #define BOOTLDR_SNAP               (* (reg8 *) BOOTLDR__SNAP)
+    
+       #define BOOTLDR_0_INTTYPE_REG           (* (reg8 *) BOOTLDR__0__INTTYPE)
+#endif /* (BOOTLDR__INTSTAT) */
+
+#endif /* CY_PSOC5A... */
+
+#endif /*  CY_PINS_BOOTLDR_H */
+
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/BOOTLDR_aliases.h b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/BOOTLDR_aliases.h
new file mode 100755 (executable)
index 0000000..7b8c969
--- /dev/null
@@ -0,0 +1,36 @@
+/*******************************************************************************
+* File Name: BOOTLDR.h  
+* Version 2.20
+*
+* Description:
+*  This file contains the Alias definitions for Per-Pin APIs in cypins.h. 
+*  Information on using these APIs can be found in the System Reference Guide.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_BOOTLDR_ALIASES_H) /* Pins BOOTLDR_ALIASES_H */
+#define CY_PINS_BOOTLDR_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define BOOTLDR_0                      (BOOTLDR__0__PC)
+#define BOOTLDR_0_INTR ((uint16)((uint16)0x0001u << BOOTLDR__0__SHIFT))
+
+#define BOOTLDR_INTR_ALL        ((uint16)(BOOTLDR_0_INTR))
+
+#endif /* End Pins BOOTLDR_ALIASES_H */
+
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c
new file mode 100755 (executable)
index 0000000..b212da6
--- /dev/null
@@ -0,0 +1,270 @@
+/****************************************************************************//**
+* \file Bootloadable_1.c
+* \version 1.60
+*
+* \brief
+*   Provides an API for the Bootloadable application.
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "Bootloadable_1.h"
+
+/**
+ \defgroup functions_group Functions
+ @{
+*/
+
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
+static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \
+                               ;
+#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/
+
+/*******************************************************************************
+* Function Name: Bootloadable_1_Load
+****************************************************************************//**
+*
+* \brief
+*  Schedules the Bootloader/Launcher to be launched and then performs
+*  a software reset to launch it
+*
+* \return
+*  This method will never return. It will load a new application and reset
+*  the device.
+*
+*******************************************************************************/
+void Bootloadable_1_Load(void) 
+{
+    /* Schedule Bootloader to start after reset */
+    Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_SCHEDULE_BTLDR);
+
+    CySoftwareReset();
+}
+
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
+/*******************************************************************************
+* Function Name: Bootloadable_1_GetActiveApplication
+****************************************************************************//**
+*
+* \brief
+*   Gets the application which will be loaded after a next reset event.
+*   NOTE Intended for the combination project type ONLY!
+*
+* \return 
+*  A number of the current active application set in the metadata section.
+*  \n  0 - app#0 is set as active.
+*  \n  1 - app#1 is set as active.
+*
+* \note If neither of the applications is set active, then the API returns 0x02.
+*
+*******************************************************************************/
+uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \
+                          
+{   
+    uint8 result = Bootloadable_1_MD_BTLDB_ACTIVE_NONE;
+    
+    if (0u != Bootloadable_1_GET_CODE_DATA( \
+              Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_0))) 
+    {
+        result = Bootloadable_1_MD_BTLDB_ACTIVE_0;
+    }
+    else if (0u != Bootloadable_1_GET_CODE_DATA( \
+                   Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_1)))
+    {
+        result = Bootloadable_1_MD_BTLDB_ACTIVE_1;    
+    }
+    else
+    {
+        /*Do nothing, result is none*/
+    }
+    
+    return (result);
+}
+
+/*******************************************************************************
+* Function Name: Bootloadable_1_SetActiveApplication
+****************************************************************************//**
+*
+* \brief 
+*   Sets the application which will be loaded after a next reset event.          
+*   
+* \details
+* Theory: 
+*   This API sets in the Flash (metadata section) the given active application 
+*   number.
+*          
+*   NOTE The active application number is not set directly, but the boolean 
+*   mark instead means that the application is active or not for the relative 
+*   metadata. Both metadata sections are updated. For example, if the second 
+*   application is to be set active, then in the metadata section for the first 
+*   application there will be a "0" written, which means that it is not active, and 
+*   for the second metadata section there will be a "1" written, which means that it is 
+*   active. 
+*
+*   NOTE Intended for the combination project type ONLY!
+*
+* \param appId  
+*   The active application number to be written to flash (metadata section) 
+*   NOTE Possible values are:
+*   0 - for the first application
+*   1 - for the second application.
+*   Any other number is considered invalid. 
+*
+* \return 
+*   A status of writing to flash operation.
+*   \n CYRET_SUCCESS - Returned if appId was successfully changed. 
+*   \n CYRET_BAD_PARAM - Returned if the parameter appID passed to the function has the 
+*                       same value as the active application ID. 
+*   \note - The other non-zero value is considered as a failure during writing to flash.  
+*
+*   \note - This API does not update Bootloader_activeApp variable.
+*
+*******************************************************************************/
+cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \
+                
+{
+    cystatus result = CYRET_SUCCESS;
+
+    uint8 CYDATA idx;
+    
+    /* If invalid application number */
+    if (appId > Bootloadable_1_MD_BTLDB_ACTIVE_1)
+    {
+        result = CYRET_BAD_PARAM;
+    }
+    else
+    {
+        /* If appID has same value as active application ID */
+        if (1u == Bootloadable_1_GET_CODE_DATA(Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId)))
+        {
+            result = CYRET_BAD_PARAM;
+        }
+        else
+        {
+            /* Updating metadata section */
+            for(idx = 0u; idx < Bootloadable_1_MAX_NUM_OF_BTLDB; idx++)
+            {
+                result |= Bootloadable_1_WriteFlashByte((uint32) Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(idx), \
+                                                                                            (uint8)(idx == appId));
+            }
+        }
+    }
+    
+    return (result);
+}
+
+/*******************************************************************************
+* Function Name: Bootloadable_1_WriteFlashByte
+****************************************************************************//**
+*
+* \brief 
+*   This API writes to flash the specified data.
+*
+* \param address 
+*   The address in flash.
+*
+* \param inputValue 
+*   One-byte data.
+*
+* \return 
+*   A status of the writing to flash procedure.
+*
+*******************************************************************************/
+static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \
+                               
+{
+    cystatus result = CYRET_SUCCESS;
+    uint32 flsAddr = address - CYDEV_FLASH_BASE;
+    uint8  rowData[CYDEV_FLS_ROW_SIZE];
+
+    #if !(CY_PSOC4)
+        uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);
+    #endif  /* !(CY_PSOC4) */
+
+    #if (CY_PSOC4)
+        uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);
+    #else
+        uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+    #endif  /* (CY_PSOC4) */
+
+    uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);
+    uint16 idx;
+
+    for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++)
+    {
+        rowData[idx] = (uint8)Bootloadable_1_GET_CODE_DATA(baseAddr + idx);
+    }
+
+    rowData[address % CYDEV_FLS_ROW_SIZE] = inputValue;
+
+    #if(CY_PSOC4)
+        result = CySysFlashWriteRow((uint32) rowNum, rowData);
+    #else
+        result = CyWriteRowData(arrayId, rowNum, rowData);
+    #endif  /* (CY_PSOC4) */
+
+    #if(CY_PSOC5)
+        /***************************************************************************
+        * When writing to flash, data in the instruction cache can become stale.
+        * Therefore, the cache data does not correlate to the data just written to
+        * flash. A call to CyFlushCache() is required to invalidate the data in the
+        * cache and force fresh information to be loaded from flash.
+        ***************************************************************************/
+        CyFlushCache();
+    #endif /* (CY_PSOC5) */
+    return (result);
+}
+#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/
+/** @} functions_group */
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used.
+*******************************************************************************/
+void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) 
+{
+    uint32 flsAddr = address - CYDEV_FLASH_BASE;
+    uint8  rowData[CYDEV_FLS_ROW_SIZE];
+
+    #if !(CY_PSOC4)
+        uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);
+    #endif  /* !(CY_PSOC4) */
+
+    #if (CY_PSOC4)
+        uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);
+    #else
+        uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+    #endif  /* (CY_PSOC4) */
+
+    uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);
+    uint16 idx;
+
+
+    for (idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++)
+    {
+        rowData[idx] = Bootloadable_1_GET_CODE_DATA(baseAddr + idx);
+    }
+    rowData[address % CYDEV_FLS_ROW_SIZE] = runType;
+
+    #if(CY_PSOC4)
+        (void) CySysFlashWriteRow((uint32) rowNum, rowData);
+    #else
+        (void) CyWriteRowData(arrayId, rowNum, rowData);
+    #endif  /* (CY_PSOC4) */
+
+    #if(CY_PSOC5)
+        /***************************************************************************
+        * When writing to flash, data in the instruction cache can become obsolete.
+        * Therefore, the cache data does not correlate to the data just written to
+        * flash. A call to CyFlushCache() is required to invalidate the data in the
+        * cache and force fresh information to be loaded from flash.
+        ***************************************************************************/
+        CyFlushCache();
+    #endif /* (CY_PSOC5) */
+}
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h
new file mode 100755 (executable)
index 0000000..acfe0c3
--- /dev/null
@@ -0,0 +1,200 @@
+/****************************************************************************//**
+* \file Bootloadable_1.c
+* \version 1.60
+*
+* \brief
+*   Provides an API for the Bootloadable application. The API includes a
+*   single function for starting the Bootloader.
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+
+
+#ifndef CY_BOOTLOADABLE_Bootloadable_1_H
+#define CY_BOOTLOADABLE_Bootloadable_1_H
+
+#include "cydevice_trm.h"
+#include "CyFlash.h"
+
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+    #error Component Bootloadable_v1_60 requires cy_boot v3.0 or later
+#endif /* !defined (CY_PSOC5LP) */
+
+
+#ifndef CYDEV_FLASH_BASE
+    #define CYDEV_FLASH_BASE                            CYDEV_FLS_BASE
+    #define CYDEV_FLASH_SIZE                            CYDEV_FLS_SIZE
+#endif /* CYDEV_FLASH_BASE */
+
+#if(CY_PSOC3)
+    #define Bootloadable_1_GET_CODE_DATA(idx)         (*((uint8  CYCODE *) (idx)))
+#else
+    #define Bootloadable_1_GET_CODE_DATA(idx)         (*((uint8  *)(CYDEV_FLASH_BASE + (idx))))
+#endif /* (CY_PSOC3) */
+
+
+/*******************************************************************************
+* This variable is used by the Bootloader/Bootloadable components to schedule which
+* application will be started after a software reset.
+*******************************************************************************/
+#if (CY_PSOC4)
+    #if defined(__ARMCC_VERSION)
+        __attribute__ ((section(".bootloaderruntype"), zero_init))
+    #elif defined (__GNUC__)
+        __attribute__ ((section(".bootloaderruntype")))
+   #elif defined (__ICCARM__)
+        #pragma location=".bootloaderruntype"
+    #endif  /* defined(__ARMCC_VERSION) */
+    extern volatile uint32 cyBtldrRunType;
+#endif  /* (CY_PSOC4) */
+
+
+/*******************************************************************************
+* Gets the reason for a device reset
+*******************************************************************************/
+#if(CY_PSOC4)
+    #define Bootloadable_1_RES_CAUSE_RESET_SOFT   (0x10u)
+    #define Bootloadable_1_GET_RUN_TYPE           \
+                        (((CY_GET_REG32(CYREG_RES_CAUSE) & Bootloadable_1_RES_CAUSE_RESET_SOFT) > 0u) \
+                            ? (cyBtldrRunType) \
+                            : 0u)
+#else
+    #define Bootloadable_1_GET_RUN_TYPE           (CY_GET_REG8(CYREG_RESET_SR0) & \
+                                                    (Bootloadable_1_START_BTLDR | Bootloadable_1_START_APP))
+#endif  /* (CY_PSOC4) */
+
+
+/*******************************************************************************
+* Schedule the Bootloader/Bootloadable to be run after a software reset.
+*******************************************************************************/
+#if(CY_PSOC4)
+    #define Bootloadable_1_SET_RUN_TYPE(x)        (cyBtldrRunType = (x))
+#else
+    #define Bootloadable_1_SET_RUN_TYPE(x)        CY_SET_REG8(CYREG_RESET_SR0, (x))
+#endif  /* (CY_PSOC4) */
+
+
+
+/***************************************
+*     Function Prototypes
+***************************************/
+extern void Bootloadable_1_Load(void) ;
+
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting from version 1.10.
+*******************************************************************************/
+#define CYBTDLR_SET_RUN_TYPE(x)     Bootloadable_1_SET_RUN_TYPE(x)
+
+/*******************************************************************************
+* Bootloadable's declarations for in-app bootloading.
+*******************************************************************************/
+#define Bootloadable_1_MD_BTLDB_ACTIVE_0          (0x00u)
+
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
+    #define Bootloadable_1_MAX_NUM_OF_BTLDB       (0x02u)
+    #define Bootloadable_1_MD_BTLDB_ACTIVE_1      (0x01u)
+    #define Bootloadable_1_MD_BTLDB_ACTIVE_NONE   (0x02u)
+    #define Bootloadable_1_MD_SIZEOF              (64u)
+    #define Bootloadable_1_MD_BASE_ADDR(appId)    (CYDEV_FLASH_BASE + (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \
+                                                                        Bootloadable_1_MD_SIZEOF))
+    #define Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId) (Bootloadable_1_MD_BASE_ADDR(appId) + 16u)
+    
+#else
+    #define Bootloadable_1_MAX_NUM_OF_BTLDB       (0x01u)
+#endif  /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/
+
+/* Mask used to indicate starting application */
+#define Bootloadable_1_SCHEDULE_BTLDB             (0x80u)
+#define Bootloadable_1_SCHEDULE_BTLDR             (0x40u)
+#define Bootloadable_1_SCHEDULE_MASK              (0xC0u)
+/*******************************************************************************
+* API prototypes
+*******************************************************************************/
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)                
+    uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \
+          ;
+    cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \
+             ;
+#endif  /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting from version 1.20
+*******************************************************************************/
+#define Bootloadable_1_START_APP                      (0x80u)
+#define Bootloadable_1_START_BTLDR                    (0x40u)
+#define Bootloadable_1_META_DATA_SIZE                 (64u)
+#define Bootloadable_1_META_APP_CHECKSUM_OFFSET       (0u)
+
+#if(CY_PSOC3)
+
+    #define Bootloadable_1_APP_ADDRESS                    uint16
+    #define Bootloadable_1_GET_CODE_WORD(idx)             (*((uint32 CYCODE *) (idx)))
+
+    /* Offset by 2 from 32 bit start because only 16 bits are needed */
+    #define Bootloadable_1_META_APP_ADDR_OFFSET           (3u)
+    #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET    (7u)
+    #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET       (11u)
+    #define Bootloadable_1_META_APP_RUN_TYPE_OFFSET       (15u)
+
+#else
+
+    #define Bootloadable_1_APP_ADDRESS                    uint32
+    #define Bootloadable_1_GET_CODE_WORD(idx)             (*((uint32 *)(CYDEV_FLASH_BASE + (idx))))
+
+    #define Bootloadable_1_META_APP_ADDR_OFFSET           (1u)
+    #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET    (5u)
+    #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET       (9u)
+    #define Bootloadable_1_META_APP_RUN_TYPE_OFFSET       (13u)
+
+#endif /* (CY_PSOC3) */
+
+#define Bootloadable_1_META_APP_ACTIVE_OFFSET             (16u)
+#define Bootloadable_1_META_APP_VERIFIED_OFFSET           (17u)
+
+#define Bootloadable_1_META_APP_BL_BUILD_VER_OFFSET       (18u)
+#define Bootloadable_1_META_APP_ID_OFFSET                 (20u)
+#define Bootloadable_1_META_APP_VER_OFFSET                (22u)
+#define Bootloadable_1_META_APP_CUST_ID_OFFSET            (24u)
+
+#define Bootloadable_1_SetFlashRunType(runType)           \
+                        Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType))
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions are intended for the application, use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* NOTE Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;
+#if(CY_PSOC4)
+    #define Bootloadable_1_SOFTWARE_RESET         CySoftwareReset()
+#else
+    #define Bootloadable_1_SOFTWARE_RESET         CySoftwareReset()
+#endif  /* (CY_PSOC4) */
+
+#if(CY_PSOC4)
+    extern uint8 appRunType;
+#endif  /* (CY_PSOC4) */
+
+
+#endif /* CY_BOOTLOADABLE_Bootloadable_1_H */
+
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c
new file mode 100755 (executable)
index 0000000..747cacc
--- /dev/null
@@ -0,0 +1,730 @@
+/*******************************************************************************
+* File Name: CFG_EEPROM.c
+* Version 3.0
+*
+*  Description:
+*   Provides the source code to the API for the EEPROM component.
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "CFG_EEPROM.h"
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Enable
+********************************************************************************
+*
+* Summary:
+*  Enable the EEPROM block. Also reads the temperature and stores it for
+*  future writes.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CFG_EEPROM_Enable(void) 
+{
+    /* Read temperature value */
+    (void)CySetTemp();
+
+    /* Start EEPROM block */
+    CyEEPROM_Start();
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Start
+********************************************************************************
+*
+* Summary:
+*  Starts EEPROM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CFG_EEPROM_Start(void) 
+{
+    CFG_EEPROM_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Stop
+********************************************************************************
+*
+* Summary:
+*  Stops and powers down EEPROM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CFG_EEPROM_Stop (void) 
+{
+    /* Stop and power down EEPROM block */
+    CyEEPROM_Stop();
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_WriteByte
+********************************************************************************
+*
+* Summary:
+*  Writes a byte of data to the EEPROM. This function blocks until
+*  the function is complete. For a reliable write procedure to occur you should
+*  call CFG_EEPROM_UpdateTemperature() function if the temperature of the
+*  silicon has been changed for more than 10C since the component was started.
+*
+* Parameters:
+*  dataByte:  The byte of data to write to the EEPROM
+*  address:   The address of data to be written. The maximum address is dependent
+*             on the EEPROM size.
+*
+* Return:
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) 
+{
+    cystatus status;
+    uint16 rowNumber;
+    uint16 byteNumber;
+    
+    CySpcStart();
+
+    if (address < CY_EEPROM_SIZE)
+    {
+        rowNumber = address/(uint16)CY_EEPROM_SIZEOF_ROW;
+        byteNumber = address - (rowNumber * ((uint16)CY_EEPROM_SIZEOF_ROW));
+        if(CYRET_SUCCESS == CySpcLock())
+        {
+            status = CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, byteNumber, &dataByte, \
+                                                                    CFG_EEPROM_SPC_BYTE_WRITE_SIZE);
+            if (CYRET_STARTED == status)
+            {
+                /* Plan for failure */
+                status = CYRET_UNKNOWN;
+
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+                /* Command to erase and program the row. */
+                if(CYRET_SUCCESS == status)
+                {
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+                    dieTemperature[1u]) == CYRET_STARTED)
+                    {
+                        /* Plan for failure */
+                        status = CYRET_UNKNOWN;
+
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait until SPC becomes idle */
+                        }
+
+                        /* SPC is idle now */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                    }
+                    else
+                    {
+                        status = CYRET_UNKNOWN;
+                    }
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+            else
+            {
+                if (CYRET_BAD_PARAM != status)
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+            CySpcUnlock();
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_ReadByte
+********************************************************************************
+*
+* Summary:
+*  Reads and returns a byte of data from the on-chip EEPROM memory. Although
+*  the data is present in the CPU memory space, this function provides an
+*  intuitive user interface, addressing the EEPROM memory as a separate block with
+*  the first EERPOM byte address equal to 0x0000.
+*
+* Parameters:
+*  address:   The address of data to be read. The maximum address is limited by the
+*             size of the EEPROM array on a specific device.
+*
+* Return:
+*  Data located at an address.
+*
+*******************************************************************************/
+uint8 CFG_EEPROM_ReadByte(uint16 address) 
+{
+    uint8 retByte;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    /* Request access to EEPROM for reading.
+    This is needed to reserve PHUB for read operation from EEPROM */
+    CyEEPROM_ReadReserve();
+    
+    retByte = *((reg8 *) (CYDEV_EE_BASE + address));
+
+    /* Release EEPROM array */
+    CyEEPROM_ReadRelease();
+    
+    CyExitCriticalSection(interruptState);
+
+    return (retByte);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_UpdateTemperature
+********************************************************************************
+*
+* Summary:
+*  Updates and stores the temperature value. This function should be called
+*  before EEPROM writes if the temperature may have been changed by more than
+*  10 degrees Celsius.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  Status of operation, 0 if operation complete, non-zero value if error
+*  was detected.
+*
+*******************************************************************************/
+uint8 CFG_EEPROM_UpdateTemperature(void) 
+{
+    return ((uint8)CySetTemp());
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_EraseSector
+********************************************************************************
+*
+* Summary:
+*  Erase an EEPROM sector (64 rows). This function blocks until the erase
+*  operation is complete. Using this API helps to erase the EEPROM sector at
+*  a time. This is faster than using individual writes but affects a cycle
+*  recourse of the whole EEPROM row.
+*
+* Parameters:
+*  sectorNumber:  The sector number to erase.
+*
+* Return:
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) 
+{
+    cystatus status;
+    
+    CySpcStart();
+
+    if(sectorNumber < (uint8) CFG_EEPROM_SECTORS_NUMBER)
+    {
+        /* See if we can get SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
+            {
+                /* Plan for failure */
+                status = CYRET_UNKNOWN;
+
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                /* SPC is idle now */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+            }
+            else
+            {
+                status = CYRET_UNKNOWN;
+            }
+
+            /* Unlock SPC so that someone else can use it. */
+            CySpcUnlock();
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Write
+********************************************************************************
+*
+* Summary:
+*  Writes a row (16 bytes) of data to the EEPROM. This function blocks until
+*  the write operation is complete. Compared to functions that write one byte,
+*  this function allows writing a whole row (16 bytes) at a time. For
+*  a reliable write procedure to occur you should call the
+*  CFG_EEPROM_UpdateTemperature() function if the temperature of the
+*  silicon has changed for more than 10C since component was started.
+*
+* Parameters:
+*  rowData:    The address of the data to write to the EEPROM.
+*  rowNumber:  The row number to write.
+*
+* Return:
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_BAD_PARAM, if the parameter rowNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) 
+{
+    cystatus status;
+    
+    CySpcStart();
+
+    if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
+    {
+        /* See if we can get SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Plan for failure */
+            status = CYRET_UNKNOWN;
+
+            /* Command to load a row of data */
+            if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
+            {
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                /* SPC is idle now */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+
+                /* Command to erase and program the row. */
+                if(status == CYRET_SUCCESS)
+                {
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+                    dieTemperature[1u]) == CYRET_STARTED)
+                    {
+                        /* Plan for failure */
+                        status = CYRET_UNKNOWN;
+
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait until SPC becomes idle */
+                        }
+
+                        /* SPC is idle now */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                    }
+                    else
+                    {
+                        status = CYRET_UNKNOWN;
+                    }
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+
+            /* Unlock SPC so that someone else can use it. */
+            CySpcUnlock();
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_StartWrite
+********************************************************************************
+*
+* Summary:
+*  Starts a write of a row (16 bytes) of data to the EEPROM.
+*  This function does not block. The function returns once the SPC has begun
+*  writing the data. This function must be used in combination with
+*  CFG_EEPROM_Query(). CFG_EEPROM_Query() must be called
+*  until it returns a status other than CYRET_STARTED. That indicates that the
+*  write has completed. Until CFG_EEPROM_Query() detects that
+*  the write is complete, the SPC is marked as locked to prevent another
+*  SPC operation from being performed. For a reliable write procedure to occur
+*  you should call CFG_EEPROM_UpdateTemperature() API if the temperature
+*  of the silicon has changed for more than 10C since component was started.
+*
+* Parameters:
+*  rowData:    The address of the data to write to the EEPROM.
+*  rowNumber:  The row number to write.
+*
+* Return:
+*  CYRET_STARTED, if the SPC command to write was successfully started.
+*  CYRET_BAD_PARAM, if the parameter rowNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+* Side effects:
+*  After calling this API, the device should not be powered down, reset or switched
+*  to low power modes until EEPROM operation is complete. 
+*  Ignoring this recommendation may lead to data corruption or silicon
+*  unexpected behavior.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
+
+{
+    cystatus status;
+    
+    CySpcStart();
+
+    if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
+    {
+        /* See if we can get SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Plan for failure */
+            status = CYRET_UNKNOWN;
+
+            /* Command to load a row of data */
+            if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
+            {
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                /* SPC is idle now */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+
+                /* Command to erase and program the row. */
+                if(status == CYRET_SUCCESS)
+                {
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+                    dieTemperature[1u]) == CYRET_STARTED)
+                    {
+                        status = CYRET_STARTED;
+                    }
+                    else
+                    {
+                        status = CYRET_UNKNOWN;
+                    }
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_StartErase
+********************************************************************************
+*
+* Summary:
+*  Starts the EEPROM sector erase. This function does not block.
+*  The function returns once the SPC has begun writing the data. This function
+*  must be used in combination with CFG_EEPROM_Query().
+*  CFG_EEPROM_Query() must be called until it returns a status
+*  other than CYRET_STARTED. That indicates the erase has been completed.
+*  Until CFG_EEPROM_Query() detects that the erase is
+*  complete, the SPC is marked as locked to prevent another SPC operation
+*  from being performed.
+*
+* Parameters:
+*  sectorNumber:  The sector number to erase.
+*
+* Return:
+*  CYRET_STARTED, if the SPC command to erase was successfully started.
+*  CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+* Side effects:
+*  After calling this API, the device should not be powered down, reset or switched
+*  to low power modes until EEPROM operation is complete.
+*  Ignoring this recommendation may lead to data corruption or silicon
+*  unexpected behavior.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) 
+{
+    cystatus status;
+    
+    CySpcStart();
+
+    if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)
+    {
+        /* See if we can get SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Plan for failure */
+            status = CYRET_UNKNOWN;
+
+            /* Command to load a row of data */
+            if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
+            {
+                status = CYRET_SUCCESS;
+            }
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Query
+********************************************************************************
+*
+* Summary:
+*  Checks the status of an earlier call to CFG_EEPROM_StartWrite() or
+*  CFG_EEPROM_StartErase().
+*  This function must be called until it returns a value other than
+*  CYRET_STARTED. Once that occurs, the write or erase has been completed and
+*  the SPC is unlocked.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  CYRET_STARTED, if the SPC command is still processing.
+*  CYRET_SUCCESS, if the operation was completed successfully.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_Query(void) 
+{
+    cystatus status;
+    
+    CySpcStart();
+
+    /* Check if SPC is idle */
+    if(CY_SPC_IDLE)
+    {
+        /* SPC is idle now */
+        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+        {
+            status = CYRET_SUCCESS;
+        }
+        else
+        {
+            status = CYRET_UNKNOWN;
+        }
+
+        /* Unlock SPC so that someone else can use it. */
+        CySpcUnlock();
+    }
+    else
+    {
+        status = CYRET_STARTED;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_ByteWritePos
+********************************************************************************
+*
+* Summary:
+*  Writes a byte of data to the EEPROM. This is a blocking call. It will not
+*  return until the write operation succeeds or fails.
+*
+* Parameters:
+*  dataByte:   The byte of data to write to the EEPROM.
+*  rowNumber:  The EEPROM row number to program.
+*  byteNumber: The byte number within the row to program.
+*
+* Return:
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
+
+{
+    cystatus status;
+
+    /* Start SPC */
+    CySpcStart();
+
+    if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW))
+    {
+        /* See if we can get SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Plan for failure */
+            status = CYRET_UNKNOWN;
+
+            /* Command to load byte of data */
+            if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\
+                                                                CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED)
+            {
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                /* SPC is idle now */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+
+                /* Command to erase and program the row. */
+                if(status == CYRET_SUCCESS)
+                {
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+                    dieTemperature[1u]) == CYRET_STARTED)
+                    {
+                        /* Plan for failure */
+                        status = CYRET_UNKNOWN;
+
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait until SPC becomes idle */
+                        }
+
+                        /* SPC is idle now */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                    }
+                    else
+                    {
+                        status = CYRET_UNKNOWN;
+                    }
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+
+            /* Unlock SPC so that someone else can use it. */
+            CySpcUnlock();
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h
new file mode 100755 (executable)
index 0000000..6323d86
--- /dev/null
@@ -0,0 +1,79 @@
+/*******************************************************************************
+* File Name: CFG_EEPROM.h
+* Version 3.0
+*
+*  Description:
+*   Provides the function definitions for the EEPROM APIs.
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_EEPROM_CFG_EEPROM_H)
+#define CY_EEPROM_CFG_EEPROM_H
+
+#include "cydevice_trm.h"
+#include "CyFlash.h"
+
+#if !defined(CY_PSOC5LP)
+    #error Component EEPROM_v3_0 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5LP) */
+
+
+/***************************************
+*        Function Prototypes
+***************************************/
+
+void CFG_EEPROM_Enable(void) ;
+void CFG_EEPROM_Start(void) ;
+void CFG_EEPROM_Stop (void) ;
+cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) \
+                                            ;
+uint8 CFG_EEPROM_ReadByte(uint16 address) ;
+uint8 CFG_EEPROM_UpdateTemperature(void) ;
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ;
+cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ;
+cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
+                                                ;
+cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) ;
+cystatus CFG_EEPROM_Query(void) ;
+cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
+                                                ;
+
+
+/****************************************
+*           API Constants
+****************************************/
+
+#define CFG_EEPROM_EEPROM_SIZE            CYDEV_EE_SIZE
+#define CFG_EEPROM_SPC_BYTE_WRITE_SIZE    (0x01u)
+
+#define CFG_EEPROM_SECTORS_NUMBER         (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
+
+#define CFG_EEPROM_AHB_REQ_SHIFT          (0x00u)
+#define CFG_EEPROM_AHB_REQ                ((uint8)(0x01u << CFG_EEPROM_AHB_REQ_SHIFT))
+#define CFG_EEPROM_AHB_ACK_SHIFT          (0x01u)
+#define CFG_EEPROM_AHB_ACK_MASK           ((uint8)(0x01u << CFG_EEPROM_AHB_ACK_SHIFT))
+
+
+/***************************************
+* Registers
+***************************************/
+#define CFG_EEPROM_SPC_EE_SCR_REG                 (*(reg8 *) CYREG_SPC_EE_SCR)
+#define CFG_EEPROM_SPC_EE_SCR_PTR                 ( (reg8 *) CYREG_SPC_EE_SCR)
+
+
+
+/***************************************
+* The following code is DEPRECATED and
+* should not be used in new projects.
+***************************************/
+#define CFG_EEPROM_ByteWrite                  CFG_EEPROM_ByteWritePos
+#define CFG_EEPROM_QueryWrite                 CFG_EEPROM_Query
+
+#endif /* CY_EEPROM_CFG_EEPROM_H */
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
new file mode 100755 (executable)
index 0000000..d881592
--- /dev/null
@@ -0,0 +1,160 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x0;
+define symbol __ICFEDIT_region_ROM_end__   = 131072 - 1;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2);
+define symbol __ICFEDIT_region_RAM_end__   = 0x20000000 + (32768 / 2) - 1;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x0400;
+/**** End of ICF editor section. ###ICF###*/
+
+
+/******** Definitions ********/
+define symbol CY_APPL_LOADABLE  = 1;
+define symbol CY_APPL_LOADER    = 0;
+define symbol CY_APPL_NUM       = 1;
+define symbol CY_APPL_MAX       = 1;
+define symbol CY_METADATA_SIZE  = 64;
+define symbol CY_CHECKSUM_EXCLUDE_SIZE = 0;
+define symbol CY_EE_IN_BTLDR    = 0x00;
+define symbol CY_EE_SIZE        = 2048;
+include "cybootloader.icf";
+if (!CY_APPL_LOADABLE) {
+    define symbol CYDEV_BTLDR_SIZE = 0;
+}
+
+define symbol CY_FLASH_SIZE     = 131072;
+define symbol CY_APPL_ORIGIN    = 0;
+define symbol CY_FLASH_ROW_SIZE = 256;
+define symbol CY_ECC_ROW_SIZE   = 32;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK      with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP        with alignment = 8, size = __ICFEDIT_size_heap__     { };
+define block HSTACK      {block HEAP, last block CSTACK};
+
+if (CY_APPL_LOADABLE)
+{
+define block LOADER     { readonly section .cybootloader };
+}
+define block APPL       with fixed order {readonly section .romvectors, readonly};
+
+/* The address of the Flash row next after the Bootloader image */
+define symbol CY_BTLDR_END      = CYDEV_BTLDR_SIZE +
+                                    ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ?
+                                    (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0);
+
+/* The start address of Standard/Loader/Loadable#1 image */
+define symbol CY_APPL1_START    = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END;
+
+/* The number of metadata records located at the end of Flash */
+define symbol CY_METADATA_CNT   = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0);
+
+/* The application area size measured in rows */
+define symbol CY_APPL_ROW_CNT   = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT;
+
+/* The start address of Loadable#2 image if any */
+define symbol CY_APPL2_START    = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE;
+
+/* The current image (Standard/Loader/Loadable) start address */
+define symbol CY_APPL_START     = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START;
+
+/* The ECC data placement address */
+define exported symbol CY_ECC_OFFSET     = (CY_APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;
+
+/* The EEPROM offset and size that can be used by current application (Standard/Loader/Loadable) */
+define symbol CY_EE_OFFSET      = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;
+define symbol CY_EE_IN_USE      = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;
+
+/* Define EEPROM region */
+define region EEPROM_region     = mem:[from (0x90200000 + CY_EE_OFFSET) size CY_EE_IN_USE];
+
+/* Define APPL region that will limit application size */
+define region APPL_region       = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE];
+
+
+/****** Initializations ******/
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+do not initialize  { readwrite section .ramvectors };
+
+/******** Placements *********/
+if (CY_APPL_LOADABLE)
+{
+".cybootloader"    : place at start of ROM_region {block LOADER};
+}
+
+"APPL"             : place at start of APPL_region {block APPL};
+
+"RAMVEC"           : place at start of RAM_region { readwrite section .ramvectors };
+"readwrite"        : place in RAM_region          { readwrite };
+"HSTACK"           : place at end of RAM_region   { block HSTACK};
+
+keep {  section .cybootloader,
+        section .cyloadermeta,
+        section .cyloadablemeta,
+        section .cyconfigecc,
+       section .cy_checksum_exclude,
+        section .cycustnvl,
+        section .cywolatch,
+        section .cyeeprom,
+        section .cyflashprotect,
+        section .cymeta };
+
+".cyloadermeta"   : place at address mem : ((CY_APPL_LOADER && !CY_APPL_LOADABLE) ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };
+if (CY_APPL_LOADABLE)
+{
+".cyloadablemeta"      : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };
+}
+
+
+/*******************************************************************************
+* Checksum Exclude Section. See cm0gcc.ld on placement details.
+*******************************************************************************/
+if (CY_APPL_LOADABLE)
+{
+    /* Align size to the flash row size */
+    define symbol CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED = CY_CHECKSUM_EXCLUDE_SIZE + ((CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE)) : 0);
+
+    if (CY_CHECKSUM_EXCLUDE_SIZE != 0)
+    {
+
+        /* General case */
+        if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2))
+        {
+            define symbol CY_CHECKSUM_EXCLUDE_START =   CY_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED;
+        }
+        else
+        {
+            define symbol CY_CHECKSUM_EXCLUDE_START =   (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED;
+        }
+
+    define symbol CY_CHECKSUM_EXCLUDE_START_ALIGNED   = CY_CHECKSUM_EXCLUDE_START + ((CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE)) : 0);
+
+    ".cy_checksum_exclude" : place at address mem : (CY_CHECKSUM_EXCLUDE_START_ALIGNED) { readonly section .cy_checksum_exclude };
+
+    } /* (CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED != 0) */
+}
+else
+{
+    ".cy_checksum_exclude" : place in ROM_region { readonly section .cy_checksum_exclude };
+}
+
+
+".cyconfigecc"    : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };
+".cycustnvl"      : place at address mem : 0x90000000 { readonly section .cycustnvl };
+".cywolatch"      : place at address mem : 0x90100000 { readonly section .cywolatch };
+".cyeeprom"       : place in EEPROM_region { readonly section .cyeeprom };
+".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect };
+".cymeta"         : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+/* EOF */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
new file mode 100755 (executable)
index 0000000..307d0e3
--- /dev/null
@@ -0,0 +1,228 @@
+#! armcc -E
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;********************************************************************************
+;* \file Cm3RealView.scat
+;* \version 5.60
+;*
+;* \brief
+;* This Linker Descriptor file describes the memory layout of the PSoC5
+;* device. The memory layout of the final binary and hex images as well as
+;* the placement in PSoC5 memory is described.
+;*
+;*  romvectors: Cypress default Interrupt service routine vector table.
+;*      This is the ISR vector table at bootup. Used only for the reset vector.
+;*
+;*  ramvectors: Cypress ram interrupt service routine vector table.
+;*      This is the ISR vector table used by the application.
+;*
+;********************************************************************************
+;* Copyright 2008-2016, Cypress Semiconductor Corporation.  All rights reserved.
+;* You may use this file only in accordance with the license, terms, conditions,
+;* disclaimers, and limitations in the end user license agreement accompanying
+;* the software package with which this file was provided.
+;********************************************************************************/
+#include "cyfitter.h"
+
+#define CY_FLASH_SIZE       131072
+#define CY_APPL_ORIGIN      0
+#define CY_FLASH_ROW_SIZE   256
+#define CY_ECC_ROW_SIZE     32
+#define CY_EE_SIZE          2048
+#define CY_METADATA_SIZE    64
+
+#define CY_CHECKSUM_EXCLUDE_SIZE        AlignExpr(0, CY_FLASH_ROW_SIZE)
+#define CY_APPL_NUM                     1
+#define CY_APPL_MAX                     1
+
+
+; Define application base address
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \
+     CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
+
+     #define CY_EE_IN_BTLDR  0
+
+    #if CY_APPL_ORIGIN
+        #define APPL1_START     CY_APPL_ORIGIN
+    #else
+        #define APPL1_START     AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE)
+    #endif
+
+    #define APPL_START      (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE))
+    #define ECC_OFFSET      ((APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE)
+    #define EE_OFFSET       (CY_EE_IN_BTLDR ? 0 : (CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1))
+    #define EE_SIZE         (CY_EE_IN_BTLDR ? CY_EE_SIZE : (CY_EE_SIZE / CY_APPL_MAX))
+
+#else
+
+    #define APPL_START      0
+    #define ECC_OFFSET      0
+    #define EE_OFFSET       0
+    #define EE_SIZE         CY_EE_SIZE
+
+#endif
+
+
+; Place Bootloader at the beginning of Flash
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \
+     CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
+
+    CYBOOTLOADER 0
+    {
+        .cybootloader +0
+        {
+            * (.cybootloader)
+        }
+    }
+
+    #if CY_APPL_ORIGIN
+        ScatterAssert(APPL_START >= LoadLimit(CYBOOTLOADER))
+    #endif
+
+#endif
+
+
+APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START)
+{
+    VECTORS +0
+    {
+        * (.romvectors)
+    }
+
+    CODE +0
+    {
+        * (+RO)
+    }
+
+    ISRVECTORS (0x20000000 - (32768 / 2)) UNINIT
+    {
+        * (.ramvectors)
+    }
+
+    NOINIT_DATA +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    DATA +0
+    {
+        .ANY (+RW, +ZI)
+    }
+
+    ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x1000) EMPTY 0x0400
+    {
+    }
+
+    ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x1000
+    {
+    }
+}
+
+
+/*******************************************************************************
+* Bootloader Metadata Section. See cm0gcc.ld on placement details.
+*******************************************************************************/
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || \
+     CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER || \
+     CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LAUNCHER)
+
+    CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE)
+    {
+        .cyloadermeta +0 { * (.cyloadermeta) }
+    }
+
+#endif
+
+
+/*******************************************************************************
+* Bootloadable Metadata Section. See cm0gcc.ld on placement details.
+*******************************************************************************/
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \
+     CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
+
+    CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE)
+    {
+        .cyloadablemeta +0 { * (.cyloadablemeta) }
+    }
+
+#endif
+
+
+/*******************************************************************************
+* Checksum Exclude Section. See cm0gcc.ld on placement details.
+*******************************************************************************/
+#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))
+
+    #if (0 != 0)
+
+        #if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2))
+            #define CY_CHECKSUM_APPL2_START             (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ), CY_FLASH_ROW_SIZE))
+            #define CY_CHECKSUM_EXCLUDE_START           AlignExpr(CY_CHECKSUM_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE)
+        #else
+            #define CY_CHECKSUM_EXCLUDE_START           AlignExpr((CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE)
+        #endif
+
+        CY_CHECKSUM_EXCLUDE (CY_CHECKSUM_EXCLUDE_START)
+        {
+            .cy_checksum_exclude +0
+            {
+                * (.cy_checksum_exclude)
+            }
+        }
+
+    #endif /* (0 != 0) */
+
+#endif
+
+
+#if (CYDEV_ECC_ENABLE == 0)
+
+    CYCONFIGECC (0x80000000 + ECC_OFFSET)
+    {
+        .cyconfigecc +0 { * (.cyconfigecc) }
+    }
+
+#endif
+
+CYCUSTNVL 0x90000000
+{
+    .cycustnvl +0 { * (.cycustnvl) }
+}
+
+CYWOLATCH 0x90100000
+{
+    .cywolatch +0 { * (.cywolatch) }
+}
+
+#if defined(CYDEV_ALLOCATE_EEPROM)
+
+    CYEEPROM 0x90200000 + EE_OFFSET (EE_SIZE)
+    {
+        .cyeeprom +0 { * (.cyeeprom) }
+    }
+
+#endif
+
+CYFLASHPROTECT 0x90400000
+{
+    .cyflashprotect +0 { * (.cyflashprotect) }
+}
+
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+
+/*******************************************************************************
+* Bootloader Metadata Section. Must be part of the image, but beyond rom memory.
+*******************************************************************************/
+#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))
+
+    CYLOADERMETA +0
+    {
+        .cyloadermeta +0 { * (.cyloadermeta) }
+    }
+
+#endif
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c
new file mode 100755 (executable)
index 0000000..9d2b67b
--- /dev/null
@@ -0,0 +1,503 @@
+/***************************************************************************//**
+* \file Cm3Start.c
+* \version 5.60
+*
+*  \brief
+*  Startup code for the ARM CM3.
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include <limits.h>
+#include "cydevice_trm.h"
+#include "cytypes.h"
+#include "cyfitter_cfg.h"
+#include "CyLib.h"
+#include "CyDmac.h"
+#include "cyfitter.h"
+
+
+#define CY_NUM_INTERRUPTS           (32u)
+#define CY_NUM_VECTORS              (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS)
+#define CY_NUM_ROM_VECTORS          (4u)
+#define CY_NVIC_APINT_PTR           ((reg32 *) CYREG_NVIC_APPLN_INTR)
+#define CY_NVIC_CFG_CTRL_PTR        ((reg32 *) CYREG_NVIC_CFG_CONTROL)
+#define CY_NVIC_APINT_PRIGROUP_3_5  (0x00000400u)  /* Priority group 3.5 split */
+#define CY_NVIC_APINT_VECTKEY       (0x05FA0000u)  /* This key is required in order to write the NVIC_APINT register */
+#define CY_NVIC_CFG_STACKALIGN      (0x00000200u)  /* This specifies that the exception stack must be 8 byte aligned */
+
+#if defined(__ARMCC_VERSION)
+    #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit)
+#elif defined (__GNUC__)
+    #define INITIAL_STACK_POINTER (&__cy_stack)
+#elif defined (__ICCARM__)
+    #pragma language=extended
+    #pragma segment="CSTACK"
+    #define INITIAL_STACK_POINTER  { .__ptr = __sfe( "CSTACK" ) }
+
+    extern void __iar_program_start( void );
+    extern void __iar_data_init3 (void);
+#endif  /* (__ARMCC_VERSION) */
+
+#if defined(__GNUC__)
+    #include <errno.h>
+    extern int  errno;
+    extern int  end;
+#endif  /* defined(__GNUC__) */
+
+/* Extern functions */
+extern void CyBtldr_CheckLaunch(void);
+
+/* Function prototypes */
+void initialize_psoc(void);
+CY_ISR(IntDefaultHandler);
+void Reset(void);
+
+/* Global variables */
+#if !defined (__ICCARM__)
+    CY_NOINIT static uint32 cySysNoInitDataValid;
+#endif  /* !defined (__ICCARM__) */
+
+
+/*******************************************************************************
+* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned.
+*******************************************************************************/
+#if defined (__ICCARM__)
+    #pragma location=".ramvectors"
+    #pragma data_alignment=256
+#else
+    CY_SECTION(".ramvectors")
+    CY_ALIGN(256)
+#endif  /* defined (__ICCARM__) */
+cyisraddress CyRamVectors[CY_NUM_VECTORS];
+
+
+/*******************************************************************************
+* Function Name: IntDefaultHandler
+****************************************************************************//**
+*
+*  This function is called for all interrupts, other than a reset that gets
+*  called before the system is setup.
+*
+* Theory:
+*  Any value other than zero is acceptable.
+*
+*******************************************************************************/
+CY_ISR(IntDefaultHandler)
+{
+    /***************************************************************************
+    * We must not get here. If we do, a serious problem occurs, so go into
+    * an infinite loop.
+    ***************************************************************************/
+
+    #if defined(__GNUC__)
+        if (errno == ENOMEM)
+        {
+            #ifdef CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK
+                CyBoot_IntDefaultHandler_Enomem_Exception_Callback();
+            #endif /* CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK */
+            
+            while(1)
+            {
+                /* Out Of Heap Space
+                 * This can be increased in the System tab of the Design Wide Resources.
+                 */
+            }
+        }
+        else
+    #endif
+        {
+            #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK
+                CyBoot_IntDefaultHandler_Exception_EntryCallback();
+            #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */
+
+            while(1)
+            {
+
+            }
+        }
+}
+
+
+#if defined(__ARMCC_VERSION)
+
+/* Local function for device reset. */
+extern void Reset(void);
+
+/* Application entry point. */
+extern void $Super$$main(void);
+
+/* Linker-generated Stack Base addresses, Two Region and One Region */
+extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit;
+
+/* RealView C Library initialization. */
+extern int __main(void);
+
+
+/*******************************************************************************
+* Function Name: Reset
+****************************************************************************//**
+*
+*  This function handles the reset interrupt for the RVDS/MDK toolchains.
+*  This is the first bit of code that is executed at startup.
+*
+*******************************************************************************/
+void Reset(void)
+{
+    #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
+
+        /* For PSoC 5LP, debugging is enabled by default */
+        #if(CYDEV_DEBUGGING_ENABLE == 0)
+            *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
+        #endif /* (CYDEV_DEBUGGING_ENABLE) */
+
+        /* Reset Status Register has Read-to-clear SW access mode.
+        * Preserve current RESET_SR0 state to make it available for next reading.
+        */
+        *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
+
+    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */
+
+    #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))
+        CyBtldr_CheckLaunch();
+    #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */
+
+    __main();
+}
+
+
+/*******************************************************************************
+* Function Name: $Sub$$main
+****************************************************************************//**
+*
+*  This function is called immediately before the users main
+*
+*******************************************************************************/
+void $Sub$$main(void)
+{
+    initialize_psoc();
+
+    /* Call original main */
+    $Super$$main();
+
+    while (1)
+    {
+        /* If main returns, it is undefined what we should do. */
+    }
+}
+
+#elif defined(__GNUC__)
+
+void Start_c(void);
+
+/* Stack Base address */
+extern void __cy_stack(void);
+
+/* Application entry point. */
+extern int main(void);
+
+/* Static objects constructors initializer */
+extern void __libc_init_array(void);
+
+typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));
+
+struct __cy_region
+{
+    __cy_byte_align8 *init; /* Initial contents of this region.  */
+    __cy_byte_align8 *data; /* Start address of region.  */
+    size_t init_size;       /* Size of initial data.  */
+    size_t zero_size;       /* Additional size to be zeroed.  */
+};
+
+extern const struct __cy_region __cy_regions[];
+extern const char __cy_region_num __attribute__((weak));
+#define __cy_region_num ((size_t)&__cy_region_num)
+
+
+/*******************************************************************************
+* System Calls of the Red Hat newlib C Library
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: _exit
+****************************************************************************//**
+*
+*  Exit a program without cleaning up files. If your system doesn't provide
+*  this, it is best to avoid linking with subroutines that require it (exit,
+*  system).
+*
+*  \param status: Status caused program exit.
+*
+*******************************************************************************/
+__attribute__((weak))
+void _exit(int status)
+{
+    CyHalt((uint8) status);
+    while(1)
+    {
+
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: _sbrk
+****************************************************************************//**
+*
+*  Increase program data space. As malloc and related functions depend on this,
+*  it is useful to have a working implementation. The following suffices for a
+*  standalone system; it exploits the symbol end automatically defined by the
+*  GNU linker.
+*
+*  \param nbytes: The number of bytes requested (if the parameter value is positive)
+*  from the heap or returned back to the heap (if the parameter value is
+*  negative).
+*
+*******************************************************************************/
+__attribute__((weak))
+void * _sbrk (int nbytes)
+{
+    extern int  end;            /* Symbol defined by linker map. Start of free memory (as symbol). */
+    void *      returnValue;
+
+    /* The statically held previous end of the heap, with its initialization. */
+    static uint8 *heapPointer = (uint8 *) &end;                 /* Previous end */
+
+    if (((heapPointer + nbytes) - (uint8 *) &end) <= CYDEV_HEAP_SIZE)
+    {
+        returnValue  = (void *) heapPointer;
+        heapPointer += nbytes;
+    }
+    else
+    {
+        errno = ENOMEM;
+        returnValue = (void *) -1;
+    }
+
+    return (returnValue);
+}
+
+
+/*******************************************************************************
+* Function Name: Reset
+****************************************************************************//**
+*
+*  This function handles the reset interrupt for the GCC toolchain. This is the
+*  first bit of code that is executed at startup.
+*
+*******************************************************************************/
+void Reset(void)
+{
+    #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
+
+        /* For PSoC 5LP, debugging is enabled by default */
+        #if(CYDEV_DEBUGGING_ENABLE == 0)
+            *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
+        #endif /* (CYDEV_DEBUGGING_ENABLE) */
+
+        /* Reset Status Register has Read-to-clear SW access mode.
+        * Preserve current RESET_SR0 state to make it available for next reading.
+        */
+        *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
+
+    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */
+
+    #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))
+        CyBtldr_CheckLaunch();
+    #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */
+
+    Start_c();
+}
+
+
+/*******************************************************************************
+* Function Name: Start_c
+****************************************************************************//**
+*
+*  This function handles initializing the .data and .bss sections in
+*  preparation for running the standard C code.  Once initialization is complete
+*  it will call main(). This function will never return.
+*
+*******************************************************************************/
+void Start_c(void)  __attribute__ ((noreturn));
+void Start_c(void)
+{
+    unsigned regions = __cy_region_num;
+    const struct __cy_region *rptr = __cy_regions;
+
+    /* Initialize memory */
+    for (regions = __cy_region_num; regions != 0u; regions--)
+    {
+        uint32 *src = (uint32 *)rptr->init;
+        uint32 *dst = (uint32 *)rptr->data;
+        unsigned limit = rptr->init_size;
+        unsigned count;
+
+        for (count = 0u; count != limit; count += sizeof (uint32))
+        {
+            *dst = *src;
+            dst++;
+            src++;
+        }
+        limit = rptr->zero_size;
+        for (count = 0u; count != limit; count += sizeof (uint32))
+        {
+            *dst = 0u;
+            dst++;
+        }
+
+        rptr++;
+    }
+
+    /* Invoke static objects constructors */
+    __libc_init_array();
+    (void) main();
+
+    while (1)
+    {
+        /* If main returns, make sure we don't return. */
+    }
+}
+
+
+#elif defined (__ICCARM__)
+
+/*******************************************************************************
+* Function Name: __low_level_init
+****************************************************************************//**
+*
+*  This function performs early initializations for the IAR Embedded
+*  Workbench IDE. It is executed in the context of a reset interrupt handler
+*  before the data sections are initialized.
+*
+* \return
+*  The value that determines whether or not data sections should be initialized
+*  by the system startup code:
+*    0 - skip data sections initialization;
+*    1 - initialize data sections;
+*
+*******************************************************************************/
+int __low_level_init(void)
+{
+    #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
+
+        /* For PSoC 5LP, debugging is enabled by default */
+        #if(CYDEV_DEBUGGING_ENABLE == 0)
+            *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
+        #endif /* (CYDEV_DEBUGGING_ENABLE) */
+
+        /* Reset Status Register has Read-to-clear SW access mode.
+        * Preserve current RESET_SR0 state to make it available for next reading.
+        */
+        *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
+
+    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */
+
+    #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))
+        CyBtldr_CheckLaunch();
+    #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */
+
+    /* Initialize data sections */
+    __iar_data_init3();
+
+    initialize_psoc();
+
+    return 0;
+}
+
+#endif /* __GNUC__ */
+
+
+/*******************************************************************************
+*
+* Default Rom Interrupt Vector table.
+*
+*******************************************************************************/
+#if defined(__ARMCC_VERSION)
+    /* Suppress diagnostic message 1296-D: extended constant initialiser used */
+    #pragma diag_suppress 1296
+#endif  /* defined(__ARMCC_VERSION) */
+
+#if defined (__ICCARM__)
+    #pragma location=".romvectors"
+    const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] =
+#else
+    CY_SECTION(".romvectors")
+    const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
+#endif  /* defined (__ICCARM__) */
+{
+    INITIAL_STACK_POINTER,   /* Initial stack pointer  0 */
+    #if defined (__ICCARM__) /* Reset handler          1 */
+        __iar_program_start,
+    #else
+        (cyisraddress)&Reset,
+    #endif  /* defined (__ICCARM__) */
+    &IntDefaultHandler,      /* NMI handler            2 */
+    &IntDefaultHandler,      /* Hard fault handler     3 */
+};
+
+#if defined(__ARMCC_VERSION)
+    #pragma diag_default 1296
+#endif  /* defined(__ARMCC_VERSION) */
+
+
+/*******************************************************************************
+* Function Name: initialize_psoc
+****************************************************************************//**
+*
+*  This function used to initialize the PSoC chip before calling main.
+*
+*******************************************************************************/
+#if (defined(__GNUC__) && !defined(__ARMCC_VERSION))
+__attribute__ ((constructor(101)))
+#endif
+void initialize_psoc(void)
+{
+    uint32 i;
+
+    /* Set Priority group 5. */
+
+    /* Writes to NVIC_APINT register require the VECTKEY in the upper half */
+    *CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5;
+    *CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN;
+
+    /* Set Ram interrupt vectors to default functions. */
+    for (i = 0u; i < CY_NUM_VECTORS; i++)
+    {
+        #if defined (__ICCARM__)
+            CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler;
+        #else
+            CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler;
+        #endif  /* defined (__ICCARM__) */
+    }
+
+    /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
+    CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);
+
+    /* Point NVIC at RAM vector table. */
+    *CYINT_VECT_TABLE = CyRamVectors;
+
+    /* Initialize the configuration registers. */
+    cyfitter_cfg();
+
+    #if(0u != DMA_CHANNELS_USED__MASK0)
+
+        /* Setup DMA - only necessary if design contains DMA component. */
+        CyDmacConfigure();
+
+    #endif  /* (0u != DMA_CHANNELS_USED__MASK0) */
+
+    #if !defined (__ICCARM__)
+        /* Actually, no need to clean this variable, just to make compiler happy. */
+        cySysNoInitDataValid = 0u;
+    #endif  /* !defined (__ICCARM__) */
+}
+
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
new file mode 100755 (executable)
index 0000000..100a893
--- /dev/null
@@ -0,0 +1,161 @@
+/***************************************************************************//**
+* \file CyBootAsmGnu.s
+* \version 5.60
+*
+*  \brief
+*   Assembly routines for GNU as.
+*
+********************************************************************************
+* \copyright
+* Copyright 2010-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+.include "cyfittergnu.inc"
+
+.syntax unified
+.text
+.thumb
+
+
+/*******************************************************************************
+* Function Name: CyDelayCycles
+****************************************************************************//**
+*
+*  Delays for the specified number of cycles.
+*
+*  \param uint32 cycles: number of cycles to delay.
+*
+*******************************************************************************/
+/* void CyDelayCycles(uint32 cycles) */
+.align 3                    /* Align to 8 byte boundary (2^n) */
+.global CyDelayCycles
+.func CyDelayCycles, CyDelayCycles
+.type CyDelayCycles, %function
+.thumb_func
+CyDelayCycles:              /* cycles bytes */
+/* If ICache is enabled */
+.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1
+
+    ADDS r0, r0, #2           /*  1    2   Round to nearest multiple of 4 */
+    LSRS r0, r0, #2           /*  1    2   Divide by 4 and set flags */
+    BEQ CyDelayCycles_done    /*  2    2   Skip if 0 */
+    NOP                       /*  1    2   Loop alignment padding */
+
+CyDelayCycles_loop:
+    SUBS r0, r0, #1           /*  1    2 */
+    MOV r0, r0                /*  1    2   Pad loop to power of two cycles */
+    BNE CyDelayCycles_loop    /*  2    2 */
+
+CyDelayCycles_done:
+    BX lr                     /*  3    2 */
+
+.else
+
+    CMP r0, #20               /*  1    2   If delay is short - jump to cycle */
+    BLS CyDelayCycles_short   /*  1    2  */
+    PUSH {r1}                 /*  2    2   PUSH r1 to stack */
+    MOVS r1, #1               /*  1    2  */
+
+    SUBS r0, r0, #20          /*  1    2   Subtract overhead */
+    LDR r1,=CYREG_CACHE_CC_CTL/*  2    2   Load flash wait cycles value */
+    LDRB r1, [r1, #0]         /*  2    2  */
+    ANDS r1, #0xC0            /*  1    2  */
+
+    LSRS r1, r1, #6           /*  1    2  */
+    PUSH {r2}                 /*  1    2   PUSH r2 to stack */
+    LDR r2, =cy_flash_cycles  /*  2    2  */
+    LDRB r1, [r2, r1]         /*  2    2  */
+
+    POP {r2}                  /*  2    2   POP r2 from stack */
+    NOP                       /*  1    2   Alignment padding */
+    NOP                       /*  1    2   Alignment padding */
+    NOP                       /*  1    2   Alignment padding */
+
+CyDelayCycles_loop:
+    SBCS r0, r0, r1           /*  1    2  */
+    BPL CyDelayCycles_loop    /*  3    2  */
+    NOP                       /*  1    2   Loop alignment padding */
+    NOP                       /*  1    2   Loop alignment padding */
+
+    POP {r1}                  /*  2    2   POP r1 from stack */
+CyDelayCycles_done:
+    BX lr                     /*  3    2  */
+    NOP                       /*  1    2   Alignment padding */
+    NOP                       /*  1    2   Alignment padding */
+
+CyDelayCycles_short:
+    SBCS r0, r0, #4           /*  1    2  */
+    BPL CyDelayCycles_short   /*  3    2  */
+    BX lr                     /*  3    2  */
+
+cy_flash_cycles:
+.byte 0x0B
+.byte 0x05
+.byte 0x07
+.byte 0x09
+.endif
+
+.endfunc
+
+
+/*******************************************************************************
+* Function Name: CyEnterCriticalSection
+****************************************************************************//**
+*
+*  CyEnterCriticalSection disables interrupts and returns a value indicating
+*  whether interrupts were previously enabled (the actual value depends on
+*  whether the device is PSoC 3 or PSoC 5).
+*
+*  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
+*  with interrupts still enabled. The test and set of the interrupt bits is not
+*  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
+*  corrupting processor state, it must be the policy that all interrupt routines
+*  restore the interrupt enable bits as they were found on entry.
+*
+* \return
+*  uint8
+*   Returns 0 if interrupts were previously enabled or 1 if interrupts
+*   were previously disabled.
+*
+*******************************************************************************/
+/* uint8 CyEnterCriticalSection(void) */
+.global CyEnterCriticalSection
+.func CyEnterCriticalSection, CyEnterCriticalSection
+.type CyEnterCriticalSection, %function
+.thumb_func
+CyEnterCriticalSection:
+    MRS r0, PRIMASK         /* Save and return interrupt state */
+    CPSID I                 /* Disable interrupts */
+    BX lr
+.endfunc
+
+
+/*******************************************************************************
+* Function Name: CyExitCriticalSection
+****************************************************************************//**
+*
+*  CyExitCriticalSection re-enables interrupts if they were enabled before
+*  CyEnterCriticalSection was called. The argument should be the value returned
+*  from CyEnterCriticalSection.
+*
+*  \param uint8 savedIntrStatus:
+*   Saved interrupt status returned by the CyEnterCriticalSection function.
+*
+*******************************************************************************/
+/* void CyExitCriticalSection(uint8 savedIntrStatus) */
+.global CyExitCriticalSection
+.func CyExitCriticalSection, CyExitCriticalSection
+.type CyExitCriticalSection, %function
+.thumb_func
+CyExitCriticalSection:
+    MSR PRIMASK, r0         /* Restore interrupt state */
+    BX lr
+.endfunc
+
+.end
+
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
new file mode 100755 (executable)
index 0000000..4b7b538
--- /dev/null
@@ -0,0 +1,156 @@
+;-------------------------------------------------------------------------------
+; FILENAME: CyBootAsmIar.s
+; Version 5.60
+;
+;  DESCRIPTION:
+;    Assembly routines for IAR Embedded Workbench IDE.
+;
+;-------------------------------------------------------------------------------
+; Copyright 2013-2015, Cypress Semiconductor Corporation.  All rights reserved.
+; You may use this file only in accordance with the license, terms, conditions,
+; disclaimers, and limitations in the end user license agreement accompanying
+; the software package with which this file was provided.
+;-------------------------------------------------------------------------------
+
+    SECTION .text:CODE:ROOT(4)
+    PUBLIC CyDelayCycles
+    PUBLIC CyEnterCriticalSection
+    PUBLIC CyExitCriticalSection
+    INCLUDE cyfitteriar.inc
+    THUMB
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyEnterCriticalSection
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  CyEnterCriticalSection disables interrupts and returns a value indicating
+;  whether interrupts were previously enabled.
+;
+;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
+;  with interrupts still enabled. The test and set of the interrupt bits is not
+;  atomic. Therefore, to avoid a corrupting processor state, it must be the policy 
+;  that all interrupt routines restore the interrupt enable bits as they were 
+;  found on entry.
+;
+; Parameters:
+;  None
+;
+; Return:
+;  uint8
+;   Returns 0 if interrupts were previously enabled or 1 if interrupts
+;   were previously disabled.
+;
+;-------------------------------------------------------------------------------
+; uint8 CyEnterCriticalSection(void)
+
+CyEnterCriticalSection:
+    MRS r0, PRIMASK         ; Save and return interrupt state
+    CPSID I                 ; Disable interrupts
+    BX lr
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyExitCriticalSection
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  CyExitCriticalSection re-enables interrupts if they were enabled before
+;  CyEnterCriticalSection was called. The argument should be the value returned
+;  from CyEnterCriticalSection.
+;
+; Parameters:
+;  uint8 savedIntrStatus:
+;   Saved interrupt status returned by the CyEnterCriticalSection function.
+;
+; Return:
+;  None
+;
+;-------------------------------------------------------------------------------
+; void CyExitCriticalSection(uint8 savedIntrStatus)
+
+CyExitCriticalSection:
+    MSR PRIMASK, r0         ; Restore interrupt state
+    BX lr
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyDelayCycles
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  Delays for the specified number of cycles.
+;
+; Parameters:
+;  uint32 cycles: number of cycles to delay.
+;
+; Return:
+;  None
+;
+;-------------------------------------------------------------------------------
+; void CyDelayCycles(uint32 cycles)
+
+CyDelayCycles: 
+    IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
+                              ; cycles bytes
+    ADDS r0, r0, #2           ;   1   2  Round to nearest multiple of 4
+    LSRS r0, r0, #2           ;   1   2  Divide by 4 and set flags
+    BEQ CyDelayCycles_done    ;   2   2  Skip if 0
+    NOP                       ;   1   2  Loop alignment padding
+CyDelayCycles_loop:
+    SUBS r0, r0, #1           ;   1   2
+    MOV r0, r0                ;   1   2  Pad loop to power of two cycles
+    BNE CyDelayCycles_loop    ;   2   2
+CyDelayCycles_done:
+    BX lr                     ;   3   2
+    
+    ELSE
+    
+    CMP r0, #20               ;   1   2  If delay is short - jump to cycle
+    BLS CyDelayCycles_short   ;   1   2
+    PUSH {r1}                 ;   2   2  PUSH r1 to stack
+    MOVS r1, #1               ;   1   2
+
+    SUBS r0, r0, #20          ;   1   2  Subtract overhead
+    LDR r1,=CYREG_CACHE_CC_CTL;   2   2  Load flash wait cycles value
+    LDRB r1, [r1, #0]         ;   2   2
+    ANDS r1, r1, #0xC0        ;   1   2
+
+    LSRS r1, r1, #6           ;   1   2
+    PUSH {r2}                 ;   1   2  PUSH r2 to stack
+    LDR r2, =cy_flash_cycles  ;   2   2
+    LDRB r1, [r2, r1]         ;   2   2
+
+    POP {r2}                  ;   2   2  POP r2 from stack
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+
+CyDelayCycles_loop:
+    SBCS r0, r0, r1           ;   1   2
+    BPL CyDelayCycles_loop    ;   3   2
+    NOP                       ;   1   2  Loop alignment padding
+    NOP                       ;   1   2  Loop alignment padding
+
+    POP {r1}                  ;   2   2  POP r1 from stack
+CyDelayCycles_done:
+    BX lr                     ;   3   2
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+CyDelayCycles_short:
+    SBCS r0, r0, #4           ;   1   2
+    BPL CyDelayCycles_short   ;   3   2
+    BX lr                     ;   3   2
+    NOP                       ;   1   2   Loop alignment padding
+
+    DATA
+cy_flash_cycles:
+byte_1 DCB 0x0B
+byte_2 DCB 0x05
+byte_3 DCB 0x07
+byte_4 DCB 0x09
+
+    ENDIF
+
+    END
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
new file mode 100755 (executable)
index 0000000..623f127
--- /dev/null
@@ -0,0 +1,161 @@
+;-------------------------------------------------------------------------------
+; FILENAME: CyBootAsmRv.s
+; Version 5.60
+;
+;  DESCRIPTION:
+;    Assembly routines for RealView.
+;
+;-------------------------------------------------------------------------------
+; Copyright 2010-2015, Cypress Semiconductor Corporation.  All rights reserved.
+; You may use this file only in accordance with the license, terms, conditions,
+; disclaimers, and limitations in the end user license agreement accompanying
+; the software package with which this file was provided.
+;-------------------------------------------------------------------------------
+
+    AREA |.text|,CODE,ALIGN=3
+    THUMB
+    EXTERN Reset
+
+    GET cyfitterrv.inc
+
+;-------------------------------------------------------------------------------
+; Function Name: CyDelayCycles
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  Delays for the specified number of cycles.
+;
+; Parameters:
+;  uint32 cycles: number of cycles to delay.
+;
+; Return:
+;  None
+;
+;-------------------------------------------------------------------------------
+; void CyDelayCycles(uint32 cycles)
+    ALIGN 8
+CyDelayCycles FUNCTION
+    EXPORT CyDelayCycles
+    IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
+                              ; cycles bytes
+    ADDS r0, r0, #2           ;   1   2  Round to nearest multiple of 4
+    LSRS r0, r0, #2           ;   1   2  Divide by 4 and set flags
+    BEQ CyDelayCycles_done    ;   2   2  Skip if 0
+    NOP                       ;   1   2  Loop alignment padding
+CyDelayCycles_loop
+    SUBS r0, r0, #1           ;   1   2
+    MOV r0, r0                ;   1   2  Pad loop to power of two cycles
+    BNE CyDelayCycles_loop    ;   2   2
+    NOP                       ;   1   2  Loop alignment padding
+CyDelayCycles_done
+    BX lr                     ;   3   2
+
+    ELSE
+
+    CMP r0, #20               ;   1   2  If delay is short - jump to cycle
+    BLS CyDelayCycles_short   ;   1   2
+    PUSH {r1}                 ;   2   2  PUSH r1 to stack
+    MOVS r1, #1               ;   1   2
+
+    SUBS r0, r0, #20          ;   1   2  Subtract overhead
+    LDR r1,=CYREG_CACHE_CC_CTL;   2   2  Load flash wait cycles value
+    LDRB r1, [r1, #0]         ;   2   2
+    ANDS r1, #0xC0            ;   1   2
+
+    LSRS r1, r1, #6           ;   1   2
+    PUSH {r2}                 ;   1   2  PUSH r2 to stack
+    LDR r2, =cy_flash_cycles  ;   2   2
+    LDRB r1, [r2, r1]         ;   2   2
+
+    POP {r2}                  ;   2   2  POP r2 from stack
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+
+CyDelayCycles_loop
+    SBCS r0, r0, r1           ;   1   2
+    BPL CyDelayCycles_loop    ;   3   2
+    NOP                       ;   1   2  Loop alignment padding
+    NOP                       ;   1   2  Loop alignment padding
+
+    POP {r1}                  ;   2   2  POP r1 from stack
+CyDelayCycles_done
+    BX lr                     ;   3   2
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+
+CyDelayCycles_short
+    SBCS r0, r0, #4           ;   1   2
+    BPL CyDelayCycles_short   ;   3   2
+    BX lr                     ;   3   2
+
+cy_flash_cycles
+byte_1 DCB 0x0B
+byte_2 DCB 0x05
+byte_3 DCB 0x07
+byte_4 DCB 0x09
+
+    ENDIF
+    ENDFUNC
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyEnterCriticalSection
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  CyEnterCriticalSection disables interrupts and returns a value indicating
+;  whether interrupts were previously enabled (the actual value depends on
+;  whether the device is PSoC 3 or PSoC 5).
+;
+;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
+;  with interrupts still enabled. The test and set of the interrupt bits is not
+;  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a
+;  corrupting processor state, it must be the policy that all interrupt routines
+;  restore the interrupt enable bits as they were found on entry.
+;
+; Parameters:
+;  None
+;
+; Return:
+;  uint8
+;   Returns 0 if interrupts were previously enabled or 1 if interrupts
+;   were previously disabled.
+;
+;-------------------------------------------------------------------------------
+; uint8 CyEnterCriticalSection(void)
+CyEnterCriticalSection FUNCTION
+    EXPORT CyEnterCriticalSection
+    MRS r0, PRIMASK         ; Save and return interrupt state
+    CPSID I                 ; Disable interrupts
+    BX lr
+    ENDFUNC
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyExitCriticalSection
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  CyExitCriticalSection re-enables interrupts if they were enabled before
+;  CyEnterCriticalSection was called. The argument should be the value returned
+;  from CyEnterCriticalSection.
+;
+; Parameters:
+;  uint8 savedIntrStatus:
+;   Saved interrupt status returned by the CyEnterCriticalSection function.
+;
+; Return:
+;  None
+;
+;-------------------------------------------------------------------------------
+; void CyExitCriticalSection(uint8 savedIntrStatus)
+CyExitCriticalSection FUNCTION
+    EXPORT CyExitCriticalSection
+    MSR PRIMASK, r0         ; Restore interrupt state
+    BX lr
+    ENDFUNC
+
+    END
+
+; [] END OF FILE
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c
new file mode 100755 (executable)
index 0000000..a7dfe26
--- /dev/null
@@ -0,0 +1,1039 @@
+/***************************************************************************//**
+* \file CyDmac.c
+* \version 5.60
+*
+* \brief
+* Provides an API for the DMAC component. The API includes functions for the
+* DMA controller, DMA channels and Transfer Descriptors. This API is the library
+* version not the auto generated code that gets generated when the user places a
+* DMA component on the schematic.
+*
+* The auto generated code would use the APi's in this module.
+*
+* \note This code is endian agnostic.
+*
+* \note The Transfer Descriptor memory can be used as regular memory if the
+* TD's are not being used.
+*
+* \note This code uses the first byte of each TD to manage the free list of
+* TD's. The user can overwrite this once the TD is allocated.
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2017, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "CyDmac.h"
+
+
+/*******************************************************************************
+* The following variables are initialized from CyDmacConfigure() function that
+* is executed from initialize_psoc() at the early initialization stage.
+* In case of IAR EW IDE, initialize_psoc() is executed before the data sections
+* are initialized. To avoid zeroing, these variables should be initialized
+* properly during segments initialization as well.
+*******************************************************************************/
+static uint8  CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;           /* Current Number of free elements on list */
+static uint8  CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */
+static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;              /* Bit map of DMA channel ownership */
+
+
+/*******************************************************************************
+* Function Name: CyDmacConfigure
+****************************************************************************//**
+*
+* Creates a linked list of all the TDs to be allocated. This function is called
+* by the startup code; you do not normally need to call it. You can call this
+* function if all of the DMA channels are inactive.
+*
+*******************************************************************************/
+void CyDmacConfigure(void) 
+{
+    uint8 dmaIndex;
+
+    /* Set TD list variables. */
+    CyDmaTdFreeIndex     = (uint8)(CY_DMA_NUMBEROF_TDS - 1u);
+    CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;
+
+    /* Make TD free list. */
+    for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--)
+    {
+        CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);
+    }
+
+    /* Make last one point to zero. */
+    CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmacError
+****************************************************************************//**
+*
+*  Returns errors of the last failed DMA transaction.
+*
+* \return Errors of the last failed DMA transaction.
+*
+*  DMAC_PERIPH_ERR:
+*   Set to 1 when a peripheral responds to a bus transaction with an error
+*   response.
+*
+*  DMAC_UNPOP_ACC:
+*   Set to 1 when an access is attempted to an invalid address.
+*
+*  DMAC_BUS_TIMEOUT:
+*   Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values
+*   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
+*
+* Theory:
+*  Once an error occurs the error bits are sticky and are only cleared by
+*  writing 1 to the error register.
+*
+*******************************************************************************/
+uint8 CyDmacError(void) 
+{
+    return((uint8)(((uint32) 0x0Eu) & *CY_DMA_ERR_PTR));
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmacClearError
+****************************************************************************//**
+*
+*  Clears the error bits in the error register of the DMAC.
+*
+* \param error:
+*   Clears the error bits in the DMAC error register.
+*
+*  \param DMAC_PERIPH_ERR:
+*   Set to 1 when a peripheral responds to a bus transaction with an error
+*   response.
+*
+*  \param DMAC_UNPOP_ACC:
+*   Set to 1 when an access is attempted to an invalid address.
+*
+*  \param DMAC_BUS_TIMEOUT:
+*   Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values
+*   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
+*
+* Theory:
+*  Once an error occurs the error bits are sticky and are only cleared by
+*  writing 1 to the error register.
+*
+*******************************************************************************/
+void CyDmacClearError(uint8 error) 
+{
+    *CY_DMA_ERR_PTR = (((uint32)0x0Fu) & ((uint32)error));
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmacErrorAddress
+****************************************************************************//**
+*
+*  When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the
+*  address of the error is written to the error address register and can be read
+*  with this function.
+*
+*  If there are multiple errors, only the address of the first is saved.
+*
+* \return The address that caused the error.
+*
+*******************************************************************************/
+uint32 CyDmacErrorAddress(void) 
+{
+    return(CY_GET_REG32(CY_DMA_ERR_ADR_PTR));
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChAlloc
+****************************************************************************//**
+*
+*  Allocates a channel from the DMAC to be used in all functions that require a
+*  channel handle.
+*
+* \return The allocated channel number. Zero is a valid channel number.
+*  DMA_INVALID_CHANNEL is returned if there are no channels available.
+*
+*******************************************************************************/
+uint8 CyDmaChAlloc(void) 
+{
+    uint8 interruptState;
+    uint8 dmaIndex;
+    uint32 channel = 1u;
+
+
+    /* Enter critical section! */
+    interruptState = CyEnterCriticalSection();
+
+    /* Look for free channel. */
+    for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)
+    {
+        if(0uL == (CyDmaChannels & channel))
+        {
+            /* Mark channel as used. */
+            CyDmaChannels |= channel;
+            break;
+        }
+
+        channel <<= 1u;
+    }
+
+    if(dmaIndex >= CY_DMA_NUMBEROF_CHANNELS)
+    {
+        dmaIndex = CY_DMA_INVALID_CHANNEL;
+    }
+
+    /* Exit critical section! */
+    CyExitCriticalSection(interruptState);
+
+    return(dmaIndex);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChFree
+****************************************************************************//**
+*
+* Frees a channel allocated by \ref DmaChAlloc().
+*
+* \param chHandle The handle previously returned by \ref CyDmaChAlloc() or \ref
+* DMA_DmaInitalize().
+*
+* \return CYRET_SUCCESS if successful.
+* \return CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChFree(uint8 chHandle) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+    uint8 interruptState;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        /* Enter critical section */
+        interruptState = CyEnterCriticalSection();
+
+        /* Clear bit mask that keeps track of ownership. */
+        CyDmaChannels &= ~(((uint32) 1u) << chHandle);
+
+        /* Exit critical section */
+        CyExitCriticalSection(interruptState);
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChEnable
+****************************************************************************//**
+*
+*  Enables the DMA channel. A software or hardware request still must happen
+*  before the channel is executed.
+*
+*  \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref
+*  DMA_DmaInitalize().
+*
+*  \param preserveTds Preserves the original TD state when the TD has completed.
+*  This parameter applies to all TDs in the channel.
+*
+*   0 - When TD is completed, the DMAC leaves the TD configuration values in
+*   their current state, and does not restore them to their original state.
+*
+*   1 - When TD is completed, the DMAC restores the original configuration
+*   values of the TD.
+*
+*  When preserveTds is set, the TD slot that equals the channel number becomes
+*  RESERVED and that becomes where the working registers exist. So, for example,
+*  if you are using CH06 and preserveTds is set, you are not allowed to use TD
+*  slot 6. That is reclaimed by the DMA engine for its private use.
+*
+*  \note Do not chain back to a completed TD if the preserveTds for the channel
+*  is set to 0. When a TD has completed preserveTds for the channel set to 0,
+*  the transfer count will be at 0. If a TD with a transfer count of 0 is
+*  started, the TD will transfer an indefinite amount of data.
+*
+*  Take extra precautions when using the hardware request (DRQ) option when the
+*  preserveTds is set to 0, as you might be requesting the wrong data.
+*
+* \return CYRET_SUCCESS if successful.
+* \return CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        if (0u != preserveTds)
+        {
+            /* Store intermediate TD states separately in CHn_SEP_TD0/1 to
+            *  preserve original TD chain
+            */
+            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;
+        }
+        else
+        {
+            /* Store intermediate and final TD states on top of original TD chain */
+            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);
+        }
+
+        /* Enable channel */
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_EN;
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChDisable
+****************************************************************************//**
+*
+* Disables the DMA channel. Once this function is called, CyDmaChStatus() may
+* be called to determine when the channel is disabled and which TDs were being
+* executed.
+*
+* If it is currently executing it will allow the current burst to finish
+* naturally.
+*
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref
+* DMA_DmaInitalize().
+*
+* \return CYRET_SUCCESS if successful.
+* \return CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChDisable(uint8 chHandle) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        /***********************************************************************
+        * Should not change configuration information of a DMA channel when it
+        * is active (or vulnerable to becoming active).
+        ***********************************************************************/
+
+        /* Disable channel */
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));
+
+        /* Store intermediate and final TD states on top of original TD chain */
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaClearPendingDrq
+****************************************************************************//**
+*
+* Clears pending the DMA data request.
+*
+* \param chHandle Handle to the dma channel.
+*
+* \return CYRET_SUCCESS if successful.
+* \return CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaClearPendingDrq(uint8 chHandle) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        CY_DMA_CH_STRUCT_PTR[chHandle].action[0] |= CY_DMA_CPU_TERM_CHAIN;
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] |= 0x01u;
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChPriority
+****************************************************************************//**
+*
+*  Sets the priority of a DMA channel. You can use this function when you want
+*  to change the priority at run time. If the priority remains the same for a
+*  DMA channel, then you can configure the priority in the .cydwr file.
+*
+*  \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref
+*  DMA_DmaInitalize().
+*
+*  \param priority Priority to set the channel to, 0 - 7.
+*
+* \return CYRET_SUCCESS if successful.
+*  \return CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) 
+{
+    uint8 value;
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        value = CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~(0x0Eu)));
+
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = value | ((uint8) ((priority & 0x7u) << 0x01u));
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChSetExtendedAddress
+****************************************************************************//**
+*
+*  Sets the high 16 bits of the source and destination addresses for the DMA
+*  channel (valid for all TDs in the chain).
+*
+*  \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref
+*  DMA_DmaInitalize().
+*
+*  \param source Upper 16 bit address of the DMA transfer source.
+*
+*  \param destination Upper 16 bit address of the DMA transfer destination.
+*
+* \return CYRET_SUCCESS if successful.
+* \return CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \
+    
+{
+    cystatus status = CYRET_BAD_PARAM;
+    reg16 *convert;
+
+    #if(CY_PSOC5)
+
+        /* 0x1FFF8000-0x1FFFFFFF needs to use alias at 0x20008000-0x2000FFFF */
+        if(source == 0x1FFFu)
+        {
+            source = 0x2000u;
+        }
+
+        if(destination == 0x1FFFu)
+        {
+            destination = 0x2000u;
+        }
+
+    #endif  /* (CY_PSOC5) */
+
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        /* Set source address */
+        convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0];
+        CY_SET_REG16(convert, source);
+
+        /* Set destination address */
+        convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2u];
+        CY_SET_REG16(convert, destination);
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChSetInitialTd
+****************************************************************************//**
+*
+* Sets the initial TD to be executed for the channel when the \ref CyDmaChEnable()
+* function is called.
+*
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or
+* \ref DMA_DmaInitialize().
+*
+* \param startTd Set the TD index as the first TD associated with the
+* channel. Zero is a valid TD index.
+*
+* \return CYRET_SUCCESS if successful.
+* \return CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1u] = startTd;
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChSetRequest
+****************************************************************************//**
+*
+*  Allows the caller to terminate a chain of TDs, terminate one TD, or create a
+*  direct request to start the DMA channel.
+*
+*  \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref
+*  DMA_DmaInitalize().
+*
+*  \param request One of the following constants. Each of the constants is a
+*  three-bit value.
+*   CPU_REQ         - Create a direct request to start the DMA channel
+*   CPU_TERM_TD     - Terminate one TD
+*   CPU_TERM_CHAIN  - Terminate a chain of TDs
+*
+* \return CYRET_SUCCESS if successful.
+* \return CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] |= (request & (CPU_REQ | CPU_TERM_TD | CPU_TERM_CHAIN));
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChGetRequest
+****************************************************************************//**
+*
+* This function allows the caller of \ref CyDmaChSetRequest() to determine if the
+* request was completed.
+*
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref
+* DMA_DmaInitalize().
+*
+* \return Returns a three-bit field, corresponding to the three bits of the
+* request, which describes the state of the previously posted request. If the
+* value is zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle
+* is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChGetRequest(uint8 chHandle) 
+{
+    cystatus status = CY_DMA_INVALID_CHANNEL;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] &
+                            (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN));
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChStatus
+****************************************************************************//**
+*
+*  Determines the status of the DMA channel.
+*
+*  \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref
+*  DMA_DmaInitalize().
+*
+*  \param currentTd The address to store the index of the current TD. Can be NULL
+*  if the value is not needed.
+*
+*  \param state The address to store the state of the channel. Can be NULL if the
+*  value is not needed.
+*
+*   STATUS_TD_ACTIVE
+*    \param 0: Channel is not currently being serviced by DMAC
+*    \param 1: Channel is currently being serviced by DMAC
+*
+*   STATUS_CHAIN_ACTIVE
+*    \param 0: TD chain is inactive; either no DMA requests have triggered a new chain
+*       or the previous chain has completed.
+*    \param 1: TD chain has been triggered by a DMA request
+*
+* \return CYRET_SUCCESS if successful.
+* \return CYRET_BAD_PARAM if chHandle is invalid.
+*
+* Theory:
+*   The caller can check on the activity of the Current TD and the Chain.
+*
+*******************************************************************************/
+cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        if(NULL != currentTd)
+        {
+            *currentTd = CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1] & 0x7Fu;
+        }
+
+        if(NULL != state)
+        {
+            *state= CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[0];
+        }
+
+        status = CYRET_SUCCESS;
+    }
+
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChSetConfiguration
+****************************************************************************//**
+*
+* Sets configuration information of the channel.
+*
+*  \param uint8 chHandle:
+*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().
+*
+*  \param uint8 burstCount:
+*   Specifies the size of bursts (1 to 127) the data transfer should be divided
+*   into. If this value is zero then the whole transfer is done in one burst.
+*
+*  \param uint8 requestPerBurst:
+*   The whole of the data can be split into multiple bursts, if this is
+*   \param required to complete the transaction:
+*    \param 0: All subsequent bursts after the first burst will be automatically
+*       requested and carried out
+*    \param 1: All subsequent bursts after the first burst must also be individually
+*       requested.
+*
+*  \param uint8 tdDone0:
+*   Selects one of the TERMOUT0 interrupt lines to signal completion. The line
+*   connected to the nrq terminal will determine the TERMOUT0_SEL definition and
+*   should be used as supplied by cyfitter.h
+*
+*  \param uint8 tdDone1:
+*   Selects one of the TERMOUT1 interrupt lines to signal completion. The line
+*   connected to the nrq terminal will determine the TERMOUT1_SEL definition and
+*   should be used as supplied by cyfitter.h
+*
+*  \param uint8 tdStop:
+*   Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD
+*   should terminate. The signal connected to the trq terminal will determine
+*   which TERMIN (termination request) is used.
+*
+* \return
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst,
+                                 uint8 tdDone0, uint8 tdDone1, uint8 tdStop) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBurst & 0x1u) << 7u));
+        CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[1] = ((uint8)((tdDone1 & 0xFu) << 4u)) | (tdDone0 & 0xFu);
+        CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[2] = 0x0Fu & tdStop;
+        CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[3] = 0u; /* burstcount_remain. */
+
+        status = CYRET_SUCCESS;
+    }
+
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdAllocate
+****************************************************************************//**
+*
+*  Allocates a TD for use with an allocated DMA channel.
+*
+* \return
+*  Zero-based index of the TD to be used by the caller. Since there are 128 TDs
+*  minus the reserved TDs (0 to 23), the value returned would range from 24 to
+*  127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs
+*  available.
+*
+*******************************************************************************/
+uint8 CyDmaTdAllocate(void) 
+{
+    uint8 interruptState;
+    uint8 element = CY_DMA_INVALID_TD;
+
+    /* Enter critical section! */
+    interruptState = CyEnterCriticalSection();
+
+    if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)
+    {
+        /* Get pointer to Next available. */
+        element = CyDmaTdFreeIndex;
+
+        /* Decrement the count. */
+        CyDmaTdCurrentNumber--;
+
+        /* Update next available pointer. */
+        CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];
+    }
+
+    /* Exit critical section! */
+    CyExitCriticalSection(interruptState);
+
+    return(element);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdFree
+****************************************************************************//**
+*
+*  Returns a TD to the free list.
+*
+*  \param uint8 tdHandle:
+*   The TD handle returned by the CyDmaTdAllocate().
+*
+*******************************************************************************/
+void CyDmaTdFree(uint8 tdHandle) 
+{
+    if(tdHandle < CY_DMA_NUMBEROF_TDS)
+    {
+        /* Enter critical section! */
+        uint8 interruptState = CyEnterCriticalSection();
+
+        /* Get pointer to Next available. */
+        CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;
+
+        /* Set new Next Available. */
+        CyDmaTdFreeIndex = tdHandle;
+
+        /* Keep track of how many left. */
+        CyDmaTdCurrentNumber++;
+
+        /* Exit critical section! */
+        CyExitCriticalSection(interruptState);
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdFreeCount
+****************************************************************************//**
+*
+*  Returns the number of free TDs available to be allocated.
+*
+* \return
+*  The number of free TDs.
+*
+*******************************************************************************/
+uint8 CyDmaTdFreeCount(void) 
+{
+    return(CyDmaTdCurrentNumber - CY_DMA_NUMBEROF_CHANNELS);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdSetConfiguration
+****************************************************************************//**
+*
+*  Configures the TD.
+*
+*  \param uint8 tdHandle:
+*   A handle previously returned by CyDmaTdAlloc().
+*
+*  \param uint16 transferCount:
+*   The size of the data transfer (in bytes) for this TD. A size of zero will
+*   cause the transfer to continue indefinitely. This parameter is limited to
+*   4095 bytes; the TD is not initialized at all when a higher value is passed.
+*
+*  \param uint8 nextTd:
+*   Zero based index of the next Transfer Descriptor in the TD chain. Zero is a
+*   valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain.
+*   DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No
+*   further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and
+*   PSoC 5LP silicons.
+*
+*  \param uint8 configuration:
+*   Stores the Bit field of configuration bits.
+*
+*   CY_DMA_TD_SWAP_EN        - Perform endian swap
+*
+*   CY_DMA_TD_SWAP_SIZE4     - Swap size = 4 bytes
+*
+*   CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger
+*                              automatically when the current TD completes.
+*
+*   CY_DMA_TD_TERMIN_EN      - Terminate this TD if a positive edge on the trq
+*                              input line occurs. The positive edge must occur
+*                              during a burst. That is the only time the DMAC
+*                              will listen for it.
+*
+*   DMA__TD_TERMOUT_EN       - When this TD completes, the TERMOUT signal will
+*                              generate a pulse. Note that this option is
+*                              instance specific with the instance name followed
+*                              by two underscores. In this example, the instance
+*                              name is DMA.
+*
+*   CY_DMA_TD_INC_DST_ADR    - Increment DST_ADR according to the size of each
+*                              data transaction in the burst.
+*
+*   CY_DMA_TD_INC_SRC_ADR    - Increment SRC_ADR according to the size of each
+*                              data transaction in the burst.
+*
+* \return
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if tdHandle or transferCount is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) \
+    
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if((tdHandle < CY_DMA_NUMBEROF_TDS) && (0u == (0xF000u & transferCount)))
+    {
+        /* Set 12 bits transfer count. */
+        reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u];
+        CY_SET_REG16(convert, transferCount);
+
+        /* Set Next TD pointer. */
+        CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u] = nextTd;
+
+        /* Configure the TD */
+        CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u] = configuration;
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdGetConfiguration
+****************************************************************************//**
+*
+*  Retrieves the configuration of the TD. If a NULL pointer is passed as a
+*  parameter, that parameter is skipped. You may request only the values you are
+*  interested in.
+*
+*  \param uint8 tdHandle:
+*   A handle previously returned by CyDmaTdAlloc().
+*
+*  \param uint16 * transferCount:
+*   The address to store the size of the data transfer (in bytes) for this TD.
+*   A size of zero could indicate that the TD has completed its transfer, or
+*   that the TD is doing an indefinite transfer.
+*
+*  \param uint8 * nextTd:
+*   The address to store the index of the next TD in the TD chain.
+*
+*  \param uint8 * configuration:
+*   The address to store the Bit field of configuration bits.
+*   See CyDmaTdSetConfiguration() function description.
+*
+* \return
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if tdHandle is invalid.
+*
+* \sideeffect
+*  If TD has a transfer count of N and is executed, the transfer count becomes
+*  0. If it is reexecuted, the Transfer count of zero will be interpreted as a
+*  request for indefinite transfer. Be careful when requesting TD with a
+*  transfer count of zero.
+*
+*******************************************************************************/
+cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) \
+    
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(tdHandle < CY_DMA_NUMBEROF_TDS)
+    {
+        /* If we have pointer */
+        if(NULL != transferCount)
+        {
+            /* Get 12 bits of transfer count */
+            reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];
+            *transferCount = 0x0FFFu & CY_GET_REG16(convert);
+        }
+
+        /* If we have pointer */
+        if(NULL != nextTd)
+        {
+            /* Get Next TD pointer */
+            *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];
+        }
+
+        /* If we have pointer */
+        if(NULL != configuration)
+        {
+            /* Get configuration TD */
+            *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];
+        }
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdSetAddress
+****************************************************************************//**
+*
+*  Sets the lower 16 bits of the source and destination addresses for this TD
+*  only.
+*
+*  \param uint8 tdHandle:
+*   A handle previously returned by CyDmaTdAlloc().
+*
+*  \param uint16 source:
+*   The lower 16 address bits of the source of the data transfer.
+*
+*  \param uint16 destination:
+*   The lower 16 address bits of the destination of the data transfer.
+*
+* \return
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if tdHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+    reg16 *convert;
+
+    if(tdHandle < CY_DMA_NUMBEROF_TDS)
+    {
+        /* Set source address */
+        convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u];
+        CY_SET_REG16(convert, source);
+
+        /* Set destination address */
+        convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u];
+        CY_SET_REG16(convert, destination);
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdGetAddress
+****************************************************************************//**
+*
+*  Retrieves the lower 16 bits of the source and/or destination addresses for
+*  this TD only. If NULL is passed for a pointer parameter, that value is
+*  skipped. You may request only the values of interest.
+*
+*  \param uint8 tdHandle:
+*   A handle previously returned by CyDmaTdAlloc().
+*
+*  \param uint16 * source:
+*   The address to store the lower 16 address bits of the source of the data
+*   transfer.
+*
+*  \param uint16 * destination:
+*   The address to store the lower 16 address bits of the destination of the
+*   data transfer.
+*
+* \return
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if tdHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+    reg16 *convert;
+
+    if(tdHandle < CY_DMA_NUMBEROF_TDS)
+    {
+        /* If we have a pointer. */
+        if(NULL != source)
+        {
+            /* Get source address */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u];
+            *source = CY_GET_REG16(convert);
+        }
+
+        /* If we have a pointer. */
+        if(NULL != destination)
+        {
+            /* Get Destination address. */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u];
+            *destination = CY_GET_REG16(convert);
+        }
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChRoundRobin
+****************************************************************************//**
+*
+* Either enables or disables the Round-Robin scheduling enforcement algorithm.
+* Within a priority level a Round-Robin fairness algorithm is enforced.
+*
+* \param uint8 chHandle:
+*  A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize().
+*
+* \param uint8 enableRR:
+*  \param 0: Disable Round-Robin fairness algorithm
+*  \param 1: Enable Round-Robin fairness algorithm
+*
+* \return
+* CYRET_SUCCESS if successful.
+* CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        if (0u != enableRR)
+        {
+            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= (uint8)CY_DMA_ROUND_ROBIN_ENABLE;
+        }
+        else
+        {
+            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE);
+        }
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h
new file mode 100755 (executable)
index 0000000..ee99e16
--- /dev/null
@@ -0,0 +1,228 @@
+/***************************************************************************//**
+* \file CyDmac.h
+* \version 5.60
+*
+* \brief Provides the function definitions for the DMA Controller.
+*
+* \note Documentation of the API's in this file is located in the System
+* Reference Guide provided with PSoC Creator.
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2017, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_BOOT_CYDMAC_H)
+#define CY_BOOT_CYDMAC_H
+
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cydevice_trm.h"
+#include "CyLib.h"
+
+
+/***************************************
+*    Function Prototypes
+***************************************/
+
+/* DMA Controller functions. */
+void    CyDmacConfigure(void) ;
+uint8   CyDmacError(void) ;
+void    CyDmacClearError(uint8 error) ;
+uint32  CyDmacErrorAddress(void) ;
+
+/* Channel specific functions. */
+uint8    CyDmaChAlloc(void) ;
+cystatus CyDmaChFree(uint8 chHandle) ;
+cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ;
+cystatus CyDmaChDisable(uint8 chHandle) ;
+cystatus CyDmaClearPendingDrq(uint8 chHandle) ;
+cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ;
+cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\
+;
+cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ;
+cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ;
+cystatus CyDmaChGetRequest(uint8 chHandle) ;
+cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ;
+cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0,
+                                 uint8 tdDone1, uint8 tdStop) ;
+cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ;
+
+/* Transfer Descriptor functions. */
+uint8    CyDmaTdAllocate(void) ;
+void     CyDmaTdFree(uint8 tdHandle) ;
+uint8    CyDmaTdFreeCount(void) ;
+cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\
+;
+cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\
+;
+cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ;
+cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ;
+
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+typedef struct dmac_ch_struct
+{
+    volatile uint8 basic_cfg[4];
+    volatile uint8 action[4];
+    volatile uint8 basic_status[4];
+    volatile uint8 reserved[4];
+
+} dmac_ch;
+
+
+typedef struct dmac_cfgmem_struct
+{
+    volatile uint8 CFG0[4];
+    volatile uint8 CFG1[4];
+
+} dmac_cfgmem;
+
+
+typedef struct dmac_tdmem_struct
+{
+    volatile uint8  TD0[4];
+    volatile uint8  TD1[4];
+
+} dmac_tdmem;
+
+
+typedef struct dmac_tdmem2_struct
+{
+    volatile uint16 xfercnt;
+    volatile uint8  next_td_ptr;
+    volatile uint8  flags;
+    volatile uint16 src_adr;
+    volatile uint16 dst_adr;
+} dmac_tdmem2;
+
+
+/***************************************
+* API Constants
+***************************************/
+
+#define CY_DMA_INVALID_CHANNEL      0xFFu   /* Invalid Channel ID */
+#define CY_DMA_INVALID_TD           0xFFu   /* Invalid TD */
+#define CY_DMA_END_CHAIN_TD         0xFFu   /* End of chain TD */
+#define CY_DMA_DISABLE_TD           0xFEu
+
+#define CY_DMA_TD_SIZE              0x08u
+
+/* "u" was removed as workaround for Keil compiler bug */
+#define CY_DMA_TD_SWAP_EN           0x80
+#define CY_DMA_TD_SWAP_SIZE4        0x40
+#define CY_DMA_TD_AUTO_EXEC_NEXT    0x20
+#define CY_DMA_TD_TERMIN_EN         0x10
+#define CY_DMA_TD_TERMOUT1_EN       0x08
+#define CY_DMA_TD_TERMOUT0_EN       0x04
+#define CY_DMA_TD_INC_DST_ADR       0x02
+#define CY_DMA_TD_INC_SRC_ADR       0x01
+
+#define CY_DMA_NUMBEROF_TDS         128u
+#define CY_DMA_NUMBEROF_CHANNELS    ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE))
+
+/* Action register bits */
+#define CY_DMA_CPU_REQ              ((uint8)(1u << 0u))
+#define CY_DMA_CPU_TERM_TD          ((uint8)(1u << 1u))
+#define CY_DMA_CPU_TERM_CHAIN       ((uint8)(1u << 2u))
+
+/* Basic Status register bits */
+#define CY_DMA_STATUS_CHAIN_ACTIVE  ((uint8)(1u << 0u))
+#define CY_DMA_STATUS_TD_ACTIVE     ((uint8)(1u << 1u))
+
+/* DMA controller register error bits */
+#define CY_DMA_BUS_TIMEOUT          (1u << 1u)
+#define CY_DMA_UNPOP_ACC            (1u << 2u)
+#define CY_DMA_PERIPH_ERR           (1u << 3u)
+
+/* Round robin bits */
+#define CY_DMA_ROUND_ROBIN_ENABLE   ((uint8)(1u << 4u))
+
+
+/*******************************************************************************
+* CyDmaChEnable() / CyDmaChDisable() API constants
+*******************************************************************************/
+#define CY_DMA_CH_BASIC_CFG_EN           (0x01u)
+#define CY_DMA_CH_BASIC_CFG_WORK_SEP     (0x20u)
+
+
+/***************************************
+* Registers
+***************************************/
+
+#define CY_DMA_CFG_REG              (*(reg32 *) CYREG_PHUB_CFG)
+#define CY_DMA_CFG_PTR              ( (reg32 *) CYREG_PHUB_CFG)
+
+#define CY_DMA_ERR_REG              (*(reg32 *) CYREG_PHUB_ERR)
+#define CY_DMA_ERR_PTR              ( (reg32 *) CYREG_PHUB_ERR)
+
+#define CY_DMA_ERR_ADR_REG          (*(reg32 *) CYREG_PHUB_ERR_ADR)
+#define CY_DMA_ERR_ADR_PTR          ( (reg32 *) CYREG_PHUB_ERR_ADR)
+
+#define CY_DMA_CH_STRUCT_REG        (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE)
+#define CY_DMA_CH_STRUCT_PTR        ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE)
+
+#define CY_DMA_CFGMEM_STRUCT_REG    (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE)
+#define CY_DMA_CFGMEM_STRUCT_PTR    ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE)
+
+#define CY_DMA_TDMEM_STRUCT_REG     (*(dmac_tdmem  CYXDATA *) CYDEV_PHUB_TDMEM0_BASE)
+#define CY_DMA_TDMEM_STRUCT_PTR     ( (dmac_tdmem  CYXDATA *) CYDEV_PHUB_TDMEM0_BASE)
+
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+#define DMA_INVALID_CHANNEL         (CY_DMA_INVALID_CHANNEL)
+#define DMA_INVALID_TD              (CY_DMA_INVALID_TD)
+#define DMA_END_CHAIN_TD            (CY_DMA_END_CHAIN_TD)
+#define DMAC_TD_SIZE                (CY_DMA_TD_SIZE)
+#define TD_SWAP_EN                  (CY_DMA_TD_SWAP_EN)
+#define TD_SWAP_SIZE4               (CY_DMA_TD_SWAP_SIZE4)
+#define TD_AUTO_EXEC_NEXT           (CY_DMA_TD_AUTO_EXEC_NEXT)
+#define TD_TERMIN_EN                (CY_DMA_TD_TERMIN_EN)
+#define TD_TERMOUT1_EN              (CY_DMA_TD_TERMOUT1_EN)
+#define TD_TERMOUT0_EN              (CY_DMA_TD_TERMOUT0_EN)
+#define TD_INC_DST_ADR              (CY_DMA_TD_INC_DST_ADR)
+#define TD_INC_SRC_ADR              (CY_DMA_TD_INC_SRC_ADR)
+#define NUMBEROF_TDS                (CY_DMA_NUMBEROF_TDS)
+#define NUMBEROF_CHANNELS           (CY_DMA_NUMBEROF_CHANNELS)
+#define CPU_REQ                     (CY_DMA_CPU_REQ)
+#define CPU_TERM_TD                 (CY_DMA_CPU_TERM_TD)
+#define CPU_TERM_CHAIN              (CY_DMA_CPU_TERM_CHAIN)
+#define STATUS_CHAIN_ACTIVE         (CY_DMA_STATUS_CHAIN_ACTIVE)
+#define STATUS_TD_ACTIVE            (CY_DMA_STATUS_TD_ACTIVE)
+#define DMAC_BUS_TIMEOUT            (CY_DMA_BUS_TIMEOUT)
+#define DMAC_UNPOP_ACC              (CY_DMA_UNPOP_ACC)
+#define DMAC_PERIPH_ERR             (CY_DMA_PERIPH_ERR)
+#define ROUND_ROBIN_ENABLE          (CY_DMA_ROUND_ROBIN_ENABLE)
+#define DMA_DISABLE_TD              (CY_DMA_DISABLE_TD)
+
+#define DMAC_CFG                    (CY_DMA_CFG_PTR)
+#define DMAC_ERR                    (CY_DMA_ERR_PTR)
+#define DMAC_ERR_ADR                (CY_DMA_ERR_ADR_PTR)
+#define DMAC_CH                     (CY_DMA_CH_STRUCT_PTR)
+#define DMAC_CFGMEM                 (CY_DMA_CFGMEM_STRUCT_PTR)
+#define DMAC_TDMEM                  (CY_DMA_TDMEM_STRUCT_PTR)
+
+#endif  /* (CY_BOOT_CYDMAC_H) */
+
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c
new file mode 100755 (executable)
index 0000000..3436c38
--- /dev/null
@@ -0,0 +1,684 @@
+/***************************************************************************//**
+* \file CyFlash.c
+* \version 5.60
+*
+* \brief Provides an API for the FLASH/EEPROM.
+*
+* \note This code is endian agnostic.
+*
+* \note Documentation of the API's in this file is located in the System
+* Reference Guide provided with PSoC Creator.
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "CyFlash.h"
+
+/*  The number of EEPROM arrays */
+#define CY_FLASH_EEPROM_NUMBER_ARRAYS                 (1u)
+
+
+/*******************************************************************************
+* Holds the die temperature, updated by CySetTemp(). Used for flash writing.
+* The first byte is the sign of the temperature (0 = negative, 1 = positive).
+* The second byte is the magnitude.
+*******************************************************************************/
+uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
+
+#if(CYDEV_ECC_ENABLE == 0)
+    static uint8 * rowBuffer = 0;
+#endif  /* (CYDEV_ECC_ENABLE == 0) */
+
+
+static cystatus CySetTempInt(void);
+static cystatus CyFlashGetSpcAlgorithm(void);
+
+
+/*******************************************************************************
+* Function Name: CyFlash_Start
+****************************************************************************//**
+*
+*  Enable the Flash.
+*
+*******************************************************************************/
+void CyFlash_Start(void) 
+{
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+
+    /***************************************************************************
+    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+    * is required for the SPC to function.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
+
+
+    /***************************************************************************
+    * The wake count defines the number of Bus Clock cycles it takes for the
+    * flash or eeprom to wake up from a low power mode independent of the chip
+    * power mode. Wake up time for these blocks is 5 us.
+    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+    * This register needs to be written with a value dependent on the Bus Clock
+    * frequency so that the duration of the cycles is equal to or greater than
+    * the 5 us delay required.
+    ***************************************************************************/
+    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+    /***************************************************************************
+    * Enable flash. Active flash macros consume current, but re-enabling a
+    * disabled flash macro takes 5us. If the CPU attempts to fetch out of the
+    * macro during that time, it will be stalled. This bit allows the flash to
+    * be enabled even if the CPU is disabled, which allows a quicker return to
+    * code execution.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_FM;
+    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;
+
+    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+    {
+        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+    }
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyFlash_Stop
+****************************************************************************//**
+*
+*  Disable the Flash.
+*
+* \sideeffect
+*  This setting is ignored as long as the CPU is currently running.  This will
+*  only take effect when the CPU is later disabled.
+*
+*******************************************************************************/
+void CyFlash_Stop(void) 
+{
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));
+    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CySetTempInt
+****************************************************************************//**
+*
+*  Sends a command to the SPC to read the die temperature. Sets a global value
+*  used by the Write function. This function must be called once before
+*  executing a series of Flash writing functions.
+*
+* \return
+*  status:
+*   CYRET_SUCCESS - if successful
+*   CYRET_LOCKED  - if Flash writing already in use
+*   CYRET_UNKNOWN - if there was an SPC error
+*
+*******************************************************************************/
+static cystatus CySetTempInt(void) 
+{
+    cystatus status;
+
+    /* Make sure SPC is powered */
+    CySpcStart();
+
+    /* Plan for failure. */
+    status = CYRET_UNKNOWN;
+
+    if(CySpcLock() == CYRET_SUCCESS)
+    {
+        /* Write the command. */
+        if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES))
+        {
+            do
+            {
+                if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE)
+                {
+                    status = CYRET_SUCCESS;
+
+                    while(CY_SPC_BUSY)
+                    {
+                        /* Spin until idle. */
+                        CyDelayUs(1u);
+                    }
+                    break;
+                }
+
+            } while(CY_SPC_BUSY);
+        }
+
+        CySpcUnlock();
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyFlashGetSpcAlgorithm
+****************************************************************************//**
+*
+*  Sends a command to the SPC to download code into RAM.
+*
+* \return
+*  status:
+*   CYRET_SUCCESS - if successful
+*   CYRET_LOCKED  - if Flash writing already in use
+*   CYRET_UNKNOWN - if there was an SPC error
+*
+*******************************************************************************/
+static cystatus CyFlashGetSpcAlgorithm(void) 
+{
+    cystatus status;
+
+    /* Make sure SPC is powered */
+    CySpcStart();
+
+    if(CySpcLock() == CYRET_SUCCESS)
+    {
+        status = CySpcGetAlgorithm();
+
+        if(CYRET_STARTED == status)
+        {
+            while(CY_SPC_BUSY)
+            {
+                /* Spin until idle. */
+                CyDelayUs(1u);
+            }
+
+            if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+            {
+                status = CYRET_SUCCESS;
+            }
+        }
+        CySpcUnlock();
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CySetTemp
+****************************************************************************//**
+*
+*  This is a wraparound for CySetTempInt(). It is used to return the second
+*  successful read of the temperature value.
+*
+* \return
+*  status:
+*   CYRET_SUCCESS if successful.
+*   CYRET_LOCKED  if Flash writing already in use
+*   CYRET_UNKNOWN if there was an SPC error.
+*
+*  uint8 dieTemperature[2]:
+*   Holds the die temperature for the flash writing algorithm. The first byte is
+*   the sign of the temperature (0 = negative, 1 = positive). The second byte is
+*   the magnitude.
+*
+*******************************************************************************/
+cystatus CySetTemp(void) 
+{
+    cystatus status = CyFlashGetSpcAlgorithm();
+
+    if(status == CYRET_SUCCESS)
+    {
+        status = CySetTempInt();
+    }
+
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CySetFlashEEBuffer
+****************************************************************************//**
+*
+*  Sets the user supplied temporary buffer to store SPC data while performing
+*  Flash and EEPROM commands. This buffer is only necessary when the Flash ECC
+*  is disabled.
+*
+*  \param buffer:
+*   The address of a block of memory to store temporary memory. The size of the
+*   block of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.
+*
+* \return
+*  status:
+*   CYRET_SUCCESS if successful.
+*   CYRET_BAD_PARAM if the buffer is NULL
+*
+*******************************************************************************/
+cystatus CySetFlashEEBuffer(uint8 * buffer) 
+{
+    cystatus status = CYRET_SUCCESS;
+
+    CySpcStart();
+
+    #if(CYDEV_ECC_ENABLE == 0)
+
+        if(NULL == buffer)
+        {
+            rowBuffer = rowBuffer;
+            status = CYRET_BAD_PARAM;
+        }
+        else if(CySpcLock() != CYRET_SUCCESS)
+        {
+            rowBuffer = rowBuffer;
+            status = CYRET_LOCKED;
+        }
+        else
+        {
+            rowBuffer = buffer;
+            CySpcUnlock();
+        }
+
+    #else
+
+        /* To suppress warning */
+        buffer = buffer;
+
+    #endif  /* (CYDEV_ECC_ENABLE == 0u) */
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyWriteRowData
+****************************************************************************//**
+*
+*  Sends a command to the SPC to load and program a row of data in
+*  Flash or EEPROM.
+*
+*  \param arrayID:    ID of the array to write.
+*   The type of write, Flash or EEPROM, is determined from the array ID.
+*   The arrays in the part are sequential starting at the first ID for the
+*   specific memory type. The array ID for the Flash memory lasts from 0x00 to
+*   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
+*  \param rowAddress: rowAddress of flash row to program.
+*  \param rowData:    Array of bytes to write.
+*
+* \return
+*  status:
+*   CYRET_SUCCESS if successful.
+*   CYRET_LOCKED if the SPC is already in use.
+*   CYRET_CANCELED if command not accepted
+*   CYRET_UNKNOWN if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
+{
+    uint16 rowSize;
+    cystatus status;
+
+    rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
+    status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
+
+    return(status);
+}
+
+
+/*******************************************************************
+* If "Enable Error Correcting Code (ECC)" and "Store Configuration
+* Data in ECC" DWR options are disabled, ECC section is available
+* for user data.
+*******************************************************************/
+#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
+
+    /*******************************************************************************
+    * Function Name: CyWriteRowConfig
+    ****************************************************************************//**
+    *
+    *  Sends a command to the SPC to load and program a row of config data in the
+    *  Flash. This function is only valid for Flash array IDs (not for EEPROM).
+    *
+    *  \param arrayId:      ID of the array to write
+    *   The arrays in the part are sequential starting at the first ID for the
+    *   specific memory type. The array ID for the Flash memory lasts
+    *   from 0x00 to 0x3F.
+    *  \param rowAddress:   The address of the sector to erase.
+    *  \param rowECC:       The array of bytes to write.
+    *
+    * \return
+    *  status:
+    *   CYRET_SUCCESS if successful.
+    *   CYRET_LOCKED if the SPC is already in use.
+    *   CYRET_CANCELED if command not accepted
+    *   CYRET_UNKNOWN if there was an SPC error.
+    *
+    *******************************************************************************/
+    cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\
+    
+    {
+        cystatus status;
+
+        status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);
+
+        return (status);
+    }
+
+#endif  /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
+
+
+
+/*******************************************************************************
+* Function Name: CyWriteRowFull
+****************************************************************************//**
+*  Sends a command to the SPC to load and program a row of data in the Flash.
+*  rowData array is expected to contain Flash and ECC data if needed.
+*
+*  \param arrayId:    FLASH or EEPROM array id.
+*  \param rowData:    Pointer to a row of data to write.
+*  \param rowNumber:  Zero based number of the row.
+*  \param rowSize:    Size of the row.
+*
+* \return
+*  CYRET_SUCCESS if successful.
+*  CYRET_LOCKED if the SPC is already in use.
+*  CYRET_CANCELED if command not accepted
+*  CYRET_UNKNOWN if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
+        
+{
+    cystatus status = CYRET_SUCCESS;
+
+    if((arrayId <=  CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS  + CY_SPC_FIRST_FLASH_ARRAYID)))
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if(arrayId > CY_SPC_LAST_EE_ARRAYID)
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if(arrayId <=  CY_SPC_LAST_FLASH_ARRAYID)
+    {
+        /* Flash */
+        if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))
+        {
+            status = CYRET_BAD_PARAM;
+        }
+    }
+    else
+    {
+        /* EEPROM */
+        if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))
+        {
+            status = CYRET_BAD_PARAM;
+        }
+
+        if(CY_EEPROM_SIZEOF_ROW != rowSize)
+        {
+            status = CYRET_BAD_PARAM;
+        }
+    }
+
+    if(rowData == NULL)
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+
+    if(status == CYRET_SUCCESS)
+    {
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Load row data into SPC internal latch */
+            status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);
+
+            if(CYRET_STARTED == status)
+            {
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait for SPC to finish and get SPC status */
+                    CyDelayUs(1u);
+                }
+
+                /* Hide SPC status */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+
+                if(CYRET_SUCCESS == status)
+                {
+                    /* Erase and program flash with data from SPC interval latch */
+                    status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+
+                    if(CYRET_STARTED == status)
+                    {
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait for SPC to finish and get SPC status */
+                            CyDelayUs(1u);
+                        }
+
+                        /* Hide SPC status */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                        else
+                        {
+                            status = CYRET_UNKNOWN;
+                        }
+                    }
+                }
+            }
+            CySpcUnlock();
+        }   /* if(CySpcLock() == CYRET_SUCCESS) */
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyFlash_SetWaitCycles
+****************************************************************************//**
+*
+*  Sets the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash. This function must be called before increasing
+*  the CPU clock frequency. It can optionally be called after lowering the CPU
+*  clock frequency in order to improve the CPU performance.
+*
+*  \param uint8 freq:
+*   Frequency of operation in Megahertz.
+*
+*******************************************************************************/
+void CyFlash_SetWaitCycles(uint8 freq) 
+{
+    uint8 interruptState;
+
+    /* Save current global interrupt enable and disable it */
+    interruptState = CyEnterCriticalSection();
+
+    /***************************************************************************
+    * The number of clock cycles the cache will wait before it samples data
+    * coming back from the Flash must be equal or greater to to the CPU frequency
+    * outlined in clock cycles.
+    ***************************************************************************/
+
+    if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_1_VALUE_MASK;
+    }
+    else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_2_VALUE_MASK;
+    }
+    else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_3_VALUE_MASK;
+    }
+#if (CY_PSOC5)
+    else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_4_VALUE_MASK;
+    }
+    else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_5_VALUE_MASK;
+    }
+#endif  /* (CY_PSOC5) */
+    else
+    {
+        /* Halt CPU in debug mode if frequency is invalid */
+        CYASSERT(0u != 0u);
+    }
+
+    /* Restore global interrupt enable state */
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyEEPROM_Start
+****************************************************************************//**
+*
+*  Enable the EEPROM.
+*
+*******************************************************************************/
+void CyEEPROM_Start(void) 
+{
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+
+    /***************************************************************************
+    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+    * is required for the SPC to function.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
+
+
+    /***************************************************************************
+    * The wake count defines the number of Bus Clock cycles it takes for the
+    * flash or EEPROM to wake up from a low power mode independent of the chip
+    * power mode. Wake up time for these blocks is 5 us.
+    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+    * This register needs to be written with a value dependent on the Bus Clock
+    * frequency so that the duration of the cycles is equal to or greater than
+    * the 5 us delay required.
+    ***************************************************************************/
+    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+    /***************************************************************************
+    * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,
+    * the EE will not acknowledge a PHUB request.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_EE;
+    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;
+
+    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+    {
+        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+    }
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyEEPROM_Stop
+****************************************************************************//**
+*
+*  Disable the EEPROM.
+*
+*******************************************************************************/
+void CyEEPROM_Stop (void) 
+{
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));
+    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyEEPROM_ReadReserve
+****************************************************************************//**
+*
+*  Request access to the EEPROM for reading and wait until access is available.
+*
+*******************************************************************************/
+void CyEEPROM_ReadReserve(void) 
+{
+    /* Make request for PHUB to have access */
+    CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;
+
+    while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))
+    {
+        /* Wait for acknowledgment from PHUB */
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyEEPROM_ReadRelease
+****************************************************************************//**
+*
+*  Release the read reservation of the EEPROM.
+*
+*******************************************************************************/
+void CyEEPROM_ReadRelease(void) 
+{
+    CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);
+}
+
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h
new file mode 100755 (executable)
index 0000000..bed86c7
--- /dev/null
@@ -0,0 +1,322 @@
+/***************************************************************************//**
+* \file CyFlash.h
+* \version 5.60
+*
+* \brief Provides the function definitions for the FLASH/EEPROM.
+*
+* \note Documentation of the API's in this file is located in the System
+* Reference Guide provided with PSoC Creator.
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2017, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_BOOT_CYFLASH_H)
+#define CY_BOOT_CYFLASH_H
+
+#include "cydevice_trm.h"
+#include "cytypes.h"
+#include "CyLib.h"
+#include "CySpc.h"
+
+#define CY_FLASH_DIE_TEMP_DATA_SIZE      (2u)    /* Die temperature data size */
+
+extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
+
+
+/***************************************
+*    API Constants
+***************************************/
+
+#define CY_FLASH_BASE               (CYDEV_FLASH_BASE)
+#define CY_FLASH_SIZE               (CYDEV_FLS_SIZE)
+#define CY_FLASH_SIZEOF_ARRAY       (CYDEV_FLS_SECTOR_SIZE)
+#define CY_FLASH_SIZEOF_ROW         (CYDEV_FLS_ROW_SIZE)
+#define CY_FLASH_SIZEOF_ECC_ROW     (CYDEV_ECC_ROW_SIZE)
+#define CY_FLASH_NUMBER_ROWS        (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)
+#define CY_FLASH_NUMBER_ARRAYS      (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)
+
+#if(CYDEV_ECC_ENABLE == 0)
+    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)
+#else
+    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW)
+#endif  /* (CYDEV_ECC_ENABLE == 0) */
+#define CY_EEPROM_BASE              (CYDEV_EE_BASE)
+#define CY_EEPROM_SIZE              (CYDEV_EE_SIZE)
+#define CY_EEPROM_SIZEOF_ARRAY      (CYDEV_EE_SIZE)     /* EEPROM has one array */
+#define CY_EEPROM_SIZEOF_ROW        (CYDEV_EEPROM_ROW_SIZE)
+#define CY_EEPROM_NUMBER_ROWS       (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)
+#define CY_EEPROM_NUMBER_ARRAYS     (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)
+#define CY_EEPROM_NUMBER_SECTORS    (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
+#define CY_EEPROM_SIZEOF_SECTOR     (CYDEV_EEPROM_SECTOR_SIZE)
+
+#if !defined(CYDEV_FLS_BASE)
+    #define CYDEV_FLS_BASE    CYDEV_FLASH_BASE
+#endif  /* !defined(CYDEV_FLS_BASE) */
+
+
+/***************************************
+*     Function Prototypes
+***************************************/
+
+/* Flash Functions */
+void     CyFlash_Start(void);
+void     CyFlash_Stop(void);
+cystatus CySetTemp(void);
+cystatus CySetFlashEEBuffer(uint8 * buffer);
+cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \
+            ;
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData);
+
+#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
+    cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \
+            ;
+#endif  /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
+
+void CyFlash_SetWaitCycles(uint8 freq) ;
+
+/* EEPROM Functions */
+void CyEEPROM_Start(void) ;
+void CyEEPROM_Stop(void) ;
+
+void CyEEPROM_ReadReserve(void) ;
+void CyEEPROM_ReadRelease(void) ;
+
+
+/***************************************
+*     Registers
+***************************************/
+/* Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ACT_CFG0_REG             (* (reg8 *) CYREG_PM_ACT_CFG0)
+#define CY_FLASH_PM_ACT_CFG0_PTR             (  (reg8 *) CYREG_PM_ACT_CFG0)
+
+/* Alternate Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ALTACT_CFG0_REG          (* (reg8 *) CYREG_PM_STBY_CFG0)
+#define CY_FLASH_PM_ALTACT_CFG0_PTR          (  (reg8 *) CYREG_PM_STBY_CFG0)
+
+/* Active Power Mode Configuration Register 12 */
+#define CY_FLASH_PM_ACT_CFG12_REG            (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_PTR            (  (reg8 *) CYREG_PM_ACT_CFG12)
+
+/* Alternate Active Power Mode Configuration Register 12 */
+#define CY_FLASH_PM_ALTACT_CFG12_REG         (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_PTR         (  (reg8 *) CYREG_PM_STBY_CFG12)
+
+/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG      (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR      (  (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+
+/* Flash macro control register */
+#define CY_FLASH_SPC_FM_EE_CR_REG            (* (reg8 *) CYREG_SPC_FM_EE_CR)
+#define CY_FLASH_SPC_FM_EE_CR_PTR            (  (reg8 *) CYREG_SPC_FM_EE_CR)
+
+
+/* Cache Control Register */
+#if (CY_PSOC3)
+
+    #define CY_FLASH_CONTROL_REG                (* (reg8 *) CYREG_CACHE_CR )
+    #define CY_FLASH_CONTROL_PTR                (  (reg8 *) CYREG_CACHE_CR )
+
+#else
+
+    #define CY_FLASH_CONTROL_REG                (* (reg8 *) CYREG_CACHE_CC_CTL )
+    #define CY_FLASH_CONTROL_PTR                (  (reg8 *) CYREG_CACHE_CC_CTL )
+
+#endif  /* (CY_PSOC3) */
+
+
+/* EEPROM Status & Control Register */
+#define CY_FLASH_EE_SCR_REG                     (* (reg8 *) CYREG_SPC_EE_SCR)
+#define CY_FLASH_EE_SCR_PTR                     (  (reg8 *) CYREG_SPC_EE_SCR)
+
+
+
+/***************************************
+*     Register Constants
+***************************************/
+
+/* Power Mode Masks */
+
+/* Enable EEPROM */
+#define CY_FLASH_PM_ACT_CFG12_EN_EE             (0x10u)
+#define CY_FLASH_PM_ALTACT_CFG12_EN_EE          (0x10u)
+
+/* Enable Flash */
+#if (CY_PSOC3)
+    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x01u)
+    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x01u)
+#else
+    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x0Fu)
+    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x0Fu)
+#endif  /* (CY_PSOC3) */
+
+
+
+/* Frequency Constants */
+#if (CY_PSOC3)
+    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xC0u)
+    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
+    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
+    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
+
+    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (22u)
+    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (44u)
+    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (67u)
+#endif  /* (CY_PSOC3) */
+
+#if (CY_PSOC5)
+    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xE0u)
+    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
+    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
+    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
+    #define CY_FLASH_CACHE_WS_4_VALUE_MASK      (0x00u)
+    #define CY_FLASH_CACHE_WS_5_VALUE_MASK      (0x20u)
+
+    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (16u)
+    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (33u)
+    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (50u)
+    #define CY_FLASH_CACHE_WS_4_FREQ_MAX        (67u)
+    #define CY_FLASH_CACHE_WS_5_FREQ_MAX        (83u)
+#endif  /* (CY_PSOC5) */
+
+#define CY_FLASH_CYCLES_MASK_SHIFT              (0x06u)
+#define CY_FLASH_CYCLES_MASK                    ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
+
+#define CY_FLASH_EE_SCR_AHB_EE_REQ              (0x01u)
+#define CY_FLASH_EE_SCR_AHB_EE_ACK              (0x02u)
+
+
+#define CY_FLASH_EE_EE_AWAKE                    (0x20u)
+
+/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ       (0xC8u)
+
+/* Enable clk_spc. This also internally enables the 36MHz IMO. */
+#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC         (0x08u)
+#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC      (0x08u)
+
+/* Default values for getting temperature. */
+
+#define CY_TEMP_NUMBER_OF_SAMPLES               (0x1u)
+#define CY_TEMP_TIMER_PERIOD                    (0xFFFu)
+#define CY_TEMP_CLK_DIV_SELECT                  (0x4u)
+#define CY_TEMP_NUM_SAMPLES                     (1 << (CY_TEMP_NUMBER_OF_SAMPLES))
+#define CY_SPC_CLK_PERIOD                       (120u)      /* nS */
+#define CY_SYS_ns_PER_TICK                      (1000u)
+#define CY_FRM_EXEC_TIME                        (1000u)     /* nS */
+
+#define CY_GET_TEMP_TIME                        ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \
+                                                    (CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \
+                                                    CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME)
+
+#define CY_TEMP_MAX_WAIT                        ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK)    /* In system ticks. */
+
+
+/*******************************************************************************
+* Thne following code is OBSOLETE and must not be used starting with cy_boot
+* 4.20.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+#if (CY_PSOC5)
+    #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
+    #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
+    #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
+    #define CY_FLASH_GREATER_51MHz              (0x00u)
+#endif  /* (CY_PSOC5) */
+
+#if (CY_PSOC3)
+    #define CY_FLASH_LESSER_OR_EQUAL_22MHz      (0x01u)
+    #define CY_FLASH_LESSER_OR_EQUAL_44MHz      (0x02u)
+    #define CY_FLASH_GREATER_44MHz              (0x03u)
+#endif  /* (CY_PSOC3) */
+
+#define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_EE_MASK                 (0x10u)
+#define CY_FLASH_PM_FLASH_MASK              (0x01u)
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.0
+*******************************************************************************/
+#define FLASH_SIZE                  (CY_FLASH_SIZE)
+#define FLASH_SIZEOF_SECTOR         (CY_FLASH_SIZEOF_ARRAY)
+#define FLASH_NUMBER_ROWS           (CY_FLASH_NUMBER_ROWS)
+#define FLASH_NUMBER_SECTORS        (CY_FLASH_NUMBER_ARRAYS)
+#define EEPROM_SIZE                 (CY_EEPROM_SIZE)
+#define EEPROM_SIZEOF_SECTOR        (CYDEV_EEPROM_SECTOR_SIZE)
+#define EEPROM_NUMBER_ROWS          (CY_EEPROM_NUMBER_ROWS)
+#define EEPROM_NUMBER_SECTORS       (CY_EEPROM_NUMBER_SECTORS)
+
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
+*******************************************************************************/
+#define FLASH_CYCLES_PTR            (CY_FLASH_CONTROL_PTR)
+
+#define TEMP_NUMBER_OF_SAMPLES      (CY_TEMP_NUMBER_OF_SAMPLES)
+#define TEMP_TIMER_PERIOD           (CY_TEMP_TIMER_PERIOD)
+#define TEMP_CLK_DIV_SELECT         (CY_TEMP_CLK_DIV_SELECT)
+#define NUM_SAMPLES                 (CY_TEMP_NUM_SAMPLES)
+#define SPC_CLK_PERIOD              (CY_SPC_CLK_PERIOD)
+#define FRM_EXEC_TIME               (CY_FRM_EXEC_TIME)
+#define GET_TEMP_TIME               (CY_GET_TEMP_TIME)
+#define TEMP_MAX_WAIT               (CY_TEMP_MAX_WAIT)
+
+#define ECC_ADDR                    (0x80u)
+
+
+#define PM_ACT_EE_PTR           (CY_FLASH_PM_ACT_EEFLASH_PTR)
+#define PM_ACT_FLASH_PTR        (CY_FLASH_PM_ACT_EEFLASH_PTR)
+
+#define PM_STBY_EE_PTR          (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
+#define PM_STBY_FLASH_PTR       (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
+
+#define PM_EE_MASK              (CY_FLASH_PM_EE_MASK)
+#define PM_FLASH_MASK           (CY_FLASH_PM_FLASH_MASK)
+
+#define FLASH_CYCLES_MASK_SHIFT     (CY_FLASH_CYCLES_MASK_SHIFT)
+#define FLASH_CYCLES_MASK           (CY_FLASH_CYCLES_MASK)
+
+
+#if (CY_PSOC3)
+
+    #define LESSER_OR_EQUAL_22MHz   (CY_FLASH_LESSER_OR_EQUAL_22MHz)
+    #define LESSER_OR_EQUAL_44MHz   (CY_FLASH_LESSER_OR_EQUAL_44MHz)
+    #define GREATER_44MHz           (CY_FLASH_GREATER_44MHz)
+
+#endif  /* (CY_PSOC3) */
+
+#if (CY_PSOC5)
+
+    #define LESSER_OR_EQUAL_16MHz   (CY_FLASH_LESSER_OR_EQUAL_16MHz)
+    #define LESSER_OR_EQUAL_33MHz   (CY_FLASH_LESSER_OR_EQUAL_33MHz)
+    #define LESSER_OR_EQUAL_50MHz   (CY_FLASH_LESSER_OR_EQUAL_50MHz)
+    #define LESSER_OR_EQUAL_67MHz   (CY_FLASH_LESSER_OR_EQUAL_67MHz)
+    #define GREATER_67MHz           (CY_FLASH_GREATER_67MHz)
+    #define GREATER_51MHz           (CY_FLASH_GREATER_51MHz)
+
+#endif  /* (CY_PSOC5) */
+
+#define AHUB_EE_REQ_ACK_PTR         (CY_FLASH_EE_SCR_PTR)
+
+
+#endif  /* (CY_BOOT_CYFLASH_H) */
+
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c
new file mode 100755 (executable)
index 0000000..43ec360
--- /dev/null
@@ -0,0 +1,2928 @@
+/***************************************************************************//**
+* \file CyLib.c
+* \version 5.60
+*
+* \brief Provides a system API for the clocking, interrupts and watchdog timer.
+*
+* \note Documentation of the API's in this file is located in the System
+* Reference Guide provided with PSoC Creator.
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2017, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "CyLib.h"
+
+
+/*******************************************************************************
+* The CyResetStatus variable is used to obtain value of RESET_SR0 register after
+* a device reset. It is set from initialize_psoc() at the early initialization
+* stage. In case of IAR EW IDE, initialize_psoc() is executed before the data
+* sections are initialized. To avoid zeroing, CyResetStatus should be placed
+* to the .noinit section.
+*******************************************************************************/
+CY_NOINIT uint8 CYXDATA CyResetStatus;
+
+
+/* Variable Vdda */
+#if(CYDEV_VARIABLE_VDDA == 1)
+
+    uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700);
+
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+
+
+/* Do not use these definitions directly in your application */
+uint32 cydelay_freq_hz  = BCLK__BUS_CLK__HZ;
+uint32 cydelay_freq_khz = (BCLK__BUS_CLK__HZ + 999u) / 1000u;
+uint8  cydelay_freq_mhz = (uint8)((BCLK__BUS_CLK__HZ + 999999u) / 1000000u);
+uint32 cydelay_32k_ms   = 32768u * ((BCLK__BUS_CLK__HZ + 999u) / 1000u);
+
+
+/* Function Prototypes */
+static uint8 CyUSB_PowerOnCheck(void)  ;
+static void CyIMO_SetTrimValue(uint8 freq) ;
+static void CyBusClk_Internal_SetDivider(uint16 divider);
+
+#if(CY_PSOC5)
+    static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];
+    static void CySysTickServiceCallbacks(void);
+    uint32 CySysTickInitVar = 0u;
+#endif  /* (CY_PSOC5) */
+
+
+#if(CY_PSOC3)
+    CY_ISR_PROTO(IntDefaultHandler);
+#endif /* (CY_PSOC3) */
+
+
+/*******************************************************************************
+* Function Name: CyPLL_OUT_Start
+****************************************************************************//**
+*
+*   Enables the PLL.  Optionally waits for it to become stable.
+*   Waits at least 250 us or until it is detected that the PLL is stable.
+*
+*   \param wait:
+*    \param 0: Return immediately after configuration
+*    \param 1: Wait for PLL lock or timeout.
+*
+* \return
+*   Status
+*    CYRET_SUCCESS - Completed successfully
+*    CYRET_TIMEOUT - Timeout occurred without detecting a stable clock.
+*     If the input source of the clock is jittery, then the lock indication
+*     may not occur.  However, after the timeout has expired the generated PLL
+*     clock can still be used.
+*
+* \sideeffect
+*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
+*  Any other use of the Fast Time Wheel will be stopped during the period of
+*  this function and then restored. This function also uses the 100 KHz ILO.
+*  If not enabled, this function will enable the 100 KHz ILO for the period of
+*  this function.
+*
+*  No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or
+*  Once Per Second interrupt may be made by interrupt routines during the period
+*  of this function execution. The current operation of the ILO, Central Time
+*  Wheel and Once Per Second interrupt are maintained during the operation of
+*  this function provided the reading of the Power Manager Interrupt Status
+*  Register is only done using the CyPmReadStatus() function.
+*
+*******************************************************************************/
+cystatus CyPLL_OUT_Start(uint8 wait) 
+{
+    cystatus status = CYRET_SUCCESS;
+
+    uint8 iloEnableState;
+    uint8 pmTwCfg0State;
+    uint8 pmTwCfg2State;
+
+
+    /* Enables PLL circuit  */
+    CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;
+
+    if(wait != 0u)
+    {
+        /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */
+        iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
+        pmTwCfg0State = CY_LIB_PM_TW_CFG0_REG;
+        pmTwCfg2State = CY_LIB_PM_TW_CFG2_REG;
+
+        CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL);
+
+        status = CYRET_TIMEOUT;
+
+        while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
+        {
+            /* Wait for interrupt status */
+            if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
+            {
+                if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
+                {
+                    status = CYRET_SUCCESS;
+                    break;
+                }
+            }
+        }
+
+        /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */
+        if(0u == iloEnableState)
+        {
+            CyILO_Stop100K();
+        }
+
+        CY_LIB_PM_TW_CFG0_REG = pmTwCfg0State;
+        CY_LIB_PM_TW_CFG2_REG = pmTwCfg2State;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyPLL_OUT_Stop
+****************************************************************************//**
+*
+*  Disables the PLL.
+*
+*******************************************************************************/
+void CyPLL_OUT_Stop(void) 
+{
+    CY_CLK_PLL_CFG0_REG &= ((uint8)(~CY_CLK_PLL_ENABLE));
+}
+
+
+/*******************************************************************************
+* Function Name: CyPLL_OUT_SetPQ
+****************************************************************************//**
+*
+*  Sets the P and Q dividers and the charge pump current.
+*  The Frequency Out will be P/Q * Frequency In.
+*  The PLL must be disabled before calling this function.
+*
+*  \param uint8 pDiv:
+*   Valid range [8 - 255].
+*
+*  \param uint8 qDiv:
+*   Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz.
+
+*  \param uint8 current:
+*   Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and
+*   datasheet for more information.
+*
+* \sideeffect
+*  If this function execution results in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling
+*  CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally
+*  called if the CPU clock frequency is lowered in order to improve the CPU
+*  performance. See CyFlash_SetWaitCycles() description for more information.
+*
+*******************************************************************************/
+void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) 
+{
+    /* Halt CPU in debug mode if PLL is enabled */
+    CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE));
+
+    if((pDiv    >= CY_CLK_PLL_MIN_P_VALUE  ) &&
+       (qDiv    <= CY_CLK_PLL_MAX_Q_VALUE  ) && (qDiv    >= CY_CLK_PLL_MIN_Q_VALUE  ) &&
+       (current >= CY_CLK_PLL_MIN_CUR_VALUE) && (current <= CY_CLK_PLL_MAX_CUR_VALUE))
+    {
+        /* Set new values */
+        CY_CLK_PLL_P_REG = pDiv;
+        CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u));
+        CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) |
+                                ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION));
+    }
+    else
+    {
+        /***********************************************************************
+        * Halt CPU in debug mode if:
+        * - P divider is less than required
+        * - Q divider is out of range
+        * - pump current is out of range
+        ***********************************************************************/
+        CYASSERT(0u != 0u);
+    }
+
+}
+
+
+/*******************************************************************************
+* Function Name: CyPLL_OUT_SetSource
+****************************************************************************//**
+*
+*  Sets the input clock source to the PLL. The PLL must be disabled before
+*  calling this function.
+*
+*   \param source: One of the three available PLL clock sources
+*    \param CY_PLL_SOURCE_IMO  :   IMO
+*    \param CY_PLL_SOURCE_XTAL :   MHz Crystal
+*    \param CY_PLL_SOURCE_DSI  :   DSI
+*
+* \sideeffect
+*  If this function execution results in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the3 Flash must be adjusted by calling
+*  CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally
+*  called if the CPU clock frequency is lowered in order to improve the CPU
+*  performance. See CyFlash_SetWaitCycles() description for more information.
+*
+*******************************************************************************/
+void CyPLL_OUT_SetSource(uint8 source) 
+{
+    /* Halt CPU in debug mode if PLL is enabled */
+    CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE));
+
+    switch(source)
+    {
+        case CY_PLL_SOURCE_IMO:
+        case CY_PLL_SOURCE_XTAL:
+        case CY_PLL_SOURCE_DSI:
+            CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | source);
+        break;
+
+        default:
+            CYASSERT(0u != 0u);
+        break;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_Start
+****************************************************************************//**
+*
+*  Enables the IMO. Optionally waits at least 6 us for it to settle.
+*
+*  \param uint8 wait:
+*   \param 0: Return immediately after configuration
+*   \param 1: Wait for at least 6 us for the IMO to settle.
+*
+* \sideeffect
+*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
+*  Any other use of the Fast Time Wheel will be stopped during the period of
+*  this function and then restored. This function also uses the 100 KHz ILO.
+*  If not enabled, this function will enable the 100 KHz ILO for the period of
+*  this function.
+*
+*  No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or
+*  Once Per Second interrupt may be made by interrupt routines during the period
+*  of this function execution. The current operation of the ILO, Central Time
+*  Wheel and Once Per Second interrupt are maintained during the operation of
+*  this function provided the reading of the Power Manager Interrupt Status
+*  Register is only done using the CyPmReadStatus() function.
+*
+*******************************************************************************/
+void CyIMO_Start(uint8 wait) 
+{
+    uint8 pmFtwCfg2Reg;
+    uint8 pmFtwCfg0Reg;
+    uint8 ilo100KhzEnable;
+
+
+    CY_LIB_PM_ACT_CFG0_REG  |= CY_LIB_PM_ACT_CFG0_IMO_EN;
+    CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN;
+
+    if(0u != wait)
+    {
+        /* Need to turn on 100KHz ILO if it happens to not already be running.*/
+        ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
+        pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;
+        pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;
+
+        CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT);
+
+        while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
+        {
+            /* Wait for interrupt status */
+        }
+
+        if(0u == ilo100KhzEnable)
+        {
+            CyILO_Stop100K();
+        }
+
+        CY_LIB_PM_TW_CFG0_REG = pmFtwCfg0Reg;
+        CY_LIB_PM_TW_CFG2_REG = pmFtwCfg2Reg;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_Stop
+****************************************************************************//**
+*
+*   Disables the IMO.
+*
+*******************************************************************************/
+void CyIMO_Stop(void) 
+{
+    CY_LIB_PM_ACT_CFG0_REG  &= ((uint8) (~CY_LIB_PM_ACT_CFG0_IMO_EN));
+    CY_LIB_PM_STBY_CFG0_REG &= ((uint8) (~CY_LIB_PM_STBY_CFG0_IMO_EN));
+}
+
+
+/*******************************************************************************
+* Function Name: CyUSB_PowerOnCheck
+****************************************************************************//**
+*
+*  Returns the USB power status value. A private function to cy_boot.
+*
+* \return
+*   uint8: one if the USB is enabled, 0 if not enabled.
+*
+*******************************************************************************/
+static uint8 CyUSB_PowerOnCheck(void)  
+{
+    uint8 poweredOn = 0u;
+
+    /* Check whether device is in Active or AltActive and if USB is powered on */
+    if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) &&
+       (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED     )))  ||
+       (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) &&
+       (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED))))
+    {
+        poweredOn = 1u;
+    }
+
+    return (poweredOn);
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_SetTrimValue
+****************************************************************************//**
+*
+*  Sets the IMO factory trim values.
+*
+*  uint8 freq - frequency for which trims must be set
+*
+*******************************************************************************/
+static void CyIMO_SetTrimValue(uint8 freq) 
+{
+    uint8 usbPowerOn = CyUSB_PowerOnCheck();
+
+    /* If USB is powered */
+    if(usbPowerOn == 1u)
+    {
+        /* Unlock USB write */
+        CY_LIB_USB_CR1_REG &= ((uint8)(~CY_LIB_USB_CLK_EN));
+    }
+    switch(freq)
+    {
+    case CY_IMO_FREQ_3MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_3MHZ_PTR);
+        break;
+
+    case CY_IMO_FREQ_6MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_6MHZ_PTR);
+        break;
+
+    case CY_IMO_FREQ_12MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_12MHZ_PTR);
+        break;
+
+    case CY_IMO_FREQ_24MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_24MHZ_PTR);
+        break;
+
+    case CY_IMO_FREQ_48MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_TR1_PTR);
+        break;
+
+    case CY_IMO_FREQ_62MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_67MHZ_PTR);
+        break;
+
+#if(CY_PSOC5)
+    case CY_IMO_FREQ_74MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_80MHZ_PTR);
+        break;
+#endif  /* (CY_PSOC5) */
+
+    case CY_IMO_FREQ_USB:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_USB_PTR);
+
+        /* If USB is powered */
+        if(usbPowerOn == 1u)
+        {
+            /* Lock USB Oscillator */
+            CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;
+        }
+        break;
+
+    default:
+            CYASSERT(0u != 0u);
+        break;
+    }
+
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_SetFreq
+****************************************************************************//**
+*
+*  Sets the frequency of the IMO. Changes may be made while the IMO is running.
+*
+*  \param freq: Frequency of IMO operation
+*       CY_IMO_FREQ_3MHZ  to set  3   MHz
+*       CY_IMO_FREQ_6MHZ  to set  6   MHz
+*       CY_IMO_FREQ_12MHZ to set 12   MHz
+*       CY_IMO_FREQ_24MHZ to set 24   MHz
+*       CY_IMO_FREQ_48MHZ to set 48   MHz
+*       CY_IMO_FREQ_62MHZ to set 62.6 MHz
+*       CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3)
+*       CY_IMO_FREQ_USB   to set 24   MHz (Trimmed for USB operation)
+*
+* \sideeffect
+*  If this function execution results in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling
+*  CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally
+*  called if the CPU clock frequency is lowered in order to improve the CPU
+*  performance. See CyFlash_SetWaitCycles() description for more information.
+*
+*  When the USB setting is chosen, the USB clock locking circuit is enabled.
+*  Otherwise this circuit is disabled. The USB block must be powered before
+*  selecting the USB setting.
+*
+*******************************************************************************/
+void CyIMO_SetFreq(uint8 freq) 
+{
+    uint8 currentFreq;
+    uint8 nextFreq;
+
+    /***************************************************************************
+    * If the IMO frequency is changed,the Trim values must also be set
+    * accordingly.This requires reading the current frequency. If the new
+    * frequency is faster, then set a new trim and then change the frequency,
+    * otherwise change the frequency and then set new trim values.
+    ***************************************************************************/
+
+    currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));
+
+    /* Check if requested frequency is USB. */
+    nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;
+
+    switch (currentFreq)
+    {
+    case 0u:
+        currentFreq = CY_IMO_FREQ_12MHZ;
+        break;
+
+    case 1u:
+        currentFreq = CY_IMO_FREQ_6MHZ;
+        break;
+
+    case 2u:
+        currentFreq = CY_IMO_FREQ_24MHZ;
+        break;
+
+    case 3u:
+        currentFreq = CY_IMO_FREQ_3MHZ;
+        break;
+
+    case 4u:
+        currentFreq = CY_IMO_FREQ_48MHZ;
+        break;
+
+    case 5u:
+        currentFreq = CY_IMO_FREQ_62MHZ;
+        break;
+
+#if(CY_PSOC5)
+    case 6u:
+        currentFreq = CY_IMO_FREQ_74MHZ;
+        break;
+#endif  /* (CY_PSOC5) */
+
+    default:
+        CYASSERT(0u != 0u);
+        break;
+    }
+
+    if (nextFreq >= currentFreq)
+    {
+        /* Set new trim first */
+        CyIMO_SetTrimValue(freq);
+    }
+
+    /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
+    switch(freq)
+    {
+    case CY_IMO_FREQ_3MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_3MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+
+    case CY_IMO_FREQ_6MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_6MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+
+    case CY_IMO_FREQ_12MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_12MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+
+    case CY_IMO_FREQ_24MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_24MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+
+    case CY_IMO_FREQ_48MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_48MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+
+    case CY_IMO_FREQ_62MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_62MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+
+#if(CY_PSOC5)
+    case CY_IMO_FREQ_74MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_74MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+#endif  /* (CY_PSOC5) */
+
+    case CY_IMO_FREQ_USB:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_24MHZ_VALUE) | CY_LIB_IMO_USBCLK_ON_SET;
+        break;
+
+    default:
+        CYASSERT(0u != 0u);
+        break;
+    }
+
+    /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */
+    if (freq == CY_IMO_FREQ_USB)
+    {
+        CyIMO_EnableDoubler();
+    }
+    else
+    {
+        CyIMO_DisableDoubler();
+    }
+
+    if (nextFreq < currentFreq)
+    {
+        /* Set the trim after setting frequency */
+        CyIMO_SetTrimValue(freq);
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_SetSource
+****************************************************************************//**
+*
+*  Sets the source of the clock output from the IMO block.
+*
+*  The output from the IMO is by default the IMO itself. Optionally the MHz
+*  Crystal or DSI input can be the source of the IMO output instead.
+*
+*   \param source: CY_IMO_SOURCE_DSI to set the DSI as source.
+*           CY_IMO_SOURCE_XTAL to set the MHz as source.
+*           CY_IMO_SOURCE_IMO to set the IMO itself.
+*
+* \sideeffect
+*  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling
+*  CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally
+*  called if the CPU clock frequency is lowered in order to improve the CPU
+*  performance. See CyFlash_SetWaitCycles() description for more information.
+*
+*******************************************************************************/
+void CyIMO_SetSource(uint8 source) 
+{
+    switch(source)
+    {
+    case CY_IMO_SOURCE_DSI:
+        CY_LIB_CLKDIST_CR_REG     &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X));
+        CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO;
+        break;
+
+    case CY_IMO_SOURCE_XTAL:
+        CY_LIB_CLKDIST_CR_REG     |= CY_LIB_CLKDIST_CR_IMO2X;
+        CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO;
+        break;
+
+    case CY_IMO_SOURCE_IMO:
+        CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO));
+        break;
+
+    default:
+        /* Incorrect source value */
+        CYASSERT(0u != 0u);
+        break;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_EnableDoubler
+****************************************************************************//**
+*
+*  Enables the IMO doubler.  The 2x frequency clock is used to convert a 24 MHz
+*  input to a 48 MHz output for use by the USB block.
+*
+*******************************************************************************/
+void CyIMO_EnableDoubler(void) 
+{
+    /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */
+    CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_DisableDoubler
+****************************************************************************//**
+*
+*   Disables the IMO doubler.
+*
+*******************************************************************************/
+void CyIMO_DisableDoubler(void) 
+{
+    CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER));
+}
+
+
+/*******************************************************************************
+* Function Name: CyMasterClk_SetSource
+****************************************************************************//**
+*
+*  Sets the source of the master clock.
+*
+*   \param source: One of the four available Master clock sources.
+*     CY_MASTER_SOURCE_IMO
+*     CY_MASTER_SOURCE_PLL
+*     CY_MASTER_SOURCE_XTAL
+*     CY_MASTER_SOURCE_DSI
+*
+* \sideeffect
+*  The current source and the new source must both be running and stable before
+*  calling this function.
+*
+*  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling
+*  CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally
+*  called if the CPU clock frequency is lowered in order to improve the CPU
+*  performance. See CyFlash_SetWaitCycles() description for more information.
+*
+*******************************************************************************/
+void CyMasterClk_SetSource(uint8 source) 
+{
+    CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) |
+                                (source & ((uint8)(~MASTER_CLK_SRC_CLEAR)));
+}
+
+
+/*******************************************************************************
+* Function Name: CyMasterClk_SetDivider
+****************************************************************************//**
+*
+*  Sets the divider value used to generate Master Clock.
+*
+*  \param uint8 divider:
+*   The valid range is [0-255]. The clock will be divided by this value + 1.
+*   For example to divide this parameter by two should be set to 1.
+*
+* \sideeffect
+*  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling
+*  CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally
+*  called if the CPU clock frequency is lowered in order to improve the CPU
+*  performance. See CyFlash_SetWaitCycles() description for more information.
+*
+*  When changing the Master or Bus clock divider value from div-by-n to div-by-1
+*  the first clock cycle output after the div-by-1 can be up to 4 ns shorter
+*  than the final/expected div-by-1 period.
+*
+*******************************************************************************/
+void CyMasterClk_SetDivider(uint8 divider) 
+{
+    CY_LIB_CLKDIST_MSTR0_REG = divider;
+}
+
+
+/*******************************************************************************
+* Function Name: CyBusClk_Internal_SetDivider
+****************************************************************************//**
+*
+*  The function used by CyBusClk_SetDivider(). For internal use only.
+*
+*   \param divider: Valid range [0-65535].
+*   The clock will be divided by this value + 1.
+*   For example, to divide this parameter by two should be set to 1.
+*
+*******************************************************************************/
+static void CyBusClk_Internal_SetDivider(uint16 divider)
+{
+    /* Mask bits to enable shadow loads  */
+    CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK;
+    CY_LIB_CLKDIST_DMASK_REG  = CY_LIB_CLKDIST_DMASK_MASK;
+
+    /* Enable mask bits to enable shadow loads */
+    CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;
+
+    /* Update Shadow Divider Value Register with new divider */
+    CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);
+    CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);
+
+
+    /***************************************************************************
+    * Copy shadow value defined in Shadow Divider Value Register
+    * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all
+    * dividers selected in Analog and Digital Clock Mask Registers
+    * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG).
+    ***************************************************************************/
+    CY_LIB_CLKDIST_LD_REG |= CY_LIB_CLKDIST_LD_LOAD;
+}
+
+
+/*******************************************************************************
+* Function Name: CyBusClk_SetDivider
+****************************************************************************//**
+*
+*  Sets the divider value used to generate the Bus Clock.
+*
+*  \param divider: Valid range [0-65535]. The clock will be divided by this value + 1.
+*  For example, to divide this parameter by two should be set to 1.
+*
+* \sideeffect
+*  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling
+*  CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally
+*  called if the CPU clock frequency is lowered in order to improve the CPU
+*  performance. See CyFlash_SetWaitCycles() description for more information.
+*
+*******************************************************************************/
+void CyBusClk_SetDivider(uint16 divider) 
+{
+    uint8  masterClkDiv;
+    uint16 busClkDiv;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    /* Work around to set bus clock divider value */
+    busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);
+    busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;
+
+    if ((divider == 0u) || (busClkDiv == 0u))
+    {
+        /* Save away master clock divider value */
+        masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;
+
+        if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)
+        {
+            /* Set master clock divider to 7 */
+            CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV);
+        }
+
+        if (divider == 0u)
+        {
+            /* Set SSS bit and divider register desired value */
+            CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;
+            CyBusClk_Internal_SetDivider(divider);
+        }
+        else
+        {
+            CyBusClk_Internal_SetDivider(divider);
+            CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));
+        }
+
+        /* Restore master clock */
+        CyMasterClk_SetDivider(masterClkDiv);
+    }
+    else
+    {
+        CyBusClk_Internal_SetDivider(divider);
+    }
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+#if(CY_PSOC3)
+
+    /*******************************************************************************
+    * Function Name: CyCpuClk_SetDivider
+    ****************************************************************************//**
+    *
+    *  Sets the divider value used to generate the CPU Clock. Only applicable for
+    *  PSoC 3 parts.
+    *
+    *  \param divider: Valid range [0-15]. The clock will be divided by this value + 1.
+    *  For example, to divide this parameter by two should be set to 1.
+    *
+    * \sideeffect
+    *  If this function execution resulted in the CPU clock frequency increasing,
+    *  then the number of clock cycles the cache will wait before it samples data
+    *  coming back from the Flash must be adjusted by calling
+    *  CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally
+    *  called if the CPU clock frequency is lowered in order to improve the CPU
+    *  performance. See CyFlash_SetWaitCycles() description for more information.
+    *
+    *******************************************************************************/
+    void CyCpuClk_SetDivider(uint8 divider) 
+    {
+            CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & CY_LIB_CLKDIST_MSTR1_DIV_MASK) |
+                                ((uint8)(divider << CY_LIB_CLKDIST_DIV_POSITION));
+    }
+
+#endif /* (CY_PSOC3) */
+
+
+/*******************************************************************************
+* Function Name: CyUsbClk_SetSource
+****************************************************************************//**
+*
+*  Sets the source of the USB clock.
+*
+*  \param source: One of the four available USB clock sources
+*    CY_LIB_USB_CLK_IMO2X     - IMO 2x
+*    CY_LIB_USB_CLK_IMO       - IMO
+*    CY_LIB_USB_CLK_PLL       - PLL
+*    CY_LIB_USB_CLK_DSI       - DSI
+*
+*******************************************************************************/
+void CyUsbClk_SetSource(uint8 source) 
+{
+    CY_LIB_CLKDIST_UCFG_REG = (CY_LIB_CLKDIST_UCFG_REG & ((uint8)(~CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK))) |
+                        (CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK & source);
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_Start1K
+****************************************************************************//**
+*
+*  Enables the ILO 1 KHz oscillator.
+*
+*  Note The ILO 1 KHz oscillator is always enabled by default, regardless of the
+*  selection in the Clock Editor. Therefore, this API is only needed if the
+*  oscillator was turned off manually.
+*
+*******************************************************************************/
+void CyILO_Start1K(void) 
+{
+    /* Set bit 1 of ILO RS */
+    CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_Stop1K
+****************************************************************************//**
+*
+*  Disables the ILO 1 KHz oscillator.
+*
+*  Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low
+*  power mode APIs are expected to be used. For more information, refer to the
+*  Power Management section of this document.
+*
+* \sideeffect
+*  PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality.
+*
+*******************************************************************************/
+void CyILO_Stop1K(void) 
+{
+    /* Clear bit 1 of ILO RS */
+    CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_Start100K
+****************************************************************************//**
+*
+*  Enables the ILO 100 KHz oscillator.
+*
+*******************************************************************************/
+void CyILO_Start100K(void) 
+{
+    CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_Stop100K
+****************************************************************************//**
+*
+*  Disables the ILO 100 KHz oscillator.
+*
+*******************************************************************************/
+void CyILO_Stop100K(void) 
+{
+    CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ));
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_Enable33K
+****************************************************************************//**
+*
+*  Enables the ILO 33 KHz divider.
+*
+*  Note that the 33 KHz clock is generated from the 100 KHz oscillator,
+*  so it must also be running in order to generate the 33 KHz output.
+*
+*******************************************************************************/
+void CyILO_Enable33K(void) 
+{
+    /* Set bit 5 of ILO RS */
+    CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_Disable33K
+****************************************************************************//**
+*
+*  Disables the ILO 33 KHz divider.
+*
+*  Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this
+*  API does not disable the 100 KHz clock.
+*
+*******************************************************************************/
+void CyILO_Disable33K(void) 
+{
+    CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ));
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_SetSource
+****************************************************************************//**
+*
+*  Sets the source of the clock output from the ILO block.
+*
+*  \param source: One of the three available ILO output sources
+*       Value        Define                Source
+*       0            CY_ILO_SOURCE_100K    ILO 100 KHz
+*       1            CY_ILO_SOURCE_33K     ILO 33 KHz
+*       2            CY_ILO_SOURCE_1K      ILO 1 KHz
+*
+*******************************************************************************/
+void CyILO_SetSource(uint8 source) 
+{
+    CY_LIB_CLKDIST_CR_REG = (CY_LIB_CLKDIST_CR_REG & CY_ILO_SOURCE_BITS_CLEAR) |
+                    (((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR)));
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_SetPowerMode
+****************************************************************************//**
+*
+* Sets the power mode used by the ILO during power down. Allows for lower power
+* down power usage resulting in a slower startup time.
+*
+* \param mode
+* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down
+* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down
+*
+* \return Prevous power mode state.
+*
+*******************************************************************************/
+uint8 CyILO_SetPowerMode(uint8 mode) 
+{
+    uint8 state;
+
+    /* Get current state. */
+    state = CY_LIB_SLOWCLK_ILO_CR0_REG;
+
+    /* Set the oscillator power mode. */
+    if(mode != CY_ILO_FAST_START)
+    {
+        CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);
+    }
+    else
+    {
+        CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));
+    }
+
+    /* Return old mode. */
+    return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_32KHZ_Start
+****************************************************************************//**
+*
+*  Enables the 32 KHz Crystal Oscillator.
+*
+*******************************************************************************/
+void CyXTAL_32KHZ_Start(void) 
+{
+    volatile uint16 i;
+
+    CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT;
+    CY_CLK_XTAL32_TR_REG  = CY_CLK_XTAL32_TR_STARTUP;
+    CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |
+                                CY_CLK_XTAL32_CFG_LP_DEFAULT;
+
+    #if(CY_PSOC3)
+        CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;
+    #endif  /* (CY_PSOC3) */
+
+    /* Enable operation of 32K Crystal Oscillator */
+    CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;
+
+    for (i = 1000u; i > 0u; i--)
+    {
+        if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))
+        {
+            /* Ready - switch to high power mode */
+            (void) CyXTAL_32KHZ_SetPowerMode(0u);
+
+            break;
+        }
+        CyDelayUs(1u);
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_32KHZ_Stop
+****************************************************************************//**
+*
+*  Disables the 32KHz Crystal Oscillator.
+*
+*******************************************************************************/
+void CyXTAL_32KHZ_Stop(void) 
+{
+    CY_CLK_XTAL32_TST_REG  = CY_CLK_XTAL32_TST_DEFAULT;
+    CY_CLK_XTAL32_TR_REG   = CY_CLK_XTAL32_TR_POWERDOWN;
+    CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |
+                             CY_CLK_XTAL32_CFG_LP_DEFAULT;
+    CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM)));
+
+    #if(CY_PSOC3)
+        CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_PDBEN));
+    #endif  /* (CY_PSOC3) */
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_32KHZ_ReadStatus
+****************************************************************************//**
+*
+*  Returns status of the 32 KHz oscillator.
+*
+* \return
+*  Value     Define                    Source
+*  20        CY_XTAL32K_ANA_STAT       Analog measurement
+*                                       1: Stable
+*                                       0: Not stable
+*
+*******************************************************************************/
+uint8 CyXTAL_32KHZ_ReadStatus(void) 
+{
+    return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT);
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_32KHZ_SetPowerMode
+****************************************************************************//**
+*
+*  Sets the power mode for the 32 KHz oscillator used during the sleep mode.
+*  Allows for lower power during sleep when there are fewer sources of noise.
+*  During the active mode the oscillator is always run in the high power mode.
+*
+*  uint8 mode
+*       \param 0: High power mode
+*       \param 1: Low power mode during sleep
+*
+* \return
+*  Previous power mode.
+*
+*******************************************************************************/
+uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) 
+{
+    uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u;
+
+    CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT;
+
+    if(1u == mode)
+    {
+        /* Low power mode during Sleep */
+        CY_CLK_XTAL32_TR_REG  = CY_CLK_XTAL32_TR_LOW_POWER;
+        CyDelayUs(10u);
+        CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |
+                                CY_CLK_XTAL32_CFG_LP_LOWPOWER;
+        CyDelayUs(20u);
+        CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM;
+    }
+    else
+    {
+        /* High power mode */
+        CY_CLK_XTAL32_TR_REG  = CY_CLK_XTAL32_TR_HIGH_POWER;
+        CyDelayUs(10u);
+        CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |
+                                CY_CLK_XTAL32_CFG_LP_DEFAULT;
+        CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM));
+    }
+
+    return(state);
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_Start
+****************************************************************************//**
+*
+*  Enables the megahertz crystal.
+*
+*  PSoC 3:
+*  Waits until the XERR bit is low (no error) for a millisecond or until the
+*  number of milliseconds specified by the wait parameter has expired.
+*
+*   \param wait: Valid range [0-255].
+*   This is the timeout value in milliseconds.
+*   The appropriate value is crystal specific.
+*
+* \return
+*   CYRET_SUCCESS - Completed successfully
+*   CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR.
+*
+* Side Effects and Restrictions:
+*  If wait is enabled (non-zero wait). Uses the Fast Timewheel to time the wait.
+*  Any other use of the Fast Timewheel (FTW) will be stopped during the period
+*  of this function and then restored.
+*
+*  Uses the 100KHz ILO.  If not enabled, this function will enable the 100KHz
+*  ILO for the period of this function. No changes to the setup of the ILO,
+*  Fast Timewheel, Central Timewheel or Once Per Second interrupt may be made
+*  by interrupt routines during the period of this function.
+*
+*  The current operation of the ILO, Central Timewheel and Once Per Second
+*  interrupt are maintained during the operation of this function provided the
+*  reading of the Power Manager Interrupt Status Register is only done using the
+*  CyPmReadStatus() function.
+*
+*******************************************************************************/
+cystatus CyXTAL_Start(uint8 wait) 
+{
+    cystatus status = CYRET_SUCCESS;
+    volatile uint8  timeout = wait;
+    volatile uint8 count;
+    uint8 iloEnableState;
+    uint8 pmTwCfg0Tmp;
+    uint8 pmTwCfg2Tmp;
+
+
+    /* Enables MHz crystal oscillator circuit  */
+    CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;
+
+
+    if(wait > 0u)
+    {
+        /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */
+        iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG;
+        pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG;
+        pmTwCfg2Tmp = CY_LIB_PM_TW_CFG2_REG;
+
+        /* Set 250 us interval */
+        CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL);
+        status = CYRET_TIMEOUT;
+
+
+        for( ; timeout > 0u; timeout--)
+        {
+            /* Read XERR bit to clear it */
+            (void) CY_CLK_XMHZ_CSR_REG;
+
+            /* Wait for 1 millisecond - 4 x 250 us */
+            for(count = 4u; count > 0u; count--)
+            {
+                while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
+                {
+                    /* Wait for FTW interrupt event */
+                }
+            }
+
+
+            /*******************************************************************
+            * High output indicates an oscillator failure.
+            * Only can be used after a start-up interval (1 ms) is completed.
+            *******************************************************************/
+            if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))
+            {
+                status = CYRET_SUCCESS;
+                break;
+            }
+        }
+
+
+        /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */
+        if(0u == (iloEnableState & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ))
+        {
+            CyILO_Stop100K();
+        }
+        CY_LIB_PM_TW_CFG0_REG = pmTwCfg0Tmp;
+        CY_LIB_PM_TW_CFG2_REG = pmTwCfg2Tmp;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_Stop
+****************************************************************************//**
+*
+*  Disables the megahertz crystal oscillator.
+*
+*******************************************************************************/
+void CyXTAL_Stop(void) 
+{
+    /* Disable oscillator. */
+    FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_EnableErrStatus
+****************************************************************************//**
+*
+*  Enables the generation of the XERR status bit for the megahertz crystal.
+*  This function is not available for PSoC5.
+*
+*******************************************************************************/
+void CyXTAL_EnableErrStatus(void) 
+{
+    /* If oscillator has insufficient amplitude, XERR bit will be high. */
+    CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB));
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_DisableErrStatus
+****************************************************************************//**
+*
+*  Disables the generation of the XERR status bit for the megahertz crystal.
+*  This function is not available for PSoC5.
+*
+*******************************************************************************/
+void CyXTAL_DisableErrStatus(void) 
+{
+    /* If oscillator has insufficient amplitude, XERR bit will be high. */
+    CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB;
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_ReadStatus
+****************************************************************************//**
+*
+*  Reads the XERR status bit for the megahertz crystal. This status bit is a
+*  sticky, clear on read. This function is not available for PSoC5.
+*
+* \return
+*   Status
+*    0: No error
+*    1: Error
+*
+*******************************************************************************/
+uint8 CyXTAL_ReadStatus(void) 
+{
+    /***************************************************************************
+    * High output indicates an oscillator failure. Only use this after a start-up
+    * interval is completed. This can be used for the status and failure recovery.
+    ***************************************************************************/
+    return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_EnableFaultRecovery
+****************************************************************************//**
+*
+*  Enables the fault recovery circuit which will switch to the IMO in the case
+*  of a fault in the megahertz crystal circuit. The crystal must be up and
+*  running with the XERR bit at 0, before calling this function to prevent
+*  an immediate fault switchover. This function is not available for PSoC5.
+*
+*******************************************************************************/
+void CyXTAL_EnableFaultRecovery(void) 
+{
+    CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT;
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_DisableFaultRecovery
+****************************************************************************//**
+*
+*  Disables the fault recovery circuit which will switch to the IMO in the case
+*  of a fault in the megahertz crystal circuit. This function is not available
+*  for PSoC5.
+*
+*******************************************************************************/
+void CyXTAL_DisableFaultRecovery(void) 
+{
+    CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT));
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_SetStartup
+****************************************************************************//**
+*
+*  Sets the startup settings for the crystal. The logic model outputs a
+*  frequency (setting + 4) MHz when enabled.
+*
+*  This is artificial as the actual frequency is determined by an attached
+*  external crystal.
+*
+*  \param setting: Valid range [0-31].
+*   The value is dependent on the frequency and quality of the crystal being
+*   used. Refer to the device TRM and datasheet for more information.
+*
+*******************************************************************************/
+void CyXTAL_SetStartup(uint8 setting) 
+{
+    CY_CLK_XMHZ_CFG0_REG = (CY_CLK_XMHZ_CFG0_REG & ((uint8)(~CY_CLK_XMHZ_CFG0_XCFG_MASK))) |
+                           (setting & CY_CLK_XMHZ_CFG0_XCFG_MASK);
+}
+
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_SetFbVoltage
+****************************************************************************//**
+*
+*  Sets the feedback reference voltage to use for the crystal circuit.
+*  This function is only available for PSoC3 and PSoC 5LP.
+*
+*  \param setting: Valid range [0-15].
+*  Refer to the device TRM and datasheet for more information.
+*
+*******************************************************************************/
+void CyXTAL_SetFbVoltage(uint8 setting) 
+{
+    CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) |
+                            (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK));
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_SetWdVoltage
+****************************************************************************//**
+*
+*  Sets the reference voltage used by the watchdog to detect a failure in the
+*  crystal circuit. This function is only available for PSoC3 and PSoC 5LP.
+*
+*  \param setting: Valid range [0-7].
+*  Refer to the device TRM and datasheet for more information.
+*
+*******************************************************************************/
+void CyXTAL_SetWdVoltage(uint8 setting) 
+{
+    CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) |
+                            (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK));
+}
+
+
+/*******************************************************************************
+* Function Name: CyHalt
+****************************************************************************//**
+*
+*  Halts the CPU.
+*
+*  \param uint8 reason: Value to be used during debugging.
+*
+*******************************************************************************/
+void CyHalt(uint8 reason) CYREENTRANT
+{
+    if(0u != reason)
+    {
+        /* To remove unreferenced local variable warning */
+    }
+
+    #if defined (__ARMCC_VERSION)
+        __breakpoint(0x0);
+    #elif defined(__GNUC__) || defined (__ICCARM__)
+        __asm("    bkpt    1");
+    #elif defined(__C51__)
+        CYDEV_HALT_CPU;
+    #endif  /* (__ARMCC_VERSION) */
+}
+
+
+/*******************************************************************************
+* Function Name: CySoftwareReset
+****************************************************************************//**
+*
+*  Forces a device software reset.
+*
+*******************************************************************************/
+void CySoftwareReset(void) 
+{
+    CY_LIB_RESET_CR2_REG |= CY_LIB_RESET_CR2_RESET;
+}
+
+
+/*******************************************************************************
+* Function Name: CyDelay
+****************************************************************************//**
+*
+*  Blocks for milliseconds.
+*
+*  Note:
+*  CyDelay has been implemented with the instruction cache assumed enabled. When
+*  the instruction cache is disabled on PSoC5, CyDelay will be two times larger.
+*  For example, with instruction cache disabled CyDelay(100) would result in
+*  about 200 ms delay instead of 100 ms.
+*
+*  \param milliseconds: number of milliseconds to delay.
+*
+*******************************************************************************/
+void CyDelay(uint32 milliseconds) CYREENTRANT
+{
+    while (milliseconds > 32768u)
+    {
+        /***********************************************************************
+        * This loop prevents overflow.At 100MHz, milliseconds * delay_freq_khz
+        * overflows at about 42 seconds.
+        ***********************************************************************/
+        CyDelayCycles(cydelay_32k_ms);
+        milliseconds = ((uint32)(milliseconds - 32768u));
+    }
+
+    CyDelayCycles(milliseconds * cydelay_freq_khz);
+}
+
+
+#if(!CY_PSOC3)
+
+    /* For PSoC3 devices function is defined in CyBootAsmKeil.a51 file */
+
+    /*******************************************************************************
+    * Function Name: CyDelayUs
+    ****************************************************************************//**
+    *
+    *  Blocks for microseconds.
+    *
+    *  Note:
+    *   CyDelay has been implemented with the instruction cache assumed enabled.
+    *   When instruction cache is disabled on PSoC5, CyDelayUs will be two times
+    *   larger. Ex: With instruction cache disabled CyDelayUs(100) would result
+    *   in about 200us delay instead of 100us.
+    *
+    *  \param uint16 microseconds: number of microseconds to delay.
+    *
+    * \sideeffect
+    *  CyDelayUS has been implemented with the instruction cache assumed enabled.
+    *  When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times
+    *  larger. For example, with the instruction cache disabled CyDelayUs(100) would
+    *  result in about 200 us delay instead of 100 us.
+    *
+    *  If the bus clock frequency is a small non-integer number, the actual delay
+    *  can be up to twice as long as the nominal value. The actual delay cannot be
+    *  shorter than the nominal one.
+    *******************************************************************************/
+    void CyDelayUs(uint16 microseconds) CYREENTRANT
+    {
+        CyDelayCycles((uint32)microseconds * cydelay_freq_mhz);
+    }
+
+#endif  /* (!CY_PSOC3) */
+
+
+/*******************************************************************************
+* Function Name: CyDelayFreq
+****************************************************************************//**
+*
+*  Sets the clock frequency for CyDelay.
+*
+*  \param freq: The frequency of the bus clock in Hertz.
+*
+*******************************************************************************/
+void CyDelayFreq(uint32 freq) CYREENTRANT
+{
+    if (freq != 0u)
+    {
+        cydelay_freq_hz = freq;
+    }
+    else
+    {
+        cydelay_freq_hz = BCLK__BUS_CLK__HZ;
+    }
+
+    cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u);
+    cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u;
+    cydelay_32k_ms   = 32768u * cydelay_freq_khz;
+}
+
+
+/*******************************************************************************
+* Function Name: CyWdtStart
+****************************************************************************//**
+*
+*  Enables the watchdog timer.
+*
+*  The timer is configured for the specified count interval, the central
+*  timewheel is cleared, the setting for the low power mode is configured and
+*  the watchdog timer is enabled.
+*
+*  Once enabled the watchdog cannot be disabled. The watchdog counts each time
+*  the Central Time Wheel (CTW) reaches the period specified. The watchdog must
+*  be cleared using the CyWdtClear() function before three ticks of the watchdog
+*  timer occur. The CTW is free running, so this will occur after between 2 and
+*  3 timer periods elapse.
+*
+*  PSoC5: The watchdog timer should not be used during sleep modes. Since the
+*  WDT cannot be disabled after it is enabled, the WDT timeout period can be
+*  set to be greater than the sleep wakeup period, then feed the dog on each
+*  wakeup from Sleep.
+*
+*  \param ticks: One of the four available timer periods. Once WDT enabled, the
+   interval cannot be changed.
+*         CYWDT_2_TICKS     -     4 - 6     ms
+*         CYWDT_16_TICKS    -    32 - 48    ms
+*         CYWDT_128_TICKS   -   256 - 384   ms
+*         CYWDT_1024_TICKS  - 2.048 - 3.072 s
+*
+*  \param lpMode: Low power mode configuration. This parameter is ignored for PSoC 5.
+*          The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed.
+*
+*          CYWDT_LPMODE_NOCHANGE - No Change
+*          CYWDT_LPMODE_MAXINTER - Switch to longest timer mode during low power
+*                                 mode
+*          CYWDT_LPMODE_DISABLED - Disable WDT during low power mode
+*
+* \sideeffect
+*  PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the
+*  ILO 1 kHz could break the active WDT functionality.
+*
+*******************************************************************************/
+void CyWdtStart(uint8 ticks, uint8 lpMode) 
+{
+    /* Set WDT interval */
+    CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_INTERVAL_MASK);
+
+    /* Reset CTW to ensure that first watchdog period is full */
+    CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;
+    CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));
+
+    /* Setting low power mode */
+    CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |
+                       (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));
+
+    /* Enables watchdog reset */
+    CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;
+}
+
+
+/*******************************************************************************
+* Function Name: CyWdtClear
+****************************************************************************//**
+*
+*  Clears (feeds) the watchdog timer.
+*
+*******************************************************************************/
+void CyWdtClear(void) 
+{
+    CY_WDT_CR_REG = CY_WDT_CR_FEED;
+}
+
+
+
+/*******************************************************************************
+* Function Name: CyVdLvDigitEnable
+****************************************************************************//**
+*
+*  Sets the voltage trip level, enables the output of the digital low-voltage
+*  monitor, and optionally configures voltage monitor to reset device upon the
+*  low-voltage event instead of generating an interrupt.
+*
+*  Note The associated interrupt enable/disable state is not changed by the
+*  function. The Interrupt component API should be used to register the
+*  interrupt service routine and to enable/disable associated interrupt.
+*
+*  \param reset: Enables device reset on digital low-voltage event:
+*   Zero - Interrupt on digital low-voltage event
+*   Non-zero - Reset on digital low-voltage event
+*
+*  \param threshold: Sets the trip point of the digital low-voltage monitoring circuit
+*   in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V
+*   (0x0F). For example, the trip point is set to 1.80 V when the threshold
+*   parameter value is 0x04. Refer to the device TRM for the exact trip voltage
+*   values.
+*
+* Side Effects and Restrictions:
+*  The voltage resets are momentary. When a voltage reset (analog/digital
+*  low-voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3
+*  registers are restored to their default values. This means that the voltage
+*  monitor circuit is no longer enabled and the device exits reset. If the
+*  supply is below the trip level and firmware enables the voltage reset
+*  functionality, the device will reset again. This will continue as long as the
+*  supply is below the trip level or as long as the user enables the reset
+*  functionality of the voltage monitor functionality.
+*
+*  When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers
+*  are cleared. This means that analog low-voltage, digital low-voltage and
+*  analog high-voltage status bits are not persistent across any voltage reset.
+*
+*******************************************************************************/
+void CyVdLvDigitEnable(uint8 reset, uint8 threshold) 
+{
+    uint32 intRegTmp;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    /* Store interrupt enable state */
+    intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK;
+
+    /* Disable VD interrupt (write 1) to protect against glitches */
+    CY_INT_CLEAR_REG = CY_VD_INT_MASK;
+
+    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));
+
+    CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) |
+                            (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));
+    CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;
+
+    /* Timeout to eliminate glitches on LVI/HVI when enabling (ID # 127412) */
+    CyDelayUs(1u);
+
+    (void) CyVdStickyStatus(CY_VD_LVID);
+
+    if(0u != reset)
+    {
+        CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN;
+    }
+    else
+    {
+        CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));
+    }
+
+    /* Clear pending interrupt */
+    CY_INT_CLR_PEND_REG = CY_VD_INT_MASK;
+
+    /* Restore interrupt enable state */
+    CY_INT_ENABLE_REG = intRegTmp;
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdLvAnalogEnable
+****************************************************************************//**
+*
+*  Sets the voltage trip level, enables the output of the analog low-voltage
+*  monitor, and optionally configures voltage monitor to reset device upon the
+*  low-voltage event instead of generating an interrupt.
+*
+*  Note The associated interrupt enable/disable state is not changed by the
+*  function. The Interrupt component API should be used to register the
+*  interrupt service routine and to enable/disable associated interrupt.
+*
+*  \param reset: Enables device reset on analog low-voltage event:
+*  Zero - Interrupt on analog low-voltage event
+*  Non-zero - Reset on analog low-voltage event
+*
+*  \param threshold: Sets the trip point of the analog low-voltage monitoring circuit
+*  in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V
+*  (0x0F). For example, the trip point is set to 1.80 V when value of the
+*  threshold parameter is 0x04. Please refer to the device TRM for the exact
+*  trip voltage values.
+*
+* Side Effects and Restrictions:
+*  The voltage resets are momentary. When a voltage reset (analog/digital
+*  low-voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3
+*  registers are restored to their default values. This means that the voltage
+*  monitor circuit is no longer enabled and the device exits reset. If the
+*  supply is below the trip level and firmware enables the voltage reset
+*  functionality, the device will reset again. This will continue as long as
+*  the supply is below the trip level or as long as the user enables the reset
+*  functionality of the voltage monitor functionality.
+*
+*  When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers
+*  are cleared. This means that analog low-voltage, digital low-voltage and
+*  analog high-voltage status bits are not persistent across any voltage reset.
+*
+*******************************************************************************/
+void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) 
+{
+    uint32 intRegTmp;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    /* Store interrupt enable state */
+    intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK;
+
+    /* Disable VD interrupt (write 1) to protect against glitches */
+    CY_INT_CLEAR_REG = CY_VD_INT_MASK;
+
+    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));
+
+    CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);
+    CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;
+
+    /* Timeout to eliminate glitches on LVI/HVI when enabling (ID # 127412) */
+    CyDelayUs(1u);
+
+    (void) CyVdStickyStatus(CY_VD_LVIA);
+
+    if(0u != reset)
+    {
+        CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN;
+    }
+    else
+    {
+        CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));
+    }
+
+    /* Clear pending interrupt */
+    CY_INT_CLR_PEND_REG = CY_VD_INT_MASK;
+
+    /* Restore interrupt enable state */
+    CY_INT_ENABLE_REG = intRegTmp;
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdLvDigitDisable
+****************************************************************************//**
+*
+*  Disables the digital low-voltage monitor, turns off device reset upon the
+*  digital low-voltage event, and clears the associated persistent status bit.
+*
+*  Note The associated interrupt enable/disable state is not changed by the
+*  function. The pending interrupt status is not cleared. The Interrupt
+*  component API should be used to manipulate with the associated interrupts.
+*
+*******************************************************************************/
+void CyVdLvDigitDisable(void) 
+{
+    CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN));
+    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));
+    (void) CyVdStickyStatus(CY_VD_LVID);
+
+    while(0u != (CyVdStickyStatus(CY_VD_LVID) & CY_VD_LVID))
+    {
+
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdLvAnalogDisable
+****************************************************************************//**
+*
+*  Disables the analog low-voltage monitor, turns off device reset upon the
+*  analog low-voltage event, and clears the associated persistent status bit.
+*
+*  Note The associated interrupt enable/disable state is not changed by the
+*  function. The pending interrupt status is not cleared. The Interrupt
+*  component API should be used to manipulate with the associated interrupts.
+*
+*******************************************************************************/
+void CyVdLvAnalogDisable(void) 
+{
+    CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN));
+    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));
+    while(0u != (CyVdStickyStatus(CY_VD_LVIA) & CY_VD_LVIA))
+    {
+
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdHvAnalogEnable
+****************************************************************************//**
+*
+*  Enables the output of the analog high-voltage monitor and sets 5.75 V
+*  threshold detection for Vdda.
+*
+*  Note The associated interrupt enable/disable state is not changed by the
+*  function. The Interrupt component API should be used to register the
+*  interrupt service routine and to enable/disable associated interrupt.
+*
+*******************************************************************************/
+void CyVdHvAnalogEnable(void) 
+{
+    uint32 intRegTmp;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    /* Store interrupt enable state */
+    intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK;
+
+    /* Disable VD interrupt (write 1) to protect against glitches */
+    CY_INT_CLEAR_REG = CY_VD_INT_MASK;
+
+    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));
+
+    CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN;
+
+    /* Timeout to eliminate glitches on the LVI/HVI when enabling (ID # 127412)  */
+    CyDelayUs(1u);
+
+    (void) CyVdStickyStatus(CY_VD_HVIA);
+
+    /* Clear pending interrupt */
+    CY_INT_CLR_PEND_REG = CY_VD_INT_MASK;
+
+    /* Restore interrupt enable state */
+    CY_INT_ENABLE_REG = intRegTmp;
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdHvAnalogDisable
+****************************************************************************//**
+*
+*  Disables the analog high-voltage monitor and clears the associated persistent
+*  status bit.
+*
+*  Note The associated interrupt enable/disable state is not changed by the
+*  function. The pending interrupt status is not cleared. The Interrupt
+*  component API should be used to manipulate with the associated interrupts.
+*
+*******************************************************************************/
+void CyVdHvAnalogDisable(void) 
+{
+    CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN));
+    while(0u != (CyVdStickyStatus(CY_VD_HVIA) & CY_VD_HVIA))
+    {
+
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdStickyStatus
+****************************************************************************//**
+*
+*  Reads and clears the voltage detection status bits in the RESET_SR0 register.
+*  The bits are set to 1 by the voltage monitor circuit when the supply is
+*  outside the detector trip point. They stay set to 1 until they are read or
+*  a POR / LVI / PRES reset occurs. This function uses a shadow register, so
+*  only the bits passed in the parameter will be cleared in the shadow register.
+*
+*  \param mask: Bits in the RESET_SR0 shadow register to clear and return.
+*   Define                  Definition
+*   CY_VD_LVID            Persistent status of digital LVI.
+*   CY_VD_LVIA            Persistent status of analog LVI.
+*   CY_VD_HVIA            Persistent status of analog HVI.
+*
+* \return
+*  Status. Same enumerated bit values as used for the mask parameter. A zero is
+*  returned for bits not used in the mask parameter.
+*
+* Side Effects and Restrictions:
+*  When an LVI reset occurs, the RESET_SR0 status registers are cleared. This
+*  means that the voltage detection status bits are not persistent across an LVI
+*  reset and cannot be used to determine a reset source.
+*
+*******************************************************************************/
+uint8 CyVdStickyStatus(uint8 mask) 
+{
+    static uint8 interruptStatus;
+    uint8 interruptState;
+    uint8 tmpStatus;
+
+    interruptState = CyEnterCriticalSection();
+
+    interruptStatus |= CY_VD_PERSISTENT_STATUS_REG;
+    tmpStatus = interruptStatus & (uint8)(CY_VD_LVID | CY_VD_LVIA | CY_VD_HVIA);
+    interruptStatus &= ((uint8)(~mask));
+
+    CyExitCriticalSection(interruptState);
+
+    return(tmpStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdRealTimeStatus
+****************************************************************************//**
+*
+*  Reads the real-time voltage detection status bits in the RESET_SR2 register.
+*  The bits are set to 1 by the voltage monitor circuit when the supply is
+*  outside the detector’s trip point, and set to 0 when the supply is inside the
+*  trip point.
+*
+* \return
+*  Status of the LVID, LVIA, and HVIA bits in the RESET_SR2 register.
+*   Define                  Definition
+*   CY_VD_LVID            Real-time status of digital LVI.
+*   CY_VD_LVIA            Real-time status of analog LVI.
+*   CY_VD_HVIA            Real-time status of analog HVI.
+*
+* Side Effects and Restrictions:
+*  When an LVI reset occurs, the RESET_SR2 status registers are cleared. This
+*  means that the voltage detection status bits are not persistent across an LVI
+*  reset and cannot be used to determine a reset source.
+*
+*******************************************************************************/
+uint8 CyVdRealTimeStatus(void) 
+{
+    uint8 interruptState;
+    uint8 vdFlagsState;
+
+    interruptState = CyEnterCriticalSection();
+    vdFlagsState = CY_VD_RT_STATUS_REG & (CY_VD_LVID | CY_VD_LVIA | CY_VD_HVIA);
+    CyExitCriticalSection(interruptState);
+
+    return(vdFlagsState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDisableInts
+****************************************************************************//**
+*
+*  Disables the interrupt enable for each interrupt.
+*
+* \return
+*  32 bit mask of previously enabled interrupts.
+*
+*******************************************************************************/
+uint32 CyDisableInts(void) 
+{
+    uint32 intState;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    #if(CY_PSOC3)
+
+        /* Get the current interrupt state. */
+        intState  = ((uint32) CY_GET_REG8(CY_INT_CLR_EN0_PTR));
+        intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN1_PTR)) << 8u));
+        intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN2_PTR)) << 16u));
+        intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN3_PTR)) << 24u));
+
+
+        /* Disable all of the interrupts. */
+        CY_SET_REG8(CY_INT_CLR_EN0_PTR, 0xFFu);
+        CY_SET_REG8(CY_INT_CLR_EN1_PTR, 0xFFu);
+        CY_SET_REG8(CY_INT_CLR_EN2_PTR, 0xFFu);
+        CY_SET_REG8(CY_INT_CLR_EN3_PTR, 0xFFu);
+
+    #else
+
+        /* Get the current interrupt state. */
+        intState = CY_GET_REG32(CY_INT_CLEAR_PTR);
+
+        /* Disable all of the interrupts. */
+        CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu);
+
+    #endif /* (CY_PSOC3) */
+
+    CyExitCriticalSection(interruptState);
+
+    return (intState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyEnableInts
+****************************************************************************//**
+*
+*  Enables interrupts to a given state.
+*
+*  \param uint32 mask: 32 bit mask of interrupts to enable.
+*
+*******************************************************************************/
+void CyEnableInts(uint32 mask) 
+{
+
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    #if(CY_PSOC3)
+
+        /* Set interrupts as enabled. */
+        CY_SET_REG8(CY_INT_SET_EN3_PTR, ((uint8) (mask >> 24u)));
+        CY_SET_REG8(CY_INT_SET_EN2_PTR, ((uint8) (mask >> 16u)));
+        CY_SET_REG8(CY_INT_SET_EN1_PTR, ((uint8) (mask >> 8u )));
+        CY_SET_REG8(CY_INT_SET_EN0_PTR, ((uint8) (mask )));
+
+    #else
+
+        CY_SET_REG32(CY_INT_ENABLE_PTR, mask);
+
+    #endif /* (CY_PSOC3) */
+
+    CyExitCriticalSection(interruptState);
+
+}
+
+#if(CY_PSOC5)
+
+    /*******************************************************************************
+    * Function Name: CyFlushCache
+    ****************************************************************************//**
+    *  Call this API after a flash row erase/write operation to invalidate or flush
+    *  any of that particular flash region content already present in the cache.
+    *  After a cache flush operation, any access to that flash region after the
+    *  erase/write operation would reload the cache with the modified data from the
+    *  flash region. If the flash region update involves multiple flash row write
+    *  operations, then the flushing of the cache can be done once at the end of
+    *  the operation as long as the flash data would not be accessed in the middle
+    *  of the multiple row update process. Else, flush the cache after every flash
+    *  row write.
+    *
+    *******************************************************************************/
+    void CyFlushCache(void)
+    {
+        uint8 interruptState;
+
+        /* Save current global interrupt enable and disable it */
+        interruptState = CyEnterCriticalSection();
+
+        /* Fill instruction prefectch unit to insure data integrity */
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+
+        /* All entries in cache are invalidated on next clock cycle. */
+        CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;
+
+        /* Once this is executed it's guaranteed the cache has been flushed */
+        (void) CY_CACHE_CONTROL_REG;
+
+        /* Flush the pipeline */
+        CY_SYS_ISB;
+
+        /* Restore global interrupt enable state */
+        CyExitCriticalSection(interruptState);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntSetSysVector
+    ****************************************************************************//**
+    *  Sets the interrupt vector of the specified system interrupt number. System
+    *  interrupts are present only for the ARM platform. These interrupts are for
+    *  SysTick, PendSV and others.
+    *
+    *  \param number: System interrupt number:
+    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
+    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
+    *    CY_INT_MEM_MANAGE_IRQN         - Memory Management Interrupt
+    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
+    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
+    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
+    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
+    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
+    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
+    *
+    *  \param address: Pointer to an interrupt service routine.
+    *
+    * \return
+    *   The old ISR vector at this location.
+    *
+    *******************************************************************************/
+    cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address)
+    {
+        cyisraddress oldIsr;
+        cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;
+
+        CYASSERT(number <= CY_INT_SYS_NUMBER_MAX);
+
+        /* Save old Interrupt service routine. */
+        oldIsr = ramVectorTable[number & CY_INT_SYS_NUMBER_MASK];
+
+        /* Set new Interrupt service routine. */
+        ramVectorTable[number & CY_INT_SYS_NUMBER_MASK] = address;
+
+        return (oldIsr);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetSysVector
+    ****************************************************************************//**
+    *
+    *  Gets the interrupt vector of the specified system interrupt number. System
+    *  interrupts are present only for the ARM platform. These interrupts are for
+    *  SysTick, PendSV and others.
+    *
+    *  \param number: System interrupt number:
+    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
+    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
+    *    CY_INT_MEMORY_MANAGEMENT_IRQN  - Memory Management Interrupt
+    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
+    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
+    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
+    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
+    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
+    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
+    *
+    * \return
+    *   Address of the ISR in the interrupt vector table.
+    *
+    *******************************************************************************/
+    cyisraddress CyIntGetSysVector(uint8 number)
+    {
+        cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;
+        CYASSERT(number <= CY_INT_SYS_NUMBER_MAX);
+
+        return ramVectorTable[number & CY_INT_SYS_NUMBER_MASK];
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntSetVector
+    ****************************************************************************//**
+    *
+    *  Sets the interrupt vector of the specified interrupt number.
+    *
+    *  \param number: Valid range [0-31].  Interrupt number
+    *  \param address: Pointer to an interrupt service routine
+    *
+    * \return
+    *   Previous interrupt vector value.
+    *
+    *******************************************************************************/
+    cyisraddress CyIntSetVector(uint8 number, cyisraddress address)
+    {
+        cyisraddress oldIsr;
+        cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        /* Save old Interrupt service routine. */
+        oldIsr = ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)];
+
+        /* Set new Interrupt service routine. */
+        ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)] = address;
+
+        return (oldIsr);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetVector
+    ****************************************************************************//**
+    *
+    *  Gets the interrupt vector of the specified interrupt number.
+    *
+    *  \param number: Valid range [0-31].  Interrupt number
+    *
+    * \return
+    *  The address of the ISR in the interrupt vector table.
+    *
+    *******************************************************************************/
+    cyisraddress CyIntGetVector(uint8 number)
+    {
+        cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        return (ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntSetPriority
+    ****************************************************************************//**
+    *
+    *  Sets the Priority of the Interrupt.
+    *
+    *  \param priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+    *  \param number: The number of the interrupt, 0 - 31.
+    *
+    *******************************************************************************/
+    void CyIntSetPriority(uint8 number, uint8 priority)
+    {
+        CYASSERT(priority <= CY_INT_PRIORITY_MAX);
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+        CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = (priority & CY_INT_PRIORITY_MASK)<< 5;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetPriority
+    ****************************************************************************//**
+    *
+    *  Gets the Priority of the Interrupt.
+    *
+    *  \param number: The number of the interrupt, 0 - 31.
+    *
+    * \return
+    *  Priority of the interrupt. 0 - 7, 0 being the highest.
+    *
+    *******************************************************************************/
+    uint8 CyIntGetPriority(uint8 number)
+    {
+        uint8 priority;
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5;
+
+        return (priority);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetState
+    ****************************************************************************//**
+    *
+    *   Gets the enable state of the specified interrupt number.
+    *
+    *   \param number: Valid range [0-31].  Interrupt number.
+    *
+    * \return
+    *   Enable status: 1 if enabled, 0 if disabled
+    *
+    *******************************************************************************/
+    uint8 CyIntGetState(uint8 number)
+    {
+        reg32 * stateReg;
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        /* Get pointer to Interrupt enable register. */
+        stateReg = CY_INT_ENABLE_PTR;
+
+        /* Get state of interrupt. */
+        return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));
+    }
+
+
+#else   /* PSoC3 */
+
+    /*******************************************************************************
+    * Function Name: IntDefaultHandler
+    ****************************************************************************//**
+    *
+    *  This function is called for all interrupts, other than a reset that gets
+    *  called before the system is setup.
+    *
+    * Theory:
+    *  Any value other than zero is acceptable.
+    *
+    *******************************************************************************/
+    CY_ISR(IntDefaultHandler)
+    {
+        #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK
+            CyBoot_IntDefaultHandler_Exception_EntryCallback();
+        #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */
+
+        while(1)
+        {
+            /***********************************************************************
+            * We must not get here. If we do, a serious problem occurs, so go
+            * into an infinite loop.
+            ***********************************************************************/
+        }
+    }
+
+
+    /*******************************************************************************
+    * Function Name: IntDefaultHandler
+    ****************************************************************************//**
+    *
+    *  This function is called during startup to initialize interrupt address vector
+    *  registers with the address of the IntDefaultHandler().
+    *
+    *******************************************************************************/
+    void CyIntInitVectors(void) 
+    {
+        uint8 i;
+
+        for (i = 0; i <= CY_INT_NUMBER_MAX; i++)
+        {
+            CY_SET_REG16(&CY_INT_VECT_TABLE[i], (uint16) &IntDefaultHandler);
+        }
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntSetVector
+    ****************************************************************************//**
+    *
+    *  Sets the interrupt vector of the specified interrupt number.
+    *
+    *  \param number:  Valid range [0-31].  Interrupt number
+    *  \param address: Pointer to an interrupt service routine
+    *
+    * \return
+    *  Previous interrupt vector value.
+    *
+    *******************************************************************************/
+    cyisraddress CyIntSetVector(uint8 number, cyisraddress address) 
+    {
+        cyisraddress oldIsr;
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        /* Save old Interrupt service routine. */
+        oldIsr = (cyisraddress) \
+                    CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]);
+
+        /* Set new Interrupt service routine. */
+        CY_SET_REG16(&CY_INT_VECT_TABLE[number], (uint16) address);
+
+        return (oldIsr);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetVector
+    ****************************************************************************//**
+    *
+    *  Gets the interrupt vector of the specified interrupt number.
+    *
+    *  \param number: Valid range [0-31].  Interrupt number
+    *
+    * \return
+    *  Address of the ISR in the interrupt vector table.
+    *
+    *******************************************************************************/
+    cyisraddress CyIntGetVector(uint8 number) 
+    {
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        return ((cyisraddress) \
+                CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntSetPriority
+    ****************************************************************************//**
+    *
+    *  Sets the Priority of the Interrupt.
+    *
+    *  \param priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+    *  \param number:   The number of the interrupt, 0 - 31.
+    *
+    *******************************************************************************/
+    void CyIntSetPriority(uint8 number, uint8 priority) 
+    {
+        CYASSERT(priority <= CY_INT_PRIORITY_MAX);
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] =
+                    (priority & CY_INT_PRIORITY_MASK) << 5;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetPriority
+    ****************************************************************************//**
+    *
+    *  Gets the Priority of the Interrupt.
+    *
+    *  \param number: The number of the interrupt, 0 - 31.
+    *
+    * \return
+    *  Priority of the interrupt. 0 - 7, 0 being the highest.
+    *
+    *******************************************************************************/
+    uint8 CyIntGetPriority(uint8 number) 
+    {
+        uint8 priority;
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5;
+
+        return (priority);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetState
+    ****************************************************************************//**
+    *
+    *   Gets the enable state of the specified interrupt number.
+    *
+    *   \param number: Valid range [0-31].  Interrupt number.
+    *
+    * \return
+    *   Enable status: 1 if enabled, 0 if disabled
+    *
+    *******************************************************************************/
+    uint8 CyIntGetState(uint8 number) 
+    {
+        reg8 * stateReg;
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        /* Get pointer to Interrupt enable register. */
+        stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);
+
+        /* Get state of interrupt. */
+        return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));
+    }
+
+#endif  /* (CY_PSOC5) */
+
+
+#if(CYDEV_VARIABLE_VDDA == 1)
+
+    /*******************************************************************************
+    * Function Name: CySetScPumps
+    ****************************************************************************//**
+    *
+    *  If 1 is passed as a parameter:
+    *   - if any of the SC blocks are used - enable pumps for the SC blocks and
+    *     start boost clock.
+    *   - For each enabled SC block set a boost clock index and enable the boost
+    *     clock.
+    *
+    *  If non-1 value is passed as a parameter:
+    *   - If all SC blocks are not used - disable pumps for the SC blocks and
+    *     stop the boost clock.
+    *   - For each enabled SC block clear the boost clock index and disable the
+    *     boost clock.
+    *
+    *  The global variable CyScPumpEnabled is updated to be equal to passed the
+    *  parameter.
+    *
+    *   \param uint8 enable: Enable/disable SC pumps and the boost clock for the enabled
+    *                 \param SC block:
+    *                 1 - Enable
+    *                 0 - Disable
+    *
+    *******************************************************************************/
+    void CySetScPumps(uint8 enable) 
+    {
+        if(1u == enable)
+        {
+            /* The SC pumps should be enabled */
+            CyScPumpEnabled = 1u;
+            /* Enable pumps if any of SC blocks are used */
+            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK))
+            {
+                CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE;
+                CyScBoostClk_Start();
+            }
+            /* Set positive pump for each enabled SC block: set clock index and enable it */
+            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN))
+            {
+                CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;
+                CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN;
+            }
+            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN))
+            {
+                CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;
+                CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN;
+            }
+            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN))
+            {
+                CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;
+                CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN;
+            }
+            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN))
+            {
+                CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;
+                CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN;
+            }
+        }
+        else
+        {
+            /* The SC pumps should be disabled */
+            CyScPumpEnabled = 0u;
+            /* Disable pumps for all SC blocks and stop boost clock */
+            CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE));
+            CyScBoostClk_Stop();
+            /* Disable boost clock and clear clock index for each SC block */
+            CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));
+            CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;
+            CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));
+            CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;
+            CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));
+            CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;
+            CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));
+            CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;
+        }
+    }
+
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+
+
+#if(CY_PSOC5)
+    /*******************************************************************************
+    * Function Name: CySysTickStart
+    ****************************************************************************//**
+    *
+    *  Configures the SysTick timer to generate interrupt every 1 ms by call to the
+    *  CySysTickInit() function and starts it by calling CySysTickEnable() function.
+    *  Refer to the corresponding function description for the details.
+
+    * \sideeffect
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickStart(void)
+    {
+        if (0u == CySysTickInitVar)
+        {
+            CySysTickInit();
+            CySysTickInitVar = 1u;
+        }
+
+        CySysTickEnable();
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickInit
+    ****************************************************************************//**
+    *
+    *  Initializes the callback addresses with pointers to NULL, associates the
+    *  SysTick system vector with the function that is responsible for calling
+    *  registered callback functions, configures SysTick timer to generate interrupt
+    * every 1 ms.
+    *
+    * \sideeffect
+    *  Clears SysTick count flag if it was set.
+    *
+    *  The 1 ms interrupt interval is configured based on the frequency determined
+    *  by PSoC Creator at build time. If System clock frequency is changed in
+    *  runtime, the CyDelayFreq() with the appropriate parameter should be called.
+    *
+    *******************************************************************************/
+    void CySysTickInit(void)
+    {
+        uint32 i;
+
+        for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+        {
+            CySysTickCallbacks[i] = (void *) 0;
+        }
+
+        (void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);
+        CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);
+        CySysTickSetReload(cydelay_freq_hz/1000u);
+        CySysTickClear();
+        CyIntEnable(CY_INT_SYSTICK_IRQN);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickEnable
+    ****************************************************************************//**
+    *
+    *  Enables the SysTick timer and its interrupt.
+    *
+    * \sideeffect
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickEnable(void)
+    {
+        CySysTickEnableInterrupt();
+        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickStop
+    ****************************************************************************//**
+    *
+    *  Stops the system timer (SysTick).
+    *
+    * \sideeffect
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickStop(void)
+    {
+        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickEnableInterrupt
+    ****************************************************************************//**
+    *
+    *  Enables the SysTick interrupt.
+    *
+    * \sideeffect
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickEnableInterrupt(void)
+    {
+        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE_INT;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickDisableInterrupt
+    ****************************************************************************//**
+    *
+    *  Disables the SysTick interrupt.
+    *
+    * \sideeffect
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickDisableInterrupt(void)
+    {
+        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE_INT));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetReload
+    ****************************************************************************//**
+    *
+    *  Sets value the counter is set to on startup and after it reaches zero. This
+    *  function do not change or reset current sysTick counter value, so it should
+    *  be cleared using CySysTickClear() API.
+    *
+    *  \param value: Valid range [0x0-0x00FFFFFF]. Counter reset value.
+    *
+    *******************************************************************************/
+    void CySysTickSetReload(uint32 value)
+    {
+        CY_SYS_SYST_RVR_REG = (value & CY_SYS_SYST_RVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetReload
+    ****************************************************************************//**
+    *
+    *  Sets value the counter is set to on startup and after it reaches zero.
+    *
+    * \return
+    *  Counter reset value
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetReload(void)
+    {
+        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_RVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetValue
+    ****************************************************************************//**
+    *
+    *  Gets current SysTick counter value.
+    *
+    * \return
+    *  Current SysTick counter value
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetValue(void)
+    {
+        return(CY_SYS_SYST_CVR_REG & CY_SYS_SYST_CVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetClockSource
+    ****************************************************************************//**
+    *
+    *  Sets the clock source for the SysTick counter.
+    *
+    *  \param clockSource: Clock source for SysTick counter
+    *         Define                     Clock Source
+    *   CY_SYS_SYST_CSR_CLK_SRC_SYSCLK     SysTick is clocked by CPU clock.
+    *   CY_SYS_SYST_CSR_CLK_SRC_LFCLK      SysTick is clocked by the low frequency
+    *                                      clock (ILO 100 KHz for PSoC 5LP, and
+    *                                      LFCLK for PSoC 4).
+    *
+    * \sideeffect
+    *  Clears SysTick count flag if it was set. If clock source is not ready this
+    *  function call will have no effect. After changing clock source to the low
+    *  frequency clock the counter and reload register values will remain unchanged
+    *  so time to the interrupt will be significantly bigger and vice versa.
+    *
+    *******************************************************************************/
+    void CySysTickSetClockSource(uint32 clockSource)
+    {
+        if (clockSource == CY_SYS_SYST_CSR_CLK_SRC_SYSCLK)
+        {
+            CY_SYS_SYST_CSR_REG |= (uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT);
+        }
+        else
+        {
+            CY_SYS_SYST_CSR_REG &= ((uint32) ~((uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT)));
+        }
+    }
+
+    
+    /*******************************************************************************
+    * Function Name: CySysTickGetClockSource
+    ****************************************************************************//**
+    *
+    *  Returns the current clock source of the SysTick counter.
+    *
+    *  \return 
+    *   CY_SYS_SYST_CSR_CLK_SRC_SYSCLK     SysTick is clocked by CPU clock.
+    *   CY_SYS_SYST_CSR_CLK_SRC_LFCLK      SysTick is clocked by the low frequency
+    *                                      clock. (ILO 100 KHz for PSoC 5LP, and
+    *                                      LFCLK for PSoC 4).
+    *******************************************************************************/
+    uint32 CySysTickGetClockSource(void)
+    {
+        return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT) & CY_SYS_SYST_CSR_CLK_SRC_SYSCLK );
+    }
+
+    
+    /*******************************************************************************
+    * Function Name: CySysTickGetCountFlag
+    ****************************************************************************//**
+    *
+    *  The count flag is set once SysTick counter reaches zero.
+    *   The flag cleared on read.
+    *
+    * \return
+    *  Returns non-zero value if flag is set, otherwise zero is returned.
+    *
+    *
+    * \sideeffect
+    *  Clears SysTick count flag if it was set.
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetCountFlag(void)
+    {
+        return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickClear
+    ****************************************************************************//**
+    *
+    *  Clears the SysTick counter for well-defined startup.
+    *
+    *******************************************************************************/
+    void CySysTickClear(void)
+    {
+        CY_SYS_SYST_CVR_REG = 0u;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetCallback
+    ****************************************************************************//**
+    *
+    *  This function allows up to five user-defined interrupt service routine
+    *  functions to be associated with the SysTick interrupt. These are specified
+    *  through the use of pointers to the function.
+    *
+    *  To set a custom callback function without the overhead of the system provided
+    *  one, use CyIntSetSysVector(CY_INT_SYSTICK_IRQN, cyisraddress <address>),
+    *  where <address> is address of the custom defined interrupt service routine.
+    *  Note: a custom callback function overrides the system defined callback
+    *  functions.
+    *
+    *  \param number: The number of the callback function addresses to be set. The valid
+    *          range is from 0 to 4.
+    *
+    *  void(*CallbackFunction(void): A pointer to the function that will be
+    *                                associated with the SysTick ISR for the
+    *                                specified number.
+    *
+    * \return
+    *  Returns the address of the previous callback function.
+    *  The NULL is returned if the specified address in not set.
+    *
+    * \sideeffect
+    *  The registered callback functions will be executed in the interrupt.
+    *
+    *******************************************************************************/
+    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)
+    {
+        cySysTickCallback retVal;
+
+        retVal = CySysTickCallbacks[number];
+        CySysTickCallbacks[number] = function;
+        return (retVal);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetCallback
+    ****************************************************************************//**
+    *
+    *  The function get the specified callback pointer.
+    *
+    *  \param number: The number of callback function address to get. The valid
+    *          range is from 0 to 4.
+    *
+    * \return
+    *  Returns the address of the specified callback function.
+    *  The NULL is returned if the specified address in not initialized.
+    *
+    *******************************************************************************/
+    cySysTickCallback CySysTickGetCallback(uint32 number)
+    {
+        return ((cySysTickCallback) CySysTickCallbacks[number]);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickServiceCallbacks
+    ****************************************************************************//**
+    *
+    *  System Tick timer interrupt routine
+    *
+    *******************************************************************************/
+    static void CySysTickServiceCallbacks(void)
+    {
+        uint32 i;
+
+        /* Verify that tick timer flag was set */
+        if (1u == CySysTickGetCountFlag())
+        {
+            for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+            {
+                if (CySysTickCallbacks[i] != (void *) 0)
+                {
+                    (void)(CySysTickCallbacks[i])();
+                }
+            }
+        }
+    }
+#endif /* (CY_PSOC5) */
+
+
+/*******************************************************************************
+* Function Name: CyGetUniqueId
+****************************************************************************//**
+*
+*  Returns the 64-bit unique ID of the device. The uniqueness of the number is
+*  guaranteed for 10 years due to the die lot number having a cycle life of 10
+*  years and even after 10 years, the probability of getting two identical
+*  numbers is very small.
+*
+*  \param uniqueId: The pointer to a two element 32-bit unsigned integer array. Returns
+*  the 64-bit unique ID of the device by loading them into the integer array
+*  pointed to by uniqueId.
+*
+*******************************************************************************/
+void CyGetUniqueId(uint32* uniqueId)
+{
+#if(CY_PSOC4)
+    uniqueId[0u]  =  (uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT0  );
+    uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT1  ) <<  8u);
+    uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT2  ) << 16u);
+    uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_WAFER ) << 24u);
+
+    uniqueId[1u]  =  (uint32)(* (reg8 *) CYREG_SFLASH_DIE_X     );
+    uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_Y     ) <<  8u);
+    uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_SORT  ) << 16u);
+    uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_MINOR ) << 24u);
+#else
+    uniqueId[0u]  =  (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_LSB   ));
+    uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_MSB   )) <<  8u);
+    uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_MLOGIC_REV_ID                )) << 16u);
+    uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WAFER_NUM )) << 24u);
+
+    uniqueId[1u]  =  (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_X_LOC     ));
+    uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_Y_LOC     )) <<  8u);
+    uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WRK_WK    )) << 16u);
+    uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_FAB_YR    )) << 24u);
+#endif  /* (CY_PSOC4) */
+}
+
+/* [] END OF FILE */
diff --git a/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h b/software/SCSI2SD/v5.5/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h
new file mode 100755 (executable)
index 0000000..37cb94e
--- /dev/null
@@ -0,0 +1,1320 @@
+/***************************************************************************//**
+* \file CyLib.h
+* \version 5.60
+*
+* \brief Provides the function definitions for the system, clocking, interrupts
+* and watchdog timer API.
+*
+* \note Documentation of the API's in this file is located in the System
+* Reference Guide provided with PSoC Creator.
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2017, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_BOOT_CYLIB_H)
+#define CY_BOOT_CYLIB_H
+
+#include <string.h>
+#include <limits.h>
+#include <ctype.h>
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cydevice_trm.h"
+#include "cyPm.h"
+
+#if(CY_PSOC3)
+    #include <PSoC3_8051.h>
+#endif  /* (CY_PSOC3) */
+
+
+#if(CYDEV_VARIABLE_VDDA == 1)
+
+    #include "CyScBoostClk.h"
+
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+
+
+/* Global variable with preserved reset status */
+extern uint8 CYXDATA CyResetStatus;
+
+
+/* Variable Vdda */
+#if(CYDEV_VARIABLE_VDDA == 1)
+
+    extern uint8 CyScPumpEnabled;
+
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+
+
+/* Do not use these definitions directly in your application */
+extern uint32 cydelay_freq_hz;
+extern uint32 cydelay_freq_khz;
+extern uint8  cydelay_freq_mhz;
+extern uint32 cydelay_32k_ms;
+
+
+/***************************************
+*    Function Prototypes
+***************************************/
+cystatus CyPLL_OUT_Start(uint8 wait) ;
+void  CyPLL_OUT_Stop(void) ;
+void  CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) ;
+void  CyPLL_OUT_SetSource(uint8 source) ;
+
+void  CyIMO_Start(uint8 wait) ;
+void  CyIMO_Stop(void) ;
+void  CyIMO_SetFreq(uint8 freq) ;
+void  CyIMO_SetSource(uint8 source) ;
+void  CyIMO_EnableDoubler(void) ;
+void  CyIMO_DisableDoubler(void) ;
+
+void  CyMasterClk_SetSource(uint8 source) ;
+void  CyMasterClk_SetDivider(uint8 divider) ;
+void  CyBusClk_SetDivider(uint16 divider) ;
+
+#if(CY_PSOC3)
+    void  CyCpuClk_SetDivider(uint8 divider) ;
+#endif  /* (CY_PSOC3) */
+
+void  CyUsbClk_SetSource(uint8 source) ;
+
+void  CyILO_Start1K(void) ;
+void  CyILO_Stop1K(void) ;
+void  CyILO_Start100K(void) ;
+void  CyILO_Stop100K(void) ;
+void  CyILO_Enable33K(void) ;
+void  CyILO_Disable33K(void) ;
+void  CyILO_SetSource(uint8 source) ;
+uint8 CyILO_SetPowerMode(uint8 mode) ;
+
+uint8 CyXTAL_32KHZ_ReadStatus(void) ;
+uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) ;
+void  CyXTAL_32KHZ_Start(void) ;
+void  CyXTAL_32KHZ_Stop(void) ;
+
+cystatus CyXTAL_Start(uint8 wait) ;
+void  CyXTAL_Stop(void) ;
+void  CyXTAL_SetStartup(uint8 setting) ;
+
+void  CyXTAL_EnableErrStatus(void) ;
+void  CyXTAL_DisableErrStatus(void) ;
+uint8 CyXTAL_ReadStatus(void) ;
+void  CyXTAL_EnableFaultRecovery(void) ;
+void  CyXTAL_DisableFaultRecovery(void) ;
+
+void CyXTAL_SetFbVoltage(uint8 setting) ;
+void CyXTAL_SetWdVoltage(uint8 setting) ;
+
+void CyWdtStart(uint8 ticks, uint8 lpMode) ;
+void CyWdtClear(void) ;
+
+/* System Function Prototypes */
+void CyDelay(uint32 milliseconds) CYREENTRANT;
+void CyDelayUs(uint16 microseconds);
+void CyDelayFreq(uint32 freq) CYREENTRANT;
+void CyDelayCycles(uint32 cycles);
+
+void CySoftwareReset(void) ;
+
+uint8 CyEnterCriticalSection(void);
+void CyExitCriticalSection(uint8 savedIntrStatus);
+void CyHalt(uint8 reason) CYREENTRANT;
+
+
+/* Interrupt Function Prototypes */
+#if(CY_PSOC5)
+    cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address)  ;
+    cyisraddress CyIntGetSysVector(uint8 number) ;
+#endif  /* (CY_PSOC5) */
+
+cyisraddress CyIntSetVector(uint8 number, cyisraddress address) ;
+cyisraddress CyIntGetVector(uint8 number) ;
+
+void  CyIntSetPriority(uint8 number, uint8 priority) ;
+uint8 CyIntGetPriority(uint8 number) ;
+
+uint8 CyIntGetState(uint8 number) ;
+
+uint32 CyDisableInts(void) ;
+void CyEnableInts(uint32 mask) ;
+
+
+#if(CY_PSOC5)
+    void CyFlushCache(void);
+#endif  /* (CY_PSOC5) */
+
+
+/* Voltage Detection Function Prototypes */
+void CyVdLvDigitEnable(uint8 reset, uint8 threshold) ;
+void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) ;
+void CyVdLvDigitDisable(void) ;
+void CyVdLvAnalogDisable(void) ;
+void CyVdHvAnalogEnable(void) ;
+void CyVdHvAnalogDisable(void) ;
+uint8 CyVdStickyStatus(uint8 mask) ;
+uint8 CyVdRealTimeStatus(void) ;
+
+void CySetScPumps(uint8 enable) ;
+
+#if(CY_PSOC5)
+    /* Default interrupt handler */
+    CY_ISR_PROTO(IntDefaultHandler);
+#endif  /* (CY_PSOC5) */
+
+#if(CY_PSOC5)
+    /** System tick timer APIs */
+    typedef void (*cySysTickCallback)(void);
+
+    void CySysTickStart(void);
+    void CySysTickInit(void);
+    void CySysTickEnable(void);
+    void CySysTickStop(void);
+    void CySysTickEnableInterrupt(void);
+    void CySysTickDisableInterrupt(void);
+    void CySysTickSetReload(uint32 value);
+    uint32 CySysTickGetReload(void);
+    uint32 CySysTickGetValue(void);
+    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function);
+    cySysTickCallback CySysTickGetCallback(uint32 number);
+    void CySysTickSetClockSource(uint32 clockSource);
+    uint32 CySysTickGetCountFlag(void);
+    void CySysTickClear(void);
+#endif  /* (CY_PSOC5) */
+
+void CyGetUniqueId(uint32* uniqueId);
+
+
+/***************************************
+* API Constants
+***************************************/
+
+
+/*******************************************************************************
+* PLL API Constants
+*******************************************************************************/
+#define CY_CLK_PLL_ENABLE               (0x01u)
+#define CY_CLK_PLL_LOCK_STATUS          (0x01u)
+
+#define CY_CLK_PLL_FTW_INTERVAL         (24u)
+
+#define CY_CLK_PLL_MAX_Q_VALUE          (16u)
+#define CY_CLK_PLL_MIN_Q_VALUE          (1u)
+#define CY_CLK_PLL_MIN_P_VALUE          (8u)
+#define CY_CLK_PLL_MIN_CUR_VALUE        (1u)
+#define CY_CLK_PLL_MAX_CUR_VALUE        (7u)
+
+#define CY_CLK_PLL_CURRENT_POSITION     (4u)
+#define CY_CLK_PLL_CURRENT_MASK         (0x8Fu)
+
+
+/*******************************************************************************
+* External 32kHz Crystal Oscillator API Constants
+*******************************************************************************/
+#define CY_XTAL32K_ANA_STAT             (0x20u)
+
+#define CY_CLK_XTAL32_CR_LPM            (0x02u)
+#define CY_CLK_XTAL32_CR_EN             (0x01u)
+#if(CY_PSOC3)
+    #define CY_CLK_XTAL32_CR_PDBEN      (0x04u)
+#endif  /* (CY_PSOC3) */
+
+#define CY_CLK_XTAL32_TR_MASK           (0x07u)
+#define CY_CLK_XTAL32_TR_STARTUP        (0x03u)
+#define CY_CLK_XTAL32_TR_HIGH_POWER     (0x06u)
+#define CY_CLK_XTAL32_TR_LOW_POWER      (0x01u)
+#define CY_CLK_XTAL32_TR_POWERDOWN      (0x00u)
+
+#define CY_CLK_XTAL32_TST_DEFAULT       (0xF3u)
+
+#define CY_CLK_XTAL32_CFG_LP_DEFAULT    (0x04u)
+#define CY_CLK_XTAL32_CFG_LP_LOWPOWER   (0x08u)
+#define CY_CLK_XTAL32_CFG_LP_MASK       (0x0Cu)
+
+#define CY_CLK_XTAL32_CFG_LP_ALLOW      (0x80u)
+
+
+/*******************************************************************************
+* External MHz Crystal Oscillator API Constants
+*******************************************************************************/
+#define CY_CLK_XMHZ_FTW_INTERVAL        (24u)
+#define CY_CLK_XMHZ_MIN_TIMEOUT         (130u)
+
+#define CY_CLK_XMHZ_CSR_ENABLE          (0x01u)
+#define CY_CLK_XMHZ_CSR_XERR            (0x80u)
+#define CY_CLK_XMHZ_CSR_XFB             (0x04u)
+#define CY_CLK_XMHZ_CSR_XPROT           (0x40u)
+
+#define CY_CLK_XMHZ_CFG0_XCFG_MASK      (0x1Fu)
+#define CY_CLK_XMHZ_CFG1_VREF_FB_MASK   (0x0Fu)
+#define CY_CLK_XMHZ_CFG1_VREF_WD_MASK   (0x70u)
+
+
+/*******************************************************************************
+* Watchdog Timer API Constants
+*******************************************************************************/
+#define CYWDT_2_TICKS               (0x0u)     /*    4 -    6 ms */
+#define CYWDT_16_TICKS              (0x1u)     /*   32 -   48 ms */
+#define CYWDT_128_TICKS             (0x2u)     /*  256 -  384 ms */
+#define CYWDT_1024_TICKS            (0x3u)     /* 2048 - 3072 ms */
+
+#define CYWDT_LPMODE_NOCHANGE       (0x00u)
+#define CYWDT_LPMODE_MAXINTER       (0x01u)
+#define CYWDT_LPMODE_DISABLED       (0x03u)
+
+#define CY_WDT_CFG_INTERVAL_MASK    (0x03u)
+#define CY_WDT_CFG_CTW_RESET        (0x80u)
+#define CY_WDT_CFG_LPMODE_SHIFT     (5u)
+#define CY_WDT_CFG_LPMODE_MASK      (0x60u)
+#define CY_WDT_CFG_WDR_EN           (0x10u)
+#define CY_WDT_CFG_CLEAR_ALL        (0x00u)
+#define CY_WDT_CR_FEED              (0x01u)
+
+
+/*******************************************************************************
+*    Voltage Detection API Constants
+*******************************************************************************/
+
+#define CY_VD_LVID_EN                (0x01u)
+#define CY_VD_LVIA_EN                (0x02u)
+#define CY_VD_HVIA_EN                (0x04u)
+
+#define CY_VD_PRESD_EN               (0x40u)
+#define CY_VD_PRESA_EN               (0x80u)
+
+#define CY_VD_LVID                   (0x01u)
+#define CY_VD_LVIA                   (0x02u)
+#define CY_VD_HVIA                   (0x04u)
+
+#define CY_VD_LVI_TRIP_LVID_MASK     (0x0Fu)
+#define CY_VD_INT_MASK               ((uint32) (0x01u))
+
+
+/*******************************************************************************
+*    Variable VDDA API Constants
+*******************************************************************************/
+#if(CYDEV_VARIABLE_VDDA == 1)
+
+    /* Active Power Mode Configuration Register 9 */
+    #define CY_LIB_ACT_CFG9_SWCAP0_EN        (0x01u)
+    #define CY_LIB_ACT_CFG9_SWCAP1_EN        (0x02u)
+    #define CY_LIB_ACT_CFG9_SWCAP2_EN        (0x04u)
+    #define CY_LIB_ACT_CFG9_SWCAP3_EN        (0x08u)
+    #define CY_LIB_ACT_CFG9_SWCAPS_MASK      (0x0Fu)
+
+    /* Switched Cap Miscellaneous Control Register */
+    #define CY_LIB_SC_MISC_PUMP_FORCE        (0x20u)
+
+    /* Switched Capacitor 0 Boost Clock Selection Register */
+    #define CY_LIB_SC_BST_CLK_EN             (0x08u)
+    #define CY_LIB_SC_BST_CLK_INDEX_MASK     (0xF8u)
+
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+
+
+/*******************************************************************************
+* Clock Distribution API Constants
+*******************************************************************************/
+#define CY_LIB_CLKDIST_AMASK_MASK       (0xF0u)
+#define CY_LIB_CLKDIST_DMASK_MASK       (0x00u)
+#define CY_LIB_CLKDIST_LD_LOAD          (0x01u)
+#define CY_LIB_CLKDIST_BCFG2_MASK       (0x80u)
+#define CY_LIB_CLKDIST_MASTERCLK_DIV    (7u)
+#define CY_LIB_CLKDIST_BCFG2_SSS        (0x40u)
+#define CY_LIB_CLKDIST_MSTR1_SRC_MASK   (0xFCu)
+#define CY_LIB_FASTCLK_IMO_DOUBLER      (0x10u)
+#define CY_LIB_FASTCLK_IMO_IMO          (0x20u)
+#define CY_LIB_CLKDIST_CR_IMO2X         (0x40u)
+#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u)
+
+#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK  (0xFCu)
+
+
+/* CyILO_SetPowerMode() */
+#define CY_ILO_CONTROL_PD_MODE          (0x10u)
+#define CY_ILO_CONTROL_PD_POSITION      (4u)
+
+#define CY_ILO_SOURCE_100K              (0u)
+#define CY_ILO_SOURCE_33K               (1u)
+#define CY_ILO_SOURCE_1K                (2u)
+
+#define CY_ILO_FAST_START               (0u)
+#define CY_ILO_SLOW_START               (1u)
+
+#define CY_ILO_SOURCE_BITS_CLEAR        (0xF3u)
+#define CY_ILO_SOURCE_1K_SET            (0x08u)
+#define CY_ILO_SOURCE_33K_SET           (0x04u)
+#define CY_ILO_SOURCE_100K_SET          (0x00u)
+
+#define CY_MASTER_SOURCE_IMO            (0u)
+#define CY_MASTER_SOURCE_PLL            (1u)
+#define CY_MASTER_SOURCE_XTAL           (2u)
+#define CY_MASTER_SOURCE_DSI            (3u)
+
+#define CY_IMO_SOURCE_IMO               (0u)
+#define CY_IMO_SOURCE_XTAL              (1u)
+#define CY_IMO_SOURCE_DSI               (2u)
+
+
+/* CyIMO_Start() */
+#define CY_LIB_PM_ACT_CFG0_IMO_EN       (0x10u)
+#define CY_LIB_PM_STBY_CFG0_IMO_EN      (0x10u)
+#define CY_LIB_CLK_IMO_FTW_TIMEOUT      (0x00u)
+
+#define CY_LIB_IMO_3MHZ_VALUE           (0x03u)
+#define CY_LIB_IMO_6MHZ_VALUE           (0x01u)
+#define CY_LIB_IMO_12MHZ_VALUE          (0x00u)
+#define CY_LIB_IMO_24MHZ_VALUE          (0x02u)
+#define CY_LIB_IMO_48MHZ_VALUE          (0x04u)
+#define CY_LIB_IMO_62MHZ_VALUE          (0x05u)
+#define CY_LIB_IMO_74MHZ_VALUE          (0x06u)
+
+
+/* CyIMO_SetFreq() */
+#define CY_IMO_FREQ_3MHZ                (0u)
+#define CY_IMO_FREQ_6MHZ                (1u)
+#define CY_IMO_FREQ_12MHZ               (2u)
+#define CY_IMO_FREQ_24MHZ               (3u)
+#define CY_IMO_FREQ_48MHZ               (4u)
+#define CY_IMO_FREQ_62MHZ               (5u)
+#if(CY_PSOC5)
+    #define CY_IMO_FREQ_74MHZ           (6u)
+#endif  /* (CY_PSOC5) */
+#define CY_IMO_FREQ_USB                 (8u)
+
+#define CY_LIB_IMO_USBCLK_ON_SET        (0x40u)
+
+
+/* CyCpuClk_SetDivider() */
+#define CY_LIB_CLKDIST_DIV_POSITION     (4u)
+#define CY_LIB_CLKDIST_MSTR1_DIV_MASK   (0x0Fu)
+
+
+/* CyIMO_SetTrimValue() */
+#define CY_LIB_USB_CLK_EN               (0x02u)
+
+
+/* CyPLL_OUT_SetSource() - parameters */
+#define CY_PLL_SOURCE_IMO               (0u)
+#define CY_PLL_SOURCE_XTAL              (1u)
+#define CY_PLL_SOURCE_DSI               (2u)
+
+
+/* CyILO_[Start|Stop][1|100K](), CyILO_[Enable|Disable]33K() */
+#define CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ   (0x02u)
+#define CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ  (0x20u)
+#define CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ (0x04u)
+
+
+/* CyUsbClk_SetSource() */
+#define CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK (0x03u)
+
+
+/* CyUsbClk_SetSource() - parameters */
+#define CY_LIB_USB_CLK_IMO2X            (0x00u)
+#define CY_LIB_USB_CLK_IMO              (0x01u)
+#define CY_LIB_USB_CLK_PLL              (0x02u)
+#define CY_LIB_USB_CLK_DSI              (0x03u)
+
+
+/* CyUSB_PowerOnCheck() */
+#define CY_ACT_USB_ENABLED              (0x01u)
+#define CY_ALT_ACT_USB_ENABLED          (0x01u)
+
+
+#if(CY_PSOC5)
+
+    /***************************************************************************
+    * Instruction Synchronization Barrier flushes the pipeline in the processor,
+    * so that all instructions following the ISB are fetched from cache or
+    * memory, after the instruction has been completed.
+    ***************************************************************************/
+
+    #if defined(__ARMCC_VERSION)
+        #define CY_SYS_ISB       __isb(0x0f)
+    #else   /* ASM for GCC & IAR */
+        #define CY_SYS_ISB       __asm volatile ("isb \n")
+    #endif /* (__ARMCC_VERSION) */
+
+#endif /* (CY_PSOC5) */
+
+
+/***************************************
+* Registers
+***************************************/
+
+
+/*******************************************************************************
+* System Registers
+*******************************************************************************/
+
+/* Software Reset Control Register */
+#define CY_LIB_RESET_CR2_REG         (* (reg8 *) CYREG_RESET_CR2)
+#define CY_LIB_RESET_CR2_PTR         (  (reg8 *) CYREG_RESET_CR2)
+
+/* Timewheel Configuration Register 0 */
+#define CY_LIB_PM_TW_CFG0_REG           (*(reg8 *) CYREG_PM_TW_CFG0)
+#define CY_LIB_PM_TW_CFG0_PTR           ( (reg8 *) CYREG_PM_TW_CFG0)
+
+/* Timewheel Configuration Register 2 */
+#define CY_LIB_PM_TW_CFG2_REG           (*(reg8 *) CYREG_PM_TW_CFG2)
+#define CY_LIB_PM_TW_CFG2_PTR           ( (reg8 *) CYREG_PM_TW_CFG2)
+
+/* USB Configuration Register */
+#define CY_LIB_CLKDIST_UCFG_REG         (*(reg8 *) CYREG_CLKDIST_UCFG)
+#define CY_LIB_CLKDIST_UCFG_PTR         ( (reg8 *) CYREG_CLKDIST_UCFG)
+
+/* Internal Main Oscillator Trim Register 1 */
+#define CY_LIB_IMO_TR1_REG              (*(reg8 *) CYREG_IMO_TR1)
+#define