+20150201 4.1
+ - Rewrite of the SD card interface to fix compatibility problems.
+ This fixes write issues with Samsung SD cards.
+ - Workaround for SCSI hosts that set 250ms timeouts. Some NCR53C80/53C9X
+ drivers (openbsd, netbsd, and others) set a byte-to-byte timeout which
+ can be exceeded by SD card latency.
+ - Upgrade to PSoC Creator 3.1 and gcc 4.8.4.
+
20150108 4.0
- Fix handling requests for LUNs other than 0 from SCSI-2 hosts.
- Handle glitches of the scsi signals to improve stability and operate with
\r
#include "device.h"\r
#include "config.h"\r
+#include "debug.h"\r
#include "USBFS.h"\r
#include "led.h"\r
\r
\r
#include <string.h>\r
\r
-static const uint16_t FIRMWARE_VERSION = 0x0403;\r
+static const uint16_t FIRMWARE_VERSION = 0x0410;\r
\r
enum USB_ENDPOINTS\r
{\r
}\r
else\r
{\r
- uint8_t spcBuffer[CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE];\r
- CyFlash_Start();\r
- CySetFlashEEBuffer(spcBuffer);\r
CySetTemp();\r
int status = CyWriteRowData(flashArray, flashRow, cmd + 1);\r
- CyFlash_Stop();\r
\r
uint8_t response[] =\r
{\r
hidPacket_send(response, sizeof(response));\r
}\r
\r
+static void\r
+sdInfoCommand()\r
+{\r
+ uint8_t response[sizeof(sdDev.csd) + sizeof(sdDev.cid)];\r
+ memcpy(response, sdDev.csd, sizeof(sdDev.csd));\r
+ memcpy(response + sizeof(sdDev.csd), sdDev.cid, sizeof(sdDev.cid));\r
+\r
+ hidPacket_send(response, sizeof(response));\r
+}\r
static void\r
processCommand(const uint8_t* cmd, size_t cmdSize)\r
{\r
Bootloadable_1_Load();\r
break;\r
\r
+ case CONFIG_SDINFO:\r
+ sdInfoCommand();\r
+ break;\r
+\r
case CONFIG_NONE: // invalid\r
default:\r
break;\r
hidBuffer[24] = scsiDev.cmdCount;\r
hidBuffer[25] = scsiDev.watchdogTick;\r
hidBuffer[26] = blockDev.state;\r
- \r
+ hidBuffer[27] = scsiDev.lastSenseASC >> 8;\r
+ hidBuffer[28] = scsiDev.lastSenseASC;\r
+\r
+\r
hidBuffer[58] = sdDev.capacity >> 24;\r
hidBuffer[59] = sdDev.capacity >> 16;\r
hidBuffer[60] = sdDev.capacity >> 8;\r
Debug_Timer_Start();\r
}\r
\r
+void debugPause()\r
+{\r
+ Debug_Timer_Stop();\r
+}\r
+\r
+void debugResume()\r
+{\r
+ Debug_Timer_Start();\r
+}\r
+\r
// Public method for storing MODE SELECT results.\r
void configSave(int scsiId, uint16_t bytesPerSector)\r
{\r
memcpy(rowCfgData, tgt, sizeof(rowData));\r
rowCfgData->bytesPerSector = bytesPerSector;\r
\r
-\r
- uint8_t spcBuffer[CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE];\r
- CyFlash_Start();\r
- CySetFlashEEBuffer(spcBuffer);\r
CySetTemp();\r
CyWriteRowData(\r
SCSI_CONFIG_ARRAY,\r
SCSI_CONFIG_0_ROW + (cfgIdx * SCSI_CONFIG_ROWS),\r
(uint8_t*)rowCfgData);\r
- CyFlash_Stop();\r
return;\r
}\r
}\r
--- /dev/null
+// Copyright (C) 2015 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef Debug_H
+#define Debug_H
+
+void debugInit(void);
+void debugPause(void);
+void debugResume(void);
+
+#endif
+
#include "scsi.h"\r
#include "scsiPhy.h"\r
#include "config.h"\r
+#include "debug.h"\r
+#include "debug.h"\r
#include "disk.h"\r
#include "sd.h"\r
#include "time.h"\r
\r
void scsiDiskPoll()\r
{\r
+ debugPause(); // TODO comment re. timeouts.\r
+\r
if (scsiDev.phase == DATA_IN &&\r
transfer.currentBlock != transfer.blocks)\r
{\r
int prep = 0;\r
int i = 0;\r
int scsiDisconnected = 0;\r
- volatile uint32_t lastActivityTime = getTime_ms();\r
+ int scsiComplete = 0;\r
+ uint32_t lastActivityTime = getTime_ms();\r
int scsiActive = 0;\r
int sdActive = 0;\r
- \r
+\r
while ((i < totalSDSectors) &&\r
- (scsiDev.phase == DATA_OUT) && // scsiDisconnect keeps our phase.\r
+ ((scsiDev.phase == DATA_OUT) || // scsiDisconnect keeps our phase.\r
+ scsiComplete) &&\r
!scsiDev.resetFlag)\r
{\r
- if ((sdActive == 1) && sdWriteSectorDMAPoll())\r
+ if ((sdActive == 1) && sdWriteSectorDMAPoll(i == (totalSDSectors - 1)))\r
{\r
sdActive = 0;\r
i++;\r
sdActive = 1;\r
}\r
\r
+ uint32_t now = getTime_ms();\r
+\r
if ((scsiActive == 1) && scsiReadDMAPoll())\r
{\r
scsiActive = 0;\r
++prep;\r
- lastActivityTime = getTime_ms();\r
+ lastActivityTime = now;\r
}\r
else if ((scsiActive == 0) &&\r
((prep - i) < buffers) &&\r
(scsiActive == 0) &&\r
!scsiDisconnected &&\r
scsiDev.discPriv &&\r
- (diffTime_ms(lastActivityTime, getTime_ms()) >= 20) &&\r
+ (diffTime_ms(lastActivityTime, now) >= 20) &&\r
(scsiDev.phase == DATA_OUT))\r
{\r
// We're transferring over the SCSI bus faster than the SD card\r
(prep == i) || // Buffers empty.\r
// Send some messages every 100ms so we don't timeout.\r
// At a minimum, a reselection involves an IDENTIFY message.\r
- (diffTime_ms(lastActivityTime, getTime_ms()) >= 100)\r
+ (diffTime_ms(lastActivityTime, now) >= 100)\r
))\r
{\r
int reconnected = scsiReconnect();\r
scsiDev.resetFlag = 1;\r
}\r
}\r
+ else if (\r
+ !scsiComplete &&\r
+ (sdActive == 1) &&\r
+ (prep == totalSDSectors) && // All scsi data read and buffered\r
+ !scsiDev.discPriv && // Prefer disconnect where possible.\r
+ (diffTime_ms(lastActivityTime, now) >= 150) &&\r
+\r
+ (scsiDev.phase == DATA_OUT) &&\r
+ !(scsiDev.cdb[scsiDev.cdbLen - 1] & 0x01) // Not linked command\r
+ )\r
+ {\r
+ // We're transferring over the SCSI bus faster than the SD card\r
+ // can write. All data is buffered, and we're just waiting for\r
+ // the SD card to complete. The host won't let us disconnect.\r
+ // Some drivers set a 250ms timeout on transfers to complete.\r
+ // SD card writes are supposed to complete\r
+ // within 200ms, but sometimes they don'to.\r
+ // Just pretend we're finished.\r
+ scsiComplete = 1;\r
+\r
+ process_Status();\r
+ process_MessageIn(); // Will go to BUS_FREE state\r
+\r
+ // Try and prevent anyone else using the SCSI bus while we're not ready.\r
+ SCSI_SetPin(SCSI_Out_BSY); \r
+ }\r
}\r
\r
+ if (scsiComplete)\r
+ {\r
+ SCSI_ClearPin(SCSI_Out_BSY);\r
+ }\r
while (\r
!scsiDev.resetFlag &&\r
scsiDisconnected &&\r
}\r
scsiDiskReset();\r
}\r
+ debugResume(); // TODO comment re. timeouts.\r
}\r
\r
void scsiDiskReset()\r
}\r
transfer.inProgress = 0;\r
transfer.multiBlock = 0;\r
+ // SD_CS_Write(1);\r
+\r
}\r
\r
void scsiDiskInit()\r
\r
const char* Notice = "Copyright (C) 2014 Michael McMaster <michael@codesrc.com>";\r
\r
+uint8_t testData[512];\r
+\r
int main()\r
{\r
timeInit();\r
\r
scsiInit();\r
scsiDiskInit();\r
- \r
+\r
uint32_t lastSDPoll = getTime_ms();\r
sdPoll();\r
- \r
+\r
+\r
+\r
+\r
while (1)\r
{\r
scsiDev.watchdogTick++;\r
scsiPoll();\r
scsiDiskPoll();\r
configPoll();\r
- \r
+\r
uint32_t now = getTime_ms();\r
if (diffTime_ms(lastSDPoll, now) > 200)\r
{\r
static void process_SelectionPhase(void);\r
static void enter_BusFree(void);\r
static void enter_MessageIn(uint8 message);\r
-static void process_MessageIn(void);\r
static void enter_Status(uint8 status);\r
-static void process_Status(void);\r
static void enter_DataIn(int len);\r
static void process_DataIn(void);\r
static void process_DataOut(void);\r
scsiDev.phase = MESSAGE_IN;\r
}\r
\r
-static void process_MessageIn()\r
+void process_MessageIn()\r
{\r
scsiEnterPhase(MESSAGE_IN);\r
scsiWriteByte(scsiDev.msgIn);\r
\r
scsiDev.lastStatus = scsiDev.status;\r
scsiDev.lastSense = scsiDev.target->sense.code;\r
+ scsiDev.lastSenseASC = scsiDev.target->sense.asc;\r
}\r
\r
-static void process_Status()\r
+void process_Status()\r
{\r
scsiEnterPhase(STATUS);\r
\r
\r
scsiDev.lastStatus = scsiDev.status;\r
scsiDev.lastSense = scsiDev.target->sense.code;\r
+ scsiDev.lastSenseASC = scsiDev.target->sense.asc;\r
+\r
\r
// Command Complete occurs AFTER a valid status has been\r
// sent. then we go bus-free.\r
// There is no guarantee that the RST line will be negated by then.\r
// NOTE: We could be connected and powered by USB for configuration,\r
// in which case TERMPWR cannot be supplied, and reset will ALWAYS\r
- // be true.\r
- CyDelay(10); // 10ms.\r
+ // be true. Therefore, the sleep here must be slow to avoid slowing\r
+ // USB comms\r
+ CyDelay(1); // 1ms.\r
}\r
\r
static void enter_SelectionPhase()\r
int phase;
- uint8 data[MAX_SECTOR_SIZE];
+ uint8 data[MAX_SECTOR_SIZE * 2];
int dataPtr; // Index into data, reset on [re]selection to savedDataPtr
int savedDataPtr; // Index into data, initially 0.
int dataLen;
uint8 watchdogTick;
uint8 lastStatus;
uint8 lastSense;
+ uint16_t lastSenseASC;
} ScsiDevice;
extern ScsiDevice scsiDev;
+void process_Status(void);
+void process_MessageIn(void);
+
void scsiInit(void);
void scsiPoll(void);
void scsiDisconnect(void);
// Global\r
SdDevice sdDev;\r
\r
+enum SD_IO_STATE { SD_DMA, SD_ACCEPTED, SD_BUSY, SD_IDLE };\r
+static int sdIOState = SD_IDLE;\r
+\r
// Private DMA variables.\r
-static int dmaInProgress = 0;\r
static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL;\r
static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL;\r
\r
// DMA descriptors\r
static uint8 sdDMARxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };\r
-static uint8 sdDMATxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };\r
+static uint8 sdDMATxTd[3] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };\r
\r
// Dummy location for DMA to send unchecked CRC bytes to\r
static uint8 discardBuffer;\r
\r
+// 2 bytes CRC, response, 8bits to close the clock..\r
+// "NCR" time is up to 8 bytes.\r
+static uint8_t writeResponseBuffer[8];\r
+\r
+static uint8_t writeStartToken = 0xFC;\r
+\r
// Source of dummy SPI bytes for DMA\r
static uint8 dummyBuffer = 0xFF;\r
\r
}\r
\r
// Read and write 1 byte.\r
-static uint8 sdSpiByte(uint8 value)\r
+static uint8_t sdSpiByte(uint8_t value)\r
{\r
SDCard_WriteTxData(value);\r
while (!(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)) {}\r
return SDCard_ReadRxData();\r
}\r
\r
-static void sdSendCRCCommand(uint8 cmd, uint32 param)\r
+static uint16_t sdDoCommand(\r
+ uint8_t cmd,\r
+ uint32_t param,\r
+ int useCRC,\r
+ int use2byteResponse)\r
{\r
- uint8 send[6];\r
+ uint8_t send[7];\r
\r
send[0] = cmd | 0x40;\r
send[1] = param >> 24;\r
send[2] = param >> 16;\r
send[3] = param >> 8;\r
send[4] = param;\r
- send[5] = (sdCrc7(send, 5, 0) << 1) | 1;\r
-\r
- for(cmd = 0; cmd < sizeof(send); cmd++)\r
+ if (useCRC)\r
{\r
- sdSpiByte(send[cmd]);\r
+ send[5] = (sdCrc7(send, 5, 0) << 1) | 1;\r
}\r
- // Allow command to process before reading result code.\r
- sdSpiByte(0xFF);\r
-}\r
+ else\r
+ {\r
+ send[5] = 1; // stop bit\r
+ }\r
+ send[6] = 0xFF; // Result code or stuff byte.\r
\r
-static void sdSendCommand(uint8 cmd, uint32 param)\r
-{\r
- uint8 send[6];\r
+ CyDmaTdSetConfiguration(sdDMATxTd[0], sizeof(send), CY_DMA_DISABLE_TD, TD_INC_SRC_ADR|SD_TX_DMA__TD_TERMOUT_EN);\r
+ CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&send), LO16((uint32)SDCard_TXDATA_PTR));\r
+ CyDmaTdSetConfiguration(sdDMARxTd[0], sizeof(send), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);\r
+ CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
+ // The DMA controller is a bit trigger-happy. It will retain\r
+ // a drq request that was triggered while the channel was\r
+ // disabled.\r
+ CyDmaClearPendingDrq(sdDMATxChan);\r
+ CyDmaClearPendingDrq(sdDMARxChan);\r
\r
- send[0] = cmd | 0x40;\r
- send[1] = param >> 24;\r
- send[2] = param >> 16;\r
- send[3] = param >> 8;\r
- send[4] = param;\r
- send[5] = 1; // 7:1 CRC, 0: Stop bit.\r
+ txDMAComplete = 0;\r
+ rxDMAComplete = 0;\r
\r
- for(cmd = 0; cmd < sizeof(send); cmd++)\r
+ CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);\r
+ CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);\r
+\r
+ // There is no flow control, so we must ensure we can read the bytes\r
+ // before we start transmitting\r
+ CyDmaChEnable(sdDMARxChan, 1);\r
+ CyDmaChEnable(sdDMATxChan, 1);\r
+\r
+ while (!(txDMAComplete && rxDMAComplete)) {}\r
+\r
+ uint16_t response = discardBuffer;\r
+ if (cmd == SD_STOP_TRANSMISSION)\r
{\r
- sdSpiByte(send[cmd]);\r
+ // Stuff byte is required for this command only.\r
+ // Part 1 Simplified standard 3.01\r
+ // "The stop command has an execution delay due to the serial command\r
+ // transmission."\r
+ response = sdSpiByte(0xFF);\r
}\r
- // Allow command to process before reading result code.\r
- sdSpiByte(0xFF);\r
-}\r
\r
-static uint8 sdReadResp()\r
-{\r
- uint8 v;\r
- uint8 i = 128;\r
- do\r
+ uint32_t start = getTime_ms();\r
+ while ((response & 0x80) && (diffTime_ms(start, getTime_ms()) <= 200))\r
+ {\r
+ response = sdSpiByte(0xFF);\r
+ }\r
+ if (use2byteResponse)\r
{\r
- v = sdSpiByte(0xFF);\r
- } while(i-- && (v & 0x80));\r
- return v;\r
+ response = (response << 8) | sdSpiByte(0xFF);\r
+ }\r
+ return response;\r
}\r
\r
-static uint8 sdCommandAndResponse(uint8 cmd, uint32 param)\r
+\r
+static uint16_t sdCommandAndResponse(uint8_t cmd, uint32_t param)\r
{\r
- sdSpiByte(0xFF);\r
- sdSendCommand(cmd, param);\r
- return sdReadResp();\r
+ // Some Samsung cards enter a busy-state after single-sector reads.\r
+ // But we also need to wait for R1B to complete from the multi-sector\r
+ // reads.\r
+ while (sdSpiByte(0xFF) == 0x00) {}\r
+ return sdDoCommand(cmd, param, 0, 0);\r
}\r
\r
-static uint8 sdCRCCommandAndResponse(uint8 cmd, uint32 param)\r
+static uint16_t sdCRCCommandAndResponse(uint8_t cmd, uint32_t param)\r
{\r
- sdSpiByte(0xFF);\r
- sdSendCRCCommand(cmd, param);\r
- return sdReadResp();\r
+ // Some Samsung cards enter a busy-state after single-sector reads.\r
+ // But we also need to wait for R1B to complete from the multi-sector\r
+ // reads.\r
+ while (sdSpiByte(0xFF) == 0x00) {}\r
+ return sdDoCommand(cmd, param, 1, 0);\r
}\r
\r
// Clear the sticky status bits on error.\r
static void sdClearStatus()\r
{\r
- uint8 r2hi = sdCRCCommandAndResponse(SD_SEND_STATUS, 0);\r
- uint8 r2lo = sdSpiByte(0xFF);\r
- (void) r2hi; (void) r2lo;\r
+ sdSpiByte(0xFF);\r
+ uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 1, 1);\r
+ (void) r2;\r
}\r
\r
-\r
void\r
sdReadMultiSectorPrep()\r
{\r
\r
scsiDev.status = CHECK_CONDITION;\r
scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE;\r
scsiDev.phase = STATUS;\r
}\r
else\r
dmaReadSector(uint8_t* outputBuffer)\r
{\r
// Wait for a start-block token.\r
- // Don't wait more than 200ms.\r
- // The standard recommends 100ms.\r
+ // Don't wait more than 200ms. The standard recommends 100ms.\r
uint32_t start = getTime_ms();\r
- uint8 token = sdSpiByte(0xFF);\r
+ uint8_t token = sdSpiByte(0xFF);\r
while (token != 0xFE && (diffTime_ms(start, getTime_ms()) <= 200))\r
{\r
+ if (token && ((token & 0xE0) == 0))\r
+ {\r
+ // Error token!\r
+ break;\r
+ }\r
token = sdSpiByte(0xFF);\r
}\r
if (token != 0xFE)\r
{\r
scsiDev.status = CHECK_CONDITION;\r
scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;\r
+ scsiDev.target->sense.asc = 0x4400 | token;\r
scsiDev.phase = STATUS;\r
}\r
+ sdClearStatus();\r
return;\r
}\r
\r
CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
\r
- dmaInProgress = 1;\r
- // The DMA controller is a bit trigger-happy. It will retain\r
- // a drq request that was triggered while the channel was\r
- // disabled.\r
- CyDmaClearPendingDrq(sdDMATxChan);\r
- CyDmaClearPendingDrq(sdDMARxChan);\r
-\r
+ sdIOState = SD_DMA;\r
txDMAComplete = 0;\r
rxDMAComplete = 0;\r
\r
CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);\r
CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);\r
\r
+ // The DMA controller is a bit trigger-happy. It will retain\r
+ // a drq request that was triggered while the channel was\r
+ // disabled.\r
+ CyDmaClearPendingDrq(sdDMATxChan);\r
+ CyDmaClearPendingDrq(sdDMARxChan);\r
+\r
// There is no flow control, so we must ensure we can read the bytes\r
// before we start transmitting\r
CyDmaChEnable(sdDMARxChan, 1);\r
if (rxDMAComplete && txDMAComplete)\r
{\r
// DMA transfer is complete\r
- dmaInProgress = 0;\r
+ sdIOState = SD_IDLE;\r
return 1;\r
}\r
else\r
\r
scsiDev.status = CHECK_CONDITION;\r
scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.target->sense.asc = LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION;\r
scsiDev.phase = STATUS;\r
}\r
else\r
\r
void sdCompleteRead()\r
{\r
- if (dmaInProgress)\r
+ if (sdIOState != SD_IDLE)\r
{\r
// Not much choice but to wait until we've completed the transfer.\r
// Cancelling the transfer can't be done as we have no way to reset\r
// the SD card.\r
while (!sdReadSectorDMAPoll()) { /* spin */ }\r
}\r
-\r
transfer.inProgress = 0;\r
\r
// We cannot send even a single "padding" byte, as we normally would when\r
// an error condition as we're trying to read past-the-end of the storage\r
// device.\r
// ie. do not use sdCommandAndResponse here.\r
- uint8 r1b;\r
- sdSendCommand(SD_STOP_TRANSMISSION, 0);\r
- r1b = sdReadResp();\r
+ uint8 r1b = sdDoCommand(SD_STOP_TRANSMISSION, 0, 0, 0);\r
\r
if (r1b)\r
{\r
- // Try very hard to make sure the transmission stops\r
- int retries = 255;\r
- while (r1b && retries)\r
- {\r
- r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0);\r
- retries--;\r
- }\r
-\r
scsiDev.status = CHECK_CONDITION;\r
scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;\r
+ scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR | r1b;\r
scsiDev.phase = STATUS;\r
}\r
\r
- // R1b has an optional trailing "busy" signal.\r
- {\r
- uint8 busy;\r
- do\r
- {\r
- busy = sdSpiByte(0xFF);\r
- } while (busy == 0);\r
- }\r
+ // R1b has an optional trailing "busy" signal, but we defer waiting on this.\r
+ // The next call so sdCommandAndResponse will wait for the busy state to\r
+ // clear.\r
}\r
\r
static void sdWaitWriteBusy()\r
void\r
sdWriteMultiSectorDMA(uint8_t* outputBuffer)\r
{\r
- sdSpiByte(0xFC); // MULTIPLE byte start token\r
+ // Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte\r
+ // We need to do this without stopping the clock\r
+ CyDmaTdSetConfiguration(sdDMATxTd[0], 1, sdDMATxTd[1], TD_INC_SRC_ADR);\r
+ CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR));\r
\r
- // Transmit 512 bytes of data and then 2 bytes CRC.\r
- CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE, sdDMATxTd[1], TD_INC_SRC_ADR);\r
- CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
- CyDmaTdSetConfiguration(sdDMATxTd[1], 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
- CyDmaTdSetAddress(sdDMATxTd[1], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
+ CyDmaTdSetConfiguration(sdDMATxTd[1], SD_SECTOR_SIZE, sdDMATxTd[2], TD_INC_SRC_ADR);\r
+ CyDmaTdSetAddress(sdDMATxTd[1], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
\r
- CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);\r
- CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
+ CyDmaTdSetConfiguration(sdDMATxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
+ CyDmaTdSetAddress(sdDMATxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
\r
+ CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE + 3, sdDMARxTd[1], 0);\r
+ CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
+ CyDmaTdSetConfiguration(sdDMARxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR);\r
+ CyDmaTdSetAddress(sdDMARxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer));\r
\r
- dmaInProgress = 1;\r
+ sdIOState = SD_DMA;\r
// The DMA controller is a bit trigger-happy. It will retain\r
// a drq request that was triggered while the channel was\r
// disabled.\r
}\r
\r
int\r
-sdWriteSectorDMAPoll()\r
+sdWriteSectorDMAPoll(int sendStopToken)\r
{\r
if (rxDMAComplete && txDMAComplete)\r
{\r
- uint8_t dataToken = sdSpiByte(0xFF); // Response\r
- if (dataToken == 0x0FF)\r
+ if (sdIOState == SD_DMA)\r
{\r
- return 0; // Write has not completed.\r
- }\r
- else if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted.\r
- {\r
- uint8 r1b, busy;\r
- \r
- sdWaitWriteBusy();\r
-\r
- r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0);\r
- (void) r1b;\r
- sdSpiByte(0xFF);\r
-\r
- // R1b has an optional trailing "busy" signal.\r
+ // Retry a few times. The data token format is:\r
+ // XXX0AAA1\r
+ int i = 0;\r
+ uint8_t dataToken;\r
do\r
{\r
- busy = sdSpiByte(0xFF);\r
- } while (busy == 0);\r
+ dataToken = writeResponseBuffer[i]; // Response\r
+ ++i;\r
+ } while (((dataToken & 0x0101) != 1) && (i < sizeof(writeResponseBuffer)));\r
+\r
+ // At this point we should either have an accepted token, or we'll\r
+ // timeout and proceed into the error case below.\r
+ if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted.\r
+ {\r
+ sdIOState = SD_IDLE;\r
\r
- // Wait for the card to come out of busy.\r
- sdWaitWriteBusy();\r
+ sdWaitWriteBusy();\r
+ sdSpiByte(0xFD); // STOP TOKEN\r
+ sdWaitWriteBusy();\r
\r
- transfer.inProgress = 0;\r
- scsiDiskReset();\r
- sdClearStatus();\r
+ transfer.inProgress = 0;\r
+ scsiDiskReset();\r
+ sdClearStatus();\r
\r
- scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
- scsiDev.phase = STATUS;\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.target->sense.code = HARDWARE_ERROR;\r
+ scsiDev.target->sense.asc = 0x6900 | dataToken;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else\r
+ {\r
+ sdIOState = SD_ACCEPTED;\r
+ }\r
}\r
- else\r
+\r
+ if (sdIOState == SD_ACCEPTED)\r
{\r
- sdWaitWriteBusy();\r
+ // Wait while the SD card is busy\r
+ if (sdSpiByte(0xFF) == 0xFF)\r
+ {\r
+ if (sendStopToken)\r
+ {\r
+ sdIOState = SD_BUSY;\r
+ transfer.inProgress = 0;\r
+\r
+ sdSpiByte(0xFD); // STOP TOKEN\r
+ }\r
+ else\r
+ {\r
+ sdIOState = SD_IDLE;\r
+ }\r
+ }\r
}\r
- // DMA transfer is complete and the SD card has accepted the write.\r
- dmaInProgress = 0;\r
\r
- return 1;\r
+ if (sdIOState == SD_BUSY)\r
+ {\r
+ // Wait while the SD card is busy\r
+ if (sdSpiByte(0xFF) == 0xFF)\r
+ {\r
+ sdIOState = SD_IDLE;\r
+ }\r
+ }\r
+\r
+ return sdIOState == SD_IDLE;\r
}\r
else\r
{\r
\r
void sdCompleteWrite()\r
{\r
- if (dmaInProgress)\r
+ if (sdIOState != SD_IDLE)\r
{\r
// Not much choice but to wait until we've completed the transfer.\r
// Cancelling the transfer can't be done as we have no way to reset\r
// the SD card.\r
- while (!sdWriteSectorDMAPoll()) { /* spin */ }\r
+ while (!sdWriteSectorDMAPoll(1)) { /* spin */ }\r
}\r
- \r
- transfer.inProgress = 0;\r
\r
- uint8 r1, r2;\r
-\r
- sdSpiByte(0xFD); // STOP TOKEN\r
- // Wait for the card to come out of busy.\r
- sdWaitWriteBusy();\r
+ transfer.inProgress = 0;\r
\r
- r1 = sdCommandAndResponse(13, 0); // send status\r
- r2 = sdSpiByte(0xFF);\r
- if (r1 || r2)\r
+ if (scsiDev.phase == DATA_OUT)\r
{\r
- sdClearStatus();\r
- scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED;\r
- scsiDev.phase = STATUS;\r
+ sdSpiByte(0xFF);\r
+ uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 0, 1);\r
+ if (r2)\r
+ {\r
+ sdClearStatus();\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.target->sense.code = HARDWARE_ERROR;\r
+ scsiDev.target->sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED;\r
+ scsiDev.phase = STATUS;\r
+ }\r
}\r
}\r
\r
uint32_t start = getTime_ms();\r
int complete;\r
uint8 status;\r
- \r
+\r
do\r
{\r
uint8 buf[4];\r
return (status == 0) && complete;\r
}\r
\r
+static void sdReadCID()\r
+{\r
+ uint8 startToken;\r
+ int maxWait, i;\r
+\r
+ uint8 status = sdCRCCommandAndResponse(SD_SEND_CID, 0);\r
+ if(status){return;}\r
+\r
+ maxWait = 1023;\r
+ do\r
+ {\r
+ startToken = sdSpiByte(0xFF);\r
+ } while(maxWait-- && (startToken != 0xFE));\r
+ if (startToken != 0xFE) { return; }\r
+\r
+ for (i = 0; i < 16; ++i)\r
+ {\r
+ sdDev.cid[i] = sdSpiByte(0xFF);\r
+ }\r
+ sdSpiByte(0xFF); // CRC\r
+ sdSpiByte(0xFF); // CRC\r
+}\r
+\r
static int sdReadCSD()\r
{\r
uint8 startToken;\r
int maxWait, i;\r
- uint8 buf[16];\r
\r
uint8 status = sdCRCCommandAndResponse(SD_SEND_CSD, 0);\r
if(status){goto bad;}\r
\r
for (i = 0; i < 16; ++i)\r
{\r
- buf[i] = sdSpiByte(0xFF);\r
+ sdDev.csd[i] = sdSpiByte(0xFF);\r
}\r
sdSpiByte(0xFF); // CRC\r
sdSpiByte(0xFF); // CRC\r
\r
- if ((buf[0] >> 6) == 0x00)\r
+ if ((sdDev.csd[0] >> 6) == 0x00)\r
{\r
// CSD version 1\r
// C_SIZE in bits [73:62]\r
- uint32 c_size = (((((uint32)buf[6]) & 0x3) << 16) | (((uint32)buf[7]) << 8) | buf[8]) >> 6;\r
- uint32 c_mult = (((((uint32)buf[9]) & 0x3) << 8) | ((uint32)buf[0xa])) >> 7;\r
- uint32 sectorSize = buf[5] & 0x0F;\r
+ uint32 c_size = (((((uint32)sdDev.csd[6]) & 0x3) << 16) | (((uint32)sdDev.csd[7]) << 8) | sdDev.csd[8]) >> 6;\r
+ uint32 c_mult = (((((uint32)sdDev.csd[9]) & 0x3) << 8) | ((uint32)sdDev.csd[0xa])) >> 7;\r
+ uint32 sectorSize = sdDev.csd[5] & 0x0F;\r
sdDev.capacity = ((c_size+1) * ((uint64)1 << (c_mult+2)) * ((uint64)1 << sectorSize)) / SD_SECTOR_SIZE;\r
}\r
- else if ((buf[0] >> 6) == 0x01)\r
+ else if ((sdDev.csd[0] >> 6) == 0x01)\r
{\r
// CSD version 2\r
// C_SIZE in bits [69:48]\r
\r
uint32 c_size =\r
- ((((uint32)buf[7]) & 0x3F) << 16) |\r
- (((uint32)buf[8]) << 8) |\r
- ((uint32)buf[7]);\r
+ ((((uint32)sdDev.csd[7]) & 0x3F) << 16) |\r
+ (((uint32)sdDev.csd[8]) << 8) |\r
+ ((uint32)sdDev.csd[7]);\r
sdDev.capacity = (c_size + 1) * 1024;\r
}\r
else\r
sdDMARxTd[1] = CyDmaTdAllocate();\r
sdDMATxTd[0] = CyDmaTdAllocate();\r
sdDMATxTd[1] = CyDmaTdAllocate();\r
+ sdDMATxTd[2] = CyDmaTdAllocate();\r
\r
SD_RX_DMA_COMPLETE_StartEx(sdRxISR);\r
SD_TX_DMA_COMPLETE_StartEx(sdTxISR);\r
sdDev.version = 0;\r
sdDev.ccs = 0;\r
sdDev.capacity = 0;\r
+ memset(sdDev.csd, 0, sizeof(sdDev.csd));\r
+ memset(sdDev.cid, 0, sizeof(sdDev.cid));\r
\r
sdInitDMA();\r
\r
SD_CS_Write(0); // Set CS active (active low)\r
CyDelayUs(1);\r
\r
- v = sdCRCCommandAndResponse(SD_GO_IDLE_STATE, 0);\r
+ sdSpiByte(0xFF);\r
+ v = sdDoCommand(SD_GO_IDLE_STATE, 0, 1, 0);\r
if(v != 1){goto bad;}\r
\r
ledOn();\r
SDCard_ClearFIFO();\r
\r
if (!sdReadCSD()) goto bad;\r
+ sdReadCID();\r
\r
result = 1;\r
goto out;\r
void sdWriteMultiSectorPrep()\r
{\r
uint8 v;\r
- \r
+\r
// Set the number of blocks to pre-erase by the multiple block write command\r
// We don't care about the response - if the command is not accepted, writes\r
// will just be a bit slower.\r
{\r
sdLBA = sdLBA * SD_SECTOR_SIZE;\r
}\r
- v = sdCommandAndResponse(25, sdLBA);\r
+ v = sdCommandAndResponse(SD_WRITE_MULTIPLE_BLOCK, sdLBA);\r
if (v)\r
{\r
scsiDiskReset();\r
sdClearStatus();\r
scsiDev.status = CHECK_CONDITION;\r
scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.target->sense.asc = 0x8800 | v;\r
scsiDev.phase = STATUS;\r
}\r
else\r
{\r
// Check if there's an SD card present.\r
if ((scsiDev.phase == BUS_FREE) &&\r
- !dmaInProgress)\r
+ (sdIOState == SD_IDLE))\r
{\r
// The CS line is pulled high by the SD card.\r
// De-assert the line, and check if it's high.\r
SD_SEND_OP_COND = 1,
SD_SEND_IF_COND = 8, // SD V2
SD_SEND_CSD = 9,
+ SD_SEND_CID = 10,
SD_STOP_TRANSMISSION = 12,
SD_SEND_STATUS = 13,
SD_SET_BLOCKLEN = 16,
SD_READ_SINGLE_BLOCK = 17,
SD_READ_MULTIPLE_BLOCK = 18,
SD_APP_SET_WR_BLK_ERASE_COUNT = 23,
+ SD_WRITE_MULTIPLE_BLOCK = 25,
SD_APP_SEND_OP_COND = 41,
SD_APP_CMD = 55,
SD_READ_OCR = 58,
int version; // SDHC = version 2.
int ccs; // Card Capacity Status. 1 = SDHC or SDXC
uint32 capacity; // in 512 byte blocks
+
+ uint8_t csd[16]; // Unparsed CSD
+ uint8_t cid[16]; // Unparsed CID
} SdDevice;
extern SdDevice sdDev;
void sdWriteMultiSectorPrep(void);
void sdWriteMultiSectorDMA(uint8_t* outputBuffer);
-int sdWriteSectorDMAPoll();
+int sdWriteSectorDMAPoll(int sendStopToken);
void sdCompleteWrite(void);
void sdReadMultiSectorPrep(void);
/*******************************************************************************\r
* File Name: Bootloadable_1.c\r
-* Version 1.20\r
+* Version 1.30\r
*\r
* Description:\r
* Provides an API for the Bootloadable application. The API includes a\r
-* single function for starting bootloader.\r
+* single function for starting the bootloader.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
* Function Name: Bootloadable_1_Load\r
********************************************************************************\r
* Summary:\r
-* Begins the bootloading algorithm, downloading a new ACD image from the host.\r
+* Begins the bootloading algorithm downloading a new ACD image from the host.\r
*\r
* Parameters:\r
* None\r
\r
\r
/*******************************************************************************\r
-* Function Name: Bootloadable_1_SetFlashByte\r
-********************************************************************************\r
-* Summary:\r
-* Sets byte at specified address in Flash.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* None\r
-*\r
+* The following code is OBSOLETE and must not be used.\r
*******************************************************************************/\r
void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) \r
{\r
uint32 flsAddr = address - CYDEV_FLASH_BASE;\r
- uint8 rowData[CYDEV_FLS_ROW_SIZE];\r
+ uint8 rowData[CYDEV_FLS_ROW_SIZE];\r
\r
#if !(CY_PSOC4)\r
- uint8 arrayId = (uint8)(flsAddr / CYDEV_FLS_SECTOR_SIZE);\r
+ uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);\r
#endif /* !(CY_PSOC4) */\r
\r
- uint16 rowNum = (uint16)((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);\r
+ #if (CY_PSOC4)\r
+ uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);\r
+ #else\r
+ uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);\r
+ #endif /* (CY_PSOC4) */\r
+\r
uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);\r
uint16 idx;\r
\r
}\r
rowData[address % CYDEV_FLS_ROW_SIZE] = runType;\r
\r
-\r
#if(CY_PSOC4)\r
- (void) CySysFlashWriteRow((uint32)rowNum, rowData);\r
+ (void) CySysFlashWriteRow((uint32) rowNum, rowData);\r
#else\r
(void) CyWriteRowData(arrayId, rowNum, rowData);\r
#endif /* (CY_PSOC4) */\r
+\r
+ #if(CY_PSOC5)\r
+ /***************************************************************************\r
+ * When writing Flash, data in the instruction cache can become stale.\r
+ * Therefore, the cache data does not correlate to the data just written to\r
+ * Flash. A call to CyFlushCache() is required to invalidate the data in the\r
+ * cache and force fresh information to be loaded from Flash.\r
+ ***************************************************************************/\r
+ CyFlushCache();\r
+ #endif /* (CY_PSOC5) */\r
}\r
\r
\r
/*******************************************************************************\r
* File Name: Bootloadable_1.h\r
-* Version 1.20\r
+* Version 1.30\r
*\r
* Description:\r
* Provides an API for the Bootloadable application. The API includes a\r
* single function for starting bootloader.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5LP are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5LP)\r
- #error Component Bootloadable_v1_20 requires cy_boot v3.0 or later\r
+ #error Component Bootloadable_v1_30 requires cy_boot v3.0 or later\r
#endif /* !defined (CY_PSOC5LP) */\r
\r
\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from version 1.10\r
+* The following code is OBSOLETE and must not be used starting from version 1.10\r
*******************************************************************************/\r
#define CYBTDLR_SET_RUN_TYPE(x) Bootloadable_1_SET_RUN_TYPE(x)\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from version 1.20\r
+* The following code is OBSOLETE and must not be used starting from version 1.20\r
*******************************************************************************/\r
#define Bootloadable_1_START_APP (0x80u)\r
#define Bootloadable_1_START_BTLDR (0x40u)\r
#define Bootloadable_1_SetFlashRunType(runType) \\r
Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType))\r
\r
-void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;\r
\r
+/*******************************************************************************\r
+* The following code is OBSOLETE and must not be used.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
+*******************************************************************************/\r
+void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;\r
#if(CY_PSOC4)\r
- #define Bootloadable_1_SOFTWARE_RESET CY_SET_REG32(CYREG_CM0_AIRCR, 0x05FA0004u)\r
+ #define Bootloadable_1_SOFTWARE_RESET CySoftwareReset()\r
#else\r
- #define Bootloadable_1_SOFTWARE_RESET CY_SET_REG8(CYREG_RESET_CR2, 0x01u)\r
+ #define Bootloadable_1_SOFTWARE_RESET CySoftwareReset()\r
#endif /* (CY_PSOC4) */\r
\r
#if(CY_PSOC4)\r
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2);\r
define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (32768 / 2) - 1;\r
/*-Sizes-*/\r
-define symbol __ICFEDIT_size_cstack__ = 0x2000;\r
+define symbol __ICFEDIT_size_cstack__ = 0x1000;\r
define symbol __ICFEDIT_size_heap__ = 0x0400;\r
/**** End of ICF editor section. ###ICF###*/\r
\r
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
define block HSTACK {block HEAP, last block CSTACK};\r
\r
+if (CY_APPL_LOADABLE)\r
+{\r
define block LOADER { readonly section .cybootloader };\r
+}\r
define block APPL with fixed order {readonly section .romvectors, readonly};\r
\r
/* The address of Flash row next after Bootloader image */\r
do not initialize { readwrite section .ramvectors };\r
\r
/******** Placements *********/\r
+if (CY_APPL_LOADABLE)\r
+{\r
".cybootloader" : place at start of ROM_region {block LOADER};\r
+}\r
+\r
"APPL" : place at start of APPL_region {block APPL};\r
\r
"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors };\r
section .cymeta };\r
\r
".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };\r
+if (CY_APPL_LOADABLE)\r
+{\r
".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };\r
+}\r
".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };\r
".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl };\r
".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch };\r
\r
;********************************************************************************\r
;* File Name: Cm3RealView.scat\r
-;* Version 4.0\r
+;* Version 4.20\r
;*\r
;* Description:\r
;* This Linker Descriptor file describes the memory layout of the PSoC5\r
;*\r
;* Note:\r
;*\r
-;* romvectors: Cypress default Interrupt sevice routine vector table.\r
+;* romvectors: Cypress default Interrupt service routine vector table.\r
;*\r
;* This is the ISR vector table at bootup. Used only for the reset vector.\r
;*\r
;*\r
;*\r
;********************************************************************************\r
-;* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+;* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
;* You may use this file only in accordance with the license, terms, conditions,\r
;* disclaimers, and limitations in the end user license agreement accompanying\r
;* the software package with which this file was provided.\r
.ANY (+RW, +ZI)\r
}\r
\r
- ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x2000) EMPTY 0x0400\r
+ ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x1000) EMPTY 0x0400\r
{\r
}\r
\r
- ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x2000\r
+ ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x1000\r
{\r
}\r
}\r
/*******************************************************************************\r
* File Name: Cm3Start.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Startup code for the ARM CM3.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
extern void __iar_data_init3 (void);\r
#endif /* (__ARMCC_VERSION) */\r
\r
+#if defined(__GNUC__)\r
+ #include <errno.h>\r
+ extern int errno;\r
+ extern int end;\r
+#endif /* defined(__GNUC__) */\r
+\r
/* Global variables */\r
#if !defined (__ICCARM__)\r
CY_NOINIT static uint32 cySysNoInitDataValid;\r
********************************************************************************\r
*\r
* Summary:\r
-* This function is called for all interrupts, other than reset, that get\r
+* This function is called for all interrupts, other than a reset that gets\r
* called before the system is setup.\r
*\r
* Parameters:\r
while(1)\r
{\r
/***********************************************************************\r
- * We should never get here. If we do, a serious problem occured, so go\r
+ * We must not get here. If we do, a serious problem occurs, so go\r
* into an infinite loop.\r
***********************************************************************/\r
}\r
\r
#if defined(__ARMCC_VERSION)\r
\r
-/* Local function for the device reset. */\r
+/* Local function for device reset. */\r
extern void Reset(void);\r
\r
/* Application entry point. */\r
********************************************************************************\r
*\r
* Summary:\r
-* This function is called imediatly before the users main\r
+* This function is called immediately before the users main\r
*\r
* Parameters:\r
* None\r
\r
while (1)\r
{\r
- /* If main returns it is undefined what we should do. */\r
+ /* If main returns, it is undefined what we should do. */\r
}\r
}\r
\r
/* Application entry point. */\r
extern int main(void);\r
\r
-/* The static objects constructors initializer */\r
+/* Static objects constructors initializer */\r
extern void __libc_init_array(void);\r
\r
typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));\r
#define __cy_region_num ((size_t)&__cy_region_num)\r
\r
\r
+/*******************************************************************************\r
+* System Calls of the Red Hat newlib C Library\r
+*******************************************************************************/\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: _exit\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Exit a program without cleaning up files. If your system doesn't provide\r
+* this, it is best to avoid linking with subroutines that require it (exit,\r
+* system).\r
+*\r
+* Parameters:\r
+* status: Status caused program exit.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+__attribute__((weak))\r
+void _exit(int status)\r
+{\r
+ /* Cause divide by 0 exception */\r
+ int x = status / (int) INT_MAX;\r
+ x = 4 / x;\r
+\r
+ while(1)\r
+ {\r
+\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: _sbrk\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Increase program data space. As malloc and related functions depend on this,\r
+* it is useful to have a working implementation. The following suffices for a\r
+* standalone system; it exploits the symbol end automatically defined by the\r
+* GNU linker.\r
+*\r
+* Parameters:\r
+* nbytes: The number of bytes requested (if the parameter value is positive)\r
+* from the heap or returned back to the heap (if the parameter value is\r
+* negative).\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+__attribute__((weak))\r
+void * _sbrk (int nbytes)\r
+{\r
+ extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). */\r
+ void * returnValue;\r
+\r
+ /* The statically held previous end of the heap, with its initialization. */\r
+ static void *heapPointer = (void *) &end; /* Previous end */\r
+\r
+ if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE)\r
+ {\r
+ returnValue = heapPointer;\r
+ heapPointer += nbytes;\r
+ }\r
+ else\r
+ {\r
+ errno = ENOMEM;\r
+ returnValue = (void *) -1;\r
+ }\r
+\r
+ return (returnValue);\r
+}\r
+\r
+\r
/*******************************************************************************\r
* Function Name: Reset\r
********************************************************************************\r
Start_c();\r
}\r
\r
-__attribute__((weak))\r
-void _exit(int status)\r
-{\r
- /* Cause a divide by 0 exception */\r
- int x = status / INT_MAX;\r
- x = 4 / x;\r
-\r
- while(1)\r
- {\r
- }\r
-}\r
\r
/*******************************************************************************\r
* Function Name: Start_c\r
*\r
* Summary:\r
* This function handles initializing the .data and .bss sections in\r
-* preperation for running standard C code. Once initialization is complete\r
+* preparation for running the standard C code. Once initialization is complete\r
* it will call main(). This function will never return.\r
*\r
* Parameters:\r
const struct __cy_region *rptr = __cy_regions;\r
\r
/* Initialize memory */\r
- for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++)\r
+ for (regions = __cy_region_num; regions != 0u; regions--)\r
{\r
uint32 *src = (uint32 *)rptr->init;\r
uint32 *dst = (uint32 *)rptr->data;\r
\r
for (count = 0u; count != limit; count += sizeof (uint32))\r
{\r
- *dst++ = *src++;\r
+ *dst = *src;\r
+ dst++;\r
+ src++;\r
}\r
limit = rptr->zero_size;\r
for (count = 0u; count != limit; count += sizeof (uint32))\r
{\r
- *dst++ = 0u;\r
+ *dst = 0u;\r
+ dst++;\r
}\r
+\r
+ rptr++;\r
}\r
\r
/* Invoke static objects constructors */\r
********************************************************************************\r
*\r
* Summary:\r
-* This function perform early initializations for the IAR Embedded\r
-* Workbench IDE. It is executed in the context of reset interrupt handler\r
+* This function performs early initializations for the IAR Embedded\r
+* Workbench IDE. It is executed in the context of a reset interrupt handler\r
* before the data sections are initialized.\r
*\r
* Parameters:\r
const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =\r
#endif /* defined (__ICCARM__) */\r
{\r
- INITIAL_STACK_POINTER, /* The initial stack pointer 0 */\r
- #if defined (__ICCARM__) /* The reset handler 1 */\r
+ INITIAL_STACK_POINTER, /* Initial stack pointer 0 */\r
+ #if defined (__ICCARM__) /* Reset handler 1 */\r
__iar_program_start,\r
#else\r
(cyisraddress)&Reset,\r
#endif /* defined (__ICCARM__) */\r
- &IntDefaultHandler, /* The NMI handler 2 */\r
- &IntDefaultHandler, /* The hard fault handler 3 */\r
+ &IntDefaultHandler, /* NMI handler 2 */\r
+ &IntDefaultHandler, /* Hard fault handler 3 */\r
};\r
\r
#if defined(__ARMCC_VERSION)\r
/* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */\r
CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);\r
\r
- /* Point NVIC at the RAM vector table. */\r
+ /* Point NVIC at RAM vector table. */\r
*CYINT_VECT_TABLE = CyRamVectors;\r
\r
/* Initialize the configuration registers. */\r
\r
#if(0u != DMA_CHANNELS_USED__MASK0)\r
\r
- /* Setup DMA - only necessary if the design contains a DMA component. */\r
+ /* Setup DMA - only necessary if design contains DMA component. */\r
CyDmacConfigure();\r
\r
#endif /* (0u != DMA_CHANNELS_USED__MASK0) */\r
/*******************************************************************************\r
* File Name: CyBootAsmGnu.s\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Assembly routines for GNU as.\r
*\r
********************************************************************************\r
-* Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
;-------------------------------------------------------------------------------\r
; FILENAME: CyBootAsmIar.s\r
-; Version 4.0\r
+; Version 4.20\r
;\r
; DESCRIPTION:\r
; Assembly routines for IAR Embedded Workbench IDE.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
;\r
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit\r
; with interrupts still enabled. The test and set of the interrupt bits is not\r
-; atomic. Therefore, to avoid corrupting processor state, it must be the policy \r
+; atomic. Therefore, to avoid a corrupting processor state, it must be the policy \r
; that all interrupt routines restore the interrupt enable bits as they were \r
; found on entry.\r
;\r
;-------------------------------------------------------------------------------\r
; FILENAME: CyBootAsmRv.s\r
-; Version 4.0\r
+; Version 4.20\r
;\r
; DESCRIPTION:\r
; Assembly routines for RealView.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
;\r
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit\r
; with interrupts still enabled. The test and set of the interrupt bits is not\r
-; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid\r
+; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a\r
; corrupting processor state, it must be the policy that all interrupt routines\r
; restore the interrupt enable bits as they were found on entry.\r
;\r
/*******************************************************************************\r
* File Name: CyDmac.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides an API for the DMAC component. The API includes functions for the\r
* not being used.\r
*\r
* This code uses the first byte of each TD to manage the free list of TD's.\r
-* The user can over write this once the TD is allocated.\r
+* The user can overwrite this once the TD is allocated.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
* are initialized. To avoid zeroing, these variables should be initialized\r
* properly during segments initialization as well.\r
*******************************************************************************/\r
-static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements in the list */\r
-static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */\r
+static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements on list */\r
+static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */\r
static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */\r
\r
\r
*\r
* Summary:\r
* Creates a linked list of all the TDs to be allocated. This function is called\r
-* by the startup code; you do not normally need to call it. You could call this\r
+* by the startup code; you do not normally need to call it. You can call this\r
* function if all of the DMA channels are inactive.\r
*\r
* Parameters:\r
CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);\r
}\r
\r
- /* Make the last one point to zero. */\r
+ /* Make last one point to zero. */\r
CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;\r
}\r
\r
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.\r
*\r
* Theory:\r
-* Once an error occurs the error bits are sticky and are only cleared by a\r
-* write 1 to the error register.\r
+* Once an error occurs the error bits are sticky and are only cleared by \r
+* writing 1 to the error register.\r
*\r
*******************************************************************************/\r
uint8 CyDmacError(void) \r
* Set to 1 when an access is attempted to an invalid address.\r
*\r
* DMAC_BUS_TIMEOUT:\r
-* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values\r
+* Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values\r
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.\r
*\r
* Return:\r
* None\r
*\r
* Theory:\r
-* Once an error occurs the error bits are sticky and are only cleared by a\r
-* write 1 to the error register.\r
+* Once an error occurs the error bits are sticky and are only cleared by \r
+* writing 1 to the error register.\r
*\r
*******************************************************************************/\r
void CyDmacClearError(uint8 error) \r
********************************************************************************\r
*\r
* Summary:\r
-* When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the\r
+* When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the\r
* address of the error is written to the error address register and can be read\r
* with this function.\r
*\r
/* Enter critical section! */\r
interruptState = CyEnterCriticalSection();\r
\r
- /* Look for a free channel. */\r
+ /* Look for free channel. */\r
for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)\r
{\r
if(0uL == (CyDmaChannels & channel))\r
{\r
- /* Mark the channel as used. */\r
+ /* Mark channel as used. */\r
CyDmaChannels |= channel;\r
break;\r
}\r
/* Enter critical section */\r
interruptState = CyEnterCriticalSection();\r
\r
- /* Clear the bit mask that keeps track of ownership. */\r
+ /* Clear bit mask that keeps track of ownership. */\r
CyDmaChannels &= ~(((uint32) 1u) << chHandle);\r
\r
/* Exit critical section */\r
* Preserves the original TD state when the TD has completed. This parameter\r
* applies to all TDs in the channel.\r
*\r
-* 0 - When a TD is completed, the DMAC leaves the TD configuration values in\r
+* 0 - When TD is completed, the DMAC leaves the TD configuration values in\r
* their current state, and does not restore them to their original state.\r
*\r
-* 1 - When a TD is completed, the DMAC restores the original configuration\r
+* 1 - When TD is completed, the DMAC restores the original configuration\r
* values of the TD.\r
*\r
* When preserveTds is set, the TD slot that equals the channel number becomes\r
{\r
if (0u != preserveTds)\r
{\r
- /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to\r
- * preserve the original TD chain\r
+ /* Store intermediate TD states separately in CHn_SEP_TD0/1 to\r
+ * preserve original TD chain\r
*/\r
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;\r
}\r
else\r
{\r
- /* Store the intermediate and final TD states on top of the original TD chain */\r
+ /* Store intermediate and final TD states on top of original TD chain */\r
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);\r
}\r
\r
/* Disable channel */\r
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));\r
\r
- /* Store the intermediate and final TD states on top of the original TD chain */\r
+ /* Store intermediate and final TD states on top of original TD chain */\r
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));\r
status = CYRET_SUCCESS;\r
}\r
********************************************************************************\r
*\r
* Summary:\r
-* Clears pending DMA data request.\r
+* Clears pending the DMA data request.\r
*\r
* Parameters:\r
* uint8 chHandle:\r
* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().\r
*\r
* uint8 startTd:\r
-* The index of TD to set as the first TD associated with the channel. Zero is\r
+* Set the TD index as the first TD associated with the channel. Zero is\r
* a valid TD index.\r
*\r
* Return:\r
\r
if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)\r
{\r
- /* Get pointer to the Next available. */\r
+ /* Get pointer to Next available. */\r
element = CyDmaTdFreeIndex;\r
\r
/* Decrement the count. */\r
CyDmaTdCurrentNumber--;\r
\r
- /* Update the next available pointer. */\r
+ /* Update next available pointer. */\r
CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];\r
}\r
\r
/* Enter critical section! */\r
uint8 interruptState = CyEnterCriticalSection();\r
\r
- /* Get pointer to the Next available. */\r
+ /* Get pointer to Next available. */\r
CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;\r
\r
/* Set new Next Available. */\r
* CYRET_BAD_PARAM if tdHandle is invalid.\r
*\r
* Side Effects:\r
-* If a TD has a transfer count of N and is executed, the transfer count becomes\r
+* If TD has a transfer count of N and is executed, the transfer count becomes\r
* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a\r
-* request for indefinite transfer. Be careful when requesting a TD with a\r
+* request for indefinite transfer. Be careful when requesting TD with a\r
* transfer count of zero.\r
*\r
*******************************************************************************/\r
\r
if(tdHandle < CY_DMA_NUMBEROF_TDS)\r
{\r
- /* If we have a pointer */\r
+ /* If we have pointer */\r
if(NULL != transferCount)\r
{\r
- /* Get the 12 bits of the transfer count */\r
+ /* Get 12 bits of transfer count */\r
reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];\r
*transferCount = 0x0FFFu & CY_GET_REG16(convert);\r
}\r
\r
- /* If we have a pointer */\r
+ /* If we have pointer */\r
if(NULL != nextTd)\r
{\r
- /* Get the Next TD pointer */\r
+ /* Get Next TD pointer */\r
*nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];\r
}\r
\r
- /* If we have a pointer */\r
+ /* If we have pointer */\r
if(NULL != configuration)\r
{\r
- /* Get the configuration the TD */\r
+ /* Get configuration TD */\r
*configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];\r
}\r
\r
/*******************************************************************************\r
* File Name: CyDmac.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides the function definitions for the DMA Controller.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#define CY_DMA_TD_SIZE 0x08u\r
\r
-/* The "u" was removed as workaround for Keil compiler bug */\r
+/* "u" was removed as workaround for Keil compiler bug */\r
#define CY_DMA_TD_SWAP_EN 0x80\r
#define CY_DMA_TD_SWAP_SIZE4 0x40\r
#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
+* The following code is OBSOLETE and must not be used.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL)\r
#define DMA_INVALID_TD (CY_DMA_INVALID_TD)\r
/*******************************************************************************\r
* File Name: CyFlash.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides an API for the FLASH/EEPROM.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#include "CyFlash.h"\r
\r
+/* The number of EEPROM arrays */\r
+#define CY_FLASH_EEPROM_NUMBER_ARRAYS (1u)\r
+\r
\r
/*******************************************************************************\r
-* Holds die temperature, updated by CySetTemp(). Used for flash writting.\r
+* Holds the die temperature, updated by CySetTemp(). Used for flash writing.\r
* The first byte is the sign of the temperature (0 = negative, 1 = positive).\r
* The second byte is the magnitude.\r
*******************************************************************************/\r
\r
\r
static cystatus CySetTempInt(void);\r
+static cystatus CyFlashGetSpcAlgorithm(void);\r
\r
\r
/*******************************************************************************\r
*******************************************************************************/\r
void CyFlash_Start(void) \r
{\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+\r
+ /***************************************************************************\r
+ * Enable SPC clock. This also internally enables the 36MHz IMO, since this\r
+ * is required for the SPC to function.\r
+ ***************************************************************************/\r
+ CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;\r
+ CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;\r
+\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;\r
+ /***************************************************************************\r
+ * The wake count defines the number of Bus Clock cycles it takes for the\r
+ * flash or eeprom to wake up from a low power mode independent of the chip\r
+ * power mode. Wake up time for these blocks is 5 us.\r
+ * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E\r
+ * (30d) defines the wake up time as 60 cycles of the Bus Clock.\r
+ * This register needs to be written with a value dependent on the Bus Clock\r
+ * frequency so that the duration of the cycles is equal to or greater than\r
+ * the 5 us delay required.\r
+ ***************************************************************************/\r
+ CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;\r
+\r
+\r
+ /***************************************************************************\r
+ * Enable flash. Active flash macros consume current, but re-enabling a\r
+ * disabled flash macro takes 5us. If the CPU attempts to fetch out of the\r
+ * macro during that time, it will be stalled. This bit allows the flash to\r
+ * be enabled even if the CPU is disabled, which allows a quicker return to\r
+ * code execution.\r
+ ***************************************************************************/\r
+ CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_FM;\r
+ CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;\r
+\r
+ while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))\r
+ {\r
+ /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */\r
+ }\r
\r
- CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
*******************************************************************************/\r
void CyFlash_Stop(void) \r
{\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));\r
+ CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
*\r
* Summary:\r
* Sends a command to the SPC to read the die temperature. Sets a global value\r
-* used by the Write functions. This function must be called once before\r
+* used by the Write function. This function must be called once before\r
* executing a series of Flash writing functions.\r
*\r
* Parameters:\r
}\r
\r
\r
+/*******************************************************************************\r
+* Function Name: CyFlashGetSpcAlgorithm\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sends a command to the SPC to download code into RAM.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* status:\r
+* CYRET_SUCCESS - if successful\r
+* CYRET_LOCKED - if Flash writing already in use\r
+* CYRET_UNKNOWN - if there was an SPC error\r
+*\r
+*******************************************************************************/\r
+static cystatus CyFlashGetSpcAlgorithm(void) \r
+{\r
+ cystatus status;\r
+\r
+ /* Make sure SPC is powered */\r
+ CySpcStart();\r
+\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ status = CySpcGetAlgorithm();\r
+\r
+ if(CYRET_STARTED == status)\r
+ {\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Spin until idle. */\r
+ CyDelayUs(1u);\r
+ }\r
+\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ }\r
+ CySpcUnlock();\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return (status);\r
+}\r
+\r
+\r
/*******************************************************************************\r
* Function Name: CySetTemp\r
********************************************************************************\r
*\r
* Summary:\r
-* This is a wraparound for CySetTempInt(). It is used to return second\r
-* successful read of temperature value.\r
+* This is a wraparound for CySetTempInt(). It is used to return the second\r
+* successful read of the temperature value.\r
*\r
* Parameters:\r
* None\r
* CYRET_UNKNOWN if there was an SPC error.\r
*\r
* uint8 dieTemperature[2]:\r
-* Holds die temperature for the flash writting algorithm. The first byte is\r
+* Holds the die temperature for the flash writing algorithm. The first byte is\r
* the sign of the temperature (0 = negative, 1 = positive). The second byte is\r
* the magnitude.\r
*\r
*******************************************************************************/\r
cystatus CySetTemp(void) \r
{\r
- cystatus status = CySetTempInt();\r
+ cystatus status = CyFlashGetSpcAlgorithm();\r
\r
if(status == CYRET_SUCCESS)\r
{\r
*\r
* Summary:\r
* Sets the user supplied temporary buffer to store SPC data while performing\r
-* flash and EEPROM commands. This buffer is only necessary when Flash ECC is\r
+* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is\r
* disabled.\r
*\r
* Parameters:\r
* buffer:\r
-* Address of block of memory to store temporary memory. The size of the block\r
+* The address of a block of memory to store temporary memory. The size of the block\r
* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.\r
*\r
* Return:\r
\r
if(NULL == buffer)\r
{\r
+ rowBuffer = rowBuffer;\r
status = CYRET_BAD_PARAM;\r
}\r
else if(CySpcLock() != CYRET_SUCCESS)\r
{\r
+ rowBuffer = rowBuffer;\r
status = CYRET_LOCKED;\r
}\r
else\r
\r
#else\r
\r
- /* To supress the warning */\r
+ /* To suppress warning */\r
buffer = buffer;\r
\r
#endif /* (CYDEV_ECC_ENABLE == 0u) */\r
}\r
\r
\r
-#if(CYDEV_ECC_ENABLE == 1)\r
-\r
- /*******************************************************************************\r
- * Function Name: CyWriteRowData\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sends a command to the SPC to load and program a row of data in\r
- * Flash or EEPROM.\r
- *\r
- * Parameters:\r
- * arrayID: ID of the array to write.\r
- * The type of write, Flash or EEPROM, is determined from the array ID.\r
- * The arrays in the part are sequential starting at the first ID for the\r
- * specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
- * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
- * rowAddress: rowAddress of flash row to program.\r
- * rowData: Array of bytes to write.\r
- *\r
- * Return:\r
- * status:\r
- * CYRET_SUCCESS if successful.\r
- * CYRET_LOCKED if the SPC is already in use.\r
- * CYRET_CANCELED if command not accepted\r
- * CYRET_UNKNOWN if there was an SPC error.\r
- *\r
- *******************************************************************************/\r
- cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) \r
- {\r
- uint16 rowSize;\r
- cystatus status;\r
-\r
- rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;\r
- status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);\r
-\r
- return(status);\r
- }\r
-\r
-#else\r
-\r
- /*******************************************************************************\r
- * Function Name: CyWriteRowData\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sends a command to the SPC to load and program a row of data in\r
- * Flash or EEPROM.\r
- *\r
- * Parameters:\r
- * arrayID : ID of the array to write.\r
- * The type of write, Flash or EEPROM, is determined from the array ID.\r
- * The arrays in the part are sequential starting at the first ID for the\r
- * specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
- * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
- * rowAddress : rowAddress of flash row to program.\r
- * rowData : Array of bytes to write.\r
- *\r
- * Return:\r
- * status:\r
- * CYRET_SUCCESS if successful.\r
- * CYRET_LOCKED if the SPC is already in use.\r
- * CYRET_CANCELED if command not accepted\r
- * CYRET_UNKNOWN if there was an SPC error.\r
- *\r
- *******************************************************************************/\r
- cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) \r
- {\r
- uint8 i;\r
- uint32 offset;\r
- uint16 rowSize;\r
- cystatus status;\r
-\r
- /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */\r
- if(NULL != rowBuffer)\r
- {\r
- if(arrayId > CY_SPC_LAST_FLASH_ARRAYID)\r
- {\r
- rowSize = CYDEV_EEPROM_ROW_SIZE;\r
- }\r
- else\r
- {\r
- rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE;\r
-\r
- /* Save the ECC area. */\r
- offset = CYDEV_ECC_BASE +\r
- ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) +\r
- ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE);\r
-\r
- for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)\r
- {\r
- *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
- }\r
- }\r
-\r
- /* Copy the rowdata to the temporary buffer. */\r
- #if(CY_PSOC3)\r
- (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);\r
- #else\r
- (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);\r
- #endif /* (CY_PSOC3) */\r
-\r
- status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);\r
- }\r
- else\r
- {\r
- status = CYRET_UNKNOWN;\r
- }\r
+/*******************************************************************************\r
+* Function Name: CyWriteRowData\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sends a command to the SPC to load and program a row of data in\r
+* Flash or EEPROM.\r
+*\r
+* Parameters:\r
+* arrayID: ID of the array to write.\r
+* The type of write, Flash or EEPROM, is determined from the array ID.\r
+* The arrays in the part are sequential starting at the first ID for the\r
+* specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
+* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
+* rowAddress: rowAddress of flash row to program.\r
+* rowData: Array of bytes to write.\r
+*\r
+* Return:\r
+* status:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_LOCKED if the SPC is already in use.\r
+* CYRET_CANCELED if command not accepted\r
+* CYRET_UNKNOWN if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) \r
+{\r
+ uint16 rowSize;\r
+ cystatus status;\r
\r
- return(status);\r
- }\r
+ rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;\r
+ status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);\r
\r
-#endif /* (CYDEV_ECC_ENABLE == 0u) */\r
+ return(status);\r
+}\r
\r
\r
+/*******************************************************************\r
+* If "Enable Error Correcting Code (ECC)" and "Store Configuration\r
+* Data in ECC" DWR options are disabled, ECC section is available\r
+* for user data.\r
+*******************************************************************/\r
#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))\r
\r
/*******************************************************************************\r
********************************************************************************\r
*\r
* Summary:\r
- * Sends a command to the SPC to load and program a row of config data in flash.\r
+ * Sends a command to the SPC to load and program a row of config data in the Flash.\r
* This function is only valid for Flash array IDs (not for EEPROM).\r
*\r
* Parameters:\r
* The arrays in the part are sequential starting at the first ID for the\r
* specific memory type. The array ID for the Flash memory lasts\r
* from 0x00 to 0x3F.\r
- * rowAddress: Address of the sector to erase.\r
- * rowECC: Array of bytes to write.\r
+ * rowAddress: The address of the sector to erase.\r
+ * rowECC: The array of bytes to write.\r
*\r
* Return:\r
* status:\r
cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\\r
\r
{\r
- uint32 offset;\r
- uint16 i;\r
cystatus status;\r
\r
- /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */\r
- if(NULL != rowBuffer)\r
- {\r
- /* Read the existing flash data. */\r
- offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) +\r
- ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE);\r
-\r
- #if (CYDEV_FLS_BASE != 0u)\r
- offset += CYDEV_FLS_BASE;\r
- #endif /* (CYDEV_FLS_BASE != 0u) */\r
-\r
- for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)\r
- {\r
- rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
- }\r
-\r
- #if(CY_PSOC3)\r
- (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],\r
- (void *)(uint32)rowECC,\r
- (int16)CYDEV_ECC_ROW_SIZE);\r
- #else\r
- (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],\r
- (const void *)rowECC,\r
- CYDEV_ECC_ROW_SIZE);\r
- #endif /* (CY_PSOC3) */\r
-\r
- status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);\r
- }\r
- else\r
- {\r
- status = CYRET_UNKNOWN;\r
- }\r
+ status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);\r
\r
return (status);\r
}\r
* Function Name: CyWriteRowFull\r
********************************************************************************\r
* Summary:\r
-* Sends a command to the SPC to load and program a row of data in flash.\r
+* Sends a command to the SPC to load and program a row of data in the Flash.\r
* rowData array is expected to contain Flash and ECC data if needed.\r
*\r
* Parameters:\r
cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \\r
\r
{\r
- cystatus status;\r
+ cystatus status = CYRET_SUCCESS;\r
\r
- if(CySpcLock() == CYRET_SUCCESS)\r
+ if((arrayId <= CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS + CY_SPC_FIRST_FLASH_ARRAYID)))\r
{\r
- /* Load row data into SPC internal latch */\r
- status = CySpcLoadRow(arrayId, rowData, rowSize);\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
\r
- if(CYRET_STARTED == status)\r
+ if(arrayId > CY_SPC_LAST_EE_ARRAYID)\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+ if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+ if(arrayId <= CY_SPC_LAST_FLASH_ARRAYID)\r
+ {\r
+ /* Flash */\r
+ if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))\r
{\r
- while(CY_SPC_BUSY)\r
- {\r
- /* Wait for SPC to finish and get SPC status */\r
- CyDelayUs(1u);\r
- }\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* EEPROM */\r
+ if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
\r
- /* Hide SPC status */\r
- if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
- {\r
- status = CYRET_SUCCESS;\r
- }\r
- else\r
- {\r
- status = CYRET_UNKNOWN;\r
- }\r
+ if(CY_EEPROM_SIZEOF_ROW != rowSize)\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+ }\r
\r
- if(CYRET_SUCCESS == status)\r
+ if(rowData == NULL)\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+\r
+ if(status == CYRET_SUCCESS)\r
+ {\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ /* Load row data into SPC internal latch */\r
+ status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);\r
+\r
+ if(CYRET_STARTED == status)\r
{\r
- /* Erase and program flash with the data from SPC interval latch */\r
- status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait for SPC to finish and get SPC status */\r
+ CyDelayUs(1u);\r
+ }\r
\r
- if(CYRET_STARTED == status)\r
+ /* Hide SPC status */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
{\r
- while(CY_SPC_BUSY)\r
- {\r
- /* Wait for SPC to finish and get SPC status */\r
- CyDelayUs(1u);\r
- }\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
\r
- /* Hide SPC status */\r
- if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
- {\r
- status = CYRET_SUCCESS;\r
- }\r
- else\r
+ if(CYRET_SUCCESS == status)\r
+ {\r
+ /* Erase and program flash with data from SPC interval latch */\r
+ status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);\r
+\r
+ if(CYRET_STARTED == status)\r
{\r
- status = CYRET_UNKNOWN;\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait for SPC to finish and get SPC status */\r
+ CyDelayUs(1u);\r
+ }\r
+\r
+ /* Hide SPC status */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
}\r
}\r
}\r
-\r
+ CySpcUnlock();\r
+ } /* if(CySpcLock() == CYRET_SUCCESS) */\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
}\r
-\r
- CySpcUnlock();\r
- }\r
- else\r
- {\r
- status = CYRET_LOCKED;\r
}\r
\r
return(status);\r
*\r
* Summary:\r
* Sets the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash. This function must be called before increasing CPU\r
-* clock frequency. It can optionally be called after lowering CPU clock\r
-* frequency in order to improve CPU performance.\r
+* coming back from the Flash. This function must be called before increasing the CPU\r
+* clock frequency. It can optionally be called after lowering the CPU clock\r
+* frequency in order to improve the CPU performance.\r
*\r
* Parameters:\r
* uint8 freq:\r
\r
/***************************************************************************\r
* The number of clock cycles the cache will wait before it samples data\r
- * coming back from Flash must be equal or greater to to the CPU frequency\r
+ * coming back from the Flash must be equal or greater to to the CPU frequency\r
* outlined in clock cycles.\r
***************************************************************************/\r
\r
- #if (CY_PSOC3)\r
-\r
- if (freq <= 22u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else if (freq <= 44u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
-\r
- #endif /* (CY_PSOC3) */\r
-\r
-\r
- #if (CY_PSOC5)\r
-\r
- if (freq <= 16u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else if (freq <= 33u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else if (freq <= 50u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
-\r
- #endif /* (CY_PSOC5) */\r
+ if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_1_VALUE_MASK;\r
+ }\r
+ else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_2_VALUE_MASK;\r
+ }\r
+ else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_3_VALUE_MASK;\r
+ }\r
+#if (CY_PSOC5)\r
+ else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_4_VALUE_MASK;\r
+ }\r
+ else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_5_VALUE_MASK;\r
+ }\r
+#endif /* (CY_PSOC5) */\r
+ else\r
+ {\r
+ /* Halt CPU in debug mode if frequency is invalid */\r
+ CYASSERT(0u != 0u);\r
+ }\r
\r
/* Restore global interrupt enable state */\r
CyExitCriticalSection(interruptState);\r
*******************************************************************************/\r
void CyEEPROM_Start(void) \r
{\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+\r
+ /***************************************************************************\r
+ * Enable SPC clock. This also internally enables the 36MHz IMO, since this\r
+ * is required for the SPC to function.\r
+ ***************************************************************************/\r
+ CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;\r
+ CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;\r
+\r
+ /***************************************************************************\r
+ * The wake count defines the number of Bus Clock cycles it takes for the\r
+ * flash or EEPROM to wake up from a low power mode independent of the chip\r
+ * power mode. Wake up time for these blocks is 5 us.\r
+ * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E\r
+ * (30d) defines the wake up time as 60 cycles of the Bus Clock.\r
+ * This register needs to be written with a value dependent on the Bus Clock\r
+ * frequency so that the duration of the cycles is equal to or greater than\r
+ * the 5 us delay required.\r
+ ***************************************************************************/\r
+ CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;\r
+\r
+\r
+ /***************************************************************************\r
+ * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,\r
+ * the EE will not acknowledge a PHUB request.\r
+ ***************************************************************************/\r
+ CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_EE;\r
+ CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;\r
+\r
+ while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))\r
+ {\r
+ /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */\r
+ }\r
+\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
*******************************************************************************/\r
void CyEEPROM_Stop (void) \r
{\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));\r
+ uint8 interruptState;\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));\r
+ CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));\r
+\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
*******************************************************************************/\r
void CyEEPROM_ReadReserve(void) \r
{\r
- /* Make a request for PHUB to have access */\r
- *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ;\r
+ /* Make request for PHUB to have access */\r
+ CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;\r
\r
- while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK))\r
+ while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))\r
{\r
- /* Wait for acknowledgement from PHUB */\r
+ /* Wait for acknowledgment from PHUB */\r
}\r
}\r
\r
*******************************************************************************/\r
void CyEEPROM_ReadRelease(void) \r
{\r
- *CY_FLASH_EE_SCR_PTR |= 0x00u;\r
+ CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);\r
}\r
\r
\r
/*******************************************************************************\r
* File Name: CyFlash.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides the function definitions for the FLASH/EEPROM.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)\r
#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)\r
\r
+#if(CYDEV_ECC_ENABLE == 0)\r
+ #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)\r
+#else\r
+ #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW)\r
+#endif /* (CYDEV_ECC_ENABLE == 0) */\r
#define CY_EEPROM_BASE (CYDEV_EE_BASE)\r
#define CY_EEPROM_SIZE (CYDEV_EE_SIZE)\r
#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE)\r
#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE)\r
-#define CY_EEPROM_NUMBER_ROWS (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE)\r
+#define CY_EEPROM_NUMBER_ROWS (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)\r
#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)\r
-\r
+#define CY_EEPROM_NUMBER_SECTORS (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)\r
+#define CY_EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE)\r
\r
#if !defined(CYDEV_FLS_BASE)\r
#define CYDEV_FLS_BASE CYDEV_FLASH_BASE\r
/***************************************\r
* Registers\r
***************************************/\r
+/* Active Power Mode Configuration Register 0 */\r
+#define CY_FLASH_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0)\r
+#define CY_FLASH_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)\r
+\r
+/* Alternate Active Power Mode Configuration Register 0 */\r
+#define CY_FLASH_PM_ALTACT_CFG0_REG (* (reg8 *) CYREG_PM_STBY_CFG0)\r
+#define CY_FLASH_PM_ALTACT_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)\r
+\r
/* Active Power Mode Configuration Register 12 */\r
-#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)\r
-#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ACT_CFG12_REG (* (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ACT_CFG12_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)\r
\r
/* Alternate Active Power Mode Configuration Register 12 */\r
-#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)\r
-#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_ALTACT_CFG12_REG (* (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_ALTACT_CFG12_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)\r
+\r
+/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */\r
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)\r
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR ( (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)\r
+\r
+/* Flash macro control register */\r
+#define CY_FLASH_SPC_FM_EE_CR_REG (* (reg8 *) CYREG_SPC_FM_EE_CR)\r
+#define CY_FLASH_SPC_FM_EE_CR_PTR ( (reg8 *) CYREG_SPC_FM_EE_CR)\r
\r
\r
/* Cache Control Register */\r
***************************************/\r
\r
/* Power Mode Masks */\r
-#define CY_FLASH_PM_EE_MASK (0x10u)\r
-#define CY_FLASH_PM_FLASH_MASK (0x01u)\r
\r
-/* Frequency Constants */\r
+/* Enable EEPROM */\r
+#define CY_FLASH_PM_ACT_CFG12_EN_EE (0x10u)\r
+#define CY_FLASH_PM_ALTACT_CFG12_EN_EE (0x10u)\r
+\r
+/* Enable Flash */\r
#if (CY_PSOC3)\r
+ #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x01u)\r
+ #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x01u)\r
+#else\r
+ #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x0Fu)\r
+ #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x0Fu)\r
+#endif /* (CY_PSOC3) */\r
+\r
\r
- #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)\r
- #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)\r
- #define CY_FLASH_GREATER_44MHz (0x03u)\r
\r
+/* Frequency Constants */\r
+#if (CY_PSOC3)\r
+ #define CY_FLASH_CACHE_WS_VALUE_MASK (0xC0u)\r
+ #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u)\r
+ #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u)\r
+ #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u)\r
+\r
+ #define CY_FLASH_CACHE_WS_1_FREQ_MAX (22u)\r
+ #define CY_FLASH_CACHE_WS_2_FREQ_MAX (44u)\r
+ #define CY_FLASH_CACHE_WS_3_FREQ_MAX (67u)\r
#endif /* (CY_PSOC3) */\r
\r
#if (CY_PSOC5)\r
-\r
- #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)\r
- #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)\r
- #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)\r
- #define CY_FLASH_GREATER_51MHz (0x00u)\r
-\r
+ #define CY_FLASH_CACHE_WS_VALUE_MASK (0xE0u)\r
+ #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u)\r
+ #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u)\r
+ #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u)\r
+ #define CY_FLASH_CACHE_WS_4_VALUE_MASK (0x00u)\r
+ #define CY_FLASH_CACHE_WS_5_VALUE_MASK (0x20u)\r
+\r
+ #define CY_FLASH_CACHE_WS_1_FREQ_MAX (16u)\r
+ #define CY_FLASH_CACHE_WS_2_FREQ_MAX (33u)\r
+ #define CY_FLASH_CACHE_WS_3_FREQ_MAX (50u)\r
+ #define CY_FLASH_CACHE_WS_4_FREQ_MAX (67u)\r
+ #define CY_FLASH_CACHE_WS_5_FREQ_MAX (83u)\r
#endif /* (CY_PSOC5) */\r
\r
#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u)\r
#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))\r
-#define CY_FLASH_EE_STARTUP_DELAY (5u)\r
\r
#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u)\r
#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u)\r
\r
\r
+#define CY_FLASH_EE_EE_AWAKE (0x20u)\r
+\r
+/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */\r
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ (0xC8u)\r
+\r
+/* Enable clk_spc. This also internally enables the 36MHz IMO. */\r
+#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC (0x08u)\r
+#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC (0x08u)\r
\r
/* Default values for getting temperature. */\r
\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
+* Thne following code is OBSOLETE and must not be used starting with cy_boot\r
+* 4.20.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
+*******************************************************************************/\r
+#if (CY_PSOC5)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)\r
+ #define CY_FLASH_GREATER_51MHz (0x00u)\r
+#endif /* (CY_PSOC5) */\r
+\r
+#if (CY_PSOC3)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)\r
+ #define CY_FLASH_GREATER_44MHz (0x03u)\r
+#endif /* (CY_PSOC3) */\r
+\r
+#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_EE_MASK (0x10u)\r
+#define CY_FLASH_PM_FLASH_MASK (0x01u)\r
+\r
+/*******************************************************************************\r
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.0\r
*******************************************************************************/\r
#define FLASH_SIZE (CY_FLASH_SIZE)\r
#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY)\r
#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)\r
#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS)\r
#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)\r
-#define CY_EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)\r
-#define CY_EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30\r
*******************************************************************************/\r
#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR)\r
\r
/*******************************************************************************\r
* File Name: CyLib.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
-* Provides system API for the clocking, interrupts and watchdog timer.\r
+* Provides a system API for the clocking, interrupts and watchdog timer.\r
*\r
* Note:\r
* Documentation of the API's in this file is located in the\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
static void CyIMO_SetTrimValue(uint8 freq) ;\r
static void CyBusClk_Internal_SetDivider(uint16 divider);\r
\r
+#if(CY_PSOC5)\r
+ static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];\r
+ static void CySysTickServiceCallbacks(void);\r
+ uint32 CySysTickInitVar = 0u;\r
+#endif /* (CY_PSOC5) */\r
+\r
\r
/*******************************************************************************\r
* Function Name: CyPLL_OUT_Start\r
* clock can still be used.\r
*\r
* Side Effects:\r
-* If wait is enabled: This function wses the Fast Time Wheel to time the wait.\r
+* If wait is enabled: This function uses the Fast Time Wheel to time the wait.\r
* Any other use of the Fast Time Wheel will be stopped during the period of\r
* this function and then restored. This function also uses the 100 KHz ILO.\r
* If not enabled, this function will enable the 100 KHz ILO for the period of\r
uint8 pmTwCfg2State;\r
\r
\r
- /* Enables the PLL circuit */\r
+ /* Enables PLL circuit */\r
CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;\r
\r
if(wait != 0u)\r
\r
while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))\r
{\r
- /* Wait for the interrupt status */\r
+ /* Wait for interrupt status */\r
if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))\r
{\r
if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
* None\r
*\r
* Side Effects:\r
-* If wait is enabled: This function wses the Fast Time Wheel to time the wait.\r
+* If wait is enabled: This function uses the Fast Time Wheel to time the wait.\r
* Any other use of the Fast Time Wheel will be stopped during the period of\r
* this function and then restored. This function also uses the 100 KHz ILO.\r
* If not enabled, this function will enable the 100 KHz ILO for the period of\r
\r
if(0u != wait)\r
{\r
- /* Need to turn on the 100KHz ILO if it happens to not already be running.*/\r
+ /* Need to turn on 100KHz ILO if it happens to not already be running.*/\r
ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;\r
pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;\r
pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;\r
\r
while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))\r
{\r
- /* Wait for the interrupt status */\r
+ /* Wait for interrupt status */\r
}\r
\r
if(0u == ilo100KhzEnable)\r
/* If USB is powered */\r
if(usbPowerOn == 1u)\r
{\r
- /* Lock the USB Oscillator */\r
+ /* Lock USB Oscillator */\r
CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;\r
}\r
break;\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
* When the USB setting is chosen, the USB clock locking circuit is enabled.\r
uint8 nextFreq;\r
\r
/***************************************************************************\r
- * When changing the IMO frequency the Trim values must also be set\r
+ * If the IMO frequency is changed,the Trim values must also be set\r
* accordingly.This requires reading the current frequency. If the new\r
- * frequency is faster, then set the new trim and then change the frequency,\r
- * otherwise change the frequency and then set the new trim values.\r
+ * frequency is faster, then set a new trim and then change the frequency,\r
+ * otherwise change the frequency and then set new trim values.\r
***************************************************************************/\r
\r
currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));\r
\r
- /* Check if the requested frequency is USB. */\r
+ /* Check if requested frequency is USB. */\r
nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;\r
\r
switch (currentFreq)\r
\r
if (nextFreq >= currentFreq)\r
{\r
- /* Set the new trim first */\r
+ /* Set new trim first */\r
CyIMO_SetTrimValue(freq);\r
}\r
\r
- /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */\r
+ /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */\r
switch(freq)\r
{\r
case CY_IMO_FREQ_3MHZ:\r
break;\r
}\r
\r
- /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */\r
+ /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */\r
if (freq == CY_IMO_FREQ_USB)\r
{\r
CyIMO_EnableDoubler();\r
\r
if (nextFreq < currentFreq)\r
{\r
- /* Set the new trim after setting the frequency */\r
+ /* Set the trim after setting frequency */\r
CyIMO_SetTrimValue(freq);\r
}\r
}\r
* Sets the source of the clock output from the IMO block.\r
*\r
* The output from the IMO is by default the IMO itself. Optionally the MHz\r
-* Crystal or a DSI input can be the source of the IMO output instead.\r
+* Crystal or DSI input can be the source of the IMO output instead.\r
*\r
* Parameters:\r
* source: CY_IMO_SOURCE_DSI to set the DSI as source.\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
*******************************************************************************/\r
void CyIMO_EnableDoubler(void) \r
{\r
- /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */\r
+ /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */\r
CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;\r
}\r
\r
* The current source and the new source must both be running and stable before\r
* calling this function.\r
*\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
*\r
* Parameters:\r
* uint8 divider:\r
-* Valid range [0-255]. The clock will be divided by this value + 1.\r
-* For example to divide by 2 this parameter should be set to 1.\r
+* The valid range is [0-255]. The clock will be divided by this value + 1.\r
+* For example to divide this parameter by two should be set to 1.\r
*\r
* Return:\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
* When changing the Master or Bus clock divider value from div-by-n to div-by-1\r
********************************************************************************\r
*\r
* Summary:\r
-* Function used by CyBusClk_SetDivider(). For internal use only.\r
+* The function used by CyBusClk_SetDivider(). For internal use only.\r
*\r
* Parameters:\r
* divider: Valid range [0-65535].\r
* The clock will be divided by this value + 1.\r
-* For example to divide by 2 this parameter should be set to 1.\r
+* For example, to divide this parameter by two should be set to 1.\r
*\r
* Return:\r
* None\r
/* Enable mask bits to enable shadow loads */\r
CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;\r
\r
- /* Update Shadow Divider Value Register with the new divider */\r
+ /* Update Shadow Divider Value Register with new divider */\r
CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);\r
CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);\r
\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets the divider value used to generate Bus Clock.\r
+* Sets the divider value used to generate the Bus Clock.\r
*\r
* Parameters:\r
* divider: Valid range [0-65535]. The clock will be divided by this value + 1.\r
-* For example to divide by 2 this parameter should be set to 1.\r
+* For example, to divide this parameter by two should be set to 1.\r
*\r
* Return:\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
\r
interruptState = CyEnterCriticalSection();\r
\r
- /* Work around to set the bus clock divider value */\r
+ /* Work around to set bus clock divider value */\r
busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);\r
busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;\r
\r
if ((divider == 0u) || (busClkDiv == 0u))\r
{\r
- /* Save away the master clock divider value */\r
+ /* Save away master clock divider value */\r
masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;\r
\r
if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)\r
\r
if (divider == 0u)\r
{\r
- /* Set the SSS bit and the divider register desired value */\r
+ /* Set SSS bit and divider register desired value */\r
CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;\r
CyBusClk_Internal_SetDivider(divider);\r
}\r
CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));\r
}\r
\r
- /* Restore the master clock */\r
+ /* Restore master clock */\r
CyMasterClk_SetDivider(masterClkDiv);\r
}\r
else\r
*\r
* Parameters:\r
* divider: Valid range [0-15]. The clock will be divided by this value + 1.\r
- * For example to divide by 2 this parameter should be set to 1.\r
+ * For example, to divide this parameter by two should be set to 1.\r
*\r
* Return:\r
* None\r
*\r
* Side Effects:\r
- * If as result of this function execution the CPU clock frequency is increased\r
- * then the number of clock cycles the cache will wait before it samples data\r
- * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
- * with appropriate parameter. It can be optionally called if CPU clock\r
- * frequency is lowered in order to improve CPU performance.\r
+ * If this function execution resulted in the CPU clock frequency increasing,\r
+* then the number of clock cycles the cache will wait before it samples data\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
*******************************************************************************/\r
void CyILO_Start1K(void) \r
{\r
- /* Set the bit 1 of ILO RS */\r
+ /* Set bit 1 of ILO RS */\r
CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;\r
}\r
\r
* Summary:\r
* Disables the ILO 1 KHz oscillator.\r
*\r
-* Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power\r
+* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power\r
* mode APIs are expected to be used. For more information, refer to the Power\r
* Management section of this document.\r
*\r
*******************************************************************************/\r
void CyILO_Stop1K(void) \r
{\r
- /* Clear the bit 1 of ILO RS */\r
+ /* Clear bit 1 of ILO RS */\r
CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));\r
}\r
\r
*******************************************************************************/\r
void CyILO_Enable33K(void) \r
{\r
- /* Set the bit 5 of ILO RS */\r
+ /* Set bit 5 of ILO RS */\r
CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;\r
}\r
\r
/* Get current state. */\r
state = CY_LIB_SLOWCLK_ILO_CR0_REG;\r
\r
- /* Set the the oscillator power mode. */\r
+ /* Set the oscillator power mode. */\r
if(mode != CY_ILO_FAST_START)\r
{\r
CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);\r
CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));\r
}\r
\r
- /* Return the old mode. */\r
+ /* Return old mode. */\r
return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);\r
}\r
\r
CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;\r
#endif /* (CY_PSOC3) */\r
\r
- /* Enable operation of the 32K Crystal Oscillator */\r
+ /* Enable operation of 32K Crystal Oscillator */\r
CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;\r
\r
for (i = 1000u; i > 0u; i--)\r
{\r
if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))\r
{\r
- /* Ready - switch to the hign power mode */\r
+ /* Ready - switch to high power mode */\r
(void) CyXTAL_32KHZ_SetPowerMode(0u);\r
\r
break;\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets the power mode for the 32 KHz oscillator used during sleep mode.\r
+* Sets the power mode for the 32 KHz oscillator used during the sleep mode.\r
* Allows for lower power during sleep when there are fewer sources of noise.\r
-* During active mode the oscillator is always run in high power mode.\r
+* During the active mode the oscillator is always run in the high power mode.\r
*\r
* Parameters:\r
* uint8 mode\r
uint8 pmTwCfg2Tmp;\r
\r
\r
- /* Enables the MHz crystal oscillator circuit */\r
+ /* Enables MHz crystal oscillator circuit */\r
CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;\r
\r
\r
/* Read XERR bit to clear it */\r
(void) CY_CLK_XMHZ_CSR_REG;\r
\r
- /* Wait for a millisecond - 4 x 250 us */\r
+ /* Wait for 1 millisecond - 4 x 250 us */\r
for(count = 4u; count > 0u; count--)\r
{\r
while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))\r
{\r
- /* Wait for the FTW interrupt event */\r
+ /* Wait for FTW interrupt event */\r
}\r
}\r
\r
\r
/*******************************************************************\r
- * High output indicates oscillator failure.\r
- * Only can be used after start-up interval (1 ms) is completed.\r
+ * High output indicates an oscillator failure.\r
+ * Only can be used after a start-up interval (1 ms) is completed.\r
*******************************************************************/\r
if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))\r
{\r
*******************************************************************************/\r
void CyXTAL_Stop(void) \r
{\r
- /* Disable the the oscillator. */\r
+ /* Disable oscillator. */\r
FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));\r
}\r
\r
*\r
* Summary:\r
* Reads the XERR status bit for the megahertz crystal. This status bit is a\r
-* sticky clear on read value. This function is not available for PSoC5.\r
+* sticky, clear on read. This function is not available for PSoC5.\r
*\r
* Parameters:\r
* None\r
uint8 CyXTAL_ReadStatus(void) \r
{\r
/***************************************************************************\r
- * High output indicates oscillator failure. Only use this after start-up\r
- * interval is completed. This can be used for status and failure recovery.\r
+ * High output indicates an oscillator failure. Only use this after a start-up\r
+ * interval is completed. This can be used for the status and failure recovery.\r
***************************************************************************/\r
return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);\r
}\r
* Enables the fault recovery circuit which will switch to the IMO in the case\r
* of a fault in the megahertz crystal circuit. The crystal must be up and\r
* running with the XERR bit at 0, before calling this function to prevent\r
-* immediate fault switchover. This function is not available for PSoC5.\r
+* an immediate fault switchover. This function is not available for PSoC5.\r
*\r
* Parameters:\r
* None\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets the startup settings for the crystal. Logic model outputs a frequency\r
+* Sets the startup settings for the crystal. The logic model outputs a frequency\r
* (setting + 4) MHz when enabled.\r
*\r
* This is artificial as the actual frequency is determined by an attached\r
*\r
* Parameters:\r
* setting: Valid range [0-31].\r
-* Value is dependent on the frequency and quality of the crystal being used.\r
+* The value is dependent on the frequency and quality of the crystal being used.\r
* Refer to the device TRM and datasheet for more information.\r
*\r
* Return:\r
********************************************************************************\r
*\r
* Summary:\r
-* Forces a software reset of the device.\r
+* Forces a device software reset.\r
*\r
* Parameters:\r
* None\r
*\r
* Note:\r
* CyDelay has been implemented with the instruction cache assumed enabled. When\r
-* instruction cache is disabled on PSoC5, CyDelay will be two times larger. For\r
-* example, with instruction cache disabled CyDelay(100) would result in about\r
-* 200 ms delay instead of 100 ms.\r
+* the instruction cache is disabled on PSoC5, CyDelay will be two times larger.\r
+* For example, with instruction cache disabled CyDelay(100) would result in\r
+* about 200 ms delay instead of 100 ms.\r
*\r
* Parameters:\r
* milliseconds: number of milliseconds to delay.\r
*\r
* Side Effects:\r
* CyDelayUS has been implemented with the instruction cache assumed enabled.\r
- * When instruction cache is disabled on PSoC 5, CyDelayUs will be two times\r
- * larger. For example, with instruction cache disabled CyDelayUs(100) would\r
+ * When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times\r
+ * larger. For example, with the instruction cache disabled CyDelayUs(100) would\r
* result in about 200 us delay instead of 100 us.\r
*\r
* If the bus clock frequency is a small non-integer number, the actual delay\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets clock frequency for CyDelay.\r
+* Sets the clock frequency for CyDelay.\r
*\r
* Parameters:\r
-* freq: Frequency of bus clock in Hertz.\r
+* freq: The frequency of the bus clock in Hertz.\r
*\r
* Return:\r
* None\r
* Enables the watchdog timer.\r
*\r
* The timer is configured for the specified count interval, the central\r
-* timewheel is cleared, the setting for low power mode is configured and the\r
+* timewheel is cleared, the setting for the low power mode is configured and the\r
* watchdog timer is enabled.\r
*\r
* Once enabled the watchdog cannot be disabled. The watchdog counts each time\r
CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;\r
CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));\r
\r
- /* Setting the low power mode */\r
+ /* Setting low power mode */\r
CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |\r
(CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));\r
\r
- /* Enables the watchdog reset */\r
+ /* Enables watchdog reset */\r
CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;\r
}\r
\r
*\r
* Summary:\r
* Enables the digital low voltage monitors to generate interrupt on Vddd\r
-* archives specified threshold and optionally resets device.\r
+* archives specified threshold and optionally resets the device.\r
*\r
* Parameters:\r
-* reset: Option to reset device at a specified Vddd threshold:\r
+* reset: The option to reset the device at a specified Vddd threshold:\r
* 0 - Device is not reset.\r
* 1 - Device is reset.\r
*\r
* threshold: Sets the trip level for the voltage monitor.\r
-* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV\r
-* interval.\r
+* Values from 1.70 V to 5.45 V are accepted with an interval of approximately\r
+* 250 mV.\r
*\r
* Return:\r
* None\r
(CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;\r
\r
- /* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
+ /* Timeout to eliminate glitches on LVI/HVI when enabling */\r
CyDelayUs(1u);\r
\r
(void)CY_VD_PERSISTENT_STATUS_REG;\r
*\r
* Summary:\r
* Enables the analog low voltage monitors to generate interrupt on Vdda\r
-* archives specified threshold and optionally resets device.\r
+* archives specified threshold and optionally resets the device.\r
*\r
* Parameters:\r
-* reset: Option to reset device at a specified Vdda threshold:\r
+* reset: The option to reset the device at a specified Vdda threshold:\r
* 0 - Device is not reset.\r
* 1 - Device is reset.\r
*\r
CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;\r
\r
- /* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
+ /* Timeout to eliminate glitches on LVI/HVI when enabling */\r
CyDelayUs(1u);\r
\r
(void)CY_VD_PERSISTENT_STATUS_REG;\r
CY_NOP;\r
CY_NOP;\r
\r
- /* All entries in the cache are invalidated on the next clock cycle. */\r
+ /* All entries in cache are invalidated on next clock cycle. */\r
CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;\r
\r
+ /* Once this is executed it's guaranteed the cache has been flushed */\r
+ (void) CY_CACHE_CONTROL_REG;\r
\r
- /***********************************************************************\r
- * The prefetch unit could/would be filled with the instructions that\r
- * succeed the flush. Since a flush is desired then theoretically those\r
- * instructions might be considered stale/invalid.\r
- ***********************************************************************/\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
+ /* Flush the pipeline */\r
+ CY_SYS_ISB;\r
\r
/* Restore global interrupt enable state */\r
CyExitCriticalSection(interruptState);\r
* SysTick, PendSV and others.\r
*\r
* Parameters:\r
- * number: Interrupt number, valid range [0-15].\r
- address: Pointer to an interrupt service routine.\r
+ * number: System interrupt number:\r
+ * CY_INT_NMI_IRQN - Non Maskable Interrupt\r
+ * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt\r
+ * CY_INT_MEM_MANAGE_IRQN - Memory Management Interrupt\r
+ * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt\r
+ * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt\r
+ * CY_INT_SVCALL_IRQN - SV Call Interrupt\r
+ * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt\r
+ * CY_INT_PEND_SV_IRQN - Pend SV Interrupt\r
+ * CY_INT_SYSTICK_IRQN - System Tick Interrupt\r
+ *\r
+ * address: Pointer to an interrupt service routine.\r
*\r
* Return:\r
* The old ISR vector at this location.\r
* SysTick, PendSV and others.\r
*\r
* Parameters:\r
- * number: The interrupt number, valid range [0-15].\r
+ * number: System interrupt number:\r
+ * CY_INT_NMI_IRQN - Non Maskable Interrupt\r
+ * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt\r
+ * CY_INT_MEMORY_MANAGEMENT_IRQN - Memory Management Interrupt\r
+ * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt\r
+ * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt\r
+ * CY_INT_SVCALL_IRQN - SV Call Interrupt\r
+ * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt\r
+ * CY_INT_PEND_SV_IRQN - Pend SV Interrupt\r
+ * CY_INT_SYSTICK_IRQN - System Tick Interrupt\r
*\r
* Return:\r
* Address of the ISR in the interrupt vector table.\r
* number: Valid range [0-31]. Interrupt number\r
*\r
* Return:\r
- * Address of the ISR in the interrupt vector table.\r
+ * The address of the ISR in the interrupt vector table.\r
*\r
*******************************************************************************/\r
cyisraddress CyIntGetVector(uint8 number)\r
\r
CYASSERT(number <= CY_INT_NUMBER_MAX);\r
\r
- /* Get a pointer to the Interrupt enable register. */\r
+ /* Get pointer to Interrupt enable register. */\r
stateReg = CY_INT_ENABLE_PTR;\r
\r
- /* Get the state of the interrupt. */\r
+ /* Get state of interrupt. */\r
return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));\r
}\r
\r
\r
CYASSERT(number <= CY_INT_NUMBER_MAX);\r
\r
- /* Get a pointer to the Interrupt enable register. */\r
+ /* Get pointer to Interrupt enable register. */\r
stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);\r
\r
- /* Get the state of the interrupt. */\r
+ /* Get state of interrupt. */\r
return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));\r
}\r
\r
* If 1 is passed as a parameter:\r
* - if any of the SC blocks are used - enable pumps for the SC blocks and\r
* start boost clock.\r
- * - For the each enabled SC block set boost clock index and enable boost\r
+ * - For each enabled SC block set a boost clock index and enable the boost\r
* clock.\r
*\r
* If non-1 value is passed as a parameter:\r
* - If all SC blocks are not used - disable pumps for the SC blocks and\r
- * stop boost clock.\r
- * - For the each enabled SC block clear boost clock index and disable boost\r
+ * stop the boost clock.\r
+ * - For each enabled SC block clear the boost clock index and disable the boost\r
* clock.\r
*\r
- * The global variable CyScPumpEnabled is updated to be equal to passed\r
+ * The global variable CyScPumpEnabled is updated to be equal to passed the\r
* parameter.\r
*\r
* Parameters:\r
- * uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block.\r
+ * uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.\r
* 1 - Enable\r
* 0 - Disable\r
*\r
#endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
\r
\r
+#if(CY_PSOC5)\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickStart\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Configures the SysTick timer to generate interrupt every 1 ms by call to the\r
+ * CySysTickInit() function and starts it by calling CySysTickEnable() function.\r
+ * Refer to the corresponding function description for the details.\r
+\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickStart(void)\r
+ {\r
+ if (0u == CySysTickInitVar)\r
+ {\r
+ CySysTickInit();\r
+ CySysTickInitVar = 1u;\r
+ }\r
+\r
+ CySysTickEnable();\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickInit\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Initializes the callback addresses with pointers to NULL, associates the\r
+ * SysTick system vector with the function that is responsible for calling\r
+ * registered callback functions, configures SysTick timer to generate interrupt\r
+ * every 1 ms.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set.\r
+ *\r
+ * The 1 ms interrupt interval is configured based on the frequency determined\r
+ * by PSoC Creator at build time. If System clock frequency is changed in\r
+ * runtime, the CyDelayFreq() with the appropriate parameter should be called.\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickInit(void)\r
+ {\r
+ uint32 i;\r
+\r
+ for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)\r
+ {\r
+ CySysTickCallbacks[i] = (void *) 0;\r
+ }\r
+\r
+ (void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);\r
+ CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);\r
+ CySysTickSetReload(cydelay_freq_hz/1000u);\r
+ CySysTickClear();\r
+ CyIntEnable(CY_INT_SYSTICK_IRQN);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickEnable\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Enables the SysTick timer and its interrupt.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickEnable(void)\r
+ {\r
+ CySysTickEnableInterrupt();\r
+ CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickStop\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Stops the system timer (SysTick).\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickStop(void)\r
+ {\r
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE));\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickEnableInterrupt\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Enables the SysTick interrupt.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickEnableInterrupt(void)\r
+ {\r
+ CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE_INT;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickDisableInterrupt\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Disables the SysTick interrupt.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickDisableInterrupt(void)\r
+ {\r
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE_INT));\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickSetReload\r
+ ********************************************************************************\r
+ *\r
projects / SCSI2SD.git / commitdiff