Merge Powerbook PCB updates

diff --git a/CHANGELOG b/CHANGELOG
index b74f36f..7c694e0 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,32 @@
+201404??               3.4
+       - Fix to ensure SCSI phase bits are set atomically.
+       - Always return the requested number of bytes for a REQUEST SENSE command
+               This is required to support the Ensoniq ASR-10.
+       - Decreased (unused) heap and stack sizes to prepare for a memory
+       write cache
+
+20140416               3.3
+       - Fix to SCSI Reset handling to avoid lockups
+       - Bug fixes to improve standards compatibility
+       - Bug fix for Unit Attention Condition, which is now enabled by default.
+               scsi2sd-config can be used to disable it for those systems that
+               truely require it (eg. Mac Plus).
+       - Added Linked commands support.
+       - Added support for configurable sector sizes between 64 and 2048 bytes.
+               The sector size can be set via the MODE SELECT command using a SCSI
+               format utility, or via scsi2sd-config
+       - Powerbook firmware added
+
+20140214               3.2
+       - Remove hacks around ATN handling, and implement proper select-with-atn
+       support.  This fix is essential for communicating with some SCSI hosts.
+       All SCSI2SD users are urged to upgrade to this firmware version.
+       - More fixes to support Apple HD SC Setup (thanks to Doug Brown!)
+       - Fixes to support SCSI1 initiators
+               * Support non-arbitrating initiators.
+               * Support single-initiator option.
+               * Set CCS response format flag in INQUIRY response.
+
 20131227               3.1
        - Fixes for better SCSI reset handling
        - Fix for reading the last sector of the SD card.

diff --git a/hardware/gerber/scsi2sd.GTO b/hardware/gerber/scsi2sd.GTO
index 445feb1..ae12863 100644 (file)
--- a/hardware/gerber/scsi2sd.GTO
+++ b/hardware/gerber/scsi2sd.GTO
@@ -1,7 +1,7 @@
-G04 start of page 13 for group -4079 idx -4079 *\r
+G04 start of page 9 for group -4079 idx -4079 *\r
 G04 Title: (unknown), topsilk *\r
 G04 Creator: pcb 20110918 *\r
-G04 CreationDate: Wed 09 Oct 2013 12:59:36 GMT UTC *\r
+G04 CreationDate: Wed 12 Feb 2014 09:37:04 GMT UTC *\r
 G04 For: michael *\r
 G04 Format: Gerber/RS-274X *\r
 G04 PCB-Dimensions: 386000 393500 *\r
@@ -9,12 +9,12 @@ G04 PCB-Coordinate-Origin: lower left *
 %MOIN*%\r
 %FSLAX25Y25*%\r
 %LNTOPSILK*%\r
-%ADD155C,0.0200*%\r
-%ADD154C,0.0060*%\r
-%ADD153C,0.0100*%\r
-%ADD152C,0.0080*%\r
-%ADD151C,0.0001*%\r
-G54D151*G36*\r
+%ADD103C,0.0200*%\r
+%ADD102C,0.0060*%\r
+%ADD101C,0.0080*%\r
+%ADD100C,0.0100*%\r
+%ADD99C,0.0001*%\r
+G54D99*G36*\r
 X307500Y241000D02*X310000D01*\r
 Y232500D01*\r
 X307500D01*\r
@@ -26,20 +26,22 @@ Y232500D01*
 X204500D01*\r
 Y240500D01*\r
 G37*\r
-G54D152*X232000Y131500D02*Y132500D01*\r
-G54D153*X368500Y263000D02*Y298500D01*\r
+G54D100*X17500Y298500D02*Y263000D01*\r
+X500D02*X17500D01*\r
+Y298500D02*X500D01*\r
+Y393000D02*X385500D01*\r
+X368500Y263000D02*Y298500D01*\r
 X385500Y393000D02*Y298500D01*\r
 X368500D01*\r
 Y263000D02*X385500D01*\r
 Y500D01*\r
-X17500Y298500D02*Y263000D01*\r
+X279500Y153000D02*Y151500D01*\r
+G54D101*X232000Y131500D02*Y132500D01*\r
+G54D100*X279500Y161500D02*Y160000D01*\r
 X385500Y500D02*X500D01*\r
 Y263000D01*\r
 Y298500D02*Y393000D01*\r
-Y263000D02*X17500D01*\r
-Y298500D02*X500D01*\r
-Y393000D02*X385500D01*\r
-G54D154*X114500Y336600D02*X114900Y337000D01*\r
+G54D102*X114500Y336600D02*X114900Y337000D01*\r
 Y335000D01*\r
 X114500D02*X115250D01*\r
 X41000Y296000D02*X43000D01*\r
@@ -184,7 +186,7 @@ X194100D01*
 X194800Y34000D01*\r
 Y31000D01*\r
 X192300Y33000D02*X194800D01*\r
-G54D152*X32500Y92000D02*X33500Y91000D01*\r
+G54D101*X32500Y92000D02*X33500Y91000D01*\r
 X29500Y92000D02*X32500D01*\r
 X28500Y91000D02*X29500Y92000D01*\r
 X28500Y91000D02*Y89000D01*\r
@@ -260,7 +262,7 @@ Y85000D01*
 X99100Y84000D02*X100100Y85000D01*\r
 X97100Y84000D02*X99100D01*\r
 X96100Y86000D02*X100100Y90000D01*\r
-G54D154*X29500Y69500D02*Y68000D01*\r
+G54D102*X29500Y69500D02*Y68000D01*\r
 Y69500D02*X30000Y70000D01*\r
 X30500D01*\r
 X31000Y69500D01*\r
@@ -470,6 +472,20 @@ X75500Y77500D02*Y76000D01*
 Y77500D02*X76000Y78000D01*\r
 X77000D01*\r
 X75000D02*X75500Y77500D01*\r
+X94500Y108500D02*X96500D01*\r
+X94500D02*Y106500D01*\r
+X95000Y107000D01*\r
+X96000D01*\r
+X96500Y106500D01*\r
+Y105000D01*\r
+X96000Y104500D02*X96500Y105000D01*\r
+X95000Y104500D02*X96000D01*\r
+X94500Y105000D02*X95000Y104500D01*\r
+X97700Y108500D02*X98700Y104500D01*\r
+X99700Y108500D01*\r
+X108500Y116200D02*X109300Y117000D01*\r
+Y113000D01*\r
+X108500D02*X110000D01*\r
 X138000Y107000D02*X138250Y106750D01*\r
 X137250Y107000D02*X138000D01*\r
 X137000Y106750D02*X137250Y107000D01*\r
@@ -578,9 +594,6 @@ X140850Y95500D01*
 Y96500D02*Y95500D01*\r
 X141450Y96500D02*X141950Y94500D01*\r
 X142450Y96500D01*\r
-X108500Y116200D02*X109300Y117000D01*\r
-Y113000D01*\r
-X108500D02*X110000D01*\r
 X109200Y124500D02*X110000D01*\r
 Y121000D01*\r
 X109500Y120500D02*X110000Y121000D01*\r
@@ -629,22 +642,11 @@ Y121200D01*
 X135700Y120500D02*X136400Y121200D01*\r
 X133900Y120500D02*X135700D01*\r
 X133900Y124500D02*X135700D01*\r
-X94500Y108500D02*X96500D01*\r
-X94500D02*Y106500D01*\r
-X95000Y107000D01*\r
-X96000D01*\r
-X96500Y106500D01*\r
-Y105000D01*\r
-X96000Y104500D02*X96500Y105000D01*\r
-X95000Y104500D02*X96000D01*\r
-X94500Y105000D02*X95000Y104500D01*\r
-X97700Y108500D02*X98700Y104500D01*\r
-X99700Y108500D01*\r
-G54D152*X359800Y330900D02*Y322100D01*\r
+G54D101*X359800Y330900D02*Y322100D01*\r
 X375200D01*\r
 Y330900D02*Y322100D01*\r
 X359800Y330900D02*X375200D01*\r
-G54D153*X118000Y354500D02*X368000D01*\r
+G54D100*X118000Y354500D02*X368000D01*\r
 X118000D02*Y334500D01*\r
 X368000D01*\r
 Y354500D02*Y334500D01*\r
@@ -659,23 +661,23 @@ X151000D01*
 Y228000D02*Y215000D01*\r
 Y210000D02*Y197000D01*\r
 Y215000D02*G75*G03X151000Y210000I0J-2500D01*G01*\r
-G54D152*X202100Y269700D02*X210900D01*\r
+G54D101*X202100Y269700D02*X210900D01*\r
 X202100D02*Y254300D01*\r
 X210900D01*\r
 Y269700D02*Y254300D01*\r
-G54D154*X152728Y204291D02*X156271D01*\r
+G54D102*X152728Y204291D02*X156271D01*\r
 Y211771D02*Y204291D01*\r
 X152728Y211771D02*X156271D01*\r
 X152728D02*Y204291D01*\r
-G54D153*X6000Y330500D02*X98000D01*\r
+G54D100*X6000Y330500D02*X98000D01*\r
 X6000D02*Y389500D01*\r
 X98000D01*\r
 Y330500D01*\r
-G54D152*X71100Y233700D02*X79900D01*\r
+G54D101*X71100Y233700D02*X79900D01*\r
 X71100D02*Y218300D01*\r
 X79900D01*\r
 Y233700D02*Y218300D01*\r
-G54D153*X37000Y318500D02*X47000D01*\r
+G54D100*X37000Y318500D02*X47000D01*\r
 X37000D02*Y298500D01*\r
 X47000D01*\r
 Y318500D02*Y298500D01*\r
@@ -691,18 +693,11 @@ X77696D02*Y300536D01*
 X78484Y318646D02*Y314709D01*\r
 X77696D02*X78484D01*\r
 X77696Y317859D02*Y314709D01*\r
-X67854Y313528D02*X70216Y315890D01*\r
-X67460Y318646D01*\r
-Y313922D01*\r
-X67854Y313528D01*\r
-X61555Y315890D02*X67460D01*\r
-X71003Y318646D02*Y313134D01*\r
-X70216Y315890D02*X73366D01*\r
-G54D152*X17000Y325500D02*X27000D01*\r
+G54D101*X17000Y325500D02*X27000D01*\r
 X17000D02*Y304500D01*\r
 X27000D01*\r
 Y325500D02*Y304500D01*\r
-G54D153*X12248Y228792D02*X31146D01*\r
+G54D100*X12248Y228792D02*X31146D01*\r
 Y257532D02*Y228792D01*\r
 X12248Y257532D02*X31146D01*\r
 X12248D02*Y228792D01*\r
@@ -712,38 +707,30 @@ X13036Y234304D02*X16185D01*
 X27209Y233516D02*X31146D01*\r
 X27209Y234304D02*Y233516D01*\r
 Y234304D02*X30359D01*\r
-X26028Y244146D02*X28390Y241784D01*\r
-X31146Y244540D01*\r
-X26422D02*X31146D01*\r
-X26422D02*X26028Y244146D01*\r
-X28390Y250445D02*Y244540D01*\r
-X25634Y240997D02*X31146D01*\r
-X28390Y241784D02*Y238634D01*\r
-G54D155*X116000Y251000D02*X206000D01*\r
+G54D103*X116000Y251000D02*X206000D01*\r
 X116000Y241000D02*X206000D01*\r
-G54D153*X201000Y251000D02*Y241000D01*\r
-G54D155*X206000D02*G75*G03X206000Y251000I0J5000D01*G01*\r
+G54D100*X201000Y251000D02*Y241000D01*\r
+G54D103*X206000D02*G75*G03X206000Y251000I0J5000D01*G01*\r
 X116000D02*G75*G03X116000Y241000I0J-5000D01*G01*\r
-G54D152*X292200Y160900D02*Y152100D01*\r
+G54D101*X292200Y160900D02*Y152100D01*\r
 X276800Y160900D02*X292200D01*\r
 X276800D02*Y152100D01*\r
 X292200D01*\r
-X291200Y160900D02*Y152100D01*\r
-G54D153*X255500Y228250D02*X289500D01*\r
+G54D100*X255500Y228250D02*X289500D01*\r
 X255500D02*Y197250D01*\r
 X289500D01*\r
 Y228250D02*Y215250D01*\r
 Y210250D02*Y197250D01*\r
 Y215250D02*G75*G03X289500Y210250I0J-2500D01*G01*\r
-G54D152*X292200Y173400D02*Y164600D01*\r
+G54D101*X292200Y173400D02*Y164600D01*\r
 X276800Y173400D02*X292200D01*\r
 X276800D02*Y164600D01*\r
 X292200D01*\r
-G54D154*X292228Y202728D02*X295771D01*\r
+G54D102*X292228Y202728D02*X295771D01*\r
 Y210208D02*Y202728D01*\r
 X292228Y210208D02*X295771D01*\r
 X292228D02*Y202728D01*\r
-G54D152*X336100Y190800D02*X344900D01*\r
+G54D101*X336100Y190800D02*X344900D01*\r
 Y206200D02*Y190800D01*\r
 X336100Y206200D02*X344900D01*\r
 X336100D02*Y190800D01*\r
@@ -751,33 +738,33 @@ X302600Y269700D02*X311400D01*
 X302600D02*Y254300D01*\r
 X311400D01*\r
 Y269700D02*Y254300D01*\r
-G54D154*X230728Y204291D02*X234271D01*\r
+G54D102*X230728Y204291D02*X234271D01*\r
 Y211771D02*Y204291D01*\r
 X230728Y211771D02*X234271D01*\r
 X230728D02*Y204291D01*\r
-G54D153*X195000Y228000D02*X229000D01*\r
+G54D100*X195000Y228000D02*X229000D01*\r
 X195000D02*Y197000D01*\r
 X229000D01*\r
 Y228000D02*Y215000D01*\r
 Y210000D02*Y197000D01*\r
 Y215000D02*G75*G03X229000Y210000I0J-2500D01*G01*\r
-G54D155*X218000Y251000D02*X308000D01*\r
+G54D103*X218000Y251000D02*X308000D01*\r
 X218000Y241000D02*X308000D01*\r
-G54D153*X303000Y251000D02*Y241000D01*\r
-G54D155*X308000D02*G75*G03X308000Y251000I0J5000D01*G01*\r
+G54D100*X303000Y251000D02*Y241000D01*\r
+G54D103*X308000D02*G75*G03X308000Y251000I0J5000D01*G01*\r
 X218000D02*G75*G03X218000Y241000I0J-5000D01*G01*\r
-G54D153*X355250Y263250D02*Y211250D01*\r
+G54D100*X355250Y263250D02*Y211250D01*\r
 X323750D02*X355250D01*\r
 X323750Y263250D02*Y211250D01*\r
 Y263250D02*X355250D01*\r
 X339750Y227250D02*Y223250D01*\r
-G54D152*X168241Y149159D02*X219659D01*\r
+G54D101*X168241Y149159D02*X219659D01*\r
 Y94841D01*\r
 X165341D01*\r
 Y146259D01*\r
 X168241Y149159D01*\r
 X167241Y146259D02*G75*G03X167241Y146259I1000J0D01*G01*\r
-G54D154*X191728Y159228D02*X195271D01*\r
+G54D102*X191728Y159228D02*X195271D01*\r
 Y166708D02*Y159228D01*\r
 X191728Y166708D02*X195271D01*\r
 X191728D02*Y159228D01*\r
@@ -805,11 +792,11 @@ X160229Y158209D02*X163772D01*
 X160229D02*Y150729D01*\r
 X163772D01*\r
 Y158209D02*Y150729D01*\r
-G54D152*X132300Y158900D02*Y150100D01*\r
+G54D101*X132300Y158900D02*Y150100D01*\r
 X147700D01*\r
 Y158900D02*Y150100D01*\r
 X132300Y158900D02*X147700D01*\r
-G54D154*X160228Y85728D02*X163771D01*\r
+G54D102*X160228Y85728D02*X163771D01*\r
 Y93208D02*Y85728D01*\r
 X160228Y93208D02*X163771D01*\r
 X160228D02*Y85728D01*\r
@@ -821,7 +808,7 @@ X197729Y83209D02*X201272D01*
 X197729D02*Y75729D01*\r
 X201272D01*\r
 Y83209D02*Y75729D01*\r
-G54D152*X165800Y67900D02*Y59100D01*\r
+G54D101*X165800Y67900D02*Y59100D01*\r
 X181200D01*\r
 Y67900D02*Y59100D01*\r
 X165800Y67900D02*X181200D01*\r
@@ -829,11 +816,11 @@ X165739Y78652D02*Y69852D01*
 X181139D01*\r
 Y78652D01*\r
 X165739D01*\r
-G54D154*X192229Y83209D02*X195772D01*\r
+G54D102*X192229Y83209D02*X195772D01*\r
 X192229D02*Y75729D01*\r
 X195772D01*\r
 Y83209D02*Y75729D01*\r
-G54D153*X114894Y73500D02*X128694D01*\r
+G54D100*X114894Y73500D02*X128694D01*\r
 X114894Y118500D02*X128694D01*\r
 Y109406D01*\r
 X128700Y109400D01*\r
@@ -843,11 +830,11 @@ Y82200D02*Y73500D01*
 Y109400D02*X120300D01*\r
 Y82200D01*\r
 X114900D02*X120300D01*\r
-G54D154*X275791Y17772D02*Y14229D01*\r
+G54D102*X275791Y17772D02*Y14229D01*\r
 X283271D01*\r
 Y17772D02*Y14229D01*\r
 X275791Y17772D02*X283271D01*\r
-G54D152*X311600Y96300D02*X320400D01*\r
+G54D101*X311600Y96300D02*X320400D01*\r
 Y111700D02*Y96300D01*\r
 X311600Y111700D02*X320400D01*\r
 X311600D02*Y96300D01*\r
@@ -855,12 +842,12 @@ X359100Y95300D02*X367900D01*
 Y110700D02*Y95300D01*\r
 X359100Y110700D02*X367900D01*\r
 X359100D02*Y95300D01*\r
-G54D153*X354750Y150750D02*Y98750D01*\r
+G54D100*X354750Y150750D02*Y98750D01*\r
 X323250D02*X354750D01*\r
 X323250Y150750D02*Y98750D01*\r
 Y150750D02*X354750D01*\r
 X339250Y114750D02*Y110750D01*\r
-G54D152*X341100Y67800D02*X349900D01*\r
+G54D101*X341100Y67800D02*X349900D01*\r
 Y83200D02*Y67800D01*\r
 X341100Y83200D02*X349900D01*\r
 X341100D02*Y67800D01*\r
@@ -884,14 +871,14 @@ X287600D02*X296400D01*
 Y83200D02*Y67800D01*\r
 X287600Y83200D02*X296400D01*\r
 X287600D02*Y67800D01*\r
-G54D154*X155221Y791D02*X192229D01*\r
+G54D102*X155221Y791D02*X192229D01*\r
 X158764D02*Y2169D01*\r
 Y10634D02*Y12799D01*\r
 X188882Y791D02*Y2169D01*\r
 Y10634D02*Y12799D01*\r
 X166047Y18508D02*X167229D01*\r
 X180024D02*X181402D01*\r
-G54D152*X162500Y38500D02*Y28500D01*\r
+G54D101*X162500Y38500D02*Y28500D01*\r
 X141500Y38500D02*X162500D01*\r
 X141500D02*Y28500D01*\r
 X162500D01*\r
@@ -899,7 +886,7 @@ X245200Y78400D02*Y69600D01*
 X229800Y78400D02*X245200D01*\r
 X229800D02*Y69600D01*\r
 X245200D01*\r
-G54D154*X256000Y7000D02*X264000D01*\r
+G54D102*X256000Y7000D02*X264000D01*\r
 X256000Y12000D02*Y7000D01*\r
 X225500Y12000D02*X256000D01*\r
 X225500D02*X223000Y9500D01*\r
@@ -910,7 +897,7 @@ X254000Y64500D02*X273000D01*
 X231000D02*X244000D01*\r
 X217500D02*X221500D01*\r
 X217500D02*Y16500D01*\r
-G54D153*X123292Y65252D02*Y46354D01*\r
+G54D100*X123292Y65252D02*Y46354D01*\r
 X152032D01*\r
 Y65252D01*\r
 X123292D01*\r
@@ -920,14 +907,7 @@ Y64464D01*
 X128016Y46354D02*Y50291D01*\r
 X128804D01*\r
 Y47141D01*\r
-X138646Y51472D02*X136284Y49110D01*\r
-X139040Y46354D01*\r
-Y51078D01*\r
-X138646Y51472D01*\r
-X139040Y49110D02*X144945D01*\r
-X135497Y51866D02*Y46354D01*\r
-X133134Y49110D02*X136284D01*\r
-G54D154*X294200Y158600D02*Y154600D01*\r
+G54D102*X294200Y158600D02*Y154600D01*\r
 X296200D01*\r
 X297400Y156800D02*X298900D01*\r
 X297400Y154600D02*X299400D01*\r

diff --git a/hardware/scsi2sd.pcb b/hardware/scsi2sd.pcb
index 1763744..8ba316c 100644 (file)
--- a/hardware/scsi2sd.pcb
+++ b/hardware/scsi2sd.pcb
@@ -6,7 +6,7 @@ FileVersion[20070407]
 PCB["" 386000 393500]
 
 Grid[500.0 0 0 1]
-Cursor[85500 251000 0.000000]
+Cursor[60000 146000 0.000000]
 PolyArea[200000000.000000]
 Thermal[0.500000]
 DRC[600 100 600 600 1200 600]
@@ -938,7 +938,6 @@ Element["" "SMD_DIODE-80-50" "LED1" "unknown" 288500 237000 5700 -3100 0 100 ""]
        ElementLine [-11700 -4400 3700 -4400 800]
        ElementLine [-11700 -4400 -11700 4400 800]
        ElementLine [-11700 4400 3700 4400 800]
-       ElementLine [2700 -4400 2700 4400 800]
 
        )
 
@@ -1735,13 +1734,6 @@ Element["" "diode-DO-214AA-SMB" "D3" "unknown" 128410 338091 -4500 10000 0 100 "
        ElementLine [-394 9055 -394 5118 1000]
        ElementLine [-394 5118 394 5118 1000]
        ElementLine [394 5118 394 8268 1000]
-       ElementLine [10236 3937 7874 6299 1000]
-       ElementLine [7874 6299 10630 9055 1000]
-       ElementLine [10630 9055 10630 4331 1000]
-       ElementLine [10630 4331 10236 3937 1000]
-       ElementLine [10630 6299 16535 6299 1000]
-       ElementLine [7087 3543 7087 9055 1000]
-       ElementLine [4724 6299 7874 6299 1000]
 
        )
 
@@ -1759,13 +1751,6 @@ Element["" "diode-DO-214AA-SMB" "D1" "unknown" 78090 83909 -2181 11182 0 100 ""]
        ElementLine [394 -9055 394 -5118 1000]
        ElementLine [-394 -5118 394 -5118 1000]
        ElementLine [-394 -8268 -394 -5118 1000]
-       ElementLine [-10236 -3937 -7874 -6299 1000]
-       ElementLine [-7874 -6299 -10630 -9055 1000]
-       ElementLine [-10630 -9055 -10630 -4331 1000]
-       ElementLine [-10630 -4331 -10236 -3937 1000]
-       ElementLine [-16535 -6299 -10630 -6299 1000]
-       ElementLine [-7087 -9055 -7087 -3543 1000]
-       ElementLine [-7874 -6299 -4724 -6299 1000]
 
        )
 
@@ -1783,13 +1768,6 @@ Element["" "diode-DO-214AA-SMB" "D2" "unknown" 22091 159590 -18000 -500 1 100 ""
        ElementLine [5118 394 9055 394 1000]
        ElementLine [5118 -394 5118 394 1000]
        ElementLine [5118 -394 8268 -394 1000]
-       ElementLine [3937 -10236 6299 -7874 1000]
-       ElementLine [6299 -7874 9055 -10630 1000]
-       ElementLine [4331 -10630 9055 -10630 1000]
-       ElementLine [4331 -10630 3937 -10236 1000]
-       ElementLine [6299 -16535 6299 -10630 1000]
-       ElementLine [3543 -7087 9055 -7087 1000]
-       ElementLine [6299 -7874 6299 -4724 1000]
 
        )
 Layer(1 "component")
@@ -3298,6 +3276,8 @@ Layer(10 "silk")
        Line[17500 95000 500 95000 1000 1600 "clearline"]
        Line[500 95000 500 500 1000 1600 "clearline"]
        Line[500 500 385500 500 1000 1600 "clearline"]
+       Line[279500 232000 279500 233500 1000 1600 "clearline"]
+       Line[279500 240500 279500 242000 1000 1600 "clearline"]
        Text[94500 284000 0 100 "5V" "clearline"]
        Text[137000 286000 0 50 "SWDIO" "clearline"]
        Text[137000 291000 0 50 "SWDCK" "clearline"]

diff --git a/hardware/symbols/diode-DO-214AA-SMB.fp b/hardware/symbols/diode-DO-214AA-SMB.fp
index de93706..df639a4 100644 (file)
--- a/hardware/symbols/diode-DO-214AA-SMB.fp
+++ b/hardware/symbols/diode-DO-214AA-SMB.fp
@@ -13,12 +13,5 @@ Element["" "" "" "" 235039 155118 0 0 0 100 ""]
        ElementLine [-394 9055 -394 5118 1000]
        ElementLine [-394 5118 394 5118 1000]
        ElementLine [394 5118 394 8268 1000]
-       ElementLine [10236 3937 7874 6299 1000]
-       ElementLine [7874 6299 10630 9055 1000]
-       ElementLine [10630 9055 10630 4331 1000]
-       ElementLine [10630 4331 10236 3937 1000]
-       ElementLine [10630 6299 16535 6299 1000]
-       ElementLine [7087 3543 7087 9055 1000]
-       ElementLine [4724 6299 7874 6299 1000]
 
        )

diff --git a/parts.ods b/parts.ods
index ec09c76..abfdf77 100644 (file)
Binary files a/parts.ods and b/parts.ods differ

diff --git a/readme.txt b/readme.txt
index 0931201..daaea7c 100644 (file)
--- a/readme.txt
+++ b/readme.txt
@@ -15,12 +15,14 @@ Features
     In-built active terminator.
     Can optional supply terminator power back to the SCSI bus
     Emulates a non-removable hard drive for maximum compatibility.
+    Supports sector sizes from 64 bytes to 2048 bytes
     Firmware updatable over USB
     Highly configurable over USB
         Selectable SCSI ID
         Selectable parity support
         Enable/disable Unit Attention Condition
         Artificial limits on the SCSI disk size (eg. limit size to 4G to avoid OS bugs) 
+        Sector size (can also be set via the SCSI MODE SELECT command, as sent by SCSI format utilities).
 
 
 Technical Specifications
@@ -55,6 +57,14 @@ Tested with a 16GB class 10 SD card, via the commands:
 
 Compatibility
 
-Tested with Linux (current), Apple Macintosh System 7.5.3 on LC-III, and LC-475
-hardware. 
+Tested with Linux (current), Apple Macintosh System 7.5.3 on LC-III, and LC-475 hardware.
 
+Users have reported success on these systems:
+
+    Mac II running System 6.0.8
+    Mac SE/30
+    Roland JS-30 Sampler
+    Akai S1000, S3200, S3000XL, MPC 2000XL, DPS 12
+    EMU Emulator E4X with EOS 3.00b and E6400 (classic) with Eos 4.01
+    Ensoniq ASR-X, ASR-10 (from v3.4, 2GB size limit)
+    HP 16601A logic analyzer

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
old mode 100644 (file)
new mode 100755 (executable)
index 7d0b80b..cbb21ba
--- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
@@ -9,8 +9,8 @@ define symbol __ICFEDIT_region_ROM_end__   = 131072 - 1;
 define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2);\r
 define symbol __ICFEDIT_region_RAM_end__   = 0x20000000 + (32768 / 2) - 1;\r
 /*-Sizes-*/\r
-define symbol __ICFEDIT_size_cstack__ = 0x4000;\r
-define symbol __ICFEDIT_size_heap__   = 0x1000;\r
+define symbol __ICFEDIT_size_cstack__ = 0x2000;\r
+define symbol __ICFEDIT_size_heap__   = 0x0256;\r
 /**** End of ICF editor section. ###ICF###*/\r
 \r
 \r

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
old mode 100644 (file)
new mode 100755 (executable)
index db96f5f..fd2a0c7
--- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
@@ -112,11 +112,11 @@ APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START)
         .ANY (+RW, +ZI)\r
     }\r
 \r
-    ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x1000 - 0x4000) EMPTY 0x1000\r
+    ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0256 - 0x2000) EMPTY 0x0256\r
     {\r
     }\r
 \r
-    ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x4000\r
+    ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x2000\r
     {\r
     }\r
 }\r

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c
new file mode 100755 (executable)
index 0000000..16a0241
--- /dev/null
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c
@@ -0,0 +1,521 @@
+/*******************************************************************************
+* File Name: SCSI_CLK.c
+* Version 2.10
+*
+*  Description:
+*   This file provides the source code to the API for the clock component.
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include <cydevice_trm.h>
+#include "SCSI_CLK.h"
+
+/* Clock Distribution registers. */
+#define CLK_DIST_LD              (* (reg8 *) CYREG_CLKDIST_LD)
+#define CLK_DIST_BCFG2           (* (reg8 *) CYREG_CLKDIST_BCFG2)
+#define BCFG2_MASK               (0x80u)
+#define CLK_DIST_DMASK           (* (reg8 *) CYREG_CLKDIST_DMASK)
+#define CLK_DIST_AMASK           (* (reg8 *) CYREG_CLKDIST_AMASK)
+
+#define HAS_CLKDIST_LD_DISABLE   (CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_Start
+********************************************************************************
+*
+* Summary:
+*  Starts the clock. Note that on startup, clocks may be already running if the
+*  "Start on Reset" option is enabled in the DWR.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_Start(void) 
+{
+    /* Set the bit to enable the clock. */
+    SCSI_CLK_CLKEN |= SCSI_CLK_CLKEN_MASK;
+       SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_Stop
+********************************************************************************
+*
+* Summary:
+*  Stops the clock and returns immediately. This API does not require the
+*  source clock to be running but may return before the hardware is actually
+*  disabled. If the settings of the clock are changed after calling this
+*  function, the clock may glitch when it is started. To avoid the clock
+*  glitch, use the StopBlock function.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_Stop(void) 
+{
+    /* Clear the bit to disable the clock. */
+    SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+       SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+}
+
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_StopBlock
+********************************************************************************
+*
+* Summary:
+*  Stops the clock and waits for the hardware to actually be disabled before
+*  returning. This ensures that the clock is never truncated (high part of the
+*  cycle will terminate before the clock is disabled and the API returns).
+*  Note that the source clock must be running or this API will never return as
+*  a stopped clock cannot be disabled.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_StopBlock(void) 
+{
+    if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
+    {
+#if HAS_CLKDIST_LD_DISABLE
+        uint16 oldDivider;
+
+        CLK_DIST_LD = 0u;
+
+        /* Clear all the mask bits except ours. */
+#if defined(SCSI_CLK__CFG3)
+        CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
+        CLK_DIST_DMASK = 0x00u;
+#else
+        CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
+        CLK_DIST_AMASK = 0x00u;
+#endif /* SCSI_CLK__CFG3 */
+
+        /* Clear mask of bus clock. */
+        CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+        oldDivider = CY_GET_REG16(SCSI_CLK_DIV_PTR);
+        CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+        CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
+
+        /* Wait for clock to be disabled */
+        while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+        /* Clear the bit to disable the clock. */
+        SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+        SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+        /* Clear the disable bit */
+        CLK_DIST_LD = 0x00u;
+        CY_SET_REG16(SCSI_CLK_DIV_PTR, oldDivider);
+#endif /* HAS_CLKDIST_LD_DISABLE */
+    }
+}
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_StandbyPower
+********************************************************************************
+*
+* Summary:
+*  Sets whether the clock is active in standby mode.
+*
+* Parameters:
+*  state:  0 to disable clock during standby, nonzero to enable.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_StandbyPower(uint8 state) 
+{
+    if(state == 0u)
+    {
+        SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+    }
+    else
+    {
+        SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetDividerRegister
+********************************************************************************
+*
+* Summary:
+*  Modifies the clock divider and, thus, the frequency. When the clock divider
+*  register is set to zero or changed from zero, the clock will be temporarily
+*  disabled in order to change the SSS mode bit. If the clock is enabled when
+*  SetDividerRegister is called, then the source clock must be running.
+*
+* Parameters:
+*  clkDivider:  Divider register value (0-65,535). This value is NOT the
+*    divider; the clock hardware divides by clkDivider plus one. For example,
+*    to divide the clock by 2, this parameter should be set to 1.
+*  restart:  If nonzero, restarts the clock divider: the current clock cycle
+*   will be truncated and the new divide value will take effect immediately. If
+*   zero, the new divide value will take effect at the end of the current clock
+*   cycle.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
+                                
+{
+    uint8 enabled;
+
+    uint8 currSrc = SCSI_CLK_GetSourceRegister();
+    uint16 oldDivider = SCSI_CLK_GetDividerRegister();
+
+    if (clkDivider != oldDivider)
+    {
+        enabled = SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK;
+
+        if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
+        {
+            /* Moving to/from SSS requires correct ordering to prevent halting the clock    */
+            if (oldDivider == 0u)
+            {
+                /* Moving away from SSS, set the divider first so when SSS is cleared we    */
+                /* don't halt the clock.  Using the shadow load isn't required as the       */
+                /* divider is ignored while SSS is set.                                     */
+                CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+                SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
+            }
+            else
+            {
+                /* Moving to SSS, set SSS which then ignores the divider and we can set     */
+                /* it without bothering with the shadow load.                               */
+                SCSI_CLK_MOD_SRC |= CYCLK_SSS;
+                CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+            }
+        }
+        else
+        {
+                       
+            if (enabled != 0u)
+            {
+                CLK_DIST_LD = 0x00u;
+
+                /* Clear all the mask bits except ours. */
+#if defined(SCSI_CLK__CFG3)
+                CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
+                CLK_DIST_DMASK = 0x00u;
+#else
+                CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
+                CLK_DIST_AMASK = 0x00u;
+#endif /* SCSI_CLK__CFG3 */
+                /* Clear mask of bus clock. */
+                CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+                /* If clock is currently enabled, disable it if async or going from N-to-1*/
+                if (((SCSI_CLK_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
+                {
+#if HAS_CLKDIST_LD_DISABLE
+                    CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+                    CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
+
+                    /* Wait for clock to be disabled */
+                    while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+                    SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+                    /* Clear the disable bit */
+                    CLK_DIST_LD = 0x00u;
+#endif /* HAS_CLKDIST_LD_DISABLE */
+                }
+            }
+
+            /* Load divide value. */
+            if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
+            {
+                /* If the clock is still enabled, use the shadow registers */
+                CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
+
+                CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
+                while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+            }
+            else
+            {
+                /* If the clock is disabled, set the divider directly */
+                CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+                               SCSI_CLK_CLKEN |= enabled;
+            }
+        }
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetDividerRegister
+********************************************************************************
+*
+* Summary:
+*  Gets the clock divider register value.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  Divide value of the clock minus 1. For example, if the clock is set to
+*  divide by 2, the return value will be 1.
+*
+*******************************************************************************/
+uint16 SCSI_CLK_GetDividerRegister(void) 
+{
+    return CY_GET_REG16(SCSI_CLK_DIV_PTR);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetModeRegister
+********************************************************************************
+*
+* Summary:
+*  Sets flags that control the operating mode of the clock. This function only
+*  changes flags from 0 to 1; flags that are already 1 will remain unchanged.
+*  To clear flags, use the ClearModeRegister function. The clock must be
+*  disabled before changing the mode.
+*
+* Parameters:
+*  clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
+*   clkMode should be a set of the following optional bits or'ed together.
+*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+*                 occur when the divider count reaches half of the divide
+*                 value.
+*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
+*                 is asserted for approximately half of its period. When
+*                 disabled, the output clock is asserted for one period of the
+*                 source clock.
+*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
+*                 be enabled for all synchronous clocks.
+*   See the Technical Reference Manual for details about setting the mode of
+*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_SetModeRegister(uint8 modeBitMask) 
+{
+    SCSI_CLK_MOD_SRC |= modeBitMask & (uint8)SCSI_CLK_MODE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_ClearModeRegister
+********************************************************************************
+*
+* Summary:
+*  Clears flags that control the operating mode of the clock. This function
+*  only changes flags from 1 to 0; flags that are already 0 will remain
+*  unchanged. To set flags, use the SetModeRegister function. The clock must be
+*  disabled before changing the mode.
+*
+* Parameters:
+*  clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
+*   clkMode should be a set of the following optional bits or'ed together.
+*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+*                 occur when the divider count reaches half of the divide
+*                 value.
+*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
+*                 is asserted for approximately half of its period. When
+*                 disabled, the output clock is asserted for one period of the
+*                 source clock.
+*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
+*                 be enabled for all synchronous clocks.
+*   See the Technical Reference Manual for details about setting the mode of
+*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) 
+{
+    SCSI_CLK_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SCSI_CLK_MODE_MASK));
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetModeRegister
+********************************************************************************
+*
+* Summary:
+*  Gets the clock mode register value.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  Bit mask representing the enabled mode bits. See the SetModeRegister and
+*  ClearModeRegister descriptions for details about the mode bits.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetModeRegister(void) 
+{
+    return SCSI_CLK_MOD_SRC & (uint8)(SCSI_CLK_MODE_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetSourceRegister
+********************************************************************************
+*
+* Summary:
+*  Sets the input source of the clock. The clock must be disabled before
+*  changing the source. The old and new clock sources must be running.
+*
+* Parameters:
+*  clkSource:  For PSoC 3 and PSoC 5 devices, clkSource should be one of the
+*   following input sources:
+*   - CYCLK_SRC_SEL_SYNC_DIG
+*   - CYCLK_SRC_SEL_IMO
+*   - CYCLK_SRC_SEL_XTALM
+*   - CYCLK_SRC_SEL_ILO
+*   - CYCLK_SRC_SEL_PLL
+*   - CYCLK_SRC_SEL_XTALK
+*   - CYCLK_SRC_SEL_DSI_G
+*   - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
+*   See the Technical Reference Manual for details on clock sources.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_SetSourceRegister(uint8 clkSource) 
+{
+    uint16 currDiv = SCSI_CLK_GetDividerRegister();
+    uint8 oldSrc = SCSI_CLK_GetSourceRegister();
+
+    if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
+        (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+    {
+        /* Switching to Master and divider is 1, set SSS, which will output master, */
+        /* then set the source so we are consistent.                                */
+        SCSI_CLK_MOD_SRC |= CYCLK_SSS;
+        SCSI_CLK_MOD_SRC =
+            (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+    }
+    else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
+            (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+    {
+        /* Switching from Master to not and divider is 1, set source, so we don't   */
+        /* lock when we clear SSS.                                                  */
+        SCSI_CLK_MOD_SRC =
+            (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+        SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
+    }
+    else
+    {
+        SCSI_CLK_MOD_SRC =
+            (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetSourceRegister
+********************************************************************************
+*
+* Summary:
+*  Gets the input source of the clock.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  The input source of the clock. See SetSourceRegister for details.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetSourceRegister(void) 
+{
+    return SCSI_CLK_MOD_SRC & SCSI_CLK_SRC_SEL_MSK;
+}
+
+
+#if defined(SCSI_CLK__CFG3)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetPhaseRegister
+********************************************************************************
+*
+* Summary:
+*  Sets the phase delay of the analog clock. This function is only available
+*  for analog clocks. The clock must be disabled before changing the phase
+*  delay to avoid glitches.
+*
+* Parameters:
+*  clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
+*   clkPhase must be from 1 to 11 inclusive. Other values, including 0,
+*   disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 
+*   produces a 10ns delay.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) 
+{
+    SCSI_CLK_PHASE = clkPhase & SCSI_CLK_PHASE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetPhase
+********************************************************************************
+*
+* Summary:
+*  Gets the phase delay of the analog clock. This function is only available
+*  for analog clocks.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  Phase of the analog clock. See SetPhaseRegister for details.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetPhaseRegister(void) 
+{
+    return SCSI_CLK_PHASE & SCSI_CLK_PHASE_MASK;
+}
+
+#endif /* SCSI_CLK__CFG3 */
+
+
+/* [] END OF FILE */

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h
new file mode 100755 (executable)
index 0000000..5c91503
--- /dev/null
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h
@@ -0,0 +1,124 @@
+/*******************************************************************************
+* File Name: SCSI_CLK.h
+* Version 2.10
+*
+*  Description:
+*   Provides the function and constant definitions for the clock component.
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CLOCK_SCSI_CLK_H)
+#define CY_CLOCK_SCSI_CLK_H
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+
+/***************************************
+* Conditional Compilation Parameters
+***************************************/
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+    #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5LP) */
+
+
+/***************************************
+*        Function Prototypes
+***************************************/
+
+void SCSI_CLK_Start(void) ;
+void SCSI_CLK_Stop(void) ;
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+void SCSI_CLK_StopBlock(void) ;
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+void SCSI_CLK_StandbyPower(uint8 state) ;
+void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart) 
+                                ;
+uint16 SCSI_CLK_GetDividerRegister(void) ;
+void SCSI_CLK_SetModeRegister(uint8 modeBitMask) ;
+void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) ;
+uint8 SCSI_CLK_GetModeRegister(void) ;
+void SCSI_CLK_SetSourceRegister(uint8 clkSource) ;
+uint8 SCSI_CLK_GetSourceRegister(void) ;
+#if defined(SCSI_CLK__CFG3)
+void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) ;
+uint8 SCSI_CLK_GetPhaseRegister(void) ;
+#endif /* defined(SCSI_CLK__CFG3) */
+
+#define SCSI_CLK_Enable()                       SCSI_CLK_Start()
+#define SCSI_CLK_Disable()                      SCSI_CLK_Stop()
+#define SCSI_CLK_SetDivider(clkDivider)         SCSI_CLK_SetDividerRegister(clkDivider, 1u)
+#define SCSI_CLK_SetDividerValue(clkDivider)    SCSI_CLK_SetDividerRegister((clkDivider) - 1u, 1u)
+#define SCSI_CLK_SetMode(clkMode)               SCSI_CLK_SetModeRegister(clkMode)
+#define SCSI_CLK_SetSource(clkSource)           SCSI_CLK_SetSourceRegister(clkSource)
+#if defined(SCSI_CLK__CFG3)
+#define SCSI_CLK_SetPhase(clkPhase)             SCSI_CLK_SetPhaseRegister(clkPhase)
+#define SCSI_CLK_SetPhaseValue(clkPhase)        SCSI_CLK_SetPhaseRegister((clkPhase) + 1u)
+#endif /* defined(SCSI_CLK__CFG3) */
+
+
+/***************************************
+*             Registers
+***************************************/
+
+/* Register to enable or disable the clock */
+#define SCSI_CLK_CLKEN              (* (reg8 *) SCSI_CLK__PM_ACT_CFG)
+#define SCSI_CLK_CLKEN_PTR          ((reg8 *) SCSI_CLK__PM_ACT_CFG)
+
+/* Register to enable or disable the clock */
+#define SCSI_CLK_CLKSTBY            (* (reg8 *) SCSI_CLK__PM_STBY_CFG)
+#define SCSI_CLK_CLKSTBY_PTR        ((reg8 *) SCSI_CLK__PM_STBY_CFG)
+
+/* Clock LSB divider configuration register. */
+#define SCSI_CLK_DIV_LSB            (* (reg8 *) SCSI_CLK__CFG0)
+#define SCSI_CLK_DIV_LSB_PTR        ((reg8 *) SCSI_CLK__CFG0)
+#define SCSI_CLK_DIV_PTR            ((reg16 *) SCSI_CLK__CFG0)
+
+/* Clock MSB divider configuration register. */
+#define SCSI_CLK_DIV_MSB            (* (reg8 *) SCSI_CLK__CFG1)
+#define SCSI_CLK_DIV_MSB_PTR        ((reg8 *) SCSI_CLK__CFG1)
+
+/* Mode and source configuration register */
+#define SCSI_CLK_MOD_SRC            (* (reg8 *) SCSI_CLK__CFG2)
+#define SCSI_CLK_MOD_SRC_PTR        ((reg8 *) SCSI_CLK__CFG2)
+
+#if defined(SCSI_CLK__CFG3)
+/* Analog clock phase configuration register */
+#define SCSI_CLK_PHASE              (* (reg8 *) SCSI_CLK__CFG3)
+#define SCSI_CLK_PHASE_PTR          ((reg8 *) SCSI_CLK__CFG3)
+#endif /* defined(SCSI_CLK__CFG3) */
+
+
+/**************************************
+*       Register Constants
+**************************************/
+
+/* Power manager register masks */
+#define SCSI_CLK_CLKEN_MASK         SCSI_CLK__PM_ACT_MSK
+#define SCSI_CLK_CLKSTBY_MASK       SCSI_CLK__PM_STBY_MSK
+
+/* CFG2 field masks */
+#define SCSI_CLK_SRC_SEL_MSK        SCSI_CLK__CFG2_SRC_SEL_MASK
+#define SCSI_CLK_MODE_MASK          (~(SCSI_CLK_SRC_SEL_MSK))
+
+#if defined(SCSI_CLK__CFG3)
+/* CFG3 phase mask */
+#define SCSI_CLK_PHASE_MASK         SCSI_CLK__CFG3_PHASE_DLY_MASK
+#endif /* defined(SCSI_CLK__CFG3) */
+
+#endif /* CY_CLOCK_SCSI_CLK_H */
+
+
+/* [] END OF FILE */

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.c
new file mode 100755 (executable)
index 0000000..34c3e24
--- /dev/null
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.c
@@ -0,0 +1,754 @@
+/*******************************************************************************
+* File Name: SCSI_CMD_TIMER.c
+* Version 2.50
+*
+* Description:
+*  The Timer component consists of a 8, 16, 24 or 32-bit timer with
+*  a selectable period between 2 and 2^Width - 1.  The timer may free run
+*  or be used as a capture timer as well.  The capture can be initiated
+*  by a positive or negative edge signal as well as via software.
+*  A trigger input can be programmed to enable the timer on rising edge
+*  falling edge, either edge or continous run.
+*  Interrupts may be generated due to a terminal count condition
+*  or a capture event.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+
+#include "SCSI_CMD_TIMER.h"
+
+uint8 SCSI_CMD_TIMER_initVar = 0u;
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_Init
+********************************************************************************
+*
+* Summary:
+*  Initialize to the schematic state
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_Init(void) 
+{
+    #if(!SCSI_CMD_TIMER_UsingFixedFunction)
+            /* Interrupt State Backup for Critical Region*/
+            uint8 SCSI_CMD_TIMER_interruptState;
+    #endif /* Interrupt state back up for Fixed Function only */
+
+    #if (SCSI_CMD_TIMER_UsingFixedFunction)
+        /* Clear all bits but the enable bit (if it's already set) for Timer operation */
+        SCSI_CMD_TIMER_CONTROL &= SCSI_CMD_TIMER_CTRL_ENABLE;
+
+        /* Clear the mode bits for continuous run mode */
+        #if (CY_PSOC5A)
+            SCSI_CMD_TIMER_CONTROL2 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_MODE_MASK));
+        #endif /* Clear bits in CONTROL2 only in PSOC5A */
+
+        #if (CY_PSOC3 || CY_PSOC5LP)
+            SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_MODE_MASK));
+        #endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */
+
+        /* Check if One Shot mode is enabled i.e. RunMode !=0*/
+        #if (SCSI_CMD_TIMER_RunModeUsed != 0x0u)
+            /* Set 3rd bit of Control register to enable one shot mode */
+            SCSI_CMD_TIMER_CONTROL |= 0x04u;
+        #endif /* One Shot enabled only when RunModeUsed is not Continuous*/
+
+        #if (SCSI_CMD_TIMER_RunModeUsed == 2)
+            #if (CY_PSOC5A)
+                /* Set last 2 bits of control2 register if one shot(halt on
+                interrupt) is enabled*/
+                SCSI_CMD_TIMER_CONTROL2 |= 0x03u;
+            #endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */
+
+            #if (CY_PSOC3 || CY_PSOC5LP)
+                /* Set last 2 bits of control3 register if one shot(halt on
+                interrupt) is enabled*/
+                SCSI_CMD_TIMER_CONTROL3 |= 0x03u;
+            #endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */
+
+        #endif /* Remove section if One Shot Halt on Interrupt is not enabled */
+
+        #if (SCSI_CMD_TIMER_UsingHWEnable != 0)
+            #if (CY_PSOC5A)
+                /* Set the default Run Mode of the Timer to Continuous */
+                SCSI_CMD_TIMER_CONTROL2 |= SCSI_CMD_TIMER_CTRL_MODE_PULSEWIDTH;
+            #endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */
+
+            #if (CY_PSOC3 || CY_PSOC5LP)
+                /* Clear and Set ROD and COD bits of CFG2 register */
+                SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_RCOD_MASK));
+                SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_RCOD;
+
+                /* Clear and Enable the HW enable bit in CFG2 register */
+                SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_ENBL_MASK));
+                SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_ENBL;
+
+                /* Set the default Run Mode of the Timer to Continuous */
+                SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_MODE_CONTINUOUS;
+            #endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */
+
+        #endif /* Configure Run Mode with hardware enable */
+
+        /* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */
+        SCSI_CMD_TIMER_RT1 &= ((uint8)(~SCSI_CMD_TIMER_RT1_MASK));
+        SCSI_CMD_TIMER_RT1 |= SCSI_CMD_TIMER_SYNC;
+
+        /*Enable DSI Sync all all inputs of the Timer*/
+        SCSI_CMD_TIMER_RT1 &= ((uint8)(~SCSI_CMD_TIMER_SYNCDSI_MASK));
+        SCSI_CMD_TIMER_RT1 |= SCSI_CMD_TIMER_SYNCDSI_EN;
+
+        /* Set the IRQ to use the status register interrupts */
+        SCSI_CMD_TIMER_CONTROL2 |= SCSI_CMD_TIMER_CTRL2_IRQ_SEL;
+    #endif /* Configuring registers of fixed function implementation */
+
+    /* Set Initial values from Configuration */
+    SCSI_CMD_TIMER_WritePeriod(SCSI_CMD_TIMER_INIT_PERIOD);
+    SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_INIT_PERIOD);
+
+    #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)/* Capture counter is enabled */
+        SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL |= SCSI_CMD_TIMER_CNTR_ENABLE;
+        SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_INIT_CAPTURE_COUNT);
+    #endif /* Configure capture counter value */
+
+    #if (!SCSI_CMD_TIMER_UsingFixedFunction)
+        #if (SCSI_CMD_TIMER_SoftwareCaptureMode)
+            SCSI_CMD_TIMER_SetCaptureMode(SCSI_CMD_TIMER_INIT_CAPTURE_MODE);
+        #endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */
+
+        #if (SCSI_CMD_TIMER_SoftwareTriggerMode)
+            if (0u == (SCSI_CMD_TIMER_CONTROL & SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE))
+            {
+                SCSI_CMD_TIMER_SetTriggerMode(SCSI_CMD_TIMER_INIT_TRIGGER_MODE);
+            }
+        #endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */
+
+        /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
+        /* Enter Critical Region*/
+        SCSI_CMD_TIMER_interruptState = CyEnterCriticalSection();
+
+        /* Use the interrupt output of the status register for IRQ output */
+        SCSI_CMD_TIMER_STATUS_AUX_CTRL |= SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK;
+
+        /* Exit Critical Region*/
+        CyExitCriticalSection(SCSI_CMD_TIMER_interruptState);
+
+        #if (SCSI_CMD_TIMER_EnableTriggerMode)
+            SCSI_CMD_TIMER_EnableTrigger();
+        #endif /* Set Trigger enable bit for UDB implementation in the control register*/
+
+        #if (SCSI_CMD_TIMER_InterruptOnCaptureCount)
+             #if (!SCSI_CMD_TIMER_ControlRegRemoved)
+                SCSI_CMD_TIMER_SetInterruptCount(SCSI_CMD_TIMER_INIT_INT_CAPTURE_COUNT);
+            #endif /* Set interrupt count in control register if control register is not removed */
+        #endif /*Set interrupt count in UDB implementation if interrupt count feature is checked.*/
+
+        SCSI_CMD_TIMER_ClearFIFO();
+    #endif /* Configure additional features of UDB implementation */
+
+    SCSI_CMD_TIMER_SetInterruptMode(SCSI_CMD_TIMER_INIT_INTERRUPT_MODE);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_Enable
+********************************************************************************
+*
+* Summary:
+*  Enable the Timer
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_Enable(void) 
+{
+    /* Globally Enable the Fixed Function Block chosen */
+    #if (SCSI_CMD_TIMER_UsingFixedFunction)
+        SCSI_CMD_TIMER_GLOBAL_ENABLE |= SCSI_CMD_TIMER_BLOCK_EN_MASK;
+        SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE |= SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK;
+    #endif /* Set Enable bit for enabling Fixed function timer*/
+
+    /* Remove assignment if control register is removed */
+    #if (!SCSI_CMD_TIMER_ControlRegRemoved || SCSI_CMD_TIMER_UsingFixedFunction)
+        SCSI_CMD_TIMER_CONTROL |= SCSI_CMD_TIMER_CTRL_ENABLE;
+    #endif /* Remove assignment if control register is removed */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_Start
+********************************************************************************
+*
+* Summary:
+*  The start function initializes the timer with the default values, the
+*  enables the timerto begin counting.  It does not enable interrupts,
+*  the EnableInt command should be called if interrupt generation is required.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Global variables:
+*  SCSI_CMD_TIMER_initVar: Is modified when this function is called for the
+*   first time. Is used to ensure that initialization happens only once.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_Start(void) 
+{
+    if(SCSI_CMD_TIMER_initVar == 0u)
+    {
+        SCSI_CMD_TIMER_Init();
+
+        SCSI_CMD_TIMER_initVar = 1u;   /* Clear this bit for Initialization */
+    }
+
+    /* Enable the Timer */
+    SCSI_CMD_TIMER_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_Stop
+********************************************************************************
+*
+* Summary:
+*  The stop function halts the timer, but does not change any modes or disable
+*  interrupts.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Side Effects: If the Enable mode is set to Hardware only then this function
+*               has no effect on the operation of the timer.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_Stop(void) 
+{
+    /* Disable Timer */
+    #if(!SCSI_CMD_TIMER_ControlRegRemoved || SCSI_CMD_TIMER_UsingFixedFunction)
+        SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_ENABLE));
+    #endif /* Remove assignment if control register is removed */
+
+    /* Globally disable the Fixed Function Block chosen */
+    #if (SCSI_CMD_TIMER_UsingFixedFunction)
+        SCSI_CMD_TIMER_GLOBAL_ENABLE &= ((uint8)(~SCSI_CMD_TIMER_BLOCK_EN_MASK));
+        SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE &= ((uint8)(~SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK));
+    #endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SetInterruptMode
+********************************************************************************
+*
+* Summary:
+*  This function selects which of the interrupt inputs may cause an interrupt.
+*  The twosources are caputure and terminal.  One, both or neither may
+*  be selected.
+*
+* Parameters:
+*  interruptMode:   This parameter is used to enable interrups on either/or
+*                   terminal count or capture.
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SetInterruptMode(uint8 interruptMode) 
+{
+    SCSI_CMD_TIMER_STATUS_MASK = interruptMode;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SoftwareCapture
+********************************************************************************
+*
+* Summary:
+*  This function forces a capture independent of the capture signal.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Side Effects:
+*  An existing hardware capture could be overwritten.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SoftwareCapture(void) 
+{
+    /* Generate a software capture by reading the counter register */
+    (void)SCSI_CMD_TIMER_COUNTER_LSB;
+    /* Capture Data is now in the FIFO */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ReadStatusRegister
+********************************************************************************
+*
+* Summary:
+*  Reads the status register and returns it's state. This function should use
+*  defined types for the bit-field information as the bits in this register may
+*  be permuteable.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  The contents of the status register
+*
+* Side Effects:
+*  Status register bits may be clear on read.
+*
+*******************************************************************************/
+uint8   SCSI_CMD_TIMER_ReadStatusRegister(void) 
+{
+    return (SCSI_CMD_TIMER_STATUS);
+}
+
+
+#if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove API if control register is removed */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ReadControlRegister
+********************************************************************************
+*
+* Summary:
+*  Reads the control register and returns it's value.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  The contents of the control register
+*
+*******************************************************************************/
+uint8 SCSI_CMD_TIMER_ReadControlRegister(void) 
+{
+    return ((uint8)SCSI_CMD_TIMER_CONTROL);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_WriteControlRegister
+********************************************************************************
+*
+* Summary:
+*  Sets the bit-field of the control register.
+*
+* Parameters:
+*  control: The contents of the control register
+*
+* Return:
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_WriteControlRegister(uint8 control) 
+{
+    SCSI_CMD_TIMER_CONTROL = control;
+}
+#endif /* Remove API if control register is removed */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ReadPeriod
+********************************************************************************
+*
+* Summary:
+*  This function returns the current value of the Period.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  The present value of the counter.
+*
+*******************************************************************************/
+uint16 SCSI_CMD_TIMER_ReadPeriod(void) 
+{
+   #if(SCSI_CMD_TIMER_UsingFixedFunction)
+       return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR));
+   #else
+       return (CY_GET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR));
+   #endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_WritePeriod
+********************************************************************************
+*
+* Summary:
+*  This function is used to change the period of the counter.  The new period
+*  will be loaded the next time terminal count is detected.
+*
+* Parameters:
+*  period: This value may be between 1 and (2^Resolution)-1.  A value of 0 will
+*          result in the counter remaining at zero.
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_WritePeriod(uint16 period) 
+{
+    #if(SCSI_CMD_TIMER_UsingFixedFunction)
+        uint16 period_temp = (uint16)period;
+        CY_SET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR, period_temp);
+    #else
+        CY_SET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR, period);
+    #endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ReadCapture
+********************************************************************************
+*
+* Summary:
+*  This function returns the last value captured.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  Present Capture value.
+*
+*******************************************************************************/
+uint16 SCSI_CMD_TIMER_ReadCapture(void) 
+{
+   #if(SCSI_CMD_TIMER_UsingFixedFunction)
+       return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
+   #else
+       return (CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
+   #endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_WriteCounter
+********************************************************************************
+*
+* Summary:
+*  This funtion is used to set the counter to a specific value
+*
+* Parameters:
+*  counter:  New counter value.
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_WriteCounter(uint16 counter) \
+                                   
+{
+   #if(SCSI_CMD_TIMER_UsingFixedFunction)
+        /* This functionality is removed until a FixedFunction HW update to
+         * allow this register to be written
+         */
+        CY_SET_REG16(SCSI_CMD_TIMER_COUNTER_LSB_PTR, (uint16)counter);
+        
+    #else
+        CY_SET_REG16(SCSI_CMD_TIMER_COUNTER_LSB_PTR, counter);
+    #endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ReadCounter
+********************************************************************************
+*
+* Summary:
+*  This function returns the current counter value.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  Present compare value.
+*
+*******************************************************************************/
+uint16 SCSI_CMD_TIMER_ReadCounter(void) 
+{
+
+    /* Force capture by reading Accumulator */
+    /* Must first do a software capture to be able to read the counter */
+    /* It is up to the user code to make sure there isn't already captured data in the FIFO */
+    (void)SCSI_CMD_TIMER_COUNTER_LSB;
+
+    /* Read the data from the FIFO (or capture register for Fixed Function)*/
+    #if(SCSI_CMD_TIMER_UsingFixedFunction)
+        return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
+    #else
+        return (CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
+    #endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
+}
+
+
+#if(!SCSI_CMD_TIMER_UsingFixedFunction) /* UDB Specific Functions */
+
+/*******************************************************************************
+ * The functions below this point are only available using the UDB
+ * implementation.  If a feature is selected, then the API is enabled.
+ ******************************************************************************/
+
+
+#if (SCSI_CMD_TIMER_SoftwareCaptureMode)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SetCaptureMode
+********************************************************************************
+*
+* Summary:
+*  This function sets the capture mode to either rising or falling edge.
+*
+* Parameters:
+*  captureMode: This parameter sets the capture mode of the UDB capture feature
+*  The parameter values are defined using the
+*  #define SCSI_CMD_TIMER__B_TIMER__CM_NONE 0
+#define SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE 1
+#define SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE 2
+#define SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE 3
+#define SCSI_CMD_TIMER__B_TIMER__CM_SOFTWARE 4
+ identifiers
+*  The following are the possible values of the parameter
+*  SCSI_CMD_TIMER__B_TIMER__CM_NONE        - Set Capture mode to None
+*  SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE  - Rising edge of Capture input
+*  SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input
+*  SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE  - Either edge of Capture input
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SetCaptureMode(uint8 captureMode) 
+{
+    /* This must only set to two bits of the control register associated */
+    captureMode = ((uint8)((uint8)captureMode << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT));
+    captureMode &= (SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK);
+
+    /* Clear the Current Setting */
+    SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK));
+
+    /* Write The New Setting */
+    SCSI_CMD_TIMER_CONTROL |= captureMode;
+}
+#endif /* Remove API if Capture Mode is not Software Controlled */
+
+
+#if (SCSI_CMD_TIMER_SoftwareTriggerMode)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SetTriggerMode
+********************************************************************************
+*
+* Summary:
+*  This function sets the trigger input mode
+*
+* Parameters:
+*  triggerMode: Pass one of the pre-defined Trigger Modes (except Software)
+    #define SCSI_CMD_TIMER__B_TIMER__TM_NONE 0x00u
+    #define SCSI_CMD_TIMER__B_TIMER__TM_RISINGEDGE 0x04u
+    #define SCSI_CMD_TIMER__B_TIMER__TM_FALLINGEDGE 0x08u
+    #define SCSI_CMD_TIMER__B_TIMER__TM_EITHEREDGE 0x0Cu
+    #define SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE 0x10u
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SetTriggerMode(uint8 triggerMode) 
+{
+    /* This must only set to two bits of the control register associated */
+    triggerMode &= SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK;
+
+    /* Clear the Current Setting */
+    SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK));
+
+    /* Write The New Setting */
+    SCSI_CMD_TIMER_CONTROL |= (triggerMode | SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE);
+
+}
+#endif /* Remove API if Trigger Mode is not Software Controlled */
+
+#if (SCSI_CMD_TIMER_EnableTriggerMode)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_EnableTrigger
+********************************************************************************
+*
+* Summary:
+*  Sets the control bit enabling Hardware Trigger mode
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_EnableTrigger(void) 
+{
+    #if (!SCSI_CMD_TIMER_ControlRegRemoved)   /* Remove assignment if control register is removed */
+        SCSI_CMD_TIMER_CONTROL |= SCSI_CMD_TIMER_CTRL_TRIG_EN;
+    #endif /* Remove code section if control register is not used */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_DisableTrigger
+********************************************************************************
+*
+* Summary:
+*  Clears the control bit enabling Hardware Trigger mode
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_DisableTrigger(void) 
+{
+    #if (!SCSI_CMD_TIMER_ControlRegRemoved)   /* Remove assignment if control register is removed */
+        SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_TRIG_EN));
+    #endif /* Remove code section if control register is not used */
+}
+#endif /* Remove API is Trigger Mode is set to None */
+
+
+#if(SCSI_CMD_TIMER_InterruptOnCaptureCount)
+#if (!SCSI_CMD_TIMER_ControlRegRemoved)   /* Remove API if control register is removed */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SetInterruptCount
+********************************************************************************
+*
+* Summary:
+*  This function sets the capture count before an interrupt is triggered.
+*
+* Parameters:
+*  interruptCount:  A value between 0 and 3 is valid.  If the value is 0, then
+*                   an interrupt will occur each time a capture occurs.
+*                   A value of 1 to 3 will cause the interrupt
+*                   to delay by the same number of captures.
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SetInterruptCount(uint8 interruptCount) 
+{
+    /* This must only set to two bits of the control register associated */
+    interruptCount &= SCSI_CMD_TIMER_CTRL_INTCNT_MASK;
+
+    /* Clear the Current Setting */
+    SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_INTCNT_MASK));
+    /* Write The New Setting */
+    SCSI_CMD_TIMER_CONTROL |= interruptCount;
+}
+#endif /* Remove API if control register is removed */
+#endif /* SCSI_CMD_TIMER_InterruptOnCaptureCount */
+
+
+#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SetCaptureCount
+********************************************************************************
+*
+* Summary:
+*  This function sets the capture count
+*
+* Parameters:
+*  captureCount: A value between 2 and 127 inclusive is valid.  A value of 1
+*                to 127 will cause the interrupt to delay by the same number of
+*                captures.
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SetCaptureCount(uint8 captureCount) 
+{
+    SCSI_CMD_TIMER_CAP_COUNT = captureCount;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ReadCaptureCount
+********************************************************************************
+*
+* Summary:
+*  This function reads the capture count setting
+*
+* Parameters:
+*  void
+*
+* Return:
+*  Returns the Capture Count Setting
+*
+*******************************************************************************/
+uint8 SCSI_CMD_TIMER_ReadCaptureCount(void) 
+{
+    return ((uint8)SCSI_CMD_TIMER_CAP_COUNT);
+}
+#endif /* SCSI_CMD_TIMER_UsingHWCaptureCounter */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ClearFIFO
+********************************************************************************
+*
+* Summary:
+*  This function clears all capture data from the capture FIFO
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ClearFIFO(void) 
+{
+    while(0u != (SCSI_CMD_TIMER_ReadStatusRegister() & SCSI_CMD_TIMER_STATUS_FIFONEMP))
+    {
+        (void)SCSI_CMD_TIMER_ReadCapture();
+    }
+}
+
+#endif /* UDB Specific Functions */
+
+
+/* [] END OF FILE */

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.c
new file mode 100755 (executable)
index 0000000..1093726
--- /dev/null
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.c
@@ -0,0 +1,356 @@
+/*******************************************************************************
+* File Name: SCSI_CMD_TIMER_ISR.c  
+* Version 1.70
+*
+*  Description:
+*   API for controlling the state of an interrupt.
+*
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_CMD_TIMER_ISR.h>
+
+#if !defined(SCSI_CMD_TIMER_ISR__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+*  Place your includes, defines and code here 
+********************************************************************************/
+/* `#START SCSI_CMD_TIMER_ISR_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE      16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_Start
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_Start(void)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_CMD_TIMER_ISR_Disable();
+
+    /* Set the ISR to point to the SCSI_CMD_TIMER_ISR Interrupt. */
+    SCSI_CMD_TIMER_ISR_SetVector(&SCSI_CMD_TIMER_ISR_Interrupt);
+
+    /* Set the priority. */
+    SCSI_CMD_TIMER_ISR_SetPriority((uint8)SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_CMD_TIMER_ISR_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_StartEx
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it.
+*
+* Parameters:  
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_StartEx(cyisraddress address)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_CMD_TIMER_ISR_Disable();
+
+    /* Set the ISR to point to the SCSI_CMD_TIMER_ISR Interrupt. */
+    SCSI_CMD_TIMER_ISR_SetVector(address);
+
+    /* Set the priority. */
+    SCSI_CMD_TIMER_ISR_SetPriority((uint8)SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_CMD_TIMER_ISR_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_Stop
+********************************************************************************
+*
+* Summary:
+*   Disables and removes the interrupt.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_Stop(void)
+{
+    /* Disable this interrupt. */
+    SCSI_CMD_TIMER_ISR_Disable();
+
+    /* Set the ISR to point to the passive one. */
+    SCSI_CMD_TIMER_ISR_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_Interrupt
+********************************************************************************
+*
+* Summary:
+*   The default Interrupt Service Routine for SCSI_CMD_TIMER_ISR.
+*
+*   Add custom code between the coments to keep the next version of this file
+*   from over writting your code.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+CY_ISR(SCSI_CMD_TIMER_ISR_Interrupt)
+{
+    /*  Place your Interrupt code here. */
+    /* `#START SCSI_CMD_TIMER_ISR_Interrupt` */
+
+    /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_SetVector
+********************************************************************************
+*
+* Summary:
+*   Change the ISR vector for the Interrupt. Note calling SCSI_CMD_TIMER_ISR_Start
+*   will override any effect this method would have had. To set the vector 
+*   before the component has been started use SCSI_CMD_TIMER_ISR_StartEx instead.
+*
+* Parameters:
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_SetVector(cyisraddress address)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_CMD_TIMER_ISR__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_GetVector
+********************************************************************************
+*
+* Summary:
+*   Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_CMD_TIMER_ISR_GetVector(void)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_CMD_TIMER_ISR__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_SetPriority
+********************************************************************************
+*
+* Summary:
+*   Sets the Priority of the Interrupt. Note calling SCSI_CMD_TIMER_ISR_Start
+*   or SCSI_CMD_TIMER_ISR_StartEx will override any effect this method 
+*   would have had. This method should only be called after 
+*   SCSI_CMD_TIMER_ISR_Start or SCSI_CMD_TIMER_ISR_StartEx has been called. To set 
+*   the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_SetPriority(uint8 priority)
+{
+    *SCSI_CMD_TIMER_ISR_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_GetPriority
+********************************************************************************
+*
+* Summary:
+*   Gets the Priority of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SCSI_CMD_TIMER_ISR_GetPriority(void)
+{
+    uint8 priority;
+
+
+    priority = *SCSI_CMD_TIMER_ISR_INTC_PRIOR >> 5;
+
+    return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_Enable
+********************************************************************************
+*
+* Summary:
+*   Enables the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_Enable(void)
+{
+    /* Enable the general interrupt. */
+    *SCSI_CMD_TIMER_ISR_INTC_SET_EN = SCSI_CMD_TIMER_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_GetState
+********************************************************************************
+*
+* Summary:
+*   Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_CMD_TIMER_ISR_GetState(void)
+{
+    /* Get the state of the general interrupt. */
+    return ((*SCSI_CMD_TIMER_ISR_INTC_SET_EN & (uint32)SCSI_CMD_TIMER_ISR__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_Disable
+********************************************************************************
+*
+* Summary:
+*   Disables the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_Disable(void)
+{
+    /* Disable the general interrupt. */
+    *SCSI_CMD_TIMER_ISR_INTC_CLR_EN = SCSI_CMD_TIMER_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_SetPending
+********************************************************************************
+*
+* Summary:
+*   Causes the Interrupt to enter the pending state, a software method of
+*   generating the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_SetPending(void)
+{
+    *SCSI_CMD_TIMER_ISR_INTC_SET_PD = SCSI_CMD_TIMER_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_ClearPending
+********************************************************************************
+*
+* Summary:
+*   Clears a pending interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_ClearPending(void)
+{
+    *SCSI_CMD_TIMER_ISR_INTC_CLR_PD = SCSI_CMD_TIMER_ISR__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.h
new file mode 100755 (executable)
index 0000000..0454ab4
--- /dev/null
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.h
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* File Name: SCSI_CMD_TIMER_ISR.h
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_CMD_TIMER_ISR_H)
+#define CY_ISR_SCSI_CMD_TIMER_ISR_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_CMD_TIMER_ISR_Start(void);
+void SCSI_CMD_TIMER_ISR_StartEx(cyisraddress address);
+void SCSI_CMD_TIMER_ISR_Stop(void);
+
+CY_ISR_PROTO(SCSI_CMD_TIMER_ISR_Interrupt);
+
+void SCSI_CMD_TIMER_ISR_SetVector(cyisraddress address);
+cyisraddress SCSI_CMD_TIMER_ISR_GetVector(void);
+
+void SCSI_CMD_TIMER_ISR_SetPriority(uint8 priority);
+uint8 SCSI_CMD_TIMER_ISR_GetPriority(void);
+
+void SCSI_CMD_TIMER_ISR_Enable(void);
+uint8 SCSI_CMD_TIMER_ISR_GetState(void);
+void SCSI_CMD_TIMER_ISR_Disable(void);
+
+void SCSI_CMD_TIMER_ISR_SetPending(void);
+void SCSI_CMD_TIMER_ISR_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_CMD_TIMER_ISR ISR. */
+#define SCSI_CMD_TIMER_ISR_INTC_VECTOR            ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_VECT)
+
+/* Address of the SCSI_CMD_TIMER_ISR ISR priority. */
+#define SCSI_CMD_TIMER_ISR_INTC_PRIOR             ((reg8 *) SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_CMD_TIMER_ISR interrupt. */
+#define SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER      SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_CMD_TIMER_ISR interrupt. */
+#define SCSI_CMD_TIMER_ISR_INTC_SET_EN            ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_CMD_TIMER_ISR interrupt. */
+#define SCSI_CMD_TIMER_ISR_INTC_CLR_EN            ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_CMD_TIMER_ISR interrupt state to pending. */
+#define SCSI_CMD_TIMER_ISR_INTC_SET_PD            ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_CMD_TIMER_ISR interrupt. */
+#define SCSI_CMD_TIMER_ISR_INTC_CLR_PD            ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_CMD_TIMER_ISR_H */
+
+
+/* [] END OF FILE */

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_PM.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_PM.c
new file mode 100755 (executable)
index 0000000..f9556fa
--- /dev/null
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_PM.c
@@ -0,0 +1,194 @@
+/*******************************************************************************
+* File Name: SCSI_CMD_TIMER_PM.c
+* Version 2.50
+*
+*  Description:
+*     This file provides the power management source code to API for the
+*     Timer.
+*
+*   Note:
+*     None
+*
+*******************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+
+#include "SCSI_CMD_TIMER.h"
+static SCSI_CMD_TIMER_backupStruct SCSI_CMD_TIMER_backup;
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SaveConfig
+********************************************************************************
+*
+* Summary:
+*     Save the current user configuration
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Global variables:
+*  SCSI_CMD_TIMER_backup:  Variables of this global structure are modified to
+*  store the values of non retention configuration registers when Sleep() API is
+*  called.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SaveConfig(void) 
+{
+    #if (!SCSI_CMD_TIMER_UsingFixedFunction)
+        /* Backup the UDB non-rentention registers for CY_UDB_V0 */
+        #if (CY_UDB_V0)
+            SCSI_CMD_TIMER_backup.TimerUdb = SCSI_CMD_TIMER_ReadCounter();
+            SCSI_CMD_TIMER_backup.TimerPeriod = SCSI_CMD_TIMER_ReadPeriod();
+            SCSI_CMD_TIMER_backup.InterruptMaskValue = SCSI_CMD_TIMER_STATUS_MASK;
+            #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+                SCSI_CMD_TIMER_backup.TimerCaptureCounter = SCSI_CMD_TIMER_ReadCaptureCount();
+            #endif /* Backup the UDB non-rentention register capture counter for CY_UDB_V0 */
+        #endif /* Backup the UDB non-rentention registers for CY_UDB_V0 */
+
+        #if (CY_UDB_V1)
+            SCSI_CMD_TIMER_backup.TimerUdb = SCSI_CMD_TIMER_ReadCounter();
+            SCSI_CMD_TIMER_backup.InterruptMaskValue = SCSI_CMD_TIMER_STATUS_MASK;
+            #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+                SCSI_CMD_TIMER_backup.TimerCaptureCounter = SCSI_CMD_TIMER_ReadCaptureCount();
+            #endif /* Back Up capture counter register  */
+        #endif /* Backup non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
+
+        #if(!SCSI_CMD_TIMER_ControlRegRemoved)
+            SCSI_CMD_TIMER_backup.TimerControlRegister = SCSI_CMD_TIMER_ReadControlRegister();
+        #endif /* Backup the enable state of the Timer component */
+    #endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_RestoreConfig
+********************************************************************************
+*
+* Summary:
+*  Restores the current user configuration.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Global variables:
+*  SCSI_CMD_TIMER_backup:  Variables of this global structure are used to
+*  restore the values of non retention registers on wakeup from sleep mode.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_RestoreConfig(void) 
+{   
+    #if (!SCSI_CMD_TIMER_UsingFixedFunction)
+        /* Restore the UDB non-rentention registers for CY_UDB_V0 */
+        #if (CY_UDB_V0)
+            /* Interrupt State Backup for Critical Region*/
+            uint8 SCSI_CMD_TIMER_interruptState;
+
+            SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_backup.TimerUdb);
+            SCSI_CMD_TIMER_WritePeriod(SCSI_CMD_TIMER_backup.TimerPeriod);
+            /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
+            /* Enter Critical Region*/
+            SCSI_CMD_TIMER_interruptState = CyEnterCriticalSection();
+            /* Use the interrupt output of the status register for IRQ output */
+            SCSI_CMD_TIMER_STATUS_AUX_CTRL |= SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK;
+            /* Exit Critical Region*/
+            CyExitCriticalSection(SCSI_CMD_TIMER_interruptState);
+            SCSI_CMD_TIMER_STATUS_MASK =SCSI_CMD_TIMER_backup.InterruptMaskValue;
+            #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+                SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_backup.TimerCaptureCounter);
+            #endif /* Restore the UDB non-rentention register capture counter for CY_UDB_V0 */
+        #endif /* Restore the UDB non-rentention registers for CY_UDB_V0 */
+
+        #if (CY_UDB_V1)
+            SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_backup.TimerUdb);
+            SCSI_CMD_TIMER_STATUS_MASK =SCSI_CMD_TIMER_backup.InterruptMaskValue;
+            #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+                SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_backup.TimerCaptureCounter);
+            #endif /* Restore Capture counter register*/
+        #endif /* Restore up non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
+
+        #if(!SCSI_CMD_TIMER_ControlRegRemoved)
+            SCSI_CMD_TIMER_WriteControlRegister(SCSI_CMD_TIMER_backup.TimerControlRegister);
+        #endif /* Restore the enable state of the Timer component */
+    #endif /* Restore non retention registers in the UDB implementation only */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_Sleep
+********************************************************************************
+*
+* Summary:
+*     Stop and Save the user configuration
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Global variables:
+*  SCSI_CMD_TIMER_backup.TimerEnableState:  Is modified depending on the
+*  enable state of the block before entering sleep mode.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_Sleep(void) 
+{
+    #if(!SCSI_CMD_TIMER_ControlRegRemoved)
+        /* Save Counter's enable state */
+        if(SCSI_CMD_TIMER_CTRL_ENABLE == (SCSI_CMD_TIMER_CONTROL & SCSI_CMD_TIMER_CTRL_ENABLE))
+        {
+            /* Timer is enabled */
+            SCSI_CMD_TIMER_backup.TimerEnableState = 1u;
+        }
+        else
+        {
+            /* Timer is disabled */
+            SCSI_CMD_TIMER_backup.TimerEnableState = 0u;
+        }
+    #endif /* Back up enable state from the Timer control register */
+    SCSI_CMD_TIMER_Stop();
+    SCSI_CMD_TIMER_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_Wakeup
+********************************************************************************
+*
+* Summary:
+*  Restores and enables the user configuration
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Global variables:
+*  SCSI_CMD_TIMER_backup.enableState:  Is used to restore the enable state of
+*  block on wakeup from sleep mode.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_Wakeup(void) 
+{
+    SCSI_CMD_TIMER_RestoreConfig();
+    #if(!SCSI_CMD_TIMER_ControlRegRemoved)
+        if(SCSI_CMD_TIMER_backup.TimerEnableState == 1u)
+        {     /* Enable Timer's operation */
+                SCSI_CMD_TIMER_Enable();
+        } /* Do nothing if Timer was disabled before */
+    #endif /* Remove this code section if Control register is removed */
+}
+
+
+/* [] END OF FILE */

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c
deleted file mode 100644 (file)
index 34503f1..0000000
--- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*******************************************************************************\r
-* File Name: SCSI_CTL_IO.c  \r
-* Version 1.70\r
-*\r
-* Description:\r
-*  This file contains API to enable firmware control of a Control Register.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "SCSI_CTL_IO.h"\r
-\r
-#if !defined(SCSI_CTL_IO_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_CTL_IO_Write\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Write a byte to the Control Register.\r
-*\r
-* Parameters:\r
-*  control:  The value to be assigned to the Control Register.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-*******************************************************************************/\r
-void SCSI_CTL_IO_Write(uint8 control) \r
-{\r
-    SCSI_CTL_IO_Control = control;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_CTL_IO_Read\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Reads the current value assigned to the Control Register.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  Returns the current value in the Control Register.\r
-*\r
-*******************************************************************************/\r
-uint8 SCSI_CTL_IO_Read(void) \r
-{\r
-    return SCSI_CTL_IO_Control;\r
-}\r
-\r
-#endif /* End check for removal by optimization */\r
-\r
-\r
-/* [] END OF FILE */\r

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h
deleted file mode 100644 (file)
index 849b8e2..0000000
--- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*******************************************************************************\r
-* File Name: SCSI_CTL_IO.h  \r
-* Version 1.70\r
-*\r
-* Description:\r
-*  This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_CONTROL_REG_SCSI_CTL_IO_H) /* CY_CONTROL_REG_SCSI_CTL_IO_H */\r
-#define CY_CONTROL_REG_SCSI_CTL_IO_H\r
-\r
-#include "cytypes.h"\r
-\r
-\r
-/***************************************\r
-*         Function Prototypes \r
-***************************************/\r
-\r
-void    SCSI_CTL_IO_Write(uint8 control) ;\r
-uint8   SCSI_CTL_IO_Read(void) ;\r
-\r
-\r
-/***************************************\r
-*            Registers        \r
-***************************************/\r
-\r
-/* Control Register */\r
-#define SCSI_CTL_IO_Control        (* (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )\r
-#define SCSI_CTL_IO_Control_PTR    (  (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )\r
-\r
-#endif /* End CY_CONTROL_REG_SCSI_CTL_IO_H */\r
-\r
-\r
-/* [] END OF FILE */\r

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c
new file mode 100755 (executable)
index 0000000..eadf7a3
--- /dev/null
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c
@@ -0,0 +1,63 @@
+/*******************************************************************************
+* File Name: SCSI_CTL_PHASE.c  
+* Version 1.70
+*
+* Description:
+*  This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_CTL_PHASE.h"
+
+#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Write
+********************************************************************************
+*
+* Summary:
+*  Write a byte to the Control Register.
+*
+* Parameters:
+*  control:  The value to be assigned to the Control Register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_Write(uint8 control) 
+{
+    SCSI_CTL_PHASE_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Control Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_CTL_PHASE_Read(void) 
+{
+    return SCSI_CTL_PHASE_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h
new file mode 100755 (executable)
index 0000000..00cbb37
--- /dev/null
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h
@@ -0,0 +1,42 @@
+/*******************************************************************************
+* File Name: SCSI_CTL_PHASE.h  
+* Version 1.70
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */
+#define CY_CONTROL_REG_SCSI_CTL_PHASE_H
+
+#include "cytypes.h"
+
+
+/***************************************
+*         Function Prototypes 
+***************************************/
+
+void    SCSI_CTL_PHASE_Write(uint8 control) ;
+uint8   SCSI_CTL_PHASE_Read(void) ;
+
+
+/***************************************
+*            Registers        
+***************************************/
+
+/* Control Register */
+#define SCSI_CTL_PHASE_Control        (* (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_CTL_PHASE_Control_PTR    (  (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_CTL_PHASE_H */
+
+
+/* [] END OF FILE */

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
old mode 100644 (file)
new mode 100755 (executable)
index e8aa91f..7b32a93
--- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
@@ -41,9 +41,9 @@
 #define SCSI_Out_BSY           SCSI_Out__BSY__PC\r
 #define SCSI_Out_ACK           SCSI_Out__ACK__PC\r
 #define SCSI_Out_RST           SCSI_Out__RST__PC\r
-#define SCSI_Out_MSG           SCSI_Out__MSG__PC\r
+#define SCSI_Out_MSG_raw               SCSI_Out__MSG_raw__PC\r
 #define SCSI_Out_SEL           SCSI_Out__SEL__PC\r
-#define SCSI_Out_CD            SCSI_Out__CD__PC\r
+#define SCSI_Out_CD_raw                SCSI_Out__CD_raw__PC\r
 #define SCSI_Out_REQ           SCSI_Out__REQ__PC\r
 #define SCSI_Out_IO_raw                SCSI_Out__IO_raw__PC\r
 \r

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c
index cce3cf3..1442597 100755 (executable)
--- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c
@@ -104,7 +104,7 @@ const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u] = {
 /*  bEndpointAddress                       */ 0x82u,\r
 /*  bmAttributes                           */ 0x03u,\r
 /*  wMaxPacketSize                         */ 0x40u, 0x00u,\r
-/*  bInterval                              */ 0x80u\r
+/*  bInterval                              */ 0x40u\r
 };\r
 \r
 /*********************************************************************\r

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld
old mode 100644 (file)
new mode 100755 (executable)
index 8dfec03..08c8807
--- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld
@@ -56,7 +56,7 @@ EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)
 PROVIDE(__cy_heap_start = _end);\r
 PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16);\r
 PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram));\r
-PROVIDE(__cy_heap_end = __cy_stack - 0x4000);\r
+PROVIDE(__cy_heap_end = __cy_stack - 0x2000);\r
 \r
 \r
 SECTIONS\r
@@ -217,14 +217,14 @@ SECTIONS
   .heap (NOLOAD) :\r
   {\r
     . = _end;\r
-    . += 0x1000;\r
+    . += 0x0256;\r
     __cy_heap_limit = .;\r
   } >ram\r
 \r
-  .stack (__cy_stack - 0x4000) (NOLOAD) :\r
+  .stack (__cy_stack - 0x2000) (NOLOAD) :\r
   {\r
     __cy_stack_limit = .;\r
-    . += 0x4000;\r
+    . += 0x2000;\r
   } >ram\r
   \r
   /* Check if data + heap + stack exceeds RAM limit */\r

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c
index 2292dca..32543d5 100755 (executable)
--- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c
@@ -31,18 +31,18 @@ const uint8 cy_bootloader[] = {
     0x00u, 0x40u, 0x00u, 0x20u, 0x11u, 0x00u, 0x00u, 0x00u,\r
     0x61u, 0x01u, 0x00u, 0x00u, 0x61u, 0x01u, 0x00u, 0x00u,\r
     0x08u, 0xB5u, 0x04u, 0x4Bu, 0x04u, 0x48u, 0x1Au, 0x68u,\r
-    0x02u, 0x60u, 0x00u, 0xF0u, 0x71u, 0xFCu, 0x00u, 0xF0u,\r
+    0x02u, 0x60u, 0x00u, 0xF0u, 0x7Bu, 0xFCu, 0x00u, 0xF0u,\r
     0xA1u, 0xF8u, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u,\r
     0xBCu, 0x76u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu,\r
     0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x48u, 0x10u, 0xB1u,\r
     0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x21u,\r
     0x21u, 0x70u, 0x10u, 0xBDu, 0x28u, 0xC1u, 0xFFu, 0x1Fu,\r
-    0x00u, 0x00u, 0x00u, 0x00u, 0xF4u, 0x1Fu, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x20u, 0x00u, 0x00u,\r
     0x08u, 0xB5u, 0x06u, 0x4Bu, 0x1Bu, 0xB1u, 0x06u, 0x48u,\r
     0x06u, 0x49u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x06u, 0x48u,\r
     0x01u, 0x68u, 0x11u, 0xB1u, 0x05u, 0x4Au, 0x02u, 0xB1u,\r
     0x90u, 0x47u, 0x08u, 0xBDu, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0xF4u, 0x1Fu, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu,\r
+    0x0Cu, 0x20u, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu,\r
     0x08u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u,\r
     0x08u, 0xB5u, 0x36u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u,\r
     0xFEu, 0x00u, 0x18u, 0x70u, 0x93u, 0xF8u, 0x22u, 0x10u,\r
@@ -70,7 +70,7 @@ const uint8 cy_bootloader[] = {
     0x03u, 0xF8u, 0x0Du, 0x0Cu, 0x13u, 0xF8u, 0x0Eu, 0x1Cu,\r
     0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Eu, 0x2Cu,\r
     0x13u, 0xF8u, 0x0Fu, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u,\r
-    0x03u, 0xF8u, 0x0Fu, 0x1Cu, 0x00u, 0xF0u, 0x94u, 0xFBu,\r
+    0x03u, 0xF8u, 0x0Fu, 0x1Cu, 0x00u, 0xF0u, 0x9Eu, 0xFBu,\r
     0xFEu, 0xE7u, 0x00u, 0xBFu, 0x00u, 0x50u, 0x00u, 0x40u,\r
     0xFEu, 0xE7u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x12u, 0x49u,\r
     0x12u, 0x4Bu, 0x4Au, 0x1Cu, 0x1Au, 0xD0u, 0x53u, 0xF8u,\r
@@ -80,9 +80,9 @@ const uint8 cy_bootloader[] = {
     0x04u, 0x32u, 0xF7u, 0xE7u, 0x53u, 0xF8u, 0x04u, 0x0Cu,\r
     0x00u, 0x22u, 0x82u, 0x42u, 0x03u, 0xD0u, 0x00u, 0x25u,\r
     0xA5u, 0x50u, 0x04u, 0x32u, 0xF9u, 0xE7u, 0x01u, 0x39u,\r
-    0x10u, 0x33u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0xEAu, 0xFEu,\r
+    0x10u, 0x33u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0xF6u, 0xFEu,\r
     0xFFu, 0xF7u, 0x6Au, 0xFFu, 0xFEu, 0xE7u, 0x00u, 0xBFu,\r
-    0x00u, 0x00u, 0x00u, 0x00u, 0x38u, 0x22u, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0x22u, 0x00u, 0x00u,\r
     0x08u, 0xB5u, 0x10u, 0x4Au, 0x10u, 0x4Bu, 0x1Au, 0x60u,\r
     0x98u, 0x68u, 0x40u, 0xF4u, 0x00u, 0x72u, 0x9Au, 0x60u,\r
     0x00u, 0x23u, 0x03u, 0x2Bu, 0x96u, 0xBFu, 0x0Du, 0x4Au,\r
@@ -96,232 +96,235 @@ const uint8 cy_bootloader[] = {
     0x61u, 0x01u, 0x00u, 0x00u, 0x00u, 0xC0u, 0xFFu, 0x1Fu,\r
     0xBCu, 0x76u, 0x00u, 0x40u, 0x04u, 0xC1u, 0xFFu, 0x1Fu,\r
     0x08u, 0xEDu, 0x00u, 0xE0u, 0x00u, 0xC1u, 0xFFu, 0x1Fu,\r
-    0xF8u, 0xB5u, 0x72u, 0xB6u, 0x5Au, 0x4Bu, 0x01u, 0x22u,\r
+    0xF8u, 0xB5u, 0x72u, 0xB6u, 0x5Fu, 0x4Bu, 0x01u, 0x22u,\r
     0xA3u, 0xF5u, 0xA0u, 0x61u, 0xA1u, 0xF5u, 0x80u, 0x75u,\r
-    0x06u, 0x20u, 0x52u, 0x24u, 0x57u, 0x4Eu, 0x1Au, 0x70u,\r
-    0x08u, 0x70u, 0x2Cu, 0x70u, 0x37u, 0x78u, 0x56u, 0x4Bu,\r
-    0x56u, 0x4Au, 0x40u, 0xF6u, 0x18u, 0x00u, 0x41u, 0xF2u,\r
+    0x06u, 0x20u, 0x52u, 0x24u, 0x5Cu, 0x4Eu, 0x1Au, 0x70u,\r
+    0x08u, 0x70u, 0x2Cu, 0x70u, 0x37u, 0x78u, 0x5Bu, 0x4Bu,\r
+    0x5Bu, 0x4Au, 0x40u, 0xF6u, 0x18u, 0x00u, 0x41u, 0xF2u,\r
     0x51u, 0x21u, 0x17u, 0x70u, 0x19u, 0x25u, 0x18u, 0x80u,\r
-    0x00u, 0x24u, 0x23u, 0xF8u, 0x02u, 0x1Cu, 0x52u, 0x4Eu,\r
+    0x00u, 0x24u, 0x23u, 0xF8u, 0x02u, 0x1Cu, 0x57u, 0x4Eu,\r
     0x4Fu, 0xF4u, 0xF0u, 0x70u, 0x37u, 0x78u, 0x07u, 0xF0u,\r
     0x01u, 0x02u, 0x42u, 0xEAu, 0x44u, 0x04u, 0x00u, 0xF0u,\r
-    0x63u, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u,\r
-    0x17u, 0xD0u, 0x03u, 0x2Cu, 0xEFu, 0xD1u, 0x4Bu, 0x48u,\r
-    0x4Bu, 0x4Fu, 0x00u, 0x26u, 0x4Fu, 0xF4u, 0x80u, 0x73u,\r
-    0x4Au, 0x4Du, 0x07u, 0x21u, 0x48u, 0x22u, 0x02u, 0x24u,\r
+    0x6Fu, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u,\r
+    0x17u, 0xD0u, 0x03u, 0x2Cu, 0xEFu, 0xD1u, 0x50u, 0x48u,\r
+    0x50u, 0x4Fu, 0x00u, 0x26u, 0x4Fu, 0xF4u, 0x80u, 0x73u,\r
+    0x4Fu, 0x4Du, 0x07u, 0x21u, 0x48u, 0x22u, 0x02u, 0x24u,\r
     0x03u, 0x80u, 0x01u, 0x70u, 0x3Eu, 0x70u, 0xBAu, 0x70u,\r
     0x06u, 0x70u, 0x46u, 0x71u, 0x00u, 0xF8u, 0x03u, 0x4Cu,\r
     0x28u, 0x78u, 0x40u, 0xF0u, 0x04u, 0x03u, 0x2Bu, 0x70u,\r
-    0x00u, 0xE0u, 0xFEu, 0xE7u, 0x42u, 0x4Fu, 0x06u, 0x21u,\r
+    0x00u, 0xE0u, 0xFEu, 0xE7u, 0x47u, 0x4Fu, 0x06u, 0x21u,\r
     0x01u, 0xFBu, 0x06u, 0x72u, 0x00u, 0x21u, 0x10u, 0x68u,\r
-    0x01u, 0x36u, 0x92u, 0x88u, 0x01u, 0xF0u, 0x91u, 0xFEu,\r
+    0x01u, 0x36u, 0x92u, 0x88u, 0x01u, 0xF0u, 0x9Du, 0xFEu,\r
     0x08u, 0x2Eu, 0xF3u, 0xD1u, 0x00u, 0x23u, 0x19u, 0x46u,\r
-    0x3Cu, 0x4Cu, 0x00u, 0x22u, 0x18u, 0x59u, 0x30u, 0x34u,\r
+    0x41u, 0x4Cu, 0x00u, 0x22u, 0x18u, 0x59u, 0x30u, 0x34u,\r
     0xC6u, 0xB2u, 0x20u, 0xF0u, 0xFFu, 0x07u, 0x04u, 0xEBu,\r
     0x41u, 0x04u, 0xD5u, 0xB2u, 0xAEu, 0x42u, 0x09u, 0xD0u,\r
     0x04u, 0xEBu, 0x42u, 0x0Cu, 0x14u, 0xF8u, 0x12u, 0x50u,\r
     0x9Cu, 0xF8u, 0x01u, 0xE0u, 0x01u, 0x32u, 0x05u, 0xF8u,\r
     0x07u, 0xE0u, 0xF2u, 0xE7u, 0x04u, 0x33u, 0xC0u, 0xB2u,\r
-    0x30u, 0x2Bu, 0x01u, 0x44u, 0xE4u, 0xD1u, 0x30u, 0x4Cu,\r
+    0x30u, 0x2Bu, 0x01u, 0x44u, 0xE4u, 0xD1u, 0x35u, 0x4Cu,\r
     0x22u, 0x78u, 0x42u, 0xF0u, 0x02u, 0x00u, 0x20u, 0x70u,\r
-    0x21u, 0x7Cu, 0x2Eu, 0x48u, 0x41u, 0xF0u, 0x02u, 0x03u,\r
-    0x2Du, 0x49u, 0x23u, 0x74u, 0x0Cu, 0x78u, 0x44u, 0xF0u,\r
-    0x40u, 0x02u, 0x0Au, 0x70u, 0x03u, 0x78u, 0x2Bu, 0x4Au,\r
-    0x43u, 0xF0u, 0x10u, 0x04u, 0x2Au, 0x4Bu, 0x04u, 0x70u,\r
+    0x21u, 0x7Cu, 0x33u, 0x48u, 0x41u, 0xF0u, 0x02u, 0x03u,\r
+    0x32u, 0x49u, 0x23u, 0x74u, 0x0Cu, 0x78u, 0x44u, 0xF0u,\r
+    0x40u, 0x02u, 0x0Au, 0x70u, 0x03u, 0x78u, 0x30u, 0x4Au,\r
+    0x43u, 0xF0u, 0x10u, 0x04u, 0x2Fu, 0x4Bu, 0x04u, 0x70u,\r
     0x18u, 0x68u, 0x5Cu, 0x68u, 0x10u, 0x60u, 0x54u, 0x60u,\r
-    0x1Au, 0x46u, 0x28u, 0x48u, 0x52u, 0xF8u, 0x08u, 0x4Fu,\r
+    0x1Au, 0x46u, 0x2Du, 0x48u, 0x52u, 0xF8u, 0x08u, 0x4Fu,\r
     0x04u, 0x60u, 0x54u, 0x68u, 0x12u, 0x89u, 0x44u, 0x60u,\r
     0x02u, 0x81u, 0x1Au, 0x46u, 0x52u, 0xF8u, 0x12u, 0x4Fu,\r
-    0x52u, 0x68u, 0x40u, 0xF8u, 0xAEu, 0x4Cu, 0x40u, 0xF8u,\r
-    0xAAu, 0x2Cu, 0x53u, 0xF8u, 0x1Au, 0x0Fu, 0x20u, 0x4Au,\r
-    0x5Bu, 0x68u, 0x10u, 0x60u, 0x1Fu, 0x48u, 0x53u, 0x60u,\r
-    0x02u, 0x78u, 0x42u, 0xF0u, 0x08u, 0x03u, 0x03u, 0x70u,\r
-    0x1Du, 0x48u, 0x1Eu, 0x4Au, 0x03u, 0x78u, 0x03u, 0xF0u,\r
-    0x07u, 0x00u, 0x1Bu, 0x09u, 0x10u, 0x70u, 0x53u, 0x70u,\r
-    0x1Bu, 0x4Au, 0x44u, 0x20u, 0x10u, 0x70u, 0x1Bu, 0x4Au,\r
-    0x0Bu, 0x46u, 0x0Cu, 0x31u, 0x53u, 0xF8u, 0x04u, 0x0Bu,\r
-    0x8Bu, 0x42u, 0x42u, 0xF8u, 0x04u, 0x0Bu, 0xF9u, 0xD1u,\r
-    0x19u, 0x88u, 0x11u, 0x80u, 0xF8u, 0xBDu, 0x00u, 0xBFu,\r
-    0x00u, 0x48u, 0x00u, 0x40u, 0x0Fu, 0x01u, 0x00u, 0x49u,\r
-    0x22u, 0x42u, 0x00u, 0x40u, 0xA1u, 0x46u, 0x00u, 0x40u,\r
-    0x25u, 0x42u, 0x00u, 0x40u, 0x04u, 0x40u, 0x00u, 0x40u,\r
-    0x06u, 0x40u, 0x00u, 0x40u, 0xE8u, 0x46u, 0x00u, 0x40u,\r
-    0xF8u, 0x1Fu, 0x00u, 0x00u, 0x28u, 0x20u, 0x00u, 0x00u,\r
-    0x03u, 0x50u, 0x01u, 0x40u, 0xC2u, 0x43u, 0x00u, 0x40u,\r
-    0xA0u, 0x43u, 0x00u, 0x40u, 0x02u, 0x51u, 0x00u, 0x40u,\r
-    0x84u, 0x20u, 0x00u, 0x00u, 0xF0u, 0x51u, 0x00u, 0x40u,\r
-    0x62u, 0x51u, 0x00u, 0x40u, 0x22u, 0x43u, 0x00u, 0x40u,\r
-    0xCFu, 0x01u, 0x00u, 0x49u, 0x6Eu, 0x58u, 0x00u, 0x40u,\r
-    0x76u, 0x58u, 0x00u, 0x40u, 0xB0u, 0x43u, 0x00u, 0x40u,\r
-    0x00u, 0x47u, 0x00u, 0x00u, 0x43u, 0x1Eu, 0x10u, 0xB5u,\r
-    0x02u, 0x46u, 0x06u, 0x2Bu, 0x0Du, 0xD8u, 0xDFu, 0xE8u,\r
-    0x03u, 0xF0u, 0x06u, 0x0Eu, 0x23u, 0x04u, 0x08u, 0x0Au,\r
-    0x21u, 0x00u, 0x16u, 0x48u, 0x08u, 0xE0u, 0x16u, 0x4Bu,\r
-    0x1Bu, 0xE0u, 0x16u, 0x48u, 0x04u, 0xE0u, 0x16u, 0x48u,\r
-    0x02u, 0xE0u, 0x00u, 0x20u, 0x00u, 0xE0u, 0x15u, 0x48u,\r
-    0x41u, 0x78u, 0x00u, 0x78u, 0x41u, 0xEAu, 0x00u, 0x20u,\r
-    0x02u, 0x2Au, 0x04u, 0xD0u, 0x03u, 0x2Au, 0x07u, 0xD0u,\r
-    0x01u, 0x2Au, 0x15u, 0xD1u, 0x04u, 0xE0u, 0x02u, 0x02u,\r
-    0x42u, 0xEAu, 0x10u, 0x23u, 0x98u, 0xB2u, 0x10u, 0xBDu,\r
-    0x00u, 0xBAu, 0x10u, 0xBDu, 0x0Cu, 0x4Bu, 0x00u, 0xE0u,\r
-    0x0Cu, 0x4Bu, 0xD8u, 0x78u, 0x9Cu, 0x78u, 0x59u, 0x78u,\r
-    0x1Bu, 0x78u, 0x40u, 0xEAu, 0x03u, 0x60u, 0x40u, 0xEAu,\r
-    0x04u, 0x23u, 0x43u, 0xEAu, 0x01u, 0x40u, 0xE3u, 0xE7u,\r
-    0x10u, 0xBDu, 0x00u, 0xBFu, 0xD2u, 0xFFu, 0x01u, 0x00u,\r
-    0xC1u, 0xFFu, 0x01u, 0x00u, 0xD6u, 0xFFu, 0x01u, 0x00u,\r
-    0xD4u, 0xFFu, 0x01u, 0x00u, 0xC5u, 0xFFu, 0x01u, 0x00u,\r
-    0xD8u, 0xFFu, 0x01u, 0x00u, 0xC9u, 0xFFu, 0x01u, 0x00u,\r
-    0x70u, 0xB5u, 0x02u, 0x20u, 0xFFu, 0xF7u, 0xB6u, 0xFFu,\r
-    0x06u, 0x46u, 0x03u, 0x20u, 0xFFu, 0xF7u, 0xB2u, 0xFFu,\r
-    0x71u, 0x1Cu, 0x00u, 0xEBu, 0x01u, 0x26u, 0x02u, 0x20u,\r
-    0xFFu, 0xF7u, 0xACu, 0xFFu, 0x00u, 0x24u, 0x01u, 0x30u,\r
-    0x01u, 0x02u, 0x25u, 0x46u, 0xB1u, 0x42u, 0x09u, 0xD2u,\r
-    0x11u, 0xF8u, 0x01u, 0x0Bu, 0x42u, 0x1Eu, 0xD3u, 0xB2u,\r
-    0x04u, 0x19u, 0xFDu, 0x2Bu, 0x98u, 0xBFu, 0x01u, 0x25u,\r
-    0xE4u, 0xB2u, 0xF3u, 0xE7u, 0x02u, 0x20u, 0xFFu, 0xF7u,\r
-    0x99u, 0xFFu, 0x0Fu, 0x49u, 0x42u, 0x1Cu, 0x13u, 0x02u,\r
-    0xDBu, 0x08u, 0x8Eu, 0x42u, 0x01u, 0xD0u, 0xF6u, 0x08u,\r
-    0x01u, 0xE0u, 0x4Fu, 0xF4u, 0x80u, 0x46u, 0xB3u, 0x42u,\r
-    0x06u, 0xD2u, 0x03u, 0xF1u, 0x90u, 0x41u, 0x08u, 0x78u,\r
-    0x01u, 0x33u, 0x02u, 0x19u, 0xD4u, 0xB2u, 0xF6u, 0xE7u,\r
-    0x05u, 0x48u, 0x64u, 0x42u, 0x02u, 0x78u, 0xE4u, 0xB2u,\r
-    0x94u, 0x42u, 0x01u, 0xD0u, 0x06u, 0x20u, 0x70u, 0xBDu,\r
-    0x00u, 0x2Du, 0xFBu, 0xD0u, 0x00u, 0x20u, 0x70u, 0xBDu,\r
-    0xC0u, 0xFFu, 0x01u, 0x00u, 0x2Du, 0xE9u, 0xF0u, 0x4Fu,\r
-    0xADu, 0xF5u, 0x61u, 0x7Du, 0x80u, 0x46u, 0x00u, 0xF0u,\r
-    0xE3u, 0xFBu, 0x62u, 0xB6u, 0x00u, 0x26u, 0xB2u, 0x46u,\r
-    0x4Fu, 0xF0u, 0x0Au, 0x09u, 0x37u, 0x46u, 0xB8u, 0xF1u,\r
-    0x00u, 0x0Fu, 0x01u, 0xD1u, 0xFFu, 0x23u, 0x00u, 0xE0u,\r
-    0x43u, 0x46u, 0x4Au, 0xA8u, 0x4Fu, 0xF4u, 0x96u, 0x71u,\r
-    0x01u, 0xAAu, 0x00u, 0xF0u, 0x0Bu, 0xFCu, 0xB8u, 0xF1u,\r
-    0x00u, 0x0Fu, 0x03u, 0xD0u, 0x09u, 0xF1u, 0xFFu, 0x39u,\r
-    0x5Fu, 0xFAu, 0x89u, 0xF9u, 0xB9u, 0xF1u, 0x00u, 0x0Fu,\r
-    0x02u, 0xD0u, 0x00u, 0x28u, 0xE7u, 0xD1u, 0x01u, 0xE0u,\r
-    0x00u, 0x28u, 0x71u, 0xD1u, 0xBDu, 0xF8u, 0x04u, 0x20u,\r
-    0x06u, 0x2Au, 0x40u, 0xF2u, 0x7Bu, 0x81u, 0x9Du, 0xF8u,\r
-    0x28u, 0x31u, 0x01u, 0x2Bu, 0x40u, 0xF0u, 0x76u, 0x81u,\r
-    0x9Du, 0xF8u, 0x2Au, 0x01u, 0x9Du, 0xF8u, 0x2Bu, 0x51u,\r
-    0x4Au, 0xA9u, 0x40u, 0xEAu, 0x05u, 0x25u, 0xECu, 0x1Du,\r
-    0x4Bu, 0x19u, 0x94u, 0x42u, 0x58u, 0x79u, 0x19u, 0x79u,\r
-    0x00u, 0xF2u, 0x66u, 0x81u, 0x9Au, 0x79u, 0x17u, 0x2Au,\r
-    0x40u, 0xF0u, 0x64u, 0x81u, 0x2Bu, 0x1Du, 0x9Bu, 0xB2u,\r
-    0x00u, 0x22u, 0x3Bu, 0xB1u, 0x0Du, 0xF2u, 0x27u, 0x14u,\r
-    0xE4u, 0x5Cu, 0x01u, 0x3Bu, 0x12u, 0x19u, 0x92u, 0xB2u,\r
-    0x9Bu, 0xB2u, 0xF6u, 0xE7u, 0x52u, 0x42u, 0x41u, 0xEAu,\r
-    0x00u, 0x20u, 0x91u, 0xB2u, 0x88u, 0x42u, 0x40u, 0xF0u,\r
-    0x53u, 0x81u, 0x4Au, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u,\r
-    0x4Du, 0x81u, 0x01u, 0x2Du, 0x4Fu, 0xF0u, 0x00u, 0x04u,\r
-    0x40u, 0xF0u, 0x3Cu, 0x81u, 0xBBu, 0xF1u, 0x01u, 0x0Fu,\r
-    0x00u, 0xF2u, 0x38u, 0x81u, 0xFFu, 0x23u, 0x8Du, 0xF8u,\r
-    0x2Cu, 0x41u, 0x8Du, 0xF8u, 0x2Du, 0x41u, 0x25u, 0x46u,\r
-    0x8Du, 0xF8u, 0x2Eu, 0x31u, 0x8Du, 0xF8u, 0x2Fu, 0x61u,\r
-    0x04u, 0x24u, 0x01u, 0x20u, 0x00u, 0x22u, 0x21u, 0x1Du,\r
-    0xADu, 0xF8u, 0x06u, 0x40u, 0x8Du, 0xF8u, 0x28u, 0x01u,\r
-    0x8Du, 0xF8u, 0x29u, 0x51u, 0x8Du, 0xF8u, 0x2Au, 0x41u,\r
-    0x8Du, 0xF8u, 0x2Bu, 0x21u, 0x8Bu, 0xB2u, 0x0Du, 0xF2u,\r
-    0x27u, 0x10u, 0xC1u, 0x5Cu, 0x01u, 0x3Bu, 0x52u, 0x18u,\r
-    0x9Bu, 0xB2u, 0x92u, 0xB2u, 0x00u, 0x2Bu, 0xF6u, 0xD1u,\r
-    0x50u, 0x42u, 0x81u, 0xB2u, 0x08u, 0x0Au, 0x4Bu, 0xAAu,\r
-    0x0Du, 0xF2u, 0x2Du, 0x13u, 0x11u, 0x55u, 0x18u, 0x55u,\r
-    0x17u, 0x21u, 0x0Du, 0xF5u, 0x97u, 0x72u, 0xE3u, 0x1Du,\r
-    0x11u, 0x55u, 0x4Au, 0xA8u, 0x99u, 0xB2u, 0x0Du, 0xF1u,\r
-    0x06u, 0x02u, 0x96u, 0x23u, 0x00u, 0xF0u, 0x60u, 0xFBu,\r
-    0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x3Fu, 0xF4u, 0x72u, 0xAFu,\r
-    0x00u, 0x2Eu, 0x00u, 0xF0u, 0x12u, 0x81u, 0x01u, 0x26u,\r
-    0x69u, 0xE7u, 0x9Du, 0xF8u, 0x29u, 0x21u, 0x9Du, 0xF8u,\r
-    0x2Cu, 0xB1u, 0xA2u, 0xF1u, 0x31u, 0x03u, 0x0Au, 0x2Bu,\r
-    0x00u, 0xF2u, 0xF7u, 0x80u, 0x01u, 0xA1u, 0x51u, 0xF8u,\r
-    0x23u, 0xF0u, 0x00u, 0xBFu, 0x89u, 0x06u, 0x00u, 0x00u,\r
-    0xADu, 0x05u, 0x00u, 0x00u, 0x43u, 0x08u, 0x00u, 0x00u,\r
-    0xA7u, 0x06u, 0x00u, 0x00u, 0x59u, 0x07u, 0x00u, 0x00u,\r
-    0x43u, 0x08u, 0x00u, 0x00u, 0x5Fu, 0x07u, 0x00u, 0x00u,\r
-    0x7Du, 0x07u, 0x00u, 0x00u, 0xA7u, 0x06u, 0x00u, 0x00u,\r
-    0x97u, 0x07u, 0x00u, 0x00u, 0x23u, 0x08u, 0x00u, 0x00u,\r
-    0x00u, 0x2Eu, 0x00u, 0xF0u, 0xDFu, 0x80u, 0x00u, 0x2Du,\r
-    0x40u, 0xF0u, 0xDCu, 0x80u, 0xFFu, 0xF7u, 0xF0u, 0xFEu,\r
-    0xD0u, 0xF1u, 0x01u, 0x02u, 0x38u, 0xBFu, 0x00u, 0x22u,\r
-    0x8Du, 0xF8u, 0x2Cu, 0x21u, 0xBBu, 0xE0u, 0x34u, 0x2Au,\r
-    0x12u, 0xD1u, 0x00u, 0x2Eu, 0x00u, 0xF0u, 0xCEu, 0x80u,\r
-    0x03u, 0x2Du, 0x40u, 0xF0u, 0xCBu, 0x80u, 0xABu, 0xF1u,\r
-    0x40u, 0x07u, 0x3Fu, 0x2Fu, 0x8Cu, 0xBFu, 0x4Fu, 0xF4u,\r
-    0x90u, 0x77u, 0x10u, 0x27u, 0x95u, 0xA8u, 0x00u, 0x21u,\r
-    0x3Au, 0x46u, 0x01u, 0xF0u, 0x86u, 0xFCu, 0x05u, 0xE0u,\r
-    0x00u, 0x2Eu, 0x00u, 0xF0u, 0xBBu, 0x80u, 0x02u, 0x2Du,\r
-    0x40u, 0xF2u, 0xB8u, 0x80u, 0x03u, 0x3Du, 0x95u, 0xABu,\r
-    0x2Au, 0x46u, 0xD8u, 0x19u, 0x0Du, 0xF2u, 0x2Fu, 0x11u,\r
-    0x01u, 0xF0u, 0x6Eu, 0xFCu, 0xABu, 0xF1u, 0x40u, 0x00u,\r
-    0x7Au, 0x19u, 0x3Fu, 0x28u, 0x96u, 0xB2u, 0x03u, 0xD8u,\r
-    0x00u, 0xF0u, 0xD2u, 0xF9u, 0x10u, 0x24u, 0x01u, 0xE0u,\r
-    0x4Fu, 0xF4u, 0x90u, 0x74u, 0xA6u, 0x42u, 0x40u, 0xF0u,\r
-    0x97u, 0x80u, 0x9Du, 0xF8u, 0x2Eu, 0x11u, 0x9Du, 0xF8u,\r
-    0x2Du, 0x71u, 0xBBu, 0xF1u, 0x3Fu, 0x0Fu, 0x47u, 0xEAu,\r
-    0x01u, 0x25u, 0x11u, 0xD8u, 0xBAu, 0xF1u, 0x00u, 0x0Fu,\r
-    0x0Eu, 0xD1u, 0x51u, 0x46u, 0x4Fu, 0xF4u, 0x90u, 0x72u,\r
-    0x02u, 0xA8u, 0x01u, 0xF0u, 0x56u, 0xFCu, 0x01u, 0x20u,\r
-    0xFFu, 0x21u, 0x02u, 0xAAu, 0x4Fu, 0xF4u, 0x90u, 0x73u,\r
-    0x00u, 0xF0u, 0x62u, 0xF9u, 0x4Fu, 0xF0u, 0x01u, 0x0Au,\r
-    0x33u, 0x46u, 0x58u, 0x46u, 0x29u, 0x46u, 0x95u, 0xAAu,\r
-    0x00u, 0xF0u, 0x5Au, 0xF9u, 0x01u, 0x26u, 0x00u, 0x28u,\r
-    0x75u, 0xD0u, 0x00u, 0x27u, 0x0Au, 0x25u, 0x75u, 0xE0u,\r
-    0x00u, 0x2Eu, 0x77u, 0xD0u, 0x7Au, 0xE0u, 0x00u, 0x2Eu,\r
-    0x74u, 0xD0u, 0x7Cu, 0x19u, 0xB4u, 0xF5u, 0x96u, 0x7Fu,\r
-    0x6Eu, 0xD8u, 0x95u, 0xA9u, 0xC8u, 0x19u, 0x2Au, 0x46u,\r
-    0x4Bu, 0xA9u, 0x01u, 0xF0u, 0x29u, 0xFCu, 0xA7u, 0xB2u,\r
-    0x00u, 0x25u, 0x63u, 0xE0u, 0x00u, 0x2Du, 0x65u, 0xD1u,\r
-    0x3Au, 0x48u, 0x02u, 0xAEu, 0x4Bu, 0xACu, 0x03u, 0xC8u,\r
-    0x86u, 0xE8u, 0x03u, 0x00u, 0x84u, 0xE8u, 0x03u, 0x00u,\r
-    0x01u, 0x26u, 0x08u, 0x24u, 0x21u, 0xE7u, 0x00u, 0x2Eu,\r
-    0x58u, 0xD0u, 0x03u, 0x2Du, 0x56u, 0xD1u, 0x9Du, 0xF8u,\r
-    0x2Eu, 0x01u, 0x9Du, 0xF8u, 0x2Du, 0x11u, 0xABu, 0xF1u,\r
-    0x40u, 0x02u, 0x3Fu, 0x2Au, 0x41u, 0xEAu, 0x00u, 0x25u,\r
-    0x0Au, 0xD8u, 0x2Du, 0x01u, 0x00u, 0x23u, 0x10u, 0x22u,\r
-    0x2Du, 0x48u, 0x11u, 0x18u, 0x4Cu, 0x5Du, 0x01u, 0x3Au,\r
-    0x23u, 0x44u, 0xDBu, 0xB2u, 0xF8u, 0xD1u, 0x26u, 0xE0u,\r
-    0x05u, 0xEBu, 0x0Bu, 0x23u, 0x1Cu, 0x02u, 0x4Fu, 0xF4u,\r
-    0x80u, 0x72u, 0x00u, 0x23u, 0x01u, 0x3Au, 0x10u, 0x5Du,\r
-    0x19u, 0x18u, 0xCBu, 0xB2u, 0x00u, 0x2Au, 0xF9u, 0xD1u,\r
-    0xBBu, 0xF1u, 0x3Fu, 0x0Fu, 0x17u, 0xD8u, 0x0Bu, 0xF5u,\r
-    0x10u, 0x34u, 0x05u, 0xEBu, 0x04u, 0x20u, 0x41u, 0x01u,\r
-    0x54u, 0x5Cu, 0x01u, 0x32u, 0x1Bu, 0x19u, 0x20u, 0x2Au,\r
-    0xDBu, 0xB2u, 0xF9u, 0xD1u, 0xBBu, 0xF1u, 0x01u, 0x0Fu,\r
-    0x09u, 0xD1u, 0xFFu, 0x2Du, 0x07u, 0xD1u, 0x1Bu, 0x4Du,\r
-    0x1Bu, 0x4Cu, 0x28u, 0x78u, 0x19u, 0x1Au, 0x23u, 0x78u,\r
-    0xCAu, 0x1Au, 0x02u, 0xF0u, 0xFFu, 0x03u, 0x5Du, 0x42u,\r
-    0x8Du, 0xF8u, 0x2Cu, 0x51u, 0x00u, 0x25u, 0x01u, 0x24u,\r
-    0xDBu, 0xE6u, 0xFFu, 0xF7u, 0x29u, 0xFEu, 0x10u, 0xB9u,\r
-    0x14u, 0x4Du, 0x80u, 0x24u, 0x2Cu, 0x70u, 0x00u, 0xF0u,\r
-    0x45u, 0xF9u, 0x0Bu, 0xE0u, 0x04u, 0x25u, 0xD0u, 0xE6u,\r
-    0x01u, 0x26u, 0x00u, 0x27u, 0x04u, 0xE0u, 0x07u, 0x46u,\r
-    0x9Au, 0xE7u, 0x05u, 0x25u, 0x00u, 0x24u, 0xC8u, 0xE6u,\r
-    0x03u, 0x25u, 0xFBu, 0xE7u, 0x04u, 0x25u, 0xF9u, 0xE7u,\r
-    0x08u, 0x25u, 0xF7u, 0xE7u, 0xB8u, 0xF1u, 0x00u, 0x0Fu,\r
-    0x01u, 0xD1u, 0x47u, 0x46u, 0x5Eu, 0xE6u, 0x00u, 0x27u,\r
-    0xEDu, 0xE6u, 0x0Du, 0xF5u, 0x61u, 0x7Du, 0xBDu, 0xE8u,\r
-    0xF0u, 0x8Fu, 0x00u, 0xBFu, 0xA8u, 0x20u, 0x00u, 0x00u,\r
-    0xFFu, 0x7Fu, 0x00u, 0x40u, 0xD0u, 0xFFu, 0x01u, 0x00u,\r
-    0xD1u, 0xFFu, 0x01u, 0x00u, 0xFAu, 0x46u, 0x00u, 0x40u,\r
-    0x10u, 0xB5u, 0xC8u, 0xB0u, 0x00u, 0xF0u, 0x92u, 0xF8u,\r
-    0x10u, 0xB1u, 0x00u, 0x20u, 0x00u, 0xF0u, 0x14u, 0xF9u,\r
-    0x68u, 0x46u, 0x00u, 0xF0u, 0x9Fu, 0xF8u, 0x10u, 0xB1u,\r
-    0x00u, 0x20u, 0x00u, 0xF0u, 0x0Du, 0xF9u, 0x16u, 0x48u,\r
-    0x03u, 0x68u, 0x19u, 0x68u, 0x00u, 0x23u, 0x0Au, 0x46u,\r
-    0x22u, 0xB1u, 0x12u, 0xF8u, 0x01u, 0x4Du, 0xE3u, 0x18u,\r
-    0xDBu, 0xB2u, 0xF9u, 0xE7u, 0x42u, 0x68u, 0x10u, 0x78u,\r
-    0xC4u, 0x1Au, 0x04u, 0xF0u, 0xFFu, 0x03u, 0x83u, 0x42u,\r
-    0x00u, 0xD1u, 0x11u, 0xB9u, 0x00u, 0x20u, 0x00u, 0xF0u,\r
-    0xF7u, 0xF8u, 0x0Cu, 0x4Cu, 0xFFu, 0xF7u, 0xD4u, 0xFDu,\r
-    0x21u, 0x78u, 0x01u, 0xF0u, 0xC0u, 0x02u, 0x40u, 0x2Au,\r
-    0x00u, 0xD0u, 0x18u, 0xB1u, 0x00u, 0x20u, 0x20u, 0x70u,\r
-    0xFFu, 0xF7u, 0x0Cu, 0xFEu, 0x14u, 0x20u, 0xFFu, 0xF7u,\r
-    0x09u, 0xFEu, 0x80u, 0x20u, 0x20u, 0x70u, 0x00u, 0xF0u,\r
-    0xE5u, 0xF8u, 0x48u, 0xB0u, 0x10u, 0xBDu, 0x00u, 0xBFu,\r
-    0x0Cu, 0xC1u, 0xFFu, 0x1Fu, 0xFAu, 0x46u, 0x00u, 0x40u,\r
-    0x08u, 0xB5u, 0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u,\r
-    0xC0u, 0x00u, 0x80u, 0x28u, 0x0Cu, 0xD1u, 0x00u, 0x21u,\r
-    0x19u, 0x70u, 0x01u, 0x20u, 0xFFu, 0xF7u, 0x6Au, 0xFDu,\r
-    0x30u, 0xB1u, 0x01u, 0x20u, 0xFFu, 0xF7u, 0x66u, 0xFDu,\r
-    0xBDu, 0xE8u, 0x08u, 0x40u, 0xFFu, 0xF7u, 0x60u, 0xBDu,\r
-    0x08u, 0xBDu, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u,\r
+    0x40u, 0xF8u, 0xC0u, 0x4Cu, 0x54u, 0x68u, 0x12u, 0x89u,\r
+    0x40u, 0xF8u, 0xBCu, 0x4Cu, 0x20u, 0xF8u, 0xB8u, 0x2Cu,\r
+    0x1Au, 0x46u, 0x52u, 0xF8u, 0x1Cu, 0x4Fu, 0x52u, 0x68u,\r
+    0x40u, 0xF8u, 0xAEu, 0x4Cu, 0x40u, 0xF8u, 0xAAu, 0x2Cu,\r
+    0x53u, 0xF8u, 0x24u, 0x0Fu, 0x1Fu, 0x4Au, 0x5Bu, 0x68u,\r
+    0x10u, 0x60u, 0x1Fu, 0x48u, 0x53u, 0x60u, 0x02u, 0x78u,\r
+    0x42u, 0xF0u, 0x08u, 0x03u, 0x03u, 0x70u, 0x1Du, 0x48u,\r
+    0x1Du, 0x4Au, 0x03u, 0x78u, 0x03u, 0xF0u, 0x07u, 0x00u,\r
+    0x1Bu, 0x09u, 0x10u, 0x70u, 0x53u, 0x70u, 0x1Bu, 0x4Au,\r
+    0x44u, 0x20u, 0x10u, 0x70u, 0x1Au, 0x4Au, 0x0Bu, 0x46u,\r
+    0x0Cu, 0x31u, 0x53u, 0xF8u, 0x04u, 0x0Bu, 0x8Bu, 0x42u,\r
+    0x42u, 0xF8u, 0x04u, 0x0Bu, 0xF9u, 0xD1u, 0x19u, 0x88u,\r
+    0x11u, 0x80u, 0xF8u, 0xBDu, 0x00u, 0x48u, 0x00u, 0x40u,\r
+    0x0Fu, 0x01u, 0x00u, 0x49u, 0x22u, 0x42u, 0x00u, 0x40u,\r
+    0xA1u, 0x46u, 0x00u, 0x40u, 0x25u, 0x42u, 0x00u, 0x40u,\r
+    0x04u, 0x40u, 0x00u, 0x40u, 0x06u, 0x40u, 0x00u, 0x40u,\r
+    0xE8u, 0x46u, 0x00u, 0x40u, 0x10u, 0x20u, 0x00u, 0x00u,\r
+    0x40u, 0x20u, 0x00u, 0x00u, 0x03u, 0x50u, 0x01u, 0x40u,\r
+    0xC2u, 0x43u, 0x00u, 0x40u, 0xA0u, 0x43u, 0x00u, 0x40u,\r
+    0x02u, 0x51u, 0x00u, 0x40u, 0x9Eu, 0x20u, 0x00u, 0x00u,\r
+    0xF0u, 0x51u, 0x00u, 0x40u, 0x62u, 0x51u, 0x00u, 0x40u,\r
+    0x22u, 0x43u, 0x00u, 0x40u, 0xCFu, 0x01u, 0x00u, 0x49u,\r
+    0x6Eu, 0x58u, 0x00u, 0x40u, 0x76u, 0x58u, 0x00u, 0x40u,\r
+    0xB0u, 0x43u, 0x00u, 0x40u, 0x00u, 0x47u, 0x00u, 0x00u,\r
+    0x43u, 0x1Eu, 0x10u, 0xB5u, 0x02u, 0x46u, 0x06u, 0x2Bu,\r
+    0x0Du, 0xD8u, 0xDFu, 0xE8u, 0x03u, 0xF0u, 0x06u, 0x0Eu,\r
+    0x23u, 0x04u, 0x08u, 0x0Au, 0x21u, 0x00u, 0x16u, 0x48u,\r
+    0x08u, 0xE0u, 0x16u, 0x4Bu, 0x1Bu, 0xE0u, 0x16u, 0x48u,\r
+    0x04u, 0xE0u, 0x16u, 0x48u, 0x02u, 0xE0u, 0x00u, 0x20u,\r
+    0x00u, 0xE0u, 0x15u, 0x48u, 0x41u, 0x78u, 0x00u, 0x78u,\r
+    0x41u, 0xEAu, 0x00u, 0x20u, 0x02u, 0x2Au, 0x04u, 0xD0u,\r
+    0x03u, 0x2Au, 0x07u, 0xD0u, 0x01u, 0x2Au, 0x15u, 0xD1u,\r
+    0x04u, 0xE0u, 0x02u, 0x02u, 0x42u, 0xEAu, 0x10u, 0x23u,\r
+    0x98u, 0xB2u, 0x10u, 0xBDu, 0x00u, 0xBAu, 0x10u, 0xBDu,\r
+    0x0Cu, 0x4Bu, 0x00u, 0xE0u, 0x0Cu, 0x4Bu, 0xD8u, 0x78u,\r
+    0x9Cu, 0x78u, 0x59u, 0x78u, 0x1Bu, 0x78u, 0x40u, 0xEAu,\r
+    0x03u, 0x60u, 0x40u, 0xEAu, 0x04u, 0x23u, 0x43u, 0xEAu,\r
+    0x01u, 0x40u, 0xE3u, 0xE7u, 0x10u, 0xBDu, 0x00u, 0xBFu,\r
+    0xD2u, 0xFFu, 0x01u, 0x00u, 0xC1u, 0xFFu, 0x01u, 0x00u,\r
+    0xD6u, 0xFFu, 0x01u, 0x00u, 0xD4u, 0xFFu, 0x01u, 0x00u,\r
+    0xC5u, 0xFFu, 0x01u, 0x00u, 0xD8u, 0xFFu, 0x01u, 0x00u,\r
+    0xC9u, 0xFFu, 0x01u, 0x00u, 0x70u, 0xB5u, 0x02u, 0x20u,\r
+    0xFFu, 0xF7u, 0xB6u, 0xFFu, 0x06u, 0x46u, 0x03u, 0x20u,\r
+    0xFFu, 0xF7u, 0xB2u, 0xFFu, 0x71u, 0x1Cu, 0x00u, 0xEBu,\r
+    0x01u, 0x26u, 0x02u, 0x20u, 0xFFu, 0xF7u, 0xACu, 0xFFu,\r
+    0x00u, 0x24u, 0x01u, 0x30u, 0x01u, 0x02u, 0x25u, 0x46u,\r
+    0xB1u, 0x42u, 0x09u, 0xD2u, 0x11u, 0xF8u, 0x01u, 0x0Bu,\r
+    0x42u, 0x1Eu, 0xD3u, 0xB2u, 0x04u, 0x19u, 0xFDu, 0x2Bu,\r
+    0x98u, 0xBFu, 0x01u, 0x25u, 0xE4u, 0xB2u, 0xF3u, 0xE7u,\r
+    0x02u, 0x20u, 0xFFu, 0xF7u, 0x99u, 0xFFu, 0x0Fu, 0x49u,\r
+    0x42u, 0x1Cu, 0x13u, 0x02u, 0xDBu, 0x08u, 0x8Eu, 0x42u,\r
+    0x01u, 0xD0u, 0xF6u, 0x08u, 0x01u, 0xE0u, 0x4Fu, 0xF4u,\r
+    0x80u, 0x46u, 0xB3u, 0x42u, 0x06u, 0xD2u, 0x03u, 0xF1u,\r
+    0x90u, 0x41u, 0x08u, 0x78u, 0x01u, 0x33u, 0x02u, 0x19u,\r
+    0xD4u, 0xB2u, 0xF6u, 0xE7u, 0x05u, 0x48u, 0x64u, 0x42u,\r
+    0x02u, 0x78u, 0xE4u, 0xB2u, 0x94u, 0x42u, 0x01u, 0xD0u,\r
+    0x06u, 0x20u, 0x70u, 0xBDu, 0x00u, 0x2Du, 0xFBu, 0xD0u,\r
+    0x00u, 0x20u, 0x70u, 0xBDu, 0xC0u, 0xFFu, 0x01u, 0x00u,\r
+    0x2Du, 0xE9u, 0xF0u, 0x4Fu, 0xADu, 0xF5u, 0x61u, 0x7Du,\r
+    0x80u, 0x46u, 0x00u, 0xF0u, 0xE5u, 0xFBu, 0x62u, 0xB6u,\r
+    0x00u, 0x26u, 0xB2u, 0x46u, 0x4Fu, 0xF0u, 0x0Au, 0x09u,\r
+    0x37u, 0x46u, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u,\r
+    0xFFu, 0x23u, 0x00u, 0xE0u, 0x43u, 0x46u, 0x4Au, 0xA8u,\r
+    0x4Fu, 0xF4u, 0x96u, 0x71u, 0x01u, 0xAAu, 0x00u, 0xF0u,\r
+    0x0Du, 0xFCu, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x03u, 0xD0u,\r
+    0x09u, 0xF1u, 0xFFu, 0x39u, 0x5Fu, 0xFAu, 0x89u, 0xF9u,\r
+    0xB9u, 0xF1u, 0x00u, 0x0Fu, 0x02u, 0xD0u, 0x00u, 0x28u,\r
+    0xE7u, 0xD1u, 0x01u, 0xE0u, 0x00u, 0x28u, 0x71u, 0xD1u,\r
+    0xBDu, 0xF8u, 0x04u, 0x20u, 0x06u, 0x2Au, 0x40u, 0xF2u,\r
+    0x7Bu, 0x81u, 0x9Du, 0xF8u, 0x28u, 0x31u, 0x01u, 0x2Bu,\r
+    0x40u, 0xF0u, 0x76u, 0x81u, 0x9Du, 0xF8u, 0x2Au, 0x01u,\r
+    0x9Du, 0xF8u, 0x2Bu, 0x51u, 0x4Au, 0xA9u, 0x40u, 0xEAu,\r
+    0x05u, 0x25u, 0xECu, 0x1Du, 0x4Bu, 0x19u, 0x94u, 0x42u,\r
+    0x58u, 0x79u, 0x19u, 0x79u, 0x00u, 0xF2u, 0x66u, 0x81u,\r
+    0x9Au, 0x79u, 0x17u, 0x2Au, 0x40u, 0xF0u, 0x64u, 0x81u,\r
+    0x2Bu, 0x1Du, 0x9Bu, 0xB2u, 0x00u, 0x22u, 0x3Bu, 0xB1u,\r
+    0x0Du, 0xF2u, 0x27u, 0x14u, 0xE4u, 0x5Cu, 0x01u, 0x3Bu,\r
+    0x12u, 0x19u, 0x92u, 0xB2u, 0x9Bu, 0xB2u, 0xF6u, 0xE7u,\r
+    0x52u, 0x42u, 0x41u, 0xEAu, 0x00u, 0x20u, 0x91u, 0xB2u,\r
+    0x88u, 0x42u, 0x40u, 0xF0u, 0x53u, 0x81u, 0x4Au, 0xE0u,\r
+    0x00u, 0x2Eu, 0x00u, 0xF0u, 0x4Du, 0x81u, 0x01u, 0x2Du,\r
+    0x4Fu, 0xF0u, 0x00u, 0x04u, 0x40u, 0xF0u, 0x3Cu, 0x81u,\r
+    0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x00u, 0xF2u, 0x38u, 0x81u,\r
+    0xFFu, 0x23u, 0x8Du, 0xF8u, 0x2Cu, 0x41u, 0x8Du, 0xF8u,\r
+    0x2Du, 0x41u, 0x25u, 0x46u, 0x8Du, 0xF8u, 0x2Eu, 0x31u,\r
+    0x8Du, 0xF8u, 0x2Fu, 0x61u, 0x04u, 0x24u, 0x01u, 0x20u,\r
+    0x00u, 0x22u, 0x21u, 0x1Du, 0xADu, 0xF8u, 0x06u, 0x40u,\r
+    0x8Du, 0xF8u, 0x28u, 0x01u, 0x8Du, 0xF8u, 0x29u, 0x51u,\r
+    0x8Du, 0xF8u, 0x2Au, 0x41u, 0x8Du, 0xF8u, 0x2Bu, 0x21u,\r
+    0x8Bu, 0xB2u, 0x0Du, 0xF2u, 0x27u, 0x10u, 0xC1u, 0x5Cu,\r
+    0x01u, 0x3Bu, 0x52u, 0x18u, 0x9Bu, 0xB2u, 0x92u, 0xB2u,\r
+    0x00u, 0x2Bu, 0xF6u, 0xD1u, 0x50u, 0x42u, 0x81u, 0xB2u,\r
+    0x08u, 0x0Au, 0x4Bu, 0xAAu, 0x0Du, 0xF2u, 0x2Du, 0x13u,\r
+    0x11u, 0x55u, 0x18u, 0x55u, 0x17u, 0x21u, 0x0Du, 0xF5u,\r
+    0x97u, 0x72u, 0xE3u, 0x1Du, 0x11u, 0x55u, 0x4Au, 0xA8u,\r
+    0x99u, 0xB2u, 0x0Du, 0xF1u, 0x06u, 0x02u, 0x96u, 0x23u,\r
+    0x00u, 0xF0u, 0x62u, 0xFBu, 0xB8u, 0xF1u, 0x00u, 0x0Fu,\r
+    0x3Fu, 0xF4u, 0x72u, 0xAFu, 0x00u, 0x2Eu, 0x00u, 0xF0u,\r
+    0x12u, 0x81u, 0x01u, 0x26u, 0x69u, 0xE7u, 0x9Du, 0xF8u,\r
+    0x29u, 0x21u, 0x9Du, 0xF8u, 0x2Cu, 0xB1u, 0xA2u, 0xF1u,\r
+    0x31u, 0x03u, 0x0Au, 0x2Bu, 0x00u, 0xF2u, 0xF7u, 0x80u,\r
+    0x01u, 0xA1u, 0x51u, 0xF8u, 0x23u, 0xF0u, 0x00u, 0xBFu,\r
+    0x9Du, 0x06u, 0x00u, 0x00u, 0xC1u, 0x05u, 0x00u, 0x00u,\r
+    0x57u, 0x08u, 0x00u, 0x00u, 0xBBu, 0x06u, 0x00u, 0x00u,\r
+    0x6Du, 0x07u, 0x00u, 0x00u, 0x57u, 0x08u, 0x00u, 0x00u,\r
+    0x73u, 0x07u, 0x00u, 0x00u, 0x91u, 0x07u, 0x00u, 0x00u,\r
+    0xBBu, 0x06u, 0x00u, 0x00u, 0xABu, 0x07u, 0x00u, 0x00u,\r
+    0x37u, 0x08u, 0x00u, 0x00u, 0x00u, 0x2Eu, 0x00u, 0xF0u,\r
+    0xDFu, 0x80u, 0x00u, 0x2Du, 0x40u, 0xF0u, 0xDCu, 0x80u,\r
+    0xFFu, 0xF7u, 0xF0u, 0xFEu, 0xD0u, 0xF1u, 0x01u, 0x02u,\r
+    0x38u, 0xBFu, 0x00u, 0x22u, 0x8Du, 0xF8u, 0x2Cu, 0x21u,\r
+    0xBBu, 0xE0u, 0x34u, 0x2Au, 0x12u, 0xD1u, 0x00u, 0x2Eu,\r
+    0x00u, 0xF0u, 0xCEu, 0x80u, 0x03u, 0x2Du, 0x40u, 0xF0u,\r
+    0xCBu, 0x80u, 0xABu, 0xF1u, 0x40u, 0x07u, 0x3Fu, 0x2Fu,\r
+    0x8Cu, 0xBFu, 0x4Fu, 0xF4u, 0x90u, 0x77u, 0x10u, 0x27u,\r
+    0x95u, 0xA8u, 0x00u, 0x21u, 0x3Au, 0x46u, 0x01u, 0xF0u,\r
+    0x88u, 0xFCu, 0x05u, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u,\r
+    0xBBu, 0x80u, 0x02u, 0x2Du, 0x40u, 0xF2u, 0xB8u, 0x80u,\r
+    0x03u, 0x3Du, 0x95u, 0xABu, 0x2Au, 0x46u, 0xD8u, 0x19u,\r
+    0x0Du, 0xF2u, 0x2Fu, 0x11u, 0x01u, 0xF0u, 0x70u, 0xFCu,\r
+    0xABu, 0xF1u, 0x40u, 0x00u, 0x7Au, 0x19u, 0x3Fu, 0x28u,\r
+    0x96u, 0xB2u, 0x03u, 0xD8u, 0x00u, 0xF0u, 0xD4u, 0xF9u,\r
+    0x10u, 0x24u, 0x01u, 0xE0u, 0x4Fu, 0xF4u, 0x90u, 0x74u,\r
+    0xA6u, 0x42u, 0x40u, 0xF0u, 0x97u, 0x80u, 0x9Du, 0xF8u,\r
+    0x2Eu, 0x11u, 0x9Du, 0xF8u, 0x2Du, 0x71u, 0xBBu, 0xF1u,\r
+    0x3Fu, 0x0Fu, 0x47u, 0xEAu, 0x01u, 0x25u, 0x11u, 0xD8u,\r
+    0xBAu, 0xF1u, 0x00u, 0x0Fu, 0x0Eu, 0xD1u, 0x51u, 0x46u,\r
+    0x4Fu, 0xF4u, 0x90u, 0x72u, 0x02u, 0xA8u, 0x01u, 0xF0u,\r
+    0x58u, 0xFCu, 0x01u, 0x20u, 0xFFu, 0x21u, 0x02u, 0xAAu,\r
+    0x4Fu, 0xF4u, 0x90u, 0x73u, 0x00u, 0xF0u, 0x64u, 0xF9u,\r
+    0x4Fu, 0xF0u, 0x01u, 0x0Au, 0x33u, 0x46u, 0x58u, 0x46u,\r
+    0x29u, 0x46u, 0x95u, 0xAAu, 0x00u, 0xF0u, 0x5Cu, 0xF9u,\r
+    0x01u, 0x26u, 0x00u, 0x28u, 0x75u, 0xD0u, 0x00u, 0x27u,\r
+    0x0Au, 0x25u, 0x75u, 0xE0u, 0x00u, 0x2Eu, 0x77u, 0xD0u,\r
+    0x7Au, 0xE0u, 0x00u, 0x2Eu, 0x74u, 0xD0u, 0x7Cu, 0x19u,\r
+    0xB4u, 0xF5u, 0x96u, 0x7Fu, 0x6Eu, 0xD8u, 0x95u, 0xA9u,\r
+    0xC8u, 0x19u, 0x2Au, 0x46u, 0x4Bu, 0xA9u, 0x01u, 0xF0u,\r
+    0x2Bu, 0xFCu, 0xA7u, 0xB2u, 0x00u, 0x25u, 0x63u, 0xE0u,\r
+    0x00u, 0x2Du, 0x65u, 0xD1u, 0x3Au, 0x48u, 0x02u, 0xAEu,\r
+    0x4Bu, 0xACu, 0x03u, 0xC8u, 0x86u, 0xE8u, 0x03u, 0x00u,\r
+    0x84u, 0xE8u, 0x03u, 0x00u, 0x01u, 0x26u, 0x08u, 0x24u,\r
+    0x21u, 0xE7u, 0x00u, 0x2Eu, 0x58u, 0xD0u, 0x03u, 0x2Du,\r
+    0x56u, 0xD1u, 0x9Du, 0xF8u, 0x2Eu, 0x01u, 0x9Du, 0xF8u,\r
+    0x2Du, 0x11u, 0xABu, 0xF1u, 0x40u, 0x02u, 0x3Fu, 0x2Au,\r
+    0x41u, 0xEAu, 0x00u, 0x25u, 0x0Au, 0xD8u, 0x2Du, 0x01u,\r
+    0x00u, 0x23u, 0x10u, 0x22u, 0x2Du, 0x48u, 0x11u, 0x18u,\r
+    0x4Cu, 0x5Du, 0x01u, 0x3Au, 0x23u, 0x44u, 0xDBu, 0xB2u,\r
+    0xF8u, 0xD1u, 0x26u, 0xE0u, 0x05u, 0xEBu, 0x0Bu, 0x23u,\r
+    0x1Cu, 0x02u, 0x4Fu, 0xF4u, 0x80u, 0x72u, 0x00u, 0x23u,\r
+    0x01u, 0x3Au, 0x10u, 0x5Du, 0x19u, 0x18u, 0xCBu, 0xB2u,\r
+    0x00u, 0x2Au, 0xF9u, 0xD1u, 0xBBu, 0xF1u, 0x3Fu, 0x0Fu,\r
+    0x17u, 0xD8u, 0x0Bu, 0xF5u, 0x10u, 0x34u, 0x05u, 0xEBu,\r
+    0x04u, 0x20u, 0x41u, 0x01u, 0x54u, 0x5Cu, 0x01u, 0x32u,\r
+    0x1Bu, 0x19u, 0x20u, 0x2Au, 0xDBu, 0xB2u, 0xF9u, 0xD1u,\r
+    0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x09u, 0xD1u, 0xFFu, 0x2Du,\r
+    0x07u, 0xD1u, 0x1Bu, 0x4Du, 0x1Bu, 0x4Cu, 0x28u, 0x78u,\r
+    0x19u, 0x1Au, 0x23u, 0x78u, 0xCAu, 0x1Au, 0x02u, 0xF0u,\r
+    0xFFu, 0x03u, 0x5Du, 0x42u, 0x8Du, 0xF8u, 0x2Cu, 0x51u,\r
+    0x00u, 0x25u, 0x01u, 0x24u, 0xDBu, 0xE6u, 0xFFu, 0xF7u,\r
+    0x29u, 0xFEu, 0x10u, 0xB9u, 0x14u, 0x4Du, 0x80u, 0x24u,\r
+    0x2Cu, 0x70u, 0x00u, 0xF0u, 0x47u, 0xF9u, 0x0Bu, 0xE0u,\r
+    0x04u, 0x25u, 0xD0u, 0xE6u, 0x01u, 0x26u, 0x00u, 0x27u,\r
+    0x04u, 0xE0u, 0x07u, 0x46u, 0x9Au, 0xE7u, 0x05u, 0x25u,\r
+    0x00u, 0x24u, 0xC8u, 0xE6u, 0x03u, 0x25u, 0xFBu, 0xE7u,\r
+    0x04u, 0x25u, 0xF9u, 0xE7u, 0x08u, 0x25u, 0xF7u, 0xE7u,\r
+    0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u, 0x47u, 0x46u,\r
+    0x5Eu, 0xE6u, 0x00u, 0x27u, 0xEDu, 0xE6u, 0x0Du, 0xF5u,\r
+    0x61u, 0x7Du, 0xBDu, 0xE8u, 0xF0u, 0x8Fu, 0x00u, 0xBFu,\r
+    0xCCu, 0x20u, 0x00u, 0x00u, 0xFFu, 0x7Fu, 0x00u, 0x40u,\r
+    0xD0u, 0xFFu, 0x01u, 0x00u, 0xD1u, 0xFFu, 0x01u, 0x00u,\r
+    0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0xC8u, 0xB0u,\r
+    0x00u, 0xF0u, 0x94u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u,\r
+    0x00u, 0xF0u, 0x16u, 0xF9u, 0x68u, 0x46u, 0x00u, 0xF0u,\r
+    0xA1u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u, 0x00u, 0xF0u,\r
+    0x0Fu, 0xF9u, 0x16u, 0x48u, 0x03u, 0x68u, 0x19u, 0x68u,\r
+    0x00u, 0x23u, 0x0Au, 0x46u, 0x22u, 0xB1u, 0x12u, 0xF8u,\r
+    0x01u, 0x4Du, 0xE3u, 0x18u, 0xDBu, 0xB2u, 0xF9u, 0xE7u,\r
+    0x42u, 0x68u, 0x10u, 0x78u, 0xC4u, 0x1Au, 0x04u, 0xF0u,\r
+    0xFFu, 0x03u, 0x83u, 0x42u, 0x00u, 0xD1u, 0x11u, 0xB9u,\r
+    0x00u, 0x20u, 0x00u, 0xF0u, 0xF9u, 0xF8u, 0x0Cu, 0x4Cu,\r
+    0xFFu, 0xF7u, 0xD4u, 0xFDu, 0x21u, 0x78u, 0x01u, 0xF0u,\r
+    0xC0u, 0x02u, 0x40u, 0x2Au, 0x00u, 0xD0u, 0x18u, 0xB1u,\r
+    0x00u, 0x20u, 0x20u, 0x70u, 0xFFu, 0xF7u, 0x0Cu, 0xFEu,\r
+    0x14u, 0x20u, 0xFFu, 0xF7u, 0x09u, 0xFEu, 0x80u, 0x20u,\r
+    0x20u, 0x70u, 0x00u, 0xF0u, 0xE7u, 0xF8u, 0x48u, 0xB0u,\r
+    0x10u, 0xBDu, 0x00u, 0xBFu, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu,\r
+    0xFAu, 0x46u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x0Au, 0x4Bu,\r
+    0x1Au, 0x78u, 0x02u, 0xF0u, 0xC0u, 0x00u, 0x80u, 0x28u,\r
+    0x0Cu, 0xD1u, 0x00u, 0x21u, 0x19u, 0x70u, 0x01u, 0x20u,\r
+    0xFFu, 0xF7u, 0x6Au, 0xFDu, 0x30u, 0xB1u, 0x01u, 0x20u,\r
+    0xFFu, 0xF7u, 0x66u, 0xFDu, 0xBDu, 0xE8u, 0x08u, 0x40u,\r
+    0xFFu, 0xF7u, 0x60u, 0xBDu, 0x08u, 0xBDu, 0x00u, 0xBFu,\r
+    0xFAu, 0x46u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u,\r
     0x02u, 0x30u, 0x80u, 0x08u, 0x00u, 0xF0u, 0x05u, 0x80u,\r
     0x00u, 0xBFu, 0x01u, 0x38u, 0x00u, 0x46u, 0x7Fu, 0xF4u,\r
     0xFCu, 0xAFu, 0x70u, 0x47u, 0xEFu, 0xF3u, 0x10u, 0x80u,\r
@@ -506,9 +509,9 @@ const uint8 cy_bootloader[] = {
     0x23u, 0xBEu, 0x00u, 0xBFu, 0xA5u, 0x43u, 0x00u, 0x40u,\r
     0x9Du, 0x60u, 0x00u, 0x40u, 0x94u, 0x43u, 0x00u, 0x40u,\r
     0x12u, 0x60u, 0x00u, 0x40u, 0xF8u, 0x51u, 0x00u, 0x40u,\r
-    0x84u, 0x60u, 0x00u, 0x40u, 0xF3u, 0x15u, 0x00u, 0x00u,\r
-    0xF1u, 0x15u, 0x00u, 0x00u, 0x31u, 0x14u, 0x00u, 0x00u,\r
-    0x89u, 0x15u, 0x00u, 0x00u, 0xBDu, 0x15u, 0x00u, 0x00u,\r
+    0x84u, 0x60u, 0x00u, 0x40u, 0x0Bu, 0x16u, 0x00u, 0x00u,\r
+    0x09u, 0x16u, 0x00u, 0x00u, 0x49u, 0x14u, 0x00u, 0x00u,\r
+    0xA1u, 0x15u, 0x00u, 0x00u, 0xD5u, 0x15u, 0x00u, 0x00u,\r
     0x18u, 0x4Bu, 0x01u, 0x22u, 0x10u, 0xB5u, 0x1Au, 0x70u,\r
     0x17u, 0x4Bu, 0x4Fu, 0xF4u, 0x00u, 0x04u, 0x1Cu, 0x60u,\r
     0x4Fu, 0xF0u, 0x80u, 0x74u, 0x1Cu, 0x60u, 0x1Au, 0x60u,\r
@@ -822,7 +825,7 @@ const uint8 cy_bootloader[] = {
     0x04u, 0x4Bu, 0x05u, 0x49u, 0x1Au, 0x78u, 0x01u, 0xEBu,\r
     0xC2u, 0x03u, 0x5Au, 0x68u, 0x02u, 0xEBu, 0xC0u, 0x00u,\r
     0xC0u, 0x68u, 0x70u, 0x47u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,\r
-    0xB0u, 0x20u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x3Du, 0x4Bu,\r
+    0xD4u, 0x20u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x3Du, 0x4Bu,\r
     0x1Au, 0x78u, 0x00u, 0x2Au, 0x74u, 0xD0u, 0x18u, 0x78u,\r
     0x41u, 0x1Eu, 0xC8u, 0xB2u, 0xFFu, 0xF7u, 0xE8u, 0xFFu,\r
     0xC3u, 0x68u, 0x05u, 0x7Au, 0x08u, 0x33u, 0x00u, 0x20u,\r
@@ -1009,9 +1012,9 @@ const uint8 cy_bootloader[] = {
     0x08u, 0x70u, 0x32u, 0xE0u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,\r
     0x00u, 0x60u, 0x00u, 0x40u, 0x01u, 0x60u, 0x00u, 0x40u,\r
     0x03u, 0x60u, 0x00u, 0x40u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,\r
-    0xB0u, 0x20u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u,\r
-    0x76u, 0x21u, 0x00u, 0x00u, 0xF2u, 0x21u, 0x00u, 0x00u,\r
-    0x6Cu, 0x21u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u,\r
+    0xD4u, 0x20u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u,\r
+    0x9Au, 0x21u, 0x00u, 0x00u, 0x16u, 0x22u, 0x00u, 0x00u,\r
+    0x90u, 0x21u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u,\r
     0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,\r
     0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,\r
     0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,\r
@@ -1039,92 +1042,94 @@ const uint8 cy_bootloader[] = {
     0x0Eu, 0x4Bu, 0x00u, 0x24u, 0xE8u, 0x1Au, 0x85u, 0x10u,\r
     0xACu, 0x42u, 0x05u, 0xD0u, 0x0Bu, 0x49u, 0x51u, 0xF8u,\r
     0x24u, 0x20u, 0x90u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u,\r
-    0x00u, 0xF0u, 0x34u, 0xF9u, 0x08u, 0x49u, 0x09u, 0x4Au,\r
+    0x00u, 0xF0u, 0x3Au, 0xF9u, 0x08u, 0x49u, 0x09u, 0x4Au,\r
     0x54u, 0x1Au, 0xA5u, 0x10u, 0x00u, 0x24u, 0xACu, 0x42u,\r
     0x05u, 0xD0u, 0x05u, 0x4Bu, 0x53u, 0xF8u, 0x24u, 0x00u,\r
     0x80u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u, 0x38u, 0xBDu,\r
-    0x10u, 0x22u, 0x00u, 0x00u, 0x10u, 0x22u, 0x00u, 0x00u,\r
-    0x10u, 0x22u, 0x00u, 0x00u, 0x18u, 0x22u, 0x00u, 0x00u,\r
+    0x34u, 0x22u, 0x00u, 0x00u, 0x34u, 0x22u, 0x00u, 0x00u,\r
+    0x34u, 0x22u, 0x00u, 0x00u, 0x3Cu, 0x22u, 0x00u, 0x00u,\r
     0x10u, 0xB5u, 0x00u, 0x23u, 0x93u, 0x42u, 0x03u, 0xD0u,\r
     0xCCu, 0x5Cu, 0xC4u, 0x54u, 0x01u, 0x33u, 0xF9u, 0xE7u,\r
     0x10u, 0xBDu, 0x82u, 0x18u, 0x03u, 0x46u, 0x93u, 0x42u,\r
     0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u,\r
-    0x70u, 0x47u, 0x00u, 0x00u, 0x58u, 0x22u, 0x00u, 0x00u,\r
-    0x81u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x10u, 0x51u, 0x00u, 0x40u, 0x30u, 0x00u, 0x50u, 0x51u,\r
+    0x70u, 0x47u, 0x00u, 0x00u, 0x80u, 0x22u, 0x00u, 0x00u,\r
+    0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+    0x10u, 0x51u, 0x00u, 0x40u, 0x20u, 0x00u, 0x50u, 0x51u,\r
     0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u, 0x00u, 0x40u,\r
     0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, 0x00u, 0x10u,\r
     0x00u, 0x14u, 0x01u, 0x40u, 0x00u, 0x08u, 0x00u, 0x40u,\r
     0x01u, 0x40u, 0x00u, 0x0Au, 0x00u, 0x4Cu, 0x01u, 0x40u,\r
     0x00u, 0x02u, 0x00u, 0x50u, 0x01u, 0x40u, 0x20u, 0x00u,\r
-    0x01u, 0x45u, 0x00u, 0x40u, 0x01u, 0x52u, 0x00u, 0x40u,\r
+    0x01u, 0x45u, 0x00u, 0x40u, 0x02u, 0x52u, 0x00u, 0x40u,\r
     0x01u, 0x17u, 0x01u, 0x40u, 0x01u, 0x19u, 0x01u, 0x40u,\r
     0x03u, 0x40u, 0x01u, 0x40u, 0x02u, 0x41u, 0x01u, 0x40u,\r
     0x02u, 0x42u, 0x01u, 0x40u, 0x02u, 0x43u, 0x01u, 0x40u,\r
     0x03u, 0x47u, 0x01u, 0x40u, 0x03u, 0x48u, 0x01u, 0x40u,\r
     0x02u, 0x4Cu, 0x01u, 0x40u, 0x01u, 0x51u, 0x01u, 0x40u,\r
-    0x7Eu, 0x02u, 0x7Cu, 0x40u, 0xEEu, 0x0Au, 0xEEu, 0x0Au,\r
-    0x33u, 0x80u, 0x36u, 0x40u, 0xCCu, 0x30u, 0xA6u, 0x40u,\r
-    0xA7u, 0x80u, 0xA6u, 0x40u, 0xA7u, 0x80u, 0xA6u, 0x40u,\r
-    0xA7u, 0x80u, 0x08u, 0x08u, 0x0Fu, 0x40u, 0xC2u, 0x0Cu,\r
-    0xAEu, 0x40u, 0xAFu, 0x80u, 0xEEu, 0x50u, 0xACu, 0x08u,\r
-    0xAFu, 0x40u, 0x00u, 0x0Au, 0x00u, 0xFFu, 0xFFu, 0x00u,\r
+    0x7Eu, 0x02u, 0x1Cu, 0x3Eu, 0x7Cu, 0x40u, 0xEEu, 0x0Au,\r
+    0xEEu, 0x0Au, 0x33u, 0x80u, 0x36u, 0x40u, 0xCCu, 0x30u,\r
+    0xA6u, 0x40u, 0xA7u, 0x80u, 0xA6u, 0x40u, 0xA7u, 0x80u,\r
+    0xA6u, 0x40u, 0xA7u, 0x80u, 0x08u, 0x08u, 0x0Fu, 0x40u,\r
+    0xC2u, 0x0Cu, 0xAEu, 0x40u, 0xAFu, 0x80u, 0xEEu, 0x50u,\r
+    0xACu, 0x08u, 0xAFu, 0x40u, 0x00u, 0x0Au, 0x00u, 0xFFu,\r
+    0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u,\r
+    0x3Eu, 0x00u, 0x00u, 0x3Eu, 0x00u, 0x00u, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0x00u, 0x69u, 0x30u, 0x13u, 0x2Eu,\r
+    0x00u, 0x14u, 0x01u, 0x01u, 0x01u, 0x00u, 0x00u, 0x00u,\r
+    0xDCu, 0x20u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
+    0x16u, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
+    0xECu, 0x20u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
+    0xEDu, 0x21u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u,\r
+    0x0Eu, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
+    0x20u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+    0x0Cu, 0x21u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,\r
+    0x01u, 0x03u, 0x40u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,\r
+    0x82u, 0x03u, 0x40u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,\r
+    0x01u, 0x00u, 0x00u, 0x00u, 0x28u, 0x21u, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0x21u, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x21u, 0x00u, 0x00u,\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0xFCu,\r
-    0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu,\r
-    0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x69u, 0x30u, 0x13u, 0x2Eu, 0x00u, 0x14u, 0x01u, 0x01u,\r
-    0x01u, 0x00u, 0x00u, 0x00u, 0xB8u, 0x20u, 0x00u, 0x00u,\r
-    0x01u, 0x00u, 0x00u, 0x00u, 0xF2u, 0x21u, 0x00u, 0x00u,\r
-    0x01u, 0x00u, 0x00u, 0x00u, 0xC8u, 0x20u, 0x00u, 0x00u,\r
-    0x01u, 0x00u, 0x00u, 0x00u, 0xC9u, 0x21u, 0x00u, 0x00u,\r
-    0x02u, 0x00u, 0x00u, 0x00u, 0xEAu, 0x20u, 0x00u, 0x00u,\r
-    0x01u, 0x00u, 0x00u, 0x00u, 0xFCu, 0x20u, 0x00u, 0x00u,\r
-    0x00u, 0x00u, 0x00u, 0x00u, 0xE8u, 0x20u, 0x00u, 0x00u,\r
-    0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x03u, 0x40u, 0x00u,\r
-    0x03u, 0x00u, 0x00u, 0x00u, 0x82u, 0x03u, 0x40u, 0x00u,\r
-    0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
-    0x04u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x38u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x2Cu, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
-    0x44u, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
-    0xDBu, 0x21u, 0x00u, 0x00u, 0x41u, 0x00u, 0x00u, 0x00u,\r
-    0x33u, 0xC2u, 0xFFu, 0x1Fu, 0x74u, 0xC2u, 0xFFu, 0x1Fu,\r
-    0x41u, 0x00u, 0x00u, 0x00u, 0xF2u, 0xC1u, 0xFFu, 0x1Fu,\r
-    0xEEu, 0xC1u, 0xFFu, 0x1Fu, 0x24u, 0x00u, 0x05u, 0x01u,\r
-    0x09u, 0x00u, 0xA1u, 0x00u, 0x09u, 0x00u, 0xA1u, 0x00u,\r
+    0x01u, 0x00u, 0x00u, 0x00u, 0x68u, 0x21u, 0x00u, 0x00u,\r
+    0x01u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x21u, 0x00u, 0x00u,\r
+    0x41u, 0x00u, 0x00u, 0x00u, 0x33u, 0xC2u, 0xFFu, 0x1Fu,\r
+    0x74u, 0xC2u, 0xFFu, 0x1Fu, 0x41u, 0x00u, 0x00u, 0x00u,\r
+    0xF2u, 0xC1u, 0xFFu, 0x1Fu, 0xEEu, 0xC1u, 0xFFu, 0x1Fu,\r
+    0x24u, 0x00u, 0x05u, 0x01u, 0x09u, 0x00u, 0xA1u, 0x00u,\r
+    0x09u, 0x00u, 0xA1u, 0x00u, 0x09u, 0x00u, 0x15u, 0x00u,\r
+    0x25u, 0xFFu, 0x75u, 0x08u, 0x95u, 0x40u, 0x91u, 0x02u,\r
     0x09u, 0x00u, 0x15u, 0x00u, 0x25u, 0xFFu, 0x75u, 0x08u,\r
-    0x95u, 0x40u, 0x91u, 0x02u, 0x09u, 0x00u, 0x15u, 0x00u,\r
-    0x25u, 0xFFu, 0x75u, 0x08u, 0x95u, 0x40u, 0x81u, 0x02u,\r
-    0xC0u, 0xC0u, 0x00u, 0x00u, 0x0Au, 0x03u, 0x30u, 0x00u,\r
-    0x30u, 0x00u, 0x30u, 0x00u, 0x31u, 0x00u, 0x04u, 0x03u,\r
-    0x09u, 0x04u, 0x2Cu, 0x03u, 0x43u, 0x00u, 0x79u, 0x00u,\r
-    0x70u, 0x00u, 0x72u, 0x00u, 0x65u, 0x00u, 0x73u, 0x00u,\r
-    0x73u, 0x00u, 0x20u, 0x00u, 0x53u, 0x00u, 0x65u, 0x00u,\r
-    0x6Du, 0x00u, 0x69u, 0x00u, 0x63u, 0x00u, 0x6Fu, 0x00u,\r
-    0x6Eu, 0x00u, 0x64u, 0x00u, 0x75u, 0x00u, 0x63u, 0x00u,\r
-    0x74u, 0x00u, 0x6Fu, 0x00u, 0x72u, 0x00u, 0x22u, 0x03u,\r
-    0x50u, 0x00u, 0x53u, 0x00u, 0x6Fu, 0x00u, 0x43u, 0x00u,\r
-    0x33u, 0x00u, 0x20u, 0x00u, 0x42u, 0x00u, 0x6Fu, 0x00u,\r
-    0x6Fu, 0x00u, 0x74u, 0x00u, 0x6Cu, 0x00u, 0x6Fu, 0x00u,\r
-    0x61u, 0x00u, 0x64u, 0x00u, 0x65u, 0x00u, 0x72u, 0x00u,\r
-    0x00u, 0x09u, 0x02u, 0x29u, 0x00u, 0x01u, 0x01u, 0x00u,\r
-    0x80u, 0x00u, 0x09u, 0x04u, 0x00u, 0x00u, 0x02u, 0x03u,\r
-    0x00u, 0x00u, 0x02u, 0x09u, 0x21u, 0x11u, 0x01u, 0x00u,\r
-    0x01u, 0x22u, 0x24u, 0x00u, 0x07u, 0x05u, 0x01u, 0x03u,\r
-    0x40u, 0x00u, 0x01u, 0x07u, 0x05u, 0x82u, 0x03u, 0x40u,\r
-    0x00u, 0x01u, 0x12u, 0x01u, 0x00u, 0x02u, 0x00u, 0x00u,\r
-    0x00u, 0x08u, 0xB4u, 0x04u, 0x1Du, 0xB7u, 0x01u, 0x30u,\r
-    0x01u, 0x02u, 0x80u, 0x01u, 0xF8u, 0xB5u, 0x00u, 0xBFu,\r
-    0xF8u, 0xBCu, 0x08u, 0xBCu, 0x9Eu, 0x46u, 0x70u, 0x47u,\r
-    0x51u, 0x00u, 0x00u, 0x00u, 0xB9u, 0x01u, 0x00u, 0x00u,\r
+    0x95u, 0x40u, 0x81u, 0x02u, 0xC0u, 0xC0u, 0x00u, 0x00u,\r
+    0x0Au, 0x03u, 0x30u, 0x00u, 0x30u, 0x00u, 0x30u, 0x00u,\r
+    0x31u, 0x00u, 0x04u, 0x03u, 0x09u, 0x04u, 0x2Cu, 0x03u,\r
+    0x43u, 0x00u, 0x79u, 0x00u, 0x70u, 0x00u, 0x72u, 0x00u,\r
+    0x65u, 0x00u, 0x73u, 0x00u, 0x73u, 0x00u, 0x20u, 0x00u,\r
+    0x53u, 0x00u, 0x65u, 0x00u, 0x6Du, 0x00u, 0x69u, 0x00u,\r
+    0x63u, 0x00u, 0x6Fu, 0x00u, 0x6Eu, 0x00u, 0x64u, 0x00u,\r
+    0x75u, 0x00u, 0x63u, 0x00u, 0x74u, 0x00u, 0x6Fu, 0x00u,\r
+    0x72u, 0x00u, 0x22u, 0x03u, 0x50u, 0x00u, 0x53u, 0x00u,\r
+    0x6Fu, 0x00u, 0x43u, 0x00u, 0x33u, 0x00u, 0x20u, 0x00u,\r
+    0x42u, 0x00u, 0x6Fu, 0x00u, 0x6Fu, 0x00u, 0x74u, 0x00u,\r
+    0x6Cu, 0x00u, 0x6Fu, 0x00u, 0x61u, 0x00u, 0x64u, 0x00u,\r
+    0x65u, 0x00u, 0x72u, 0x00u, 0x00u, 0x09u, 0x02u, 0x29u,\r
+    0x00u, 0x01u, 0x01u, 0x00u, 0x80u, 0x00u, 0x09u, 0x04u,\r
+    0x00u, 0x00u, 0x02u, 0x03u, 0x00u, 0x00u, 0x02u, 0x09u,\r
+    0x21u, 0x11u, 0x01u, 0x00u, 0x01u, 0x22u, 0x24u, 0x00u,\r
+    0x07u, 0x05u, 0x01u, 0x03u, 0x40u, 0x00u, 0x01u, 0x07u,\r
+    0x05u, 0x82u, 0x03u, 0x40u, 0x00u, 0x01u, 0x12u, 0x01u,\r
+    0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x08u, 0xB4u, 0x04u,\r
+    0x1Du, 0xB7u, 0x01u, 0x30u, 0x01u, 0x02u, 0x80u, 0x01u,\r
     0xF8u, 0xB5u, 0x00u, 0xBFu, 0xF8u, 0xBCu, 0x08u, 0xBCu,\r
-    0x9Eu, 0x46u, 0x70u, 0x47u, 0x2Du, 0x00u, 0x00u, 0x00u,\r
-    0x38u, 0x22u, 0x00u, 0x00u, 0x08u, 0xC1u, 0xFFu, 0x1Fu,\r
-    0x20u, 0x00u, 0x00u, 0x00u, 0x50u, 0x01u, 0x00u, 0x00u,\r
-    0x00u, 0x00u, 0x00u, 0x00u, 0xECu, 0x1Fu, 0x00u, 0x00u,\r
-    0xF0u, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du,\r
+    0x9Eu, 0x46u, 0x70u, 0x47u, 0x51u, 0x00u, 0x00u, 0x00u,\r
+    0xB9u, 0x01u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x00u, 0xBFu,\r
+    0xF8u, 0xBCu, 0x08u, 0xBCu, 0x9Eu, 0x46u, 0x70u, 0x47u,\r
+    0x2Du, 0x00u, 0x00u, 0x00u, 0x60u, 0x22u, 0x00u, 0x00u,\r
+    0x08u, 0xC1u, 0xFFu, 0x1Fu, 0x20u, 0x00u, 0x00u, 0x00u,\r
+    0x50u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x20u, 0x00u, 0x00u,\r
+    0x08u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du,\r
     0x00u, 0xFAu, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u,\r
     0x00u, 0x90u, 0xD0u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u,\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
@@ -1142,11 +1147,6 @@ const uint8 cy_bootloader[] = {
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
 \r
 #if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
@@ -1158,7 +1158,7 @@ __attribute__ ((__section__(".cymeta"), used))
 #endif\r
 const uint8 cy_metadata[] = {\r
     0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u,\r
-    0x2Eu, 0x1Fu, 0x88u, 0x6Bu};\r
+    0x2Eu, 0x1Fu, 0x8Cu, 0x6Bu};\r
 \r
 #if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
 __attribute__ ((__section__(".cycustnvl"), used))\r

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
index bc90348..46fd82e 100755 (executable)
--- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
@@ -13,6 +13,32 @@
 #define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
+/* SCSI_CTL_PHASE */\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+\r
 /* USBFS_arb_int */\r
 #define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
@@ -33,16 +59,6 @@
 #define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
-/* SCSI_ATN_ISR */\r
-#define SCSI_ATN_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_ATN_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_ATN_ISR__INTC_MASK 0x800u\r
-#define SCSI_ATN_ISR__INTC_NUMBER 11u\r
-#define SCSI_ATN_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_ATN_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_11\r
-#define SCSI_ATN_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_ATN_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
 /* SCSI_Out_DBx */\r
 #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
 #define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX\r
@@ -514,8 +530,8 @@
 #define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
 #define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB07_MSK\r
 #define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_RxStsReg__4__POS 4\r
 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
@@ -523,9 +539,9 @@
 #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
 #define SDCard_BSPIM_RxStsReg__6__POS 6\r
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB04_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB04_ST\r
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
 #define SDCard_BSPIM_TxStsReg__0__POS 0\r
 #define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
@@ -572,28 +588,6 @@
 #define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
-/* SCSI_CTL_IO */\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-\r
 /* SCSI_In_DBx */\r
 #define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
 #define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE\r
@@ -1038,21 +1032,21 @@
 #define SD_Data_Clk__PM_STBY_MSK 0x01u\r
 \r
 /* SD_Init_Clk */\r
-#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
-#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
-#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
+#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG2_CFG0\r
+#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG2_CFG1\r
+#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG2_CFG2\r
 #define SD_Init_Clk__CFG2_SRC_SEL_MASK 0x07u\r
-#define SD_Init_Clk__INDEX 0x01u\r
+#define SD_Init_Clk__INDEX 0x02u\r
 #define SD_Init_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define SD_Init_Clk__PM_ACT_MSK 0x02u\r
+#define SD_Init_Clk__PM_ACT_MSK 0x04u\r
 #define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define SD_Init_Clk__PM_STBY_MSK 0x02u\r
+#define SD_Init_Clk__PM_STBY_MSK 0x04u\r
 \r
 /* scsiTarget */\r
 #define scsiTarget_StatusReg__0__MASK 0x01u\r
 #define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
 #define scsiTarget_StatusReg__1__MASK 0x02u\r
 #define scsiTarget_StatusReg__1__POS 1\r
 #define scsiTarget_StatusReg__2__MASK 0x04u\r
@@ -1060,9 +1054,9 @@
 #define scsiTarget_StatusReg__3__MASK 0x08u\r
 #define scsiTarget_StatusReg__3__POS 3\r
 #define scsiTarget_StatusReg__MASK 0x0Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB00_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB00_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
 #define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
 #define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
 #define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK\r
@@ -1301,7 +1295,6 @@
 #define SCSI_ATN__DM2 CYREG_PRT12_DM2\r
 #define SCSI_ATN__DR CYREG_PRT12_DR\r
 #define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_ATN__INTSTAT CYREG_PICU12_INTSTAT\r
 #define SCSI_ATN__INT__MASK 0x20u\r
 #define SCSI_ATN__INT__PC CYREG_PRT12_PC5\r
 #define SCSI_ATN__INT__PORT 12u\r
@@ -1322,7 +1315,17 @@
 #define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
 #define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
 #define SCSI_ATN__SLW CYREG_PRT12_SLW\r
-#define SCSI_ATN__SNAP CYREG_PICU12_SNAP\r
+\r
+/* SCSI_CLK */\r
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
+#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u\r
+#define SCSI_CLK__INDEX 0x01u\r
+#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define SCSI_CLK__PM_ACT_MSK 0x02u\r
+#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define SCSI_CLK__PM_STBY_MSK 0x02u\r
 \r
 /* SCSI_Out */\r
 #define SCSI_Out__0__AG CYREG_PRT4_AG\r
@@ -1676,33 +1679,33 @@
 #define SCSI_Out__BSY__PS CYREG_PRT0_PS\r
 #define SCSI_Out__BSY__SHIFT 7\r
 #define SCSI_Out__BSY__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__CD__AG CYREG_PRT0_AG\r
-#define SCSI_Out__CD__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__CD__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__CD__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__CD__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__CD__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__CD__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__CD__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__CD__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__CD__DR CYREG_PRT0_DR\r
-#define SCSI_Out__CD__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__CD__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__CD__MASK 0x04u\r
-#define SCSI_Out__CD__PC CYREG_PRT0_PC2\r
-#define SCSI_Out__CD__PORT 0u\r
-#define SCSI_Out__CD__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__CD__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__CD__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__CD__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__CD__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__CD__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__CD__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__CD__PS CYREG_PRT0_PS\r
-#define SCSI_Out__CD__SHIFT 2\r
-#define SCSI_Out__CD__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__CD_raw__MASK 0x04u\r
+#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2\r
+#define SCSI_Out__CD_raw__PORT 0u\r
+#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__CD_raw__SHIFT 2\r
+#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
 #define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG\r
 #define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX\r
 #define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE\r
@@ -1757,33 +1760,33 @@
 #define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
 #define SCSI_Out__IO_raw__SHIFT 0\r
 #define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__MSG__AG CYREG_PRT0_AG\r
-#define SCSI_Out__MSG__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__MSG__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__MSG__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__MSG__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__MSG__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__MSG__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__MSG__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__MSG__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__MSG__DR CYREG_PRT0_DR\r
-#define SCSI_Out__MSG__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__MSG__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__MSG__MASK 0x10u\r
-#define SCSI_Out__MSG__PC CYREG_PRT0_PC4\r
-#define SCSI_Out__MSG__PORT 0u\r
-#define SCSI_Out__MSG__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__MSG__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__MSG__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__MSG__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__MSG__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__MSG__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__MSG__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__MSG__PS CYREG_PRT0_PS\r
-#define SCSI_Out__MSG__SHIFT 4\r
-#define SCSI_Out__MSG__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__MSG_raw__MASK 0x10u\r
+#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4\r
+#define SCSI_Out__MSG_raw__PORT 0u\r
+#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__MSG_raw__SHIFT 4\r
+#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW\r
 #define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
 #define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
 #define SCSI_Out__REQ__BIE CYREG_PRT0_BIE\r
@@ -2671,9 +2674,9 @@
 #define CYDEV_CHIP_FAMILY_PSOC5 3u\r
 #define CYDEV_CHIP_DIE_PSOC5LP 4u\r
 #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP\r
-#define BCLK__BUS_CLK__HZ 64000000U\r
-#define BCLK__BUS_CLK__KHZ 64000U\r
-#define BCLK__BUS_CLK__MHZ 64U\r
+#define BCLK__BUS_CLK__HZ 60000000U\r
+#define BCLK__BUS_CLK__KHZ 60000U\r
+#define BCLK__BUS_CLK__MHZ 60U\r
 #define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT\r
 #define CYDEV_CHIP_DIE_LEOPARD 1u\r
 #define CYDEV_CHIP_DIE_PANTHER 3u\r
@@ -2732,7 +2735,7 @@
 #define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG\r
 #define CYDEV_DMA_CHANNELS_AVAILABLE 24u\r
 #define CYDEV_ECC_ENABLE 0\r
-#define CYDEV_HEAP_SIZE 0x1000\r
+#define CYDEV_HEAP_SIZE 0x0256\r
 #define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
 #define CYDEV_INTR_RISING 0x00000000u\r
 #define CYDEV_PROJ_TYPE 2\r
@@ -2741,7 +2744,7 @@
 #define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3\r
 #define CYDEV_PROJ_TYPE_STANDARD 0\r
 #define CYDEV_PROTECTION_ENABLE 0\r
-#define CYDEV_STACK_SIZE 0x4000\r
+#define CYDEV_STACK_SIZE 0x2000\r
 #define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP \r
 #define CYDEV_USE_BUNDLED_CMSIS 1\r
 #define CYDEV_VARIABLE_VDDA 0\r

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
index 6c7544e..4e6f1da 100755 (executable)
--- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
+++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
@@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode)
 }\r
 #endif\r
 \r
-#define CY_CFG_BASE_ADDR_COUNT 34u\r
+#define CY_CFG_BASE_ADDR_COUNT 33u\r
 CYPACKED typedef struct\r
 {\r
        uint8 offset;\r
@@ -189,8 +189,10 @@ static void ClockSetup(void)
        /* Configure Digital Clocks based on settings from Clock DWR */\r
        CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0001u);\r
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x10u);\r
-       CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x001Du);\r
-       CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x19u);\r
+       CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u);\r
+       CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u);\r
+       CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x001Du);\r
+       CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);\r
 \r
        /* Configure ILO based on settings from Clock DWR */\r
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);\r
@@ -200,7 +202,7 @@ static void ClockSetup(void)
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));\r
 \r
        /* Configure PLL based on settings from Clock DWR */\r
-       CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u);\r
+       CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0919u);\r
        CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);\r
        /* Wait up to 250us for the PLL to lock */\r
        pllLock = 0u;\r
@@ -226,7 +228,7 @@ static void ClockSetup(void)
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);\r
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);\r
 \r
-       CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x02u)));\r
+       CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x06u)));\r
 }\r
 \r
 \r
@@ -313,7 +315,7 @@ void cyfitter_cfg(void)
 {\r
        /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */\r
        static const uint8 CYCODE BS_IOPINS0_0_VAL[] = {\r
-               0x00u, 0xFFu, 0xFFu, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u};\r
+               0x00u, 0xFFu, 0xFFu, 0x00u, 0x17u, 0x00u, 0x00u, 0x00u};\r
 \r
        /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */\r
        static const uint8 CYCODE BS_IOPINS0_7_VAL[] = {\r
@@ -362,222 +364,207 @@ void cyfitter_cfg(void)
 \r
        {\r
                static const uint32 CYCODE cy_cfg_addr_table[] = {\r
-                       0x40004503u, /* Base address: 0x40004500 Count: 3 */\r
-                       0x40005209u, /* Base address: 0x40005200 Count: 9 */\r
+                       0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
+                       0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
                        0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
-                       0x40010044u, /* Base address: 0x40010000 Count: 68 */\r
-                       0x40010135u, /* Base address: 0x40010100 Count: 53 */\r
-                       0x4001023Eu, /* Base address: 0x40010200 Count: 62 */\r
-                       0x40010350u, /* Base address: 0x40010300 Count: 80 */\r
-                       0x4001044Bu, /* Base address: 0x40010400 Count: 75 */\r
-                       0x40010554u, /* Base address: 0x40010500 Count: 84 */\r
-                       0x40010605u, /* Base address: 0x40010600 Count: 5 */\r
-                       0x4001074Bu, /* Base address: 0x40010700 Count: 75 */\r
-                       0x40010911u, /* Base address: 0x40010900 Count: 17 */\r
-                       0x40010A37u, /* Base address: 0x40010A00 Count: 55 */\r
-                       0x40010B35u, /* Base address: 0x40010B00 Count: 53 */\r
-                       0x40010D0Fu, /* Base address: 0x40010D00 Count: 15 */\r
-                       0x40010F02u, /* Base address: 0x40010F00 Count: 2 */\r
+                       0x40010048u, /* Base address: 0x40010000 Count: 72 */\r
+                       0x4001012Cu, /* Base address: 0x40010100 Count: 44 */\r
+                       0x40010235u, /* Base address: 0x40010200 Count: 53 */\r
+                       0x4001034Fu, /* Base address: 0x40010300 Count: 79 */\r
+                       0x40010448u, /* Base address: 0x40010400 Count: 72 */\r
+                       0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
+                       0x40010606u, /* Base address: 0x40010600 Count: 6 */\r
+                       0x40010747u, /* Base address: 0x40010700 Count: 71 */\r
+                       0x40010901u, /* Base address: 0x40010900 Count: 1 */\r
+                       0x40010B0Cu, /* Base address: 0x40010B00 Count: 12 */\r
+                       0x40010C3Bu, /* Base address: 0x40010C00 Count: 59 */\r
+                       0x40010D39u, /* Base address: 0x40010D00 Count: 57 */\r
+                       0x40010F04u, /* Base address: 0x40010F00 Count: 4 */\r
                        0x40011504u, /* Base address: 0x40011500 Count: 4 */\r
-                       0x40011642u, /* Base address: 0x40011600 Count: 66 */\r
-                       0x40011747u, /* Base address: 0x40011700 Count: 71 */\r
-                       0x40011908u, /* Base address: 0x40011900 Count: 8 */\r
-                       0x40011B05u, /* Base address: 0x40011B00 Count: 5 */\r
-                       0x4001400Fu, /* Base address: 0x40014000 Count: 15 */\r
-                       0x4001410Du, /* Base address: 0x40014100 Count: 13 */\r
-                       0x40014206u, /* Base address: 0x40014200 Count: 6 */\r
-                       0x40014308u, /* Base address: 0x40014300 Count: 8 */\r
-                       0x4001440Au, /* Base address: 0x40014400 Count: 10 */\r
-                       0x40014514u, /* Base address: 0x40014500 Count: 20 */\r
-                       0x40014609u, /* Base address: 0x40014600 Count: 9 */\r
-                       0x40014709u, /* Base address: 0x40014700 Count: 9 */\r
-                       0x4001480Bu, /* Base address: 0x40014800 Count: 11 */\r
-                       0x40014907u, /* Base address: 0x40014900 Count: 7 */\r
+                       0x4001164Du, /* Base address: 0x40011600 Count: 77 */\r
+                       0x4001173Fu, /* Base address: 0x40011700 Count: 63 */\r
+                       0x40011901u, /* Base address: 0x40011900 Count: 1 */\r
+                       0x4001400Cu, /* Base address: 0x40014000 Count: 12 */\r
+                       0x4001410Fu, /* Base address: 0x40014100 Count: 15 */\r
+                       0x4001420Bu, /* Base address: 0x40014200 Count: 11 */\r
+                       0x40014306u, /* Base address: 0x40014300 Count: 6 */\r
+                       0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
+                       0x40014513u, /* Base address: 0x40014500 Count: 19 */\r
+                       0x4001460Au, /* Base address: 0x40014600 Count: 10 */\r
+                       0x40014703u, /* Base address: 0x40014700 Count: 3 */\r
+                       0x4001480Du, /* Base address: 0x40014800 Count: 13 */\r
+                       0x40014908u, /* Base address: 0x40014900 Count: 8 */\r
                        0x40014C02u, /* Base address: 0x40014C00 Count: 2 */\r
-                       0x40015006u, /* Base address: 0x40015000 Count: 6 */\r
+                       0x4001500Au, /* Base address: 0x40015000 Count: 10 */\r
                        0x40015101u, /* Base address: 0x40015100 Count: 1 */\r
                };\r
 \r
                static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
                        {0x36u, 0x02u},\r
-                       {0x65u, 0x02u},\r
                        {0x7Eu, 0x02u},\r
+                       {0x00u, 0x12u},\r
                        {0x01u, 0x01u},\r
-                       {0x18u, 0x0Cu},\r
-                       {0x19u, 0x04u},\r
+                       {0x18u, 0x04u},\r
+                       {0x19u, 0x08u},\r
                        {0x1Cu, 0x61u},\r
-                       {0x20u, 0x50u},\r
-                       {0x21u, 0x98u},\r
-                       {0x30u, 0x05u},\r
-                       {0x31u, 0x09u},\r
+                       {0x20u, 0xA8u},\r
+                       {0x21u, 0xC8u},\r
+                       {0x30u, 0x03u},\r
+                       {0x31u, 0x06u},\r
                        {0x7Cu, 0x40u},\r
-                       {0x33u, 0x03u},\r
+                       {0x33u, 0x01u},\r
                        {0x87u, 0x0Fu},\r
-                       {0x00u, 0x0Du},\r
-                       {0x03u, 0x04u},\r
-                       {0x04u, 0x01u},\r
-                       {0x06u, 0x32u},\r
-                       {0x07u, 0x24u},\r
-                       {0x08u, 0x02u},\r
-                       {0x09u, 0x24u},\r
-                       {0x0Au, 0x54u},\r
-                       {0x0Bu, 0x12u},\r
-                       {0x0Du, 0x24u},\r
-                       {0x0Eu, 0x10u},\r
-                       {0x0Fu, 0x09u},\r
-                       {0x14u, 0x62u},\r
-                       {0x16u, 0x08u},\r
-                       {0x1Bu, 0x03u},\r
-                       {0x1Cu, 0x02u},\r
-                       {0x1Eu, 0x0Du},\r
-                       {0x1Fu, 0x18u},\r
+                       {0x03u, 0x08u},\r
+                       {0x04u, 0x21u},\r
+                       {0x06u, 0x42u},\r
+                       {0x07u, 0x40u},\r
+                       {0x08u, 0x42u},\r
+                       {0x0Au, 0x28u},\r
+                       {0x0Bu, 0x48u},\r
+                       {0x0Cu, 0x0Du},\r
+                       {0x0Fu, 0x06u},\r
+                       {0x10u, 0x02u},\r
+                       {0x11u, 0x01u},\r
+                       {0x12u, 0x0Du},\r
+                       {0x14u, 0x22u},\r
+                       {0x15u, 0x48u},\r
+                       {0x16u, 0x84u},\r
+                       {0x17u, 0x12u},\r
+                       {0x18u, 0xC0u},\r
+                       {0x1Bu, 0x30u},\r
+                       {0x1Cu, 0x0Du},\r
+                       {0x1Du, 0x01u},\r
                        {0x20u, 0x0Du},\r
-                       {0x23u, 0x20u},\r
+                       {0x21u, 0x48u},\r
+                       {0x23u, 0x24u},\r
                        {0x24u, 0x0Du},\r
+                       {0x25u, 0x01u},\r
                        {0x28u, 0x0Du},\r
-                       {0x29u, 0x40u},\r
-                       {0x2Cu, 0x0Du},\r
-                       {0x30u, 0x70u},\r
-                       {0x33u, 0x40u},\r
-                       {0x35u, 0x07u},\r
-                       {0x36u, 0x0Fu},\r
-                       {0x37u, 0x38u},\r
-                       {0x3Au, 0x80u},\r
+                       {0x29u, 0x01u},\r
+                       {0x2Cu, 0x10u},\r
+                       {0x30u, 0x0Fu},\r
+                       {0x33u, 0x01u},\r
+                       {0x34u, 0xE0u},\r
+                       {0x35u, 0x70u},\r
+                       {0x36u, 0x10u},\r
+                       {0x37u, 0x0Eu},\r
+                       {0x38u, 0x20u},\r
+                       {0x39u, 0x08u},\r
+                       {0x3Au, 0x02u},\r
+                       {0x3Eu, 0x40u},\r
                        {0x3Fu, 0x04u},\r
                        {0x58u, 0x0Bu},\r
                        {0x59u, 0x04u},\r
-                       {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x99u},\r
+                       {0x5Cu, 0x19u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x24u},\r
-                       {0x82u, 0x09u},\r
-                       {0x85u, 0x08u},\r
-                       {0x87u, 0x04u},\r
-                       {0x8Au, 0x18u},\r
-                       {0x8Bu, 0x09u},\r
-                       {0x8Eu, 0x03u},\r
-                       {0x96u, 0x24u},\r
-                       {0x98u, 0x24u},\r
-                       {0x9Au, 0x12u},\r
-                       {0x9Eu, 0x20u},\r
-                       {0x9Fu, 0x06u},\r
-                       {0xA1u, 0x08u},\r
-                       {0xA2u, 0x80u},\r
-                       {0xA3u, 0x03u},\r
-                       {0xA6u, 0x04u},\r
-                       {0xAAu, 0x40u},\r
-                       {0xACu, 0x40u},\r
-                       {0xAEu, 0x80u},\r
-                       {0xAFu, 0x08u},\r
-                       {0xB0u, 0xC0u},\r
-                       {0xB1u, 0x0Eu},\r
-                       {0xB4u, 0x38u},\r
-                       {0xB5u, 0x01u},\r
+                       {0x83u, 0x04u},\r
+                       {0x84u, 0x02u},\r
+                       {0x87u, 0x10u},\r
+                       {0x8Cu, 0x01u},\r
+                       {0x8Eu, 0x02u},\r
+                       {0x8Fu, 0x08u},\r
+                       {0x90u, 0x07u},\r
+                       {0x95u, 0x01u},\r
+                       {0x97u, 0x04u},\r
+                       {0x99u, 0x01u},\r
+                       {0x9Bu, 0x02u},\r
+                       {0xA0u, 0x02u},\r
+                       {0xA1u, 0x06u},\r
+                       {0xA3u, 0x01u},\r
+                       {0xA4u, 0x06u},\r
+                       {0xAAu, 0x05u},\r
+                       {0xABu, 0x07u},\r
+                       {0xADu, 0x08u},\r
+                       {0xAEu, 0x07u},\r
+                       {0xAFu, 0x10u},\r
+                       {0xB3u, 0x07u},\r
                        {0xB6u, 0x07u},\r
-                       {0xBEu, 0x01u},\r
-                       {0xBFu, 0x10u},\r
+                       {0xB7u, 0x18u},\r
+                       {0xBFu, 0x40u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x99u},\r
+                       {0xDCu, 0x11u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x60u},\r
-                       {0x03u, 0x60u},\r
-                       {0x05u, 0x50u},\r
-                       {0x06u, 0x40u},\r
-                       {0x07u, 0x04u},\r
-                       {0x0Au, 0x22u},\r
-                       {0x0Du, 0x14u},\r
-                       {0x0Eu, 0x01u},\r
-                       {0x11u, 0x14u},\r
-                       {0x13u, 0x41u},\r
-                       {0x15u, 0x40u},\r
-                       {0x16u, 0xA4u},\r
-                       {0x18u, 0x40u},\r
-                       {0x1Au, 0x02u},\r
-                       {0x1Du, 0x50u},\r
-                       {0x1Eu, 0x40u},\r
-                       {0x21u, 0x20u},\r
-                       {0x22u, 0x84u},\r
-                       {0x23u, 0x08u},\r
-                       {0x25u, 0x10u},\r
-                       {0x27u, 0x80u},\r
-                       {0x29u, 0x01u},\r
-                       {0x2Bu, 0x04u},\r
-                       {0x2Cu, 0x02u},\r
-                       {0x2Fu, 0x40u},\r
+                       {0x00u, 0x20u},\r
+                       {0x03u, 0x21u},\r
+                       {0x05u, 0x08u},\r
+                       {0x06u, 0x01u},\r
+                       {0x08u, 0x40u},\r
+                       {0x0Au, 0x64u},\r
+                       {0x0Fu, 0x80u},\r
+                       {0x10u, 0x88u},\r
+                       {0x11u, 0x04u},\r
+                       {0x12u, 0x02u},\r
+                       {0x16u, 0x42u},\r
+                       {0x17u, 0x24u},\r
+                       {0x19u, 0x80u},\r
+                       {0x1Au, 0x44u},\r
+                       {0x1Fu, 0x80u},\r
+                       {0x21u, 0x68u},\r
+                       {0x24u, 0x20u},\r
+                       {0x26u, 0x44u},\r
+                       {0x27u, 0x20u},\r
+                       {0x28u, 0x08u},\r
+                       {0x2Au, 0x04u},\r
+                       {0x2Bu, 0xC0u},\r
+                       {0x2Du, 0x40u},\r
+                       {0x2Fu, 0x84u},\r
+                       {0x30u, 0x02u},\r
                        {0x31u, 0x20u},\r
-                       {0x32u, 0x80u},\r
-                       {0x37u, 0x80u},\r
-                       {0x39u, 0x28u},\r
-                       {0x3Au, 0x42u},\r
-                       {0x3Bu, 0x80u},\r
-                       {0x3Cu, 0x10u},\r
-                       {0x3Fu, 0x04u},\r
-                       {0x58u, 0x84u},\r
-                       {0x59u, 0x02u},\r
-                       {0x5Bu, 0x10u},\r
+                       {0x33u, 0x44u},\r
+                       {0x37u, 0x24u},\r
+                       {0x38u, 0x20u},\r
+                       {0x39u, 0x89u},\r
+                       {0x3Du, 0x80u},\r
+                       {0x3Fu, 0x09u},\r
                        {0x6Du, 0x40u},\r
-                       {0x78u, 0x02u},\r
-                       {0x7Cu, 0x80u},\r
-                       {0x7Fu, 0x01u},\r
-                       {0x80u, 0x40u},\r
-                       {0x81u, 0x20u},\r
-                       {0x86u, 0x80u},\r
-                       {0xC0u, 0xDFu},\r
-                       {0xC2u, 0xE5u},\r
+                       {0x78u, 0x01u},\r
+                       {0x81u, 0x2Cu},\r
+                       {0x8Eu, 0x05u},\r
+                       {0xC0u, 0xA7u},\r
+                       {0xC2u, 0x1Fu},\r
                        {0xC4u, 0xFFu},\r
-                       {0xCAu, 0x95u},\r
-                       {0xCCu, 0x1Cu},\r
-                       {0xCEu, 0x6Fu},\r
-                       {0xD6u, 0x0Fu},\r
+                       {0xCAu, 0xB7u},\r
+                       {0xCCu, 0x6Fu},\r
+                       {0xCEu, 0xDFu},\r
                        {0xDEu, 0x01u},\r
                        {0xE0u, 0x04u},\r
-                       {0xE4u, 0x08u},\r
-                       {0x0Cu, 0x01u},\r
-                       {0x14u, 0x01u},\r
-                       {0x18u, 0x02u},\r
-                       {0x2Eu, 0x01u},\r
-                       {0x36u, 0x03u},\r
-                       {0x3Au, 0xC0u},\r
-                       {0x58u, 0x04u},\r
+                       {0x05u, 0x01u},\r
+                       {0x37u, 0x01u},\r
+                       {0x3Fu, 0x40u},\r
+                       {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x09u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x84u, 0x96u},\r
-                       {0x85u, 0x10u},\r
-                       {0x86u, 0x69u},\r
-                       {0x87u, 0x2Du},\r
-                       {0x89u, 0x67u},\r
-                       {0x8Au, 0xFFu},\r
-                       {0x8Bu, 0x18u},\r
-                       {0x8Cu, 0x33u},\r
-                       {0x8Du, 0x02u},\r
-                       {0x8Eu, 0xCCu},\r
-                       {0x94u, 0x55u},\r
-                       {0x96u, 0xAAu},\r
-                       {0x9Bu, 0x40u},\r
-                       {0xA0u, 0x0Fu},\r
-                       {0xA1u, 0x02u},\r
-                       {0xA2u, 0xF0u},\r
-                       {0xA4u, 0xFFu},\r
-                       {0xA5u, 0x01u},\r
-                       {0xA7u, 0x02u},\r
-                       {0xADu, 0x16u},\r
-                       {0xAEu, 0xFFu},\r
-                       {0xAFu, 0x48u},\r
-                       {0xB1u, 0x08u},\r
-                       {0xB3u, 0x70u},\r
-                       {0xB5u, 0x07u},\r
-                       {0xB6u, 0xFFu},\r
-                       {0xBEu, 0x40u},\r
-                       {0xBFu, 0x01u},\r
-                       {0xC0u, 0x32u},\r
-                       {0xC1u, 0x05u},\r
-                       {0xC2u, 0x40u},\r
-                       {0xC5u, 0xD2u},\r
-                       {0xC6u, 0x0Cu},\r
-                       {0xC7u, 0xEFu},\r
+                       {0x80u, 0x01u},\r
+                       {0x83u, 0x04u},\r
+                       {0x85u, 0x80u},\r
+                       {0x88u, 0x04u},\r
+                       {0x8Bu, 0x24u},\r
+                       {0x8Fu, 0x20u},\r
+                       {0x93u, 0x18u},\r
+                       {0x95u, 0x24u},\r
+                       {0x97u, 0x09u},\r
+                       {0x9Fu, 0x03u},\r
+                       {0xA1u, 0x24u},\r
+                       {0xA3u, 0x12u},\r
+                       {0xA9u, 0x40u},\r
+                       {0xACu, 0x02u},\r
+                       {0xB0u, 0x01u},\r
+                       {0xB1u, 0x38u},\r
+                       {0xB3u, 0x40u},\r
+                       {0xB4u, 0x04u},\r
+                       {0xB5u, 0x80u},\r
+                       {0xB6u, 0x02u},\r
+                       {0xB7u, 0x07u},\r
+                       {0xBEu, 0x51u},\r
+                       {0xBFu, 0x14u},\r
+                       {0xC0u, 0x61u},\r
+                       {0xC1u, 0x03u},\r
+                       {0xC2u, 0x20u},\r
+                       {0xC5u, 0x2Cu},\r
+                       {0xC6u, 0x0Du},\r
+                       {0xC7u, 0xFEu},\r
                        {0xC8u, 0x37u},\r
                        {0xC9u, 0xFFu},\r
                        {0xCAu, 0xFFu},\r
@@ -588,744 +575,727 @@ void cyfitter_cfg(void)
                        {0xD9u, 0x04u},\r
                        {0xDAu, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x90u},\r
-                       {0xDDu, 0x09u},\r
+                       {0xDCu, 0x10u},\r
+                       {0xDDu, 0x01u},\r
                        {0xDFu, 0x01u},\r
                        {0xE2u, 0xC0u},\r
                        {0xE6u, 0x80u},\r
                        {0xE8u, 0x40u},\r
                        {0xE9u, 0x40u},\r
                        {0xEEu, 0x08u},\r
-                       {0x01u, 0x80u},\r
-                       {0x02u, 0x10u},\r
-                       {0x03u, 0x04u},\r
-                       {0x04u, 0x08u},\r
-                       {0x05u, 0x40u},\r
-                       {0x07u, 0x10u},\r