if (track > 1)
{
scsiDev.status = CHECK_CONDITION;
- scsiDev.target->sense.code = ILLEGAL_REQUEST;
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;
scsiDev.phase = STATUS;
}
else
memcpy(scsiDev.data, SimpleTOC, len);
uint32_t capacity = getScsiCapacity(
+ scsiDev.target->device,
scsiDev.target->cfg->sdSectorStart,
- scsiDev.target->liveCfg.bytesPerSector,
+ scsiDev.target->state.bytesPerSector,
scsiDev.target->cfg->scsiSectors);
// Replace start of leadout track
if (session > 1)
{
scsiDev.status = CHECK_CONDITION;
- scsiDev.target->sense.code = ILLEGAL_REQUEST;
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;
scsiDev.phase = STATUS;
}
else
default:
{
scsiDev.status = CHECK_CONDITION;
- scsiDev.target->sense.code = ILLEGAL_REQUEST;
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;
scsiDev.phase = STATUS;
}
}
\r
#include <string.h>\r
\r
-static const uint16_t FIRMWARE_VERSION = 0x0484;\r
+static const uint16_t FIRMWARE_VERSION = 0x0485;\r
\r
// 1 flash row\r
static const uint8_t DEFAULT_CONFIG[256] =\r
static int usbDebugEpState;\r
static int usbReady;\r
\r
-static void initBoardConfig(BoardConfig* config) {\r
+static void initBoardConfig(S2S_BoardConfig* config) {\r
memcpy(\r
config,\r
(\r
(CY_FLASH_SIZEOF_ARRAY * (size_t) SCSI_CONFIG_ARRAY) +\r
(CY_FLASH_SIZEOF_ROW * SCSI_CONFIG_BOARD_ROW)\r
),\r
- sizeof(BoardConfig));\r
+ sizeof(S2S_BoardConfig));\r
\r
if (memcmp(config->magic, "BCFG", 4)) {\r
// Set a default from the deprecated flags, or 0 if\r
}\r
}\r
\r
-void configInit(BoardConfig* config)\r
+void configInit(S2S_BoardConfig* config)\r
{\r
// The USB block will be powered by an internal 3.3V regulator.\r
// The PSoC must be operating between 4.6V and 5V for the regulator\r
usbReady = 0; // We don't know if host is connected yet.\r
\r
int invalid = 1;\r
- uint8_t* rawConfig = getConfigByIndex(0);\r
+ uint8_t* rawConfig = (uint8_t*)getConfigByIndex(0);\r
int i;\r
for (i = 0; i < 64; ++i)\r
{\r
static void\r
sdInfoCommand()\r
{\r
- uint8_t response[sizeof(sdDev.csd) + sizeof(sdDev.cid)];\r
- memcpy(response, sdDev.csd, sizeof(sdDev.csd));\r
- memcpy(response + sizeof(sdDev.csd), sdDev.cid, sizeof(sdDev.cid));\r
+ uint8_t response[sizeof(sdCard.csd) + sizeof(sdCard.cid)];\r
+ memcpy(response, sdCard.csd, sizeof(sdCard.csd));\r
+ memcpy(response + sizeof(sdCard.csd), sdCard.cid, sizeof(sdCard.cid));\r
\r
hidPacket_send(response, sizeof(response));\r
}\r
hidPacket_send(response, sizeof(response));\r
}\r
\r
+static void\r
+deviceListCommand()\r
+{\r
+ int deviceCount;\r
+ S2S_Device** devices = s2s_GetDevices(&deviceCount);\r
+ \r
+ uint8_t response[16] = // Make larger if there can be more than 2 devices\r
+ {\r
+ deviceCount\r
+ };\r
+ \r
+ int pos = 1;\r
+ \r
+ for (int i = 0; i < deviceCount; ++i)\r
+ {\r
+ response[pos++] = devices[i]->deviceType;\r
+ \r
+ uint32_t capacity = devices[i]->getCapacity(devices[i]);\r
+ response[pos++] = capacity >> 24;\r
+ response[pos++] = capacity >> 16;\r
+ response[pos++] = capacity >> 8;\r
+ response[pos++] = capacity;\r
+ }\r
+ \r
+ hidPacket_send(response, pos);\r
+}\r
+\r
+static void\r
+deviceEraseCommand(const uint8_t* cmd)\r
+{\r
+ int deviceCount;\r
+ S2S_Device** devices = s2s_GetDevices(&deviceCount);\r
+ \r
+ uint32_t sectorNum =\r
+ ((uint32_t)cmd[2]) << 24 |\r
+ ((uint32_t)cmd[3]) << 16 |\r
+ ((uint32_t)cmd[4]) << 8 |\r
+ ((uint32_t)cmd[5]);\r
+\r
+ uint32_t count =\r
+ ((uint32_t)cmd[6]) << 24 |\r
+ ((uint32_t)cmd[7]) << 16 |\r
+ ((uint32_t)cmd[8]) << 8 |\r
+ ((uint32_t)cmd[9]);\r
+\r
+ devices[cmd[1]]->erase(devices[cmd[1]], sectorNum, count);\r
+ \r
+ uint8_t response[] =\r
+ {\r
+ CONFIG_STATUS_GOOD\r
+ };\r
+ hidPacket_send(response, sizeof(response));\r
+}\r
+\r
+static void\r
+deviceWriteCommand(const uint8_t* cmd)\r
+{\r
+ int deviceCount;\r
+ S2S_Device** devices = s2s_GetDevices(&deviceCount);\r
+ \r
+ uint32_t sectorNum =\r
+ ((uint32_t)cmd[2]) << 24 |\r
+ ((uint32_t)cmd[3]) << 16 |\r
+ ((uint32_t)cmd[4]) << 8 |\r
+ ((uint32_t)cmd[5]);\r
+\r
+ devices[cmd[1]]->write(devices[cmd[1]], sectorNum, 1, &cmd[6]);\r
+ \r
+ uint8_t response[] =\r
+ {\r
+ CONFIG_STATUS_GOOD\r
+ };\r
+ hidPacket_send(response, sizeof(response));\r
+}\r
+\r
+\r
+static void\r
+deviceReadCommand(const uint8_t* cmd)\r
+{\r
+ int deviceCount;\r
+ S2S_Device** devices = s2s_GetDevices(&deviceCount);\r
+ \r
+ uint32_t sectorNum =\r
+ ((uint32_t)cmd[2]) << 24 |\r
+ ((uint32_t)cmd[3]) << 16 |\r
+ ((uint32_t)cmd[4]) << 8 |\r
+ ((uint32_t)cmd[5]);\r
+\r
+ uint8_t response[512];\r
+ devices[cmd[1]]->read(devices[cmd[1]], sectorNum, 1, &response[0]);\r
+ \r
+ hidPacket_send(&response[0], 512);\r
+}\r
+\r
static void\r
processCommand(const uint8_t* cmd, size_t cmdSize)\r
{\r
scsiTestCommand();\r
break;\r
\r
+ case S2S_CMD_DEV_LIST:\r
+ deviceListCommand();\r
+ break;\r
+\r
+ case S2S_CMD_DEV_ERASE:\r
+ deviceEraseCommand(cmd);\r
+ break;\r
+\r
+ case S2S_CMD_DEV_WRITE:\r
+ deviceWriteCommand(cmd);\r
+ break;\r
+\r
+ case S2S_CMD_DEV_READ:\r
+ deviceReadCommand(cmd);\r
+ break;\r
+ \r
case CONFIG_NONE: // invalid\r
default:\r
break;\r
hidBuffer[23] = scsiDev.msgCount;\r
hidBuffer[24] = scsiDev.cmdCount;\r
hidBuffer[25] = scsiDev.watchdogTick;\r
- hidBuffer[26] = blockDev.state;\r
+ hidBuffer[26] = 0; // OBSOLETE. Previously media state\r
hidBuffer[27] = scsiDev.lastSenseASC >> 8;\r
hidBuffer[28] = scsiDev.lastSenseASC;\r
hidBuffer[29] = scsiReadDBxPins();\r
hidBuffer[30] = LastTrace;\r
\r
- hidBuffer[58] = sdDev.capacity >> 24;\r
- hidBuffer[59] = sdDev.capacity >> 16;\r
- hidBuffer[60] = sdDev.capacity >> 8;\r
- hidBuffer[61] = sdDev.capacity;\r
+ hidBuffer[58] = sdCard.capacity >> 24;\r
+ hidBuffer[59] = sdCard.capacity >> 16;\r
+ hidBuffer[60] = sdCard.capacity >> 8;\r
+ hidBuffer[61] = sdCard.capacity;\r
\r
hidBuffer[62] = FIRMWARE_VERSION >> 8;\r
hidBuffer[63] = FIRMWARE_VERSION;\r
int cfgIdx;\r
for (cfgIdx = 0; cfgIdx < MAX_SCSI_TARGETS; ++cfgIdx)\r
{\r
- const TargetConfig* tgt = getConfigByIndex(cfgIdx);\r
+ const S2S_TargetCfg* tgt = getConfigByIndex(cfgIdx);\r
if ((tgt->scsiId & CONFIG_TARGET_ID_BITS) == scsiId)\r
{\r
// Save row to flash\r
// We only save the first row of the configuration\r
// this contains the parameters changeable by a MODE SELECT command\r
uint8_t rowData[CYDEV_FLS_ROW_SIZE];\r
- TargetConfig* rowCfgData = (TargetConfig*)&rowData;\r
+ S2S_TargetCfg* rowCfgData = (S2S_TargetCfg*)&rowData;\r
memcpy(rowCfgData, tgt, sizeof(rowData));\r
rowCfgData->bytesPerSector = bytesPerSector;\r
\r
}\r
\r
\r
-const TargetConfig* getConfigByIndex(int i)\r
+const S2S_TargetCfg* getConfigByIndex(int i)\r
{\r
if (i <= 3)\r
{\r
size_t row = SCSI_CONFIG_0_ROW + (i * SCSI_CONFIG_ROWS);\r
- return (const TargetConfig*)\r
+ return (const S2S_TargetCfg*)\r
(\r
CY_FLASH_BASE +\r
(CY_FLASH_SIZEOF_ARRAY * (size_t) SCSI_CONFIG_ARRAY) +\r
);\r
} else {\r
size_t row = SCSI_CONFIG_4_ROW + ((i-4) * SCSI_CONFIG_ROWS);\r
- return (const TargetConfig*)\r
+ return (const S2S_TargetCfg*)\r
(\r
CY_FLASH_BASE +\r
(CY_FLASH_SIZEOF_ARRAY * (size_t) SCSI_CONFIG_ARRAY) +\r
}\r
}\r
\r
-const TargetConfig* getConfigById(int scsiId)\r
+const S2S_TargetCfg* getConfigById(int scsiId)\r
{\r
int i;\r
for (i = 0; i < MAX_SCSI_TARGETS; ++i)\r
{\r
- const TargetConfig* tgt = getConfigByIndex(i);\r
+ const S2S_TargetCfg* tgt = getConfigByIndex(i);\r
if ((tgt->scsiId & CONFIG_TARGET_ID_BITS) == scsiId)\r
{\r
return tgt;\r
#include "device.h"\r
#include "scsi2sd.h"\r
\r
-void configInit(BoardConfig* config);\r
+void configInit(S2S_BoardConfig* config);\r
void debugInit(void);\r
void configPoll(void);\r
void configSave(int scsiId, uint16_t byesPerSector);\r
\r
-const TargetConfig* getConfigByIndex(int index);\r
-const TargetConfig* getConfigById(int scsiId);\r
+const S2S_TargetCfg* getConfigByIndex(int index);\r
+const S2S_TargetCfg* getConfigById(int scsiId);\r
\r
#endif\r
// Nowhere to store this data!\r
// Shouldn't happen - our buffer should be many magnitudes larger\r
// than the required size for diagnostic parameters.\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;\r
scsiDev.status = CHECK_CONDITION;\r
scsiDev.phase = STATUS;\r
}\r
// 64bit linear address, then convert back again.\r
uint64 fromByteAddr =\r
scsiByteAddress(\r
- scsiDev.target->liveCfg.bytesPerSector,\r
+ scsiDev.target->state.bytesPerSector,\r
scsiDev.target->cfg->headsPerCylinder,\r
scsiDev.target->cfg->sectorsPerTrack,\r
suppliedFmt,\r
&scsiDev.data[6]);\r
\r
scsiSaveByteAddress(\r
- scsiDev.target->liveCfg.bytesPerSector,\r
+ scsiDev.target->state.bytesPerSector,\r
scsiDev.target->cfg->headsPerCylinder,\r
scsiDev.target->cfg->sectorsPerTrack,\r
translateFmt,\r
{\r
// error.\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;\r
scsiDev.phase = STATUS;\r
}\r
\r
{\r
// error.\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;\r
scsiDev.phase = STATUS;\r
}\r
}\r
{\r
// error.\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;\r
scsiDev.phase = STATUS;\r
}\r
}\r
// Section 4.3.14\r
void scsiWriteSectorBuffer()\r
{\r
- scsiDev.dataLen = scsiDev.target->liveCfg.bytesPerSector;\r
+ scsiDev.dataLen = scsiDev.target->state.bytesPerSector;\r
scsiDev.phase = DATA_OUT;\r
scsiDev.postDataOutHook = doWriteBuffer;\r
}\r
#include <string.h>\r
\r
// Global\r
-BlockDevice blockDev;\r
Transfer transfer;\r
\r
-static int doSdInit()\r
-{\r
- int result = 0;\r
- if (blockDev.state & DISK_PRESENT)\r
- {\r
- result = sdInit();\r
-\r
- if (result)\r
- {\r
- blockDev.state = blockDev.state | DISK_INITIALISED;\r
- }\r
- }\r
- return result;\r
-}\r
-\r
// Callback once all data has been read in the data out phase.\r
static void doFormatUnitComplete(void)\r
{\r
{\r
// Save the "MODE SELECT savable parameters"\r
configSave(\r
- scsiDev.target->targetId,\r
- scsiDev.target->liveCfg.bytesPerSector);\r
+ scsiDev.target->cfg->scsiId & CONFIG_TARGET_ID_BITS,\r
+ scsiDev.target->state.bytesPerSector);\r
}\r
\r
if (IP)\r
int pmi = scsiDev.cdb[8] & 1;\r
\r
uint32_t capacity = getScsiCapacity(\r
+ scsiDev.target->device,\r
scsiDev.target->cfg->sdSectorStart,\r
- scsiDev.target->liveCfg.bytesPerSector,\r
+ scsiDev.target->state.bytesPerSector,\r
scsiDev.target->cfg->scsiSectors);\r
\r
if (!pmi && lba)\r
// assume that delays are constant across each block. But the spec\r
// says we must return this error if pmi is specified incorrectly.\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;\r
scsiDev.phase = STATUS;\r
}\r
else if (capacity > 0)\r
scsiDev.data[2] = highestBlock >> 8;\r
scsiDev.data[3] = highestBlock;\r
\r
- uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector;\r
+ uint32_t bytesPerSector = scsiDev.target->state.bytesPerSector;\r
scsiDev.data[4] = bytesPerSector >> 24;\r
scsiDev.data[5] = bytesPerSector >> 16;\r
scsiDev.data[6] = bytesPerSector >> 8;\r
else\r
{\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = NOT_READY;\r
- scsiDev.target->sense.asc = MEDIUM_NOT_PRESENT;\r
+ scsiDev.target->state.sense.code = NOT_READY;\r
+ scsiDev.target->state.sense.asc = MEDIUM_NOT_PRESENT;\r
scsiDev.phase = STATUS;\r
}\r
}\r
CyDelay(10);\r
}\r
\r
- uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector;\r
+ uint32_t bytesPerSector = scsiDev.target->state.bytesPerSector;\r
+ MEDIA_STATE* mediaState = &(scsiDev.target->device->mediaState);\r
\r
- if (unlikely(blockDev.state & DISK_WP) ||\r
- unlikely(scsiDev.target->cfg->deviceType == CONFIG_OPTICAL))\r
+ if (unlikely(*mediaState & MEDIA_WP) ||\r
+ unlikely(scsiDev.target->cfg->deviceType == CONFIG_OPTICAL) ||\r
+ (scsiDev.target->cfg->storageDevice != CONFIG_STOREDEVICE_SD))\r
\r
{\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = WRITE_PROTECTED;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = WRITE_PROTECTED;\r
scsiDev.phase = STATUS;\r
}\r
else if (unlikely(((uint64) lba) + blocks >\r
getScsiCapacity(\r
+ scsiDev.target->device,\r
scsiDev.target->cfg->sdSectorStart,\r
bytesPerSector,\r
scsiDev.target->cfg->scsiSectors\r
))\r
{\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\r
scsiDev.phase = STATUS;\r
}\r
else\r
}\r
\r
uint32_t capacity = getScsiCapacity(\r
+ scsiDev.target->device,\r
scsiDev.target->cfg->sdSectorStart,\r
- scsiDev.target->liveCfg.bytesPerSector,\r
+ scsiDev.target->state.bytesPerSector,\r
scsiDev.target->cfg->scsiSectors);\r
if (unlikely(((uint64) lba) + blocks > capacity))\r
{\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\r
scsiDev.phase = STATUS;\r
}\r
else\r
scsiDev.phase = DATA_IN;\r
scsiDev.dataLen = 0; // No data yet\r
\r
- uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector;\r
+ uint32_t bytesPerSector = scsiDev.target->state.bytesPerSector;\r
uint32_t sdSectorPerSCSISector = SDSectorsPerSCSISector(bytesPerSector);\r
uint32_t sdSectors =\r
blocks * sdSectorPerSCSISector;\r
(sdSectors == 1) &&\r
!(scsiDev.boardCfg.flags & CONFIG_ENABLE_CACHE)\r
) ||\r
- unlikely(((uint64) lba) + blocks == capacity)\r
+ unlikely(((uint64) lba) + blocks == capacity) ||\r
+ (scsiDev.target->cfg->storageDevice != CONFIG_STOREDEVICE_SD)\r
)\r
{\r
// We get errors on reading the last sector using a multi-sector\r
{\r
if (lba >=\r
getScsiCapacity(\r
+ scsiDev.target->device,\r
scsiDev.target->cfg->sdSectorStart,\r
- scsiDev.target->liveCfg.bytesPerSector,\r
+ scsiDev.target->state.bytesPerSector,\r
scsiDev.target->cfg->scsiSectors)\r
)\r
{\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\r
scsiDev.phase = STATUS;\r
}\r
else\r
\r
static int doTestUnitReady()\r
{\r
+ MEDIA_STATE* mediaState = &(scsiDev.target->device->mediaState);\r
+\r
int ready = 1;\r
- if (likely(blockDev.state == (DISK_STARTED | DISK_PRESENT | DISK_INITIALISED)))\r
+ if (likely(*mediaState == (MEDIA_STARTED | MEDIA_PRESENT | MEDIA_INITIALISED)))\r
{\r
// nothing to do.\r
}\r
- else if (unlikely(!(blockDev.state & DISK_STARTED)))\r
+ else if (unlikely(!(*mediaState & MEDIA_STARTED)))\r
{\r
ready = 0;\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = NOT_READY;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED;\r
+ scsiDev.target->state.sense.code = NOT_READY;\r
+ scsiDev.target->state.sense.asc = LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED;\r
scsiDev.phase = STATUS;\r
}\r
- else if (unlikely(!(blockDev.state & DISK_PRESENT)))\r
+ else if (unlikely(!(*mediaState & MEDIA_PRESENT)))\r
{\r
ready = 0;\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = NOT_READY;\r
- scsiDev.target->sense.asc = MEDIUM_NOT_PRESENT;\r
+ scsiDev.target->state.sense.code = NOT_READY;\r
+ scsiDev.target->state.sense.asc = MEDIUM_NOT_PRESENT;\r
scsiDev.phase = STATUS;\r
}\r
- else if (unlikely(!(blockDev.state & DISK_INITIALISED)))\r
+ else if (unlikely(!(*mediaState & MEDIA_INITIALISED)))\r
{\r
ready = 0;\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = NOT_READY;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE;\r
+ scsiDev.target->state.sense.code = NOT_READY;\r
+ scsiDev.target->state.sense.asc = LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE;\r
scsiDev.phase = STATUS;\r
}\r
return ready;\r
//int immed = scsiDev.cdb[1] & 1;\r
int start = scsiDev.cdb[4] & 1;\r
\r
+ MEDIA_STATE* mediaState = &(scsiDev.target->device->mediaState);\r
if (start)\r
{\r
- blockDev.state = blockDev.state | DISK_STARTED;\r
- if (!(blockDev.state & DISK_INITIALISED))\r
+ *mediaState = *mediaState | MEDIA_STARTED;\r
+ if (!(*mediaState & MEDIA_INITIALISED))\r
{\r
- doSdInit();\r
+ if (*mediaState & MEDIA_PRESENT)\r
+ {\r
+ *mediaState = *mediaState | MEDIA_INITIALISED;\r
+ }\r
}\r
}\r
else\r
{\r
- blockDev.state &= ~DISK_STARTED;\r
+ *mediaState &= ~MEDIA_STARTED;\r
}\r
}\r
else if (unlikely(command == 0x00))\r
// TODO. This means they are supplying data to verify against.\r
// Technically we should probably grab the data and compare it.\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;\r
scsiDev.phase = STATUS;\r
}\r
}\r
\r
void scsiDiskPoll()\r
{\r
- uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector;\r
+ uint32_t bytesPerSector = scsiDev.target->state.bytesPerSector;\r
\r
if (scsiDev.phase == DATA_IN &&\r
transfer.currentBlock != transfer.blocks)\r
int i = 0;\r
int scsiActive = 0;\r
int sdActive = 0;\r
+ \r
+ int isSDDevice = scsiDev.target->cfg->storageDevice == CONFIG_STOREDEVICE_SD;\r
+ \r
while ((i < totalSDSectors) &&\r
likely(scsiDev.phase == DATA_IN) &&\r
likely(!scsiDev.resetFlag))\r
CyExitCriticalSection(intr);\r
}\r
\r
- if (sdActive && !sdBusy && sdReadSectorDMAPoll())\r
- {\r
- sdActive = 0;\r
- prep++;\r
- }\r
+ if (isSDDevice)\r
+ {\r
+ if (sdActive && !sdBusy && sdReadSectorDMAPoll())\r
+ {\r
+ sdActive = 0;\r
+ prep++;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ S2S_Device* device = scsiDev.target->device;\r
+ if (sdActive && device->readAsyncPoll(device))\r
+ {\r
+ sdActive = 0;\r
+ prep++;\r
+ }\r
+ }\r
\r
// Usually SD is slower than the SCSI interface.\r
// Prioritise starting the read of the next sector over starting a\r
(prep - i < buffers) &&\r
(prep < totalSDSectors))\r
{\r
- // Start an SD transfer if we have space.\r
- if (transfer.multiBlock)\r
- {\r
- sdReadMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]);\r
- }\r
- else\r
- {\r
- sdReadSingleSectorDMA(sdLBA + prep, &scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]);\r
- }\r
- sdActive = 1;\r
+ if (isSDDevice)\r
+ {\r
+ // Start an SD transfer if we have space.\r
+ if (transfer.multiBlock)\r
+ {\r
+ sdReadMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]);\r
+ }\r
+ else\r
+ {\r
+ sdReadSingleSectorDMA(sdLBA + prep, &scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]);\r
+ }\r
+ sdActive = 1;\r
+ }\r
+ else\r
+ {\r
+ // Sync Read onboard flash\r
+ S2S_Device* device = scsiDev.target->device;\r
+ device->readAsync(device, sdLBA + prep, 1, &scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]);\r
+ sdActive = 1;\r
+ }\r
}\r
\r
if (scsiActive && !scsiBusy && scsiWriteDMAPoll())\r
scsiDev.phase = STATUS;\r
}\r
scsiDiskReset();\r
+ \r
+ // Wait for current DMA transfer done then deselect (if reset encountered)\r
+ if (!isSDDevice)\r
+ {\r
+ S2S_Device* device = scsiDev.target->device;\r
+ while (!device->readAsyncPoll(device))\r
+ {\r
+ }\r
+ }\r
}\r
else if (scsiDev.phase == DATA_OUT &&\r
transfer.currentBlock != transfer.blocks)\r
(scsiDev.boardCfg.flags & CONFIG_ENABLE_PARITY) &&\r
(scsiDev.compatMode >= COMPAT_SCSI2))\r
{\r
- scsiDev.target->sense.code = ABORTED_COMMAND;\r
- scsiDev.target->sense.asc = SCSI_PARITY_ERROR;\r
+ scsiDev.target->state.sense.code = ABORTED_COMMAND;\r
+ scsiDev.target->state.sense.asc = SCSI_PARITY_ERROR;\r
scsiDev.status = CHECK_CONDITION;;\r
}\r
scsiDev.phase = STATUS;\r
{\r
scsiDiskReset();\r
\r
- // Don't require the host to send us a START STOP UNIT command\r
- blockDev.state = DISK_STARTED;\r
// WP pin not available for micro-sd\r
// TODO read card WP register\r
#if 0\r
#ifndef DISK_H
#define DISK_H
-typedef enum
-{
- DISK_STARTED = 1, // Controlled via START STOP UNIT
- DISK_PRESENT = 2, // SD card is physically present
- DISK_INITIALISED = 4, // SD card responded to init sequence
- DISK_WP = 8 // Write-protect.
-} DISK_STATE;
-
typedef enum
{
TRANSFER_READ,
TRANSFER_WRITE
} TRANSFER_DIR;
-typedef struct
-{
- int state;
-} BlockDevice;
-
typedef struct
{
int multiBlock; // True if we're using a multi-block SPI transfer.
uint32 currentBlock;
} Transfer;
-extern BlockDevice blockDev;
extern Transfer transfer;
void scsiDiskInit(void);
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+
+#include "device.h"
+#include "flash.h"
+
+#include "config.h"
+#include "led.h"
+#include "time.h"
+
+typedef struct
+{
+ S2S_Device dev;
+
+ S2S_Target targets[MAX_SCSI_TARGETS];
+
+ uint32_t capacity; // in 512 byte blocks
+
+ // CFI info
+ uint8_t manufacturerID;
+ uint8_t deviceID[2];
+
+
+} SpiFlash;
+
+static void spiFlash_earlyInit(S2S_Device* dev);
+static void spiFlash_init(S2S_Device* dev);
+static S2S_Target* spiFlash_getTargets(S2S_Device* dev, int* count);
+static uint32_t spiFlash_getCapacity(S2S_Device* dev);
+static int spiFlash_pollMediaChange(S2S_Device* dev);
+static void spiFlash_pollMediaBusy(S2S_Device* dev);
+static void spiFlash_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count);
+static void spiFlash_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
+static void spiFlash_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
+static int spiFlash_readAsyncPoll(S2S_Device* dev);
+static void spiFlash_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
+
+SpiFlash spiFlash = {
+ {
+ spiFlash_earlyInit,
+ spiFlash_init,
+ spiFlash_getTargets,
+ spiFlash_getCapacity,
+ spiFlash_pollMediaChange,
+ spiFlash_pollMediaBusy,
+ spiFlash_erase,
+ spiFlash_read,
+ spiFlash_readAsync,
+ spiFlash_readAsyncPoll,
+ spiFlash_write,
+ 0, // initial mediaState
+ CONFIG_STOREDEVICE_FLASH
+ }
+};
+
+S2S_Device* spiFlashDevice = &(spiFlash.dev);
+
+// Private DMA variables.
+static uint8 spiFlashDMARxChan = CY_DMA_INVALID_CHANNEL;
+static uint8 spiFlashDMATxChan = CY_DMA_INVALID_CHANNEL;
+static uint8_t spiFlashDmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
+static uint8_t spiFlashDmaTxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
+
+// Source of dummy SPI bytes for DMA
+static uint8_t dummyBuffer[2] __attribute__((aligned(4))) = {0xFF, 0xFF};
+// Dummy location for DMA to sink usless data to
+static uint8 discardBuffer[2] __attribute__((aligned(4)));
+
+
+volatile uint8_t spiFlashRxDMAComplete = 1;
+volatile uint8_t spiFlashTxDMAComplete = 1;
+
+CY_ISR_PROTO(spiFlashRxISR);
+CY_ISR(spiFlashRxISR)
+{
+ spiFlashRxDMAComplete = 1;
+}
+CY_ISR_PROTO(spiFlashTxISR);
+CY_ISR(spiFlashTxISR)
+{
+ spiFlashTxDMAComplete = 1;
+}
+
+// Read and write 1 byte.
+static uint8_t spiFlashByte(uint8_t value)
+{
+ NOR_SPI_WriteTxData(value);
+ while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {}
+ return NOR_SPI_ReadRxData();
+}
+
+static void spiFlash_earlyInit(S2S_Device* dev)
+{
+ SpiFlash* spiFlash = (SpiFlash*)dev;
+
+ for (int i = 0; i < MAX_SCSI_TARGETS; ++i)
+ {
+ spiFlash->targets[i].device = dev;
+
+ const S2S_TargetCfg* cfg = getConfigByIndex(i);
+ if (cfg->storageDevice == CONFIG_STOREDEVICE_FLASH)
+ {
+ spiFlash->targets[i].cfg = (S2S_TargetCfg*)cfg;
+ }
+ else
+ {
+ spiFlash->targets[i].cfg = NULL;
+ }
+ }
+
+ // Don't require the host to send us a START STOP UNIT command
+ spiFlash->dev.mediaState = MEDIA_STARTED;
+
+ // DMA stuff
+ spiFlashDMATxChan =
+ NOR_TX_DMA_DmaInitialize(
+ 2, // Bytes per burst
+ 1, // request per burst
+ HI16(CYDEV_SRAM_BASE),
+ HI16(CYDEV_PERIPH_BASE)
+ );
+
+ spiFlashDMARxChan =
+ NOR_RX_DMA_DmaInitialize(
+ 1, // Bytes per burst
+ 1, // request per burst
+ HI16(CYDEV_PERIPH_BASE),
+ HI16(CYDEV_SRAM_BASE)
+ );
+
+ CyDmaChDisable(spiFlashDMATxChan);
+ CyDmaChDisable(spiFlashDMARxChan);
+
+ NOR_RX_DMA_COMPLETE_StartEx(spiFlashRxISR);
+ NOR_TX_DMA_COMPLETE_StartEx(spiFlashTxISR);
+
+ spiFlashDmaRxTd[0] = CyDmaTdAllocate();
+ spiFlashDmaRxTd[1] = CyDmaTdAllocate();
+
+ spiFlashDmaTxTd[0] = CyDmaTdAllocate();
+ spiFlashDmaTxTd[1] = CyDmaTdAllocate();
+}
+
+static void spiFlash_init(S2S_Device* dev)
+{
+ SpiFlash* spiFlash = (SpiFlash*)dev;
+ spiFlash->capacity = 0;
+
+ nNOR_WP_Write(1); // We don't need write Protect
+ nNOR_CS_Write(1); // Deselect
+
+ NOR_SPI_Start();
+ CyDelayUs(1);
+
+ nNOR_CS_Write(0); // Select
+ CyDelayCycles(4); // Tiny delay
+
+ // JEDEC standard "Read Identification" command
+ // returns CFI information
+ spiFlashByte(0x9F);
+
+ // 1 byte manufacturer ID
+ spiFlash->manufacturerID = spiFlashByte(0xFF);
+
+ // 2 bytes device ID
+ spiFlash->deviceID[0] = spiFlashByte(0xFF);
+ spiFlash->deviceID[1] = spiFlashByte(0xFF);
+
+ uint8_t bytesFollowing = spiFlashByte(0xFF);
+
+ // Chances are this says 0, which means up to 512 bytes.
+ // But ignore it for now and just get the capacity.
+ for (int i = 0; i < 0x23; ++i)
+ {
+ spiFlashByte(0xFF);
+ }
+
+ // Capacity is 2^n at offset 0x27
+ //spiFlash->capacity = (1 << spiFlashByte(0xFF)) / 512;
+ // Record value in 512-byte sectors.
+ spiFlash->capacity = 1 << (spiFlashByte(0xFF) - 9);
+
+ if (spiFlash->capacity > 0)
+ {
+ spiFlash->dev.mediaState |= MEDIA_PRESENT | MEDIA_INITIALISED;
+ }
+
+ // Don't bother reading the rest. Deselecting will cancel the command.
+
+ nNOR_CS_Write(1); // Deselect
+}
+
+static S2S_Target* spiFlash_getTargets(S2S_Device* dev, int* count)
+{
+ SpiFlash* spiFlash = (SpiFlash*)dev;
+ *count = MAX_SCSI_TARGETS;
+ return spiFlash->targets;
+}
+
+static uint32_t spiFlash_getCapacity(S2S_Device* dev)
+{
+ SpiFlash* spiFlash = (SpiFlash*)dev;
+ return spiFlash->capacity;
+}
+
+static int spiFlash_pollMediaChange(S2S_Device* dev)
+{
+ // Non-removable
+ return 0;
+}
+
+static void spiFlash_pollMediaBusy(S2S_Device* dev)
+{
+ // Non-removable
+}
+
+static void spiFlash_WaitForWIP()
+{
+ int inProgress = 1;
+ while (inProgress)
+ {
+ nNOR_CS_Write(0);
+ uint8_t status = spiFlashByte(0x05); // Read Status Register 1;
+ inProgress = status & 1;
+ nNOR_CS_Write(1);
+ }
+}
+
+static void spiFlash_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count)
+{
+ // SpiFlash* spiFlash = (SpiFlash*)dev;
+
+ nNOR_CS_Write(0); // Select
+
+ // Send the WREN - Write Enable command
+ spiFlashByte(0x06);
+
+ // We NEED to deselect the device now for writes to work
+ nNOR_CS_Write(1);
+
+ // For now we assume 256kb sectors. This needs to be expanded to cater for
+ // different sector sizes. We safely assume it will always be >= 512 bytes.
+ const uint32_t flashSectorSize = 256*1024;
+
+ // We don't have enough memory to do a read-modify-write cycle, so the caller
+ // had better line these up on sector boundaries.
+ for (uint32_t linearAddress = sectorNumber * 512;
+ linearAddress < (sectorNumber + count) * 512;
+ linearAddress += flashSectorSize)
+ {
+ nNOR_CS_Write(0);
+
+ spiFlashByte(0xDC);
+
+ // 4-byte address
+ spiFlashByte(linearAddress >> 24);
+ spiFlashByte(linearAddress >> 16);
+ spiFlashByte(linearAddress >> 8);
+ spiFlashByte(linearAddress);
+
+ // Initiate erase
+ nNOR_CS_Write(1);
+
+ spiFlash_WaitForWIP();
+ }
+
+ nNOR_CS_Write(0);
+
+ // Send the WREN - Write Disable command
+ spiFlashByte(0x04);
+
+ nNOR_CS_Write(1); // Deselect
+}
+
+static void spiFlash_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer)
+{
+ // SpiFlash* spiFlash = (SpiFlash*)dev;
+
+ nNOR_CS_Write(0); // Select
+
+ // Send the WREN - Write Enable command
+ spiFlashByte(0x06);
+
+ // We NEED to deselect the device now for writes to work
+ nNOR_CS_Write(1);
+
+ // We're assuming here that the page size is 512 bytes or more.
+ for (unsigned int i = 0; i < count; ++i)
+ {
+ nNOR_CS_Write(0);
+
+ spiFlashByte(0x12);
+
+ uint32_t linearAddress = (sectorNumber + i) * 512;
+ spiFlashByte(linearAddress >> 24);
+ spiFlashByte(linearAddress >> 16);
+ spiFlashByte(linearAddress >> 8);
+ spiFlashByte(linearAddress);
+
+ for (int off = 0; off < 512; ++off)
+ {
+ spiFlashByte(buffer[i * 512 + off]);
+ }
+
+ // Initiate write
+ nNOR_CS_Write(1);
+
+ spiFlash_WaitForWIP();
+ }
+
+ nNOR_CS_Write(0);
+
+ // Send the WREN - Write Disable command
+ spiFlashByte(0x04);
+
+ nNOR_CS_Write(1); // Deselect
+}
+
+static void spiFlash_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer)
+{
+ // SpiFlash* spiFlash = (SpiFlash*)dev;
+
+ nNOR_CS_Write(0); // Select
+ spiFlashByte(0x13);
+
+ uint32_t linearAddress = sectorNumber * 512;
+ spiFlashByte(linearAddress >> 24);
+ spiFlashByte(linearAddress >> 16);
+ spiFlashByte(linearAddress >> 8);
+ spiFlashByte(linearAddress);
+
+ // There's no harm in reading -extra- data, so keep the FIFO
+ // one step ahead.
+ NOR_SPI_WriteTxData(0xFF);
+ NOR_SPI_WriteTxData(0xFF);
+ NOR_SPI_WriteTxData(0xFF);
+
+ for (int off = 0; off < count * 512; ++off)
+ {
+ NOR_SPI_WriteTxData(0xFF);
+
+ while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {}
+ buffer[off] = NOR_SPI_ReadRxData();
+ }
+
+ // Read and discard the extra bytes of data. It was only used to improve
+ // performance with a full FIFO.
+ for (int i = 0; i < 3; ++i)
+ {
+ while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {}
+ NOR_SPI_ReadRxData();
+ }
+
+ nNOR_CS_Write(1); // Deselect
+}
+
+static void spiFlash_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer)
+{
+ // SpiFlash* spiFlash = (SpiFlash*)dev;
+
+ nNOR_CS_Write(0); // Select
+ spiFlashByte(0x13);
+
+ uint32_t linearAddress = sectorNumber * 512;
+
+ // DMA implementation
+ // send is static as the address must remain consistent for the static
+ // DMA descriptors to work.
+ // Size must be divisible by 2 to suit 2-byte-burst TX DMA channel.
+ static uint8_t send[4] __attribute__((aligned(4)));
+ send[0] = linearAddress >> 24;
+ send[1] = linearAddress >> 16;
+ send[2] = linearAddress >> 8;
+ send[3] = linearAddress;
+
+ // Prepare DMA transfer
+ CyDmaTdSetConfiguration(spiFlashDmaTxTd[0], sizeof(send), spiFlashDmaTxTd[1], TD_INC_SRC_ADR);
+ CyDmaTdSetAddress(spiFlashDmaTxTd[0], LO16((uint32)&send), LO16((uint32)NOR_SPI_TXDATA_PTR));
+
+ CyDmaTdSetConfiguration(
+ spiFlashDmaTxTd[1],
+ count * 512,
+ CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes
+ NOR_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete
+ );
+ CyDmaTdSetAddress(
+ spiFlashDmaTxTd[1],
+ LO16((uint32)&dummyBuffer),
+ LO16((uint32)NOR_SPI_TXDATA_PTR));
+
+ CyDmaTdSetConfiguration(spiFlashDmaRxTd[0], sizeof(send), spiFlashDmaRxTd[1], 0);
+ CyDmaTdSetAddress(spiFlashDmaRxTd[0], LO16((uint32)NOR_SPI_RXDATA_PTR), LO16((uint32)&discardBuffer));
+
+ CyDmaTdSetConfiguration(
+ spiFlashDmaRxTd[1],
+ count * 512,
+ CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes
+ TD_INC_DST_ADR |
+ NOR_RX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete
+ );
+
+ CyDmaTdSetAddress(
+ spiFlashDmaRxTd[1],
+ LO16((uint32)NOR_SPI_RXDATA_PTR),
+ LO16((uint32)buffer)
+ );
+
+ CyDmaChSetInitialTd(spiFlashDMATxChan, spiFlashDmaTxTd[0]);
+ CyDmaChSetInitialTd(spiFlashDMARxChan, spiFlashDmaRxTd[0]);
+
+ // The DMA controller is a bit trigger-happy. It will retain
+ // a drq request that was triggered while the channel was
+ // disabled.
+ CyDmaChSetRequest(spiFlashDMATxChan, CY_DMA_CPU_REQ);
+ CyDmaClearPendingDrq(spiFlashDMARxChan);
+
+ spiFlashTxDMAComplete = 0;
+ spiFlashRxDMAComplete = 0;
+
+ CyDmaChEnable(spiFlashDMARxChan, 1);
+ CyDmaChEnable(spiFlashDMATxChan, 1);
+}
+
+static int spiFlash_readAsyncPoll(S2S_Device* dev)
+{
+ // SpiFlash* spiFlash = (SpiFlash*)dev;
+
+ int allComplete = 0;
+ uint8_t intr = CyEnterCriticalSection();
+ allComplete = spiFlashTxDMAComplete && spiFlashRxDMAComplete;
+ CyExitCriticalSection(intr);
+
+ if (allComplete)
+ {
+ nNOR_CS_Write(1); // Deselect
+ }
+
+ return allComplete;
+}
\ No newline at end of file
--- /dev/null
+// Copyright (C) 2020 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef S2S_FLASH_H
+#define S2S_FLASH_H
+
+#include "storedevice.h"
+
+extern S2S_Device* spiFlashDevice;
+
+
+#endif
#include <string.h>\r
\r
uint32_t getScsiCapacity(\r
+ S2S_Device* device,\r
uint32_t sdSectorStart,\r
uint16_t bytesPerSector,\r
uint32_t scsiSectors)\r
{\r
+ uint32_t devCapacity = device->getCapacity(device);\r
+ \r
uint32_t capacity =\r
- (sdDev.capacity - sdSectorStart) /\r
+ (devCapacity - sdSectorStart) /\r
SDSectorsPerSCSISector(bytesPerSector);\r
\r
- if (sdDev.capacity == 0)\r
+ if (devCapacity == 0)\r
{\r
capacity = 0;\r
}\r
- else if (sdSectorStart >= sdDev.capacity)\r
+ else if (sdSectorStart >= devCapacity)\r
{\r
capacity = 0;\r
}\r
#include "device.h"
#include "config.h"
+#include "storedevice.h"
#include "sd.h"
-
+
typedef enum
{
ADDRESS_BLOCK = 0,
}
uint32_t getScsiCapacity(
+ S2S_Device* device,
uint32_t sdSectorStart,
uint16_t bytesPerSector,
uint32_t scsiSectors);
'S','C','S','I','-','2'
};
-static void useCustomVPD(const TargetConfig* cfg, int pageCode)
+static void useCustomVPD(const S2S_TargetCfg* cfg, int pageCode)
{
int cfgIdx = 0;
int found = 0;
{
// error.
scsiDev.status = CHECK_CONDITION;
- scsiDev.target->sense.code = ILLEGAL_REQUEST;
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;
scsiDev.phase = STATUS;
}
}
{
// error.
scsiDev.status = CHECK_CONDITION;
- scsiDev.target->sense.code = ILLEGAL_REQUEST;
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;
scsiDev.phase = STATUS;
}
else
{
- const TargetConfig* config = scsiDev.target->cfg;
+ const S2S_TargetCfg* config = scsiDev.target->cfg;
memcpy(scsiDev.data, StandardResponse, sizeof(StandardResponse));
scsiDev.data[1] = scsiDev.target->cfg->deviceTypeModifier;
{
memcpy(scsiDev.data, UnitSerialNumber, sizeof(UnitSerialNumber));
scsiDev.dataLen = sizeof(UnitSerialNumber);
- const TargetConfig* config = scsiDev.target->cfg;
+ const S2S_TargetCfg* config = scsiDev.target->cfg;
memcpy(&scsiDev.data[4], config->serial, sizeof(config->serial));
scsiDev.phase = DATA_IN;
}
{
// error.
scsiDev.status = CHECK_CONDITION;
- scsiDev.target->sense.code = ILLEGAL_REQUEST;
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;
scsiDev.phase = STATUS;
}
{\r
timeInit();\r
ledInit();\r
+ s2s_deviceEarlyInit();\r
traceInit();\r
\r
// Enable global interrupts.\r
++delaySeconds;\r
}\r
\r
- uint32_t lastSDPoll = getTime_ms();\r
- sdCheckPresent();\r
+ s2s_deviceInit();\r
\r
while (1)\r
{\r
\r
if (unlikely(scsiDev.phase == BUS_FREE))\r
{\r
- if (unlikely(elapsedTime_ms(lastSDPoll) > 200))\r
+ if (s2s_pollMediaChange())\r
{\r
- lastSDPoll = getTime_ms();\r
- sdCheckPresent();\r
+ scsiPhyConfig();\r
+ scsiInit();\r
}\r
else\r
{\r
CyExitCriticalSection(interruptState);\r
}\r
}\r
- else if ((scsiDev.phase >= 0) && (blockDev.state & DISK_PRESENT))\r
+ else if ((scsiDev.phase >= 0) &&\r
+ scsiDev.target &&\r
+ (scsiDev.target->device->mediaState & MEDIA_PRESENT))\r
{\r
- // don't waste time scanning SD cards while we're doing disk IO\r
- lastSDPoll = getTime_ms();\r
+ scsiDev.target->device->pollMediaBusy(scsiDev.target->device);\r
}\r
}\r
return 0;\r
}\r
}\r
\r
-static int useCustomPages(const TargetConfig* cfg, int pc, int pageCode, int* idx)\r
+static int useCustomPages(const S2S_TargetCfg* cfg, int pc, int pageCode, int* idx)\r
{\r
int found = 0;\r
int cfgIdx = 0;\r
}\r
\r
static void doModeSense(\r
- int sixByteCmd, int dbd, int pc, int pageCode, int allocLength)\r
+ S2S_Device* dev,\r
+ int sixByteCmd,\r
+ int dbd,\r
+ int pc,\r
+ int pageCode,\r
+ int allocLength)\r
{\r
////////////// Mode Parameter Header\r
////////////////////////////////////\r
mediumType = 0; // We should support various floppy types here!\r
// Contains cache bits (0) and a Write-Protect bit.\r
deviceSpecificParam =\r
- (blockDev.state & DISK_WP) ? 0x80 : 0;\r
+ (dev->mediaState & MEDIA_WP) ? 0x80 : 0;\r
density = 0; // reserved for direct access\r
break;\r
\r
case CONFIG_FLOPPY_14MB:\r
mediumType = 0x1E; // 90mm/3.5"\r
deviceSpecificParam =\r
- (blockDev.state & DISK_WP) ? 0x80 : 0;\r
+ (dev->mediaState & MEDIA_WP) ? 0x80 : 0;\r
density = 0; // reserved for direct access\r
break;\r
\r
case CONFIG_SEQUENTIAL:\r
mediumType = 0; // reserved\r
deviceSpecificParam =\r
- (blockDev.state & DISK_WP) ? 0x80 : 0;\r
- density = 0x13; // DAT Data Storage, X3B5/88-185A \r
+ (dev->mediaState & MEDIA_WP) ? 0x80 : 0;\r
+ density = 0x13; // DAT Data Storage, X3B5/88-185A\r
break;\r
\r
case CONFIG_MO:\r
- mediumType = 0x03; // Optical reversible or erasable medium\r
+ mediumType = 0x03; // Optical reversible or erasable medium\r
deviceSpecificParam =\r
- (blockDev.state & DISK_WP) ? 0x80 : 0;\r
+ (dev->mediaState & MEDIA_WP) ? 0x80 : 0;\r
density = 0x00; // Default\r
break;\r
\r
scsiDev.data[idx++] = 0; // reserved\r
\r
// Block length\r
- uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector;\r
+ uint32_t bytesPerSector = scsiDev.target->state.bytesPerSector;\r
scsiDev.data[idx++] = bytesPerSector >> 16;\r
scsiDev.data[idx++] = bytesPerSector >> 8;\r
scsiDev.data[idx++] = bytesPerSector & 0xFF;\r
scsiDev.data[idx+11] = sectorsPerTrack & 0xFF;\r
\r
// Fill out the configured bytes-per-sector\r
- uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector;\r
+ uint32_t bytesPerSector = scsiDev.target->state.bytesPerSector;\r
scsiDev.data[idx+12] = bytesPerSector >> 8;\r
scsiDev.data[idx+13] = bytesPerSector & 0xFF;\r
}\r
uint32 sector;\r
LBA2CHS(\r
getScsiCapacity(\r
+ scsiDev.target->device,\r
scsiDev.target->cfg->sdSectorStart,\r
- scsiDev.target->liveCfg.bytesPerSector,\r
+ scsiDev.target->state.bytesPerSector,\r
scsiDev.target->cfg->scsiSectors),\r
&cyl,\r
&head,\r
// Unknown Page Code\r
pageFound = 0;\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;\r
scsiDev.phase = STATUS;\r
}\r
else\r
}\r
else\r
{\r
- scsiDev.target->liveCfg.bytesPerSector = bytesPerSector;\r
+ scsiDev.target->state.bytesPerSector = bytesPerSector;\r
if (bytesPerSector != scsiDev.target->cfg->bytesPerSector)\r
{\r
- configSave(scsiDev.target->targetId, bytesPerSector);\r
+ configSave(scsiDev.target->cfg->scsiId & CONFIG_TARGET_ID_BITS, bytesPerSector);\r
}\r
}\r
}\r
goto bad;\r
}\r
\r
- scsiDev.target->liveCfg.bytesPerSector = bytesPerSector;\r
+ scsiDev.target->state.bytesPerSector = bytesPerSector;\r
if (scsiDev.cdb[1] & 1) // SP Save Pages flag\r
{\r
- configSave(scsiDev.target->targetId, bytesPerSector);\r
+ configSave(scsiDev.target->cfg->scsiId & CONFIG_TARGET_ID_BITS, bytesPerSector);\r
}\r
}\r
break;\r
goto out;\r
bad:\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = INVALID_FIELD_IN_PARAMETER_LIST;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_PARAMETER_LIST;\r
\r
out:\r
scsiDev.phase = STATUS;\r
}\r
\r
-int scsiModeCommand()\r
+int scsiModeCommand(S2S_Device* dev)\r
{\r
int commandHandled = 1;\r
\r
// SCSI1 standard: (CCS X3T9.2/86-52)\r
// "An Allocation Length of zero indicates that no MODE SENSE data shall\r
// be transferred. This condition shall not be considered as an error."\r
- doModeSense(1, dbd, pc, pageCode, allocLength);\r
+ doModeSense(dev, 1, dbd, pc, pageCode, allocLength);\r
}\r
else if (command == 0x5A)\r
{\r
int allocLength =\r
(((uint16) scsiDev.cdb[7]) << 8) +\r
scsiDev.cdb[8];\r
- doModeSense(0, dbd, pc, pageCode, allocLength);\r
+ doModeSense(dev, 0, dbd, pc, pageCode, allocLength);\r
}\r
else if (command == 0x15)\r
{\r
#ifndef MODE_H
#define MODE_H
-int scsiModeCommand(void);
+int scsiModeCommand(S2S_Device* dev);
#endif
scsiDev.phase = STATUS;\r
\r
scsiDev.lastStatus = scsiDev.status;\r
- scsiDev.lastSense = scsiDev.target->sense.code;\r
- scsiDev.lastSenseASC = scsiDev.target->sense.asc;\r
+ scsiDev.lastSense = scsiDev.target->state.sense.code;\r
+ scsiDev.lastSenseASC = scsiDev.target->state.sense.asc;\r
}\r
\r
void process_Status()\r
}\r
else if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_OMTI)\r
{\r
- scsiDev.status |= (scsiDev.target->targetId & 0x03) << 5;\r
+ scsiDev.status |= (scsiDev.target->cfg->scsiId & 0x03) << 5;\r
scsiWriteByte(scsiDev.status);\r
}\r
else\r
}\r
\r
scsiDev.lastStatus = scsiDev.status;\r
- scsiDev.lastSense = scsiDev.target->sense.code;\r
- scsiDev.lastSenseASC = scsiDev.target->sense.asc;\r
+ scsiDev.lastSense = scsiDev.target->state.sense.code;\r
+ scsiDev.lastSenseASC = scsiDev.target->state.sense.asc;\r
\r
\r
// Command Complete occurs AFTER a valid status has been\r
(scsiDev.boardCfg.flags & CONFIG_ENABLE_PARITY) &&\r
(scsiDev.compatMode >= COMPAT_SCSI2))\r
{\r
- scsiDev.target->sense.code = ABORTED_COMMAND;\r
- scsiDev.target->sense.asc = SCSI_PARITY_ERROR;\r
+ scsiDev.target->state.sense.code = ABORTED_COMMAND;\r
+ scsiDev.target->state.sense.asc = SCSI_PARITY_ERROR;\r
enter_Status(CHECK_CONDITION);\r
}\r
}\r
// http://bitsavers.trailing-edge.com/pdf/xebec/104524C_S1410Man_Aug83.pdf\r
if ((scsiDev.lun > 0) && (scsiDev.boardCfg.flags & CONFIG_MAP_LUNS_TO_IDS))\r
{\r
- int tgtIndex;\r
- for (tgtIndex = 0; tgtIndex < MAX_SCSI_TARGETS; ++tgtIndex)\r
+ S2S_Target* lunTarget = s2s_DeviceFindByScsiId(scsiDev.lun);\r
+ if (lunTarget != NULL)\r
{\r
- if (scsiDev.targets[tgtIndex].targetId == scsiDev.lun)\r
- {\r
- scsiDev.target = &scsiDev.targets[tgtIndex];\r
- scsiDev.lun = 0;\r
- break;\r
- }\r
+ scsiDev.target = lunTarget;\r
+ scsiDev.lun = 0;\r
}\r
}\r
\r
control = scsiDev.cdb[scsiDev.cdbLen - 1];\r
\r
scsiDev.cmdCount++;\r
- const TargetConfig* cfg = scsiDev.target->cfg;\r
+ const S2S_TargetCfg* cfg = scsiDev.target->cfg;\r
\r
if (unlikely(scsiDev.resetFlag))\r
{\r
(scsiDev.boardCfg.flags & CONFIG_ENABLE_PARITY) &&\r
(scsiDev.compatMode >= COMPAT_SCSI2))\r
{\r
- scsiDev.target->sense.code = ABORTED_COMMAND;\r
- scsiDev.target->sense.asc = SCSI_PARITY_ERROR;\r
+ scsiDev.target->state.sense.code = ABORTED_COMMAND;\r
+ scsiDev.target->state.sense.asc = SCSI_PARITY_ERROR;\r
enter_Status(CHECK_CONDITION);\r
}\r
else if ((control & 0x02) && ((control & 0x01) == 0) &&\r
likely(scsiDev.target->cfg->quirks != CONFIG_QUIRKS_XEBEC))\r
{\r
// FLAG set without LINK flag.\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;\r
enter_Status(CHECK_CONDITION);\r
}\r
else if (command == 0x12)\r
{\r
// Completely non-standard\r
allocLength = 4;\r
- if (scsiDev.target->sense.code == NO_SENSE)\r
+ if (scsiDev.target->state.sense.code == NO_SENSE)\r
scsiDev.data[0] = 0;\r
- else if (scsiDev.target->sense.code == ILLEGAL_REQUEST)\r
+ else if (scsiDev.target->state.sense.code == ILLEGAL_REQUEST)\r
scsiDev.data[0] = 0x20; // Illegal command\r
- else if (scsiDev.target->sense.code == NOT_READY)\r
+ else if (scsiDev.target->state.sense.code == NOT_READY)\r
scsiDev.data[0] = 0x04; // Drive not ready\r
else\r
scsiDev.data[0] = 0x11; // Uncorrectable data error\r
\r
memset(scsiDev.data, 0, 256); // Max possible alloc length\r
scsiDev.data[0] = 0xF0;\r
- scsiDev.data[2] = scsiDev.target->sense.code & 0x0F;\r
+ scsiDev.data[2] = scsiDev.target->state.sense.code & 0x0F;\r
\r
scsiDev.data[3] = transfer.lba >> 24;\r
scsiDev.data[4] = transfer.lba >> 16;\r
\r
// Additional bytes if there are errors to report\r
scsiDev.data[7] = 10; // additional length\r
- scsiDev.data[12] = scsiDev.target->sense.asc >> 8;\r
- scsiDev.data[13] = scsiDev.target->sense.asc;\r
+ scsiDev.data[12] = scsiDev.target->state.sense.asc >> 8;\r
+ scsiDev.data[13] = scsiDev.target->state.sense.asc;\r
}\r
\r
// Silently truncate results. SCSI-2 spec 8.2.14.\r
enter_DataIn(allocLength);\r
\r
// This is a good time to clear out old sense information.\r
- scsiDev.target->sense.code = NO_SENSE;\r
- scsiDev.target->sense.asc = NO_ADDITIONAL_SENSE_INFORMATION;\r
+ scsiDev.target->state.sense.code = NO_SENSE;\r
+ scsiDev.target->state.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION;\r
}\r
// Some old SCSI drivers do NOT properly support\r
// unitAttention. eg. the Mac Plus would trigger a SCSI reset\r
// on receiving the unit attention response on boot, thus\r
// triggering another unit attention condition.\r
- else if (scsiDev.target->unitAttention &&\r
+ else if (scsiDev.target->state.unitAttention &&\r
(scsiDev.boardCfg.flags & CONFIG_ENABLE_UNIT_ATTENTION))\r
{\r
- scsiDev.target->sense.code = UNIT_ATTENTION;\r
- scsiDev.target->sense.asc = scsiDev.target->unitAttention;\r
+ scsiDev.target->state.sense.code = UNIT_ATTENTION;\r
+ scsiDev.target->state.sense.asc = scsiDev.target->state.unitAttention;\r
\r
// If initiator doesn't do REQUEST SENSE for the next command, then\r
// data is lost.\r
- scsiDev.target->unitAttention = 0;\r
+ scsiDev.target->state.unitAttention = 0;\r
\r
enter_Status(CHECK_CONDITION);\r
}\r
else if (scsiDev.lun)\r
{\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_SUPPORTED;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = LOGICAL_UNIT_NOT_SUPPORTED;\r
enter_Status(CHECK_CONDITION);\r
}\r
else if (command == 0x17 || command == 0x16)\r
{\r
doReserveRelease();\r
}\r
- else if ((scsiDev.target->reservedId >= 0) &&\r
- (scsiDev.target->reservedId != scsiDev.initiatorId))\r
+ else if ((scsiDev.target->state.reservedId >= 0) &&\r
+ (scsiDev.target->state.reservedId != scsiDev.initiatorId))\r
{\r
enter_Status(CONFLICT);\r
}\r
{\r
scsiReadBuffer();\r
}\r
- else if (!scsiModeCommand() && !scsiVendorCommand())\r
+ else if (!scsiModeCommand(scsiDev.target->device) && !scsiVendorCommand())\r
{\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = INVALID_COMMAND_OPERATION_CODE;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = INVALID_COMMAND_OPERATION_CODE;\r
enter_Status(CHECK_CONDITION);\r
}\r
\r
uint8 command = scsiDev.cdb[0];\r
\r
int canRelease =\r
- (!thirdPty && (scsiDev.initiatorId == scsiDev.target->reservedId)) ||\r
+ (!thirdPty && (scsiDev.initiatorId == scsiDev.target->state.reservedId)) ||\r
(thirdPty &&\r
- (scsiDev.target->reserverId == scsiDev.initiatorId) &&\r
- (scsiDev.target->reservedId == thirdPtyId)\r
+ (scsiDev.target->state.reserverId == scsiDev.initiatorId) &&\r
+ (scsiDev.target->state.reservedId == thirdPtyId)\r
);\r
\r
if (extentReservation)\r
{\r
// Not supported.\r
- scsiDev.target->sense.code = ILLEGAL_REQUEST;\r
- scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.target->state.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB;\r
enter_Status(CHECK_CONDITION);\r
}\r
else if (command == 0x17) // release\r
{\r
- if ((scsiDev.target->reservedId < 0) || canRelease)\r
+ if ((scsiDev.target->state.reservedId < 0) || canRelease)\r
{\r
- scsiDev.target->reservedId = -1;\r
- scsiDev.target->reserverId = -1;\r
+ scsiDev.target->state.reservedId = -1;\r
+ scsiDev.target->state.reserverId = -1;\r
}\r
else\r
{\r
}\r
else // assume reserve.\r
{\r
- if ((scsiDev.target->reservedId < 0) || canRelease)\r
+ if ((scsiDev.target->state.reservedId < 0) || canRelease)\r
{\r
- scsiDev.target->reserverId = scsiDev.initiatorId;\r
+ scsiDev.target->state.reserverId = scsiDev.initiatorId;\r
if (thirdPty)\r
{\r
- scsiDev.target->reservedId = thirdPtyId;\r
+ scsiDev.target->state.reservedId = thirdPtyId;\r
}\r
else\r
{\r
- scsiDev.target->reservedId = scsiDev.initiatorId;\r
+ scsiDev.target->state.reservedId = scsiDev.initiatorId;\r
}\r
}\r
else\r
\r
if (scsiDev.target)\r
{\r
- if (scsiDev.target->unitAttention != POWER_ON_RESET)\r
+ if (scsiDev.target->state.unitAttention != POWER_ON_RESET)\r
{\r
- scsiDev.target->unitAttention = SCSI_BUS_RESET;\r
+ scsiDev.target->state.unitAttention = SCSI_BUS_RESET;\r
}\r
- scsiDev.target->reservedId = -1;\r
- scsiDev.target->reserverId = -1;\r
- scsiDev.target->sense.code = NO_SENSE;\r
- scsiDev.target->sense.asc = NO_ADDITIONAL_SENSE_INFORMATION;\r
+ scsiDev.target->state.reservedId = -1;\r
+ scsiDev.target->state.reserverId = -1;\r
+ scsiDev.target->state.sense.code = NO_SENSE;\r
+ scsiDev.target->state.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION;\r
}\r
scsiDev.target = NULL;\r
scsiDiskReset();\r
int goodParity = (Lookup_OddParity[mask] == SCSI_ReadPin(SCSI_In_DBP));\r
int atnFlag = SCSI_ReadFilt(SCSI_Filt_ATN);\r
\r
- int tgtIndex;\r
- TargetState* target = NULL;\r
- for (tgtIndex = 0; tgtIndex < MAX_SCSI_TARGETS; ++tgtIndex)\r
+ S2S_Target* target = NULL;\r
+ for (int testIdx = 0; testIdx < 8; ++testIdx)\r
{\r
- if (mask & (1 << scsiDev.targets[tgtIndex].targetId))\r
- {\r
- target = &scsiDev.targets[tgtIndex];\r
- break;\r
- }\r
+ if (mask & (1 << testIdx))\r
+ {\r
+ target = s2s_DeviceFindByScsiId(testIdx);\r
+ if (target)\r
+ {\r
+ break;\r
+ }\r
+ }\r
}\r
+\r
sel &= (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL);\r
bsy |= SCSI_ReadFilt(SCSI_Filt_BSY);\r
#ifdef SCSI_In_IO\r
// controllers don't generate parity bits.\r
if (!scsiDev.atnFlag)\r
{\r
- target->unitAttention = 0;\r
+ target->state.unitAttention = 0;\r
scsiDev.compatMode = COMPAT_SCSI1;\r
}\r
else if (!(scsiDev.boardCfg.flags & CONFIG_ENABLE_SCSI2))\r
// SCSI1/SASI initiators may not set their own ID.\r
{\r
int i;\r
- uint8_t initiatorMask = mask ^ (1 << target->targetId);\r
+ uint8_t initiatorMask = mask ^ (1 << (target->cfg->scsiId & CONFIG_TARGET_ID_BITS));\r
scsiDev.initiatorId = -1;\r
for (i = 0; i < 8; ++i)\r
{\r
\r
scsiDiskReset();\r
\r
- scsiDev.target->unitAttention = SCSI_BUS_RESET;\r
+ scsiDev.target->state.unitAttention = SCSI_BUS_RESET;\r
\r
// ANY initiator can reset the reservation state via this message.\r
- scsiDev.target->reservedId = -1;\r
- scsiDev.target->reserverId = -1;\r
+ scsiDev.target->state.reservedId = -1;\r
+ scsiDev.target->state.reserverId = -1;\r
enter_BusFree();\r
}\r
else if (scsiDev.msgOut == 0x05)\r
scsiDev.target = NULL;\r
scsiDev.compatMode = COMPAT_UNKNOWN;\r
\r
- int i;\r
- for (i = 0; i < MAX_SCSI_TARGETS; ++i)\r
+ int deviceCount;\r
+ S2S_Device** allDevices = s2s_GetDevices(&deviceCount);\r
+ for (int devIdx = 0; devIdx < deviceCount; ++devIdx)\r
{\r
- const TargetConfig* cfg = getConfigByIndex(i);\r
- if (cfg && (cfg->scsiId & CONFIG_TARGET_ENABLED))\r
- {\r
- scsiDev.targets[i].targetId = cfg->scsiId & CONFIG_TARGET_ID_BITS;\r
- scsiDev.targets[i].cfg = cfg;\r
+ int targetCount;\r
+ S2S_Target* targets = allDevices[devIdx]->getTargets(allDevices[devIdx], &targetCount);\r
\r
- scsiDev.targets[i].liveCfg.bytesPerSector = cfg->bytesPerSector;\r
- }\r
- else\r
+ for (int i = 0; i < targetCount; ++i)\r
{\r
- scsiDev.targets[i].targetId = 0xff;\r
- scsiDev.targets[i].cfg = NULL;\r
+ S2S_TargetState* state = &(targets[i].state);\r
+\r
+ state->reservedId = -1;\r
+ state->reserverId = -1;\r
+ state->unitAttention = POWER_ON_RESET;\r
+ state->sense.code = NO_SENSE;\r
+ state->sense.asc = NO_ADDITIONAL_SENSE_INFORMATION;\r
+\r
+ if (targets[i].cfg)\r
+ {\r
+ state->bytesPerSector = targets[i].cfg->bytesPerSector;\r
+ }\r
}\r
- scsiDev.targets[i].reservedId = -1;\r
- scsiDev.targets[i].reserverId = -1;\r
- scsiDev.targets[i].unitAttention = POWER_ON_RESET;\r
- scsiDev.targets[i].sense.code = NO_SENSE;\r
- scsiDev.targets[i].sense.asc = NO_ADDITIONAL_SENSE_INFORMATION;\r
}\r
}\r
\r
{\r
// Arbitrate.\r
ledOn();\r
- uint8_t scsiIdMask = 1 << scsiDev.target->targetId;\r
+ uint8_t scsiIdMask = 1 << (scsiDev.target->cfg->scsiId & CONFIG_TARGET_ID_BITS);\r
SCSI_Out_Bits_Write(scsiIdMask);\r
SCSI_Out_Ctl_Write(1); // Write bits manually.\r
SCSI_SetPin(SCSI_Out_BSY);\r
#ifndef SCSI_H
#define SCSI_H
+#include "storedevice.h"
#include "geometry.h"
-#include "sense.h"
typedef enum
{
#define MAX_SECTOR_SIZE 8192
#define MIN_SECTOR_SIZE 64
-// Shadow parameters, possibly not saved to flash yet.
-// Set via Mode Select
typedef struct
{
- uint16_t bytesPerSector;
-} LiveCfg;
-
-typedef struct
-{
- uint8_t targetId;
-
- const TargetConfig* cfg;
-
- LiveCfg liveCfg;
-
- ScsiSense sense;
-
- uint16 unitAttention; // Set to the sense qualifier key to be returned.
-
- // Only let the reserved initiator talk to us.
- // A 3rd party may be sending the RESERVE/RELEASE commands
- int reservedId; // 0 -> 7 if reserved. -1 if not reserved.
- int reserverId; // 0 -> 7 if reserved. -1 if not reserved.
-} TargetState;
-
-typedef struct
-{
- TargetState targets[MAX_SCSI_TARGETS];
- TargetState* target;
- BoardConfig boardCfg;
-
+ S2S_Target* target;
+ S2S_BoardConfig boardCfg;
// Set to true (1) if the ATN flag was set, and we need to
// enter the MESSAGE_OUT phase.
\r
#include <string.h>\r
\r
+static void sd_earlyInit(S2S_Device* dev);\r
+static void sd_deviceInit(S2S_Device* dev);\r
+static S2S_Target* sd_getTargets(S2S_Device* dev, int* count);\r
+static uint32_t sd_getCapacity(S2S_Device* dev);\r
+static int sd_pollMediaChange(S2S_Device* dev);\r
+static void sd_pollMediaBusy(S2S_Device* dev);\r
+static void sd_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count);\r
+static void sd_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);\r
+static void sd_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);\r
+static int sd_readAsyncPoll(S2S_Device* dev);\r
+static void sd_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);\r
+\r
+\r
// Global\r
-SdDevice sdDev;\r
+SdCard sdCard = {\r
+ {\r
+ sd_earlyInit,\r
+ sd_deviceInit,\r
+ sd_getTargets,\r
+ sd_getCapacity,\r
+ sd_pollMediaChange,\r
+ sd_pollMediaBusy,\r
+ sd_erase,\r
+ sd_read,\r
+ sd_readAsync,\r
+ sd_readAsyncPoll,\r
+ sd_write,\r
+ 0, // initial mediaState\r
+ CONFIG_STOREDEVICE_SD\r
+ }\r
+};\r
+S2S_Device* sdDevice = &(sdCard.dev);\r
\r
enum SD_CMD_STATE { CMD_STATE_IDLE, CMD_STATE_READ, CMD_STATE_WRITE };\r
static int sdCmdState = CMD_STATE_IDLE;\r
{\r
uint32_t tmpNextLBA = sdLBA + sdSectors;\r
\r
- if (!sdDev.ccs)\r
+ if (!sdCard.ccs)\r
{\r
sdLBA = sdLBA * SD_SECTOR_SIZE;\r
tmpNextLBA = tmpNextLBA * SD_SECTOR_SIZE;\r
sdClearStatus();\r
\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.target->state.sense.code = HARDWARE_ERROR;\r
+ scsiDev.target->state.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
scsiDev.phase = STATUS;\r
}\r
else\r
if (scsiDev.status != CHECK_CONDITION)\r
{\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;\r
+ scsiDev.target->state.sense.code = HARDWARE_ERROR;\r
+ scsiDev.target->state.sense.asc = UNRECOVERED_READ_ERROR;\r
scsiDev.phase = STATUS;\r
}\r
sdClearStatus();\r
sdPreCmdState(CMD_STATE_READ);\r
\r
uint8 v;\r
- if (!sdDev.ccs)\r
+ if (!sdCard.ccs)\r
{\r
lba = lba * SD_SECTOR_SIZE;\r
}\r
sdClearStatus();\r
\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.target->state.sense.code = HARDWARE_ERROR;\r
+ scsiDev.target->state.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
scsiDev.phase = STATUS;\r
}\r
else\r
if (unlikely(r1b) && (scsiDev.phase == DATA_IN))\r
{\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;\r
+ scsiDev.target->state.sense.code = HARDWARE_ERROR;\r
+ scsiDev.target->state.sense.asc = UNRECOVERED_READ_ERROR;\r
scsiDev.phase = STATUS;\r
}\r
}\r
sdClearStatus();\r
\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.target->state.sense.code = HARDWARE_ERROR;\r
+ scsiDev.target->state.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
scsiDev.phase = STATUS;\r
}\r
else\r
{\r
sdClearStatus();\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED;\r
+ scsiDev.target->state.sense.code = HARDWARE_ERROR;\r
+ scsiDev.target->state.sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED;\r
scsiDev.phase = STATUS;\r
}\r
}\r
if (status == SD_R1_IDLE)\r
{\r
// Version 2 card.\r
- sdDev.version = 2;\r
+ sdCard.version = 2;\r
// Read 32bit response. Should contain the same bytes that\r
// we sent in the command parameter.\r
sdSpiByte(0xFF);\r
else if (status & SD_R1_ILLEGAL)\r
{\r
// Version 1 card.\r
- sdDev.version = 1;\r
+ sdCard.version = 1;\r
sdClearStatus();\r
break;\r
}\r
buf[i] = sdSpiByte(0xFF);\r
}\r
\r
- sdDev.ccs = (buf[0] & 0x40) ? 1 : 0;\r
+ sdCard.ccs = (buf[0] & 0x40) ? 1 : 0;\r
complete = (buf[0] & 0x80);\r
\r
} while (!status &&\r
\r
for (i = 0; i < 16; ++i)\r
{\r
- sdDev.cid[i] = sdSpiByte(0xFF);\r
+ sdCard.cid[i] = sdSpiByte(0xFF);\r
}\r
sdSpiByte(0xFF); // CRC\r
sdSpiByte(0xFF); // CRC\r
\r
for (i = 0; i < 16; ++i)\r
{\r
- sdDev.csd[i] = sdSpiByte(0xFF);\r
+ sdCard.csd[i] = sdSpiByte(0xFF);\r
}\r
sdSpiByte(0xFF); // CRC\r
sdSpiByte(0xFF); // CRC\r
\r
- if ((sdDev.csd[0] >> 6) == 0x00)\r
+ if ((sdCard.csd[0] >> 6) == 0x00)\r
{\r
// CSD version 1\r
// C_SIZE in bits [73:62]\r
- uint32 c_size = (((((uint32)sdDev.csd[6]) & 0x3) << 16) | (((uint32)sdDev.csd[7]) << 8) | sdDev.csd[8]) >> 6;\r
- uint32 c_mult = (((((uint32)sdDev.csd[9]) & 0x3) << 8) | ((uint32)sdDev.csd[0xa])) >> 7;\r
- uint32 sectorSize = sdDev.csd[5] & 0x0F;\r
- sdDev.capacity = ((c_size+1) * ((uint64)1 << (c_mult+2)) * ((uint64)1 << sectorSize)) / SD_SECTOR_SIZE;\r
+ uint32 c_size = (((((uint32)sdCard.csd[6]) & 0x3) << 16) | (((uint32)sdCard.csd[7]) << 8) | sdCard.csd[8]) >> 6;\r
+ uint32 c_mult = (((((uint32)sdCard.csd[9]) & 0x3) << 8) | ((uint32)sdCard.csd[0xa])) >> 7;\r
+ uint32 sectorSize = sdCard.csd[5] & 0x0F;\r
+ sdCard.capacity = ((c_size+1) * ((uint64)1 << (c_mult+2)) * ((uint64)1 << sectorSize)) / SD_SECTOR_SIZE;\r
}\r
- else if ((sdDev.csd[0] >> 6) == 0x01)\r
+ else if ((sdCard.csd[0] >> 6) == 0x01)\r
{\r
// CSD version 2\r
// C_SIZE in bits [69:48]\r
\r
uint32 c_size =\r
- ((((uint32)sdDev.csd[7]) & 0x3F) << 16) |\r
- (((uint32)sdDev.csd[8]) << 8) |\r
- ((uint32)sdDev.csd[7]);\r
- sdDev.capacity = (c_size + 1) * 1024;\r
+ ((((uint32)sdCard.csd[7]) & 0x3F) << 16) |\r
+ (((uint32)sdCard.csd[8]) << 8) |\r
+ ((uint32)sdCard.csd[7]);\r
+ sdCard.capacity = (c_size + 1) * 1024;\r
}\r
else\r
{\r
uint8 v;\r
\r
sdCmdState = CMD_STATE_IDLE;\r
- sdDev.version = 0;\r
- sdDev.ccs = 0;\r
- sdDev.capacity = 0;\r
- memset(sdDev.csd, 0, sizeof(sdDev.csd));\r
- memset(sdDev.cid, 0, sizeof(sdDev.cid));\r
+ sdCard.version = 0;\r
+ sdCard.ccs = 0;\r
+ sdCard.capacity = 0;\r
+ memset(sdCard.csd, 0, sizeof(sdCard.csd));\r
+ memset(sdCard.cid, 0, sizeof(sdCard.cid));\r
\r
sdInitDMA();\r
\r
if (!sdOpCond()) goto bad; // ACMD41. Wait for init completes.\r
if (!sdReadOCR()) goto bad; // CMD58. Get CCS flag. Only valid after init.\r
\r
- // This command will be ignored if sdDev.ccs is set.\r
+ // This command will be ignored if sdCard.ccs is set.\r
// SDHC and SDXC are always 512bytes.\r
v = sdCRCCommandAndResponse(SD_SET_BLOCKLEN, SD_SECTOR_SIZE); //Force sector size\r
if(v){goto bad;}\r
\r
bad:\r
SD_Data_Clk_SetDivider(clkDiv25MHz); // Restore the clock for our next retry\r
- sdDev.capacity = 0;\r
+ sdCard.capacity = 0;\r
\r
out:\r
sdClearStatus();\r
{\r
uint32_t tmpNextLBA = sdLBA + sdSectors;\r
\r
- if (!sdDev.ccs)\r
+ if (!sdCard.ccs)\r
{\r
sdLBA = sdLBA * SD_SECTOR_SIZE;\r
tmpNextLBA = tmpNextLBA * SD_SECTOR_SIZE;\r
scsiDiskReset();\r
sdClearStatus();\r
scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.target->state.sense.code = HARDWARE_ERROR;\r
+ scsiDev.target->state.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
scsiDev.phase = STATUS;\r
}\r
else\r
uint8_t cs = SD_CS_Read();\r
SD_CS_SetDriveMode(SD_CS_DM_STRONG) ;\r
\r
- if (cs && !(blockDev.state & DISK_PRESENT))\r
+ if (cs && !(sdCard.dev.mediaState & MEDIA_PRESENT))\r
{\r
static int firstInit = 1;\r
\r
\r
if (sdInit())\r
{\r
- blockDev.state |= DISK_PRESENT | DISK_INITIALISED;\r
+ sdCard.dev.mediaState |= MEDIA_PRESENT | MEDIA_INITIALISED;\r
\r
// Always "start" the device. Many systems (eg. Apple System 7)\r
// won't respond properly to\r
// LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED sense\r
// code, even if they stopped it first with\r
// START STOP UNIT command.\r
- blockDev.state |= DISK_STARTED;\r
+ sdCard.dev.mediaState |= MEDIA_STARTED;\r
\r
if (!firstInit)\r
{\r
int i;\r
for (i = 0; i < MAX_SCSI_TARGETS; ++i)\r
{\r
- scsiDev.targets[i].unitAttention = PARAMETERS_CHANGED;\r
+ sdCard.targets[i].state.unitAttention = PARAMETERS_CHANGED;\r
}\r
}\r
firstInit = 0;\r
}\r
}\r
- else if (!cs && (blockDev.state & DISK_PRESENT))\r
+ else if (!cs && (sdCard.dev.mediaState & MEDIA_PRESENT))\r
{\r
- sdDev.capacity = 0;\r
- blockDev.state &= ~DISK_PRESENT;\r
- blockDev.state &= ~DISK_INITIALISED;\r
+ sdCard.capacity = 0;\r
+ sdCard.dev.mediaState &= ~MEDIA_PRESENT;\r
+ sdCard.dev.mediaState &= ~MEDIA_INITIALISED;\r
int i;\r
for (i = 0; i < MAX_SCSI_TARGETS; ++i)\r
{\r
- scsiDev.targets[i].unitAttention = PARAMETERS_CHANGED;\r
+ sdCard.targets[i].state.unitAttention = PARAMETERS_CHANGED;\r
}\r
}\r
}\r
firstCheck = 0;\r
}\r
\r
+static void sd_earlyInit(S2S_Device* dev)\r
+{\r
+ SdCard* sdCardDevice = (SdCard*)dev;\r
+\r
+ for (int i = 0; i < MAX_SCSI_TARGETS; ++i)\r
+ {\r
+ sdCardDevice->targets[i].device = dev;\r
+ \r
+ const S2S_TargetCfg* cfg = getConfigByIndex(i);\r
+ if (cfg->storageDevice == CONFIG_STOREDEVICE_SD)\r
+ {\r
+ sdCardDevice->targets[i].cfg = (S2S_TargetCfg*)cfg;\r
+ }\r
+ else\r
+ {\r
+ sdCardDevice->targets[i].cfg = NULL;\r
+ }\r
+ }\r
+ sdCardDevice->lastPollMediaTime = getTime_ms();\r
+\r
+ // Don't require the host to send us a START STOP UNIT command\r
+ sdCardDevice->dev.mediaState = MEDIA_STARTED;\r
+}\r
+\r
+static void sd_deviceInit(S2S_Device* dev)\r
+{\r
+ sdCheckPresent();\r
+}\r
+\r
+static S2S_Target* sd_getTargets(S2S_Device* dev, int* count)\r
+{\r
+ SdCard* sdCardDevice = (SdCard*)dev;\r
+ *count = MAX_SCSI_TARGETS;\r
+ return sdCardDevice->targets;\r
+}\r
+\r
+static uint32_t sd_getCapacity(S2S_Device* dev)\r
+{\r
+ SdCard* sdCardDevice = (SdCard*)dev;\r
+ return sdCardDevice->capacity;\r
+}\r
+\r
+static int sd_pollMediaChange(S2S_Device* dev)\r
+{\r
+ SdCard* sdCardDevice = (SdCard*)dev;\r
+ if (elapsedTime_ms(sdCardDevice->lastPollMediaTime) > 200)\r
+ {\r
+ sdCardDevice->lastPollMediaTime = getTime_ms();\r
+ sdCheckPresent();\r
+ return 0;\r
+ }\r
+ else\r
+ {\r
+ return 0;\r
+ }\r
+}\r
+\r
+static void sd_pollMediaBusy(S2S_Device* dev)\r
+{\r
+ SdCard* sdCardDevice = (SdCard*)dev;\r
+ sdCardDevice->lastPollMediaTime = getTime_ms();\r
+}\r
+\r
+static void sd_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count)\r
+{\r
+ // TODO\r
+}\r
+\r
+static void sd_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer)\r
+{\r
+ // TODO\r
+}\r
+\r
+static void sd_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer)\r
+{\r
+ // TODO\r
+}\r
+\r
+\r
+static int sd_readAsyncPoll(S2S_Device* dev)\r
+{\r
+ return 1;\r
+}\r
+\r
+\r
+static void sd_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer)\r
+{\r
+ // TODO\r
+}\r
#ifndef SD_H
#define SD_H
+#include "storedevice.h"
+
#define SD_SECTOR_SIZE 512
typedef enum
typedef struct
{
+ S2S_Device dev;
+
+ S2S_Target targets[MAX_SCSI_TARGETS];
+
int version; // SDHC = version 2.
int ccs; // Card Capacity Status. 1 = SDHC or SDXC
- uint32 capacity; // in 512 byte blocks
+ uint32_t capacity; // in 512 byte blocks
uint8_t csd[16]; // Unparsed CSD
uint8_t cid[16]; // Unparsed CID
-} SdDevice;
-extern SdDevice sdDev;
+ uint32_t lastPollMediaTime;
+} SdCard;
+
+extern SdCard sdCard;
+extern S2S_Device* sdDevice;
+
extern volatile uint8_t sdRxDMAComplete;
extern volatile uint8_t sdTxDMAComplete;
typedef struct
{
- uint8 code;
- uint16 asc;
+ uint8_t code;
+ uint16_t asc;
} ScsiSense;
#endif
--- /dev/null
+// Copyright (C) 2020 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#include "storedevice.h"
+
+#include "device.h"
+
+#ifdef NOR_SPI_DATA_WIDTH
+#include "flash.h"
+#endif
+
+#include "sd.h"
+
+#include <stddef.h>
+#include <string.h>
+
+S2S_Target* s2s_DeviceFindByScsiId(int scsiId)
+{
+ int deviceCount;
+ S2S_Device** devices = s2s_GetDevices(&deviceCount);
+ for (int deviceIdx = 0; deviceIdx < deviceCount; ++deviceIdx)
+ {
+ int targetCount;
+ S2S_Target* targets = devices[deviceIdx]->getTargets(devices[deviceIdx], &targetCount);
+ for (int targetIdx = 0; targetIdx < targetCount; ++targetIdx)
+ {
+ S2S_Target* target = targets + targetIdx;
+ if (target &&
+ target->cfg &&
+ (target->cfg->scsiId & CONFIG_TARGET_ENABLED) &&
+ ((target->cfg->scsiId & CONFIG_TARGET_ID_BITS) == scsiId))
+ {
+ return target;
+ }
+ }
+ }
+
+ return NULL;
+}
+
+S2S_Device** s2s_GetDevices(int* count)
+{
+ static S2S_Device* allDevices[2];
+
+ *count = 1;
+ allDevices[0] = sdDevice;
+
+ #ifdef NOR_SPI_DATA_WIDTH
+ *count = 2;
+ allDevices[1] = spiFlashDevice;
+ #endif
+
+ return allDevices;
+}
+
+void s2s_deviceEarlyInit()
+{
+ int count;
+ S2S_Device** devices = s2s_GetDevices(&count);
+ for (int i = 0; i < count; ++i)
+ {
+ devices[i]->earlyInit(devices[i]);
+ }
+}
+
+void s2s_deviceInit()
+{
+ int count;
+ S2S_Device** devices = s2s_GetDevices(&count);
+ for (int i = 0; i < count; ++i)
+ {
+ devices[i]->init(devices[i]);
+ }
+}
+
+int s2s_pollMediaChange()
+{
+ int result = 0;
+ int count;
+ S2S_Device** devices = s2s_GetDevices(&count);
+ for (int i = 0; i < count; ++i)
+ {
+ int devResult = devices[i]->pollMediaChange(devices[i]);
+ result = result || devResult;
+ }
+ return result;
+}
--- /dev/null
+// Copyright (C) 2020 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef S2S_DEVICE_H
+#define S2S_DEVICE_H
+
+#include "scsi2sd.h"
+#include "sense.h"
+
+#include <stdint.h>
+
+struct S2S_DeviceStruct;
+typedef struct S2S_DeviceStruct S2S_Device;
+
+struct S2S_TargetStruct;
+typedef struct S2S_TargetStruct S2S_Target;
+
+struct S2S_TargetStateStruct;
+typedef struct S2S_TargetStateStruct S2S_TargetState;
+
+typedef enum
+{
+ MEDIA_STARTED = 1, // Controlled via START STOP UNIT
+ MEDIA_PRESENT = 2, // SD card is physically present
+ MEDIA_INITIALISED = 4, // SD card responded to init sequence
+ MEDIA_WP = 8 // Write-protect.
+} MEDIA_STATE;
+
+struct S2S_TargetStateStruct
+{
+ ScsiSense sense;
+
+ uint16_t unitAttention; // Set to the sense qualifier key to be returned.
+
+ // Only let the reserved initiator talk to us.
+ // A 3rd party may be sending the RESERVE/RELEASE commands
+ int reservedId; // 0 -> 7 if reserved. -1 if not reserved.
+ int reserverId; // 0 -> 7 if reserved. -1 if not reserved.
+
+ // Shadow parameters, possibly not saved to flash yet.
+ // Set via Mode Select
+ uint16_t bytesPerSector;
+};
+
+struct S2S_TargetStruct
+{
+ S2S_Device* device;
+ S2S_TargetCfg* cfg;
+
+ S2S_TargetState state;
+};
+
+struct S2S_DeviceStruct
+{
+ void (*earlyInit)(S2S_Device* dev);
+ void (*init)(S2S_Device* dev);
+
+ S2S_Target* (*getTargets)(S2S_Device* dev, int* count);
+
+ // Get the number of 512 byte blocks
+ uint32_t (*getCapacity)(S2S_Device* dev);
+
+ int (*pollMediaChange)(S2S_Device* dev);
+ void (*pollMediaBusy)(S2S_Device* dev);
+
+ void (*erase)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count);
+ void (*read)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
+ void (*readAsync)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
+ int (*readAsyncPoll)(S2S_Device* dev);
+ void (*write)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
+
+ MEDIA_STATE mediaState;
+ CONFIG_STOREDEVICE deviceType;
+};
+
+S2S_Target* s2s_DeviceFindByScsiId(int scsiId);
+
+S2S_Device** s2s_GetDevices(int* count);
+
+void s2s_deviceEarlyInit();
+void s2s_deviceInit();
+int s2s_pollMediaChange();
+#endif
+
+
***************************************/
#define NOR_SPI_INT_ON_SPI_DONE ((uint8) (0u << NOR_SPI_STS_SPI_DONE_SHIFT))
-#define NOR_SPI_INT_ON_TX_EMPTY ((uint8) (0u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT))
+#define NOR_SPI_INT_ON_TX_EMPTY ((uint8) (1u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT))
#define NOR_SPI_INT_ON_TX_NOT_FULL ((uint8) (0u << \
NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT))
#define NOR_SPI_INT_ON_BYTE_COMP ((uint8) (0u << NOR_SPI_STS_BYTE_COMPLETE_SHIFT))
#define NOR_SPI_INT_ON_RX_FULL ((uint8) (0u << \
NOR_SPI_STS_RX_FIFO_FULL_SHIFT))
-#define NOR_SPI_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \
+#define NOR_SPI_INT_ON_RX_NOT_EMPTY ((uint8) (1u << \
NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT))
#define NOR_SPI_INT_ON_RX_OVER ((uint8) (0u << \
NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT))
/*******************************************************************************
* File Name: cydevice.h
* OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 4.2
+* PSoC Creator 4.4
*
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
+* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* File Name: cydevice_trm.h
*
-* PSoC Creator 4.2
+* PSoC Creator 4.4
*
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
+* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* File Name: cydevicegnu.inc
* OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 4.2
+* PSoC Creator 4.4
*
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
+* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* File Name: cydevicegnu_trm.inc
*
-* PSoC Creator 4.2
+* PSoC Creator 4.4
*
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
+* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
;
; File Name: cydeviceiar.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 4.2
+; PSoC Creator 4.4
;
; Description:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
-; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
+; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
; File Name: cydeviceiar_trm.inc
;
-; PSoC Creator 4.2
+; PSoC Creator 4.4
;
; Description:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
-; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
+; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
; File Name: cydevicerv.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 4.2
+; PSoC Creator 4.4
;
; Description:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
-; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
+; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
; File Name: cydevicerv_trm.inc
;
-; PSoC Creator 4.2
+; PSoC Creator 4.4
;
; Description:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
-; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
+; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
/*******************************************************************************
* File Name: cyfitter.h
*
-* PSoC Creator 4.2
+* PSoC Creator 4.4
*
* Description:
*
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
+* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_1__INTC_MASK 0x80u
-#define USBFS_ep_1__INTC_NUMBER 7u
+#define USBFS_ep_1__INTC_MASK 0x200u
+#define USBFS_ep_1__INTC_NUMBER 9u
#define USBFS_ep_1__INTC_PRIOR_NUM 7u
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_9
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_2__INTC_MASK 0x100u
-#define USBFS_ep_2__INTC_NUMBER 8u
+#define USBFS_ep_2__INTC_MASK 0x400u
+#define USBFS_ep_2__INTC_NUMBER 10u
#define USBFS_ep_2__INTC_PRIOR_NUM 7u
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_10
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_3__INTC_MASK 0x200u
-#define USBFS_ep_3__INTC_NUMBER 9u
+#define USBFS_ep_3__INTC_MASK 0x800u
+#define USBFS_ep_3__INTC_NUMBER 11u
#define USBFS_ep_3__INTC_PRIOR_NUM 7u
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_11
#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_4__INTC_MASK 0x400u
-#define USBFS_ep_4__INTC_NUMBER 10u
+#define USBFS_ep_4__INTC_MASK 0x2000u
+#define USBFS_ep_4__INTC_NUMBER 13u
#define USBFS_ep_4__INTC_PRIOR_NUM 7u
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_13
#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define NOR_SO__SLW CYREG_PRT15_SLW
/* SDCard */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB04_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB04_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB04_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB04_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB04_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
-#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB06_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB06_ST
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB11_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB11_ST
/* SD_SCK */
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1
#define SD_SCK__SHIFT 1u
#define SD_SCK__SLW CYREG_PRT3_SLW
-/* NOR_CTL */
-#define NOR_CTL_Sync_ctrl_reg__0__MASK 0x01u
-#define NOR_CTL_Sync_ctrl_reg__0__POS 0
-#define NOR_CTL_Sync_ctrl_reg__1__MASK 0x02u
-#define NOR_CTL_Sync_ctrl_reg__1__POS 1
-#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
-#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
-#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
-#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
-#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
-#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
-#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
-#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
-#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
-#define NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
-#define NOR_CTL_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB06_CTL
-#define NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
-#define NOR_CTL_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB06_CTL
-#define NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
-#define NOR_CTL_Sync_ctrl_reg__MASK 0x03u
-#define NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define NOR_CTL_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB06_MSK
-
/* NOR_SCK */
#define NOR_SCK__0__INTTYPE CYREG_PICU3_INTTYPE7
#define NOR_SCK__0__MASK 0x80u
#define NOR_SCK__SLW CYREG_PRT3_SLW
/* NOR_SPI */
-#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
-#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
-#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
-#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
-#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB08_CTL
-#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
-#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB08_CTL
-#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
-#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB08_MSK
-#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
-#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB08_MSK
-#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
-#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
-#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB08_ST
-#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
-#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
+#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
+#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
+#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
+#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
+#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
+#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
+#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
+#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
+#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
+#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
+#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define NOR_SPI_BSPIM_RxStsReg__4__MASK 0x10u
#define NOR_SPI_BSPIM_RxStsReg__4__POS 4
#define NOR_SPI_BSPIM_RxStsReg__5__MASK 0x20u
#define NOR_SPI_BSPIM_RxStsReg__6__MASK 0x40u
#define NOR_SPI_BSPIM_RxStsReg__6__POS 6
#define NOR_SPI_BSPIM_RxStsReg__MASK 0x70u
-#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK
-#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
-#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST
+#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
+#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0
#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1
#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0
#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define NOR_SPI_BSPIM_TxStsReg__0__MASK 0x01u
#define NOR_SPI_BSPIM_TxStsReg__0__POS 0
#define NOR_SPI_BSPIM_TxStsReg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB09_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB09_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
#define NOR_Clock__PM_STBY_MSK 0x01u
/* SD_RX_DMA */
-#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SD_RX_DMA__DRQ_NUMBER 2u
+#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL1
+#define SD_RX_DMA__DRQ_NUMBER 4u
#define SD_RX_DMA__NUMBEROF_TDS 0u
#define SD_RX_DMA__PRIORITY 0u
#define SD_RX_DMA__TERMIN_EN 0u
#define SD_RX_DMA__TERMIN_SEL 0u
#define SD_RX_DMA__TERMOUT0_EN 1u
-#define SD_RX_DMA__TERMOUT0_SEL 2u
+#define SD_RX_DMA__TERMOUT0_SEL 4u
#define SD_RX_DMA__TERMOUT1_EN 0u
#define SD_RX_DMA__TERMOUT1_SEL 0u
#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x80u
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 7u
#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_7
#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SD_TX_DMA */
-#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SD_TX_DMA__DRQ_NUMBER 3u
+#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL1
+#define SD_TX_DMA__DRQ_NUMBER 5u
#define SD_TX_DMA__NUMBEROF_TDS 0u
#define SD_TX_DMA__PRIORITY 1u
#define SD_TX_DMA__TERMIN_EN 0u
#define SD_TX_DMA__TERMIN_SEL 0u
#define SD_TX_DMA__TERMOUT0_EN 1u
-#define SD_TX_DMA__TERMOUT0_SEL 3u
+#define SD_TX_DMA__TERMOUT0_SEL 5u
#define SD_TX_DMA__TERMOUT1_EN 0u
#define SD_TX_DMA__TERMOUT1_SEL 0u
#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x100u
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 8u
#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_8
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define nNOR_HOLD__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define nNOR_HOLD__SLW CYREG_PRT12_SLW
+/* NOR_RX_DMA */
+#define NOR_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define NOR_RX_DMA__DRQ_NUMBER 0u
+#define NOR_RX_DMA__NUMBEROF_TDS 0u
+#define NOR_RX_DMA__PRIORITY 2u
+#define NOR_RX_DMA__TERMIN_EN 0u
+#define NOR_RX_DMA__TERMIN_SEL 0u
+#define NOR_RX_DMA__TERMOUT0_EN 1u
+#define NOR_RX_DMA__TERMOUT0_SEL 0u
+#define NOR_RX_DMA__TERMOUT1_EN 0u
+#define NOR_RX_DMA__TERMOUT1_SEL 0u
+#define NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define NOR_RX_DMA_COMPLETE__INTC_MASK 0x02u
+#define NOR_RX_DMA_COMPLETE__INTC_NUMBER 1u
+#define NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_1
+#define NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* NOR_TX_DMA */
+#define NOR_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define NOR_TX_DMA__DRQ_NUMBER 1u
+#define NOR_TX_DMA__NUMBEROF_TDS 0u
+#define NOR_TX_DMA__PRIORITY 2u
+#define NOR_TX_DMA__TERMIN_EN 0u
+#define NOR_TX_DMA__TERMIN_SEL 0u
+#define NOR_TX_DMA__TERMOUT0_EN 1u
+#define NOR_TX_DMA__TERMOUT0_SEL 1u
+#define NOR_TX_DMA__TERMOUT1_EN 0u
+#define NOR_TX_DMA__TERMOUT1_SEL 0u
+#define NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define NOR_TX_DMA_COMPLETE__INTC_MASK 0x04u
+#define NOR_TX_DMA_COMPLETE__INTC_NUMBER 2u
+#define NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2
+#define NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
/* SCSI_Noise */
#define SCSI_Noise__0__AG CYREG_PRT4_AG
#define SCSI_Noise__0__AMUX CYREG_PRT4_AMUX
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST
/* Debug_Timer */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
/* SCSI_RX_DMA */
#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SCSI_RX_DMA__DRQ_NUMBER 0u
+#define SCSI_RX_DMA__DRQ_NUMBER 2u
#define SCSI_RX_DMA__NUMBEROF_TDS 0u
#define SCSI_RX_DMA__PRIORITY 2u
#define SCSI_RX_DMA__TERMIN_EN 0u
#define SCSI_RX_DMA__TERMIN_SEL 0u
#define SCSI_RX_DMA__TERMOUT0_EN 1u
-#define SCSI_RX_DMA__TERMOUT0_SEL 0u
+#define SCSI_RX_DMA__TERMOUT0_SEL 2u
#define SCSI_RX_DMA__TERMOUT1_EN 0u
#define SCSI_RX_DMA__TERMOUT1_SEL 0u
#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u
-#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u
+#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x10u
+#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 4u
#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_TX_DMA */
#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SCSI_TX_DMA__DRQ_NUMBER 1u
+#define SCSI_TX_DMA__DRQ_NUMBER 3u
#define SCSI_TX_DMA__NUMBEROF_TDS 0u
#define SCSI_TX_DMA__PRIORITY 2u
#define SCSI_TX_DMA__TERMIN_EN 0u
#define SCSI_TX_DMA__TERMIN_SEL 0u
#define SCSI_TX_DMA__TERMOUT0_EN 1u
-#define SCSI_TX_DMA__TERMOUT0_SEL 1u
+#define SCSI_TX_DMA__TERMOUT0_SEL 3u
#define SCSI_TX_DMA__TERMOUT1_EN 0u
#define SCSI_TX_DMA__TERMOUT1_SEL 0u
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x40u
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 6u
#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6
#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_RST_ISR */
#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RST_ISR__INTC_MASK 0x02u
-#define SCSI_RST_ISR__INTC_NUMBER 1u
+#define SCSI_RST_ISR__INTC_MASK 0x08u
+#define SCSI_RST_ISR__INTC_NUMBER 3u
#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3
#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_SEL_ISR */
#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_SEL_ISR__INTC_MASK 0x08u
-#define SCSI_SEL_ISR__INTC_NUMBER 3u
+#define SCSI_SEL_ISR__INTC_MASK 0x20u
+#define SCSI_SEL_ISR__INTC_NUMBER 5u
#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u
-#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3
+#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_5
#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB15_MSK
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB15_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK
+#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
/* SCSI_Glitch_Ctl */
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U
#define BCLK__BUS_CLK__KHZ 50000U
#define BCLK__BUS_CLK__MHZ 50U
#define CY_PROJECT_NAME "SCSI2SD"
-#define CY_VERSION "PSoC Creator 4.2"
+#define CY_VERSION "PSoC Creator 4.4"
#define CYDEV_CHIP_DIE_LEOPARD 1u
-#define CYDEV_CHIP_DIE_PSOC4A 18u
+#define CYDEV_CHIP_DIE_PSOC4A 26u
#define CYDEV_CHIP_DIE_PSOC5LP 2u
#define CYDEV_CHIP_DIE_PSOC5TM 3u
#define CYDEV_CHIP_DIE_TMA4 4u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
#define CYDEV_CHIP_JTAG_ID 0x2E133069u
#define CYDEV_CHIP_MEMBER_3A 1u
-#define CYDEV_CHIP_MEMBER_4A 18u
-#define CYDEV_CHIP_MEMBER_4D 13u
+#define CYDEV_CHIP_MEMBER_4A 26u
+#define CYDEV_CHIP_MEMBER_4AA 25u
+#define CYDEV_CHIP_MEMBER_4AB 30u
+#define CYDEV_CHIP_MEMBER_4AC 14u
+#define CYDEV_CHIP_MEMBER_4AD 15u
+#define CYDEV_CHIP_MEMBER_4AE 16u
+#define CYDEV_CHIP_MEMBER_4D 20u
#define CYDEV_CHIP_MEMBER_4E 6u
-#define CYDEV_CHIP_MEMBER_4F 19u
+#define CYDEV_CHIP_MEMBER_4F 27u
#define CYDEV_CHIP_MEMBER_4G 4u
-#define CYDEV_CHIP_MEMBER_4H 17u
-#define CYDEV_CHIP_MEMBER_4I 23u
-#define CYDEV_CHIP_MEMBER_4J 14u
-#define CYDEV_CHIP_MEMBER_4K 15u
-#define CYDEV_CHIP_MEMBER_4L 22u
-#define CYDEV_CHIP_MEMBER_4M 21u
-#define CYDEV_CHIP_MEMBER_4N 10u
-#define CYDEV_CHIP_MEMBER_4O 7u
-#define CYDEV_CHIP_MEMBER_4P 20u
-#define CYDEV_CHIP_MEMBER_4Q 12u
-#define CYDEV_CHIP_MEMBER_4R 8u
-#define CYDEV_CHIP_MEMBER_4S 11u
-#define CYDEV_CHIP_MEMBER_4T 9u
+#define CYDEV_CHIP_MEMBER_4H 24u
+#define CYDEV_CHIP_MEMBER_4I 32u
+#define CYDEV_CHIP_MEMBER_4J 21u
+#define CYDEV_CHIP_MEMBER_4K 22u
+#define CYDEV_CHIP_MEMBER_4L 31u
+#define CYDEV_CHIP_MEMBER_4M 29u
+#define CYDEV_CHIP_MEMBER_4N 11u
+#define CYDEV_CHIP_MEMBER_4O 8u
+#define CYDEV_CHIP_MEMBER_4P 28u
+#define CYDEV_CHIP_MEMBER_4Q 17u
+#define CYDEV_CHIP_MEMBER_4R 9u
+#define CYDEV_CHIP_MEMBER_4S 12u
+#define CYDEV_CHIP_MEMBER_4T 10u
#define CYDEV_CHIP_MEMBER_4U 5u
-#define CYDEV_CHIP_MEMBER_4V 16u
+#define CYDEV_CHIP_MEMBER_4V 23u
+#define CYDEV_CHIP_MEMBER_4W 13u
+#define CYDEV_CHIP_MEMBER_4X 7u
+#define CYDEV_CHIP_MEMBER_4Y 18u
+#define CYDEV_CHIP_MEMBER_4Z 19u
#define CYDEV_CHIP_MEMBER_5A 3u
#define CYDEV_CHIP_MEMBER_5B 2u
-#define CYDEV_CHIP_MEMBER_6A 24u
-#define CYDEV_CHIP_MEMBER_FM3 28u
-#define CYDEV_CHIP_MEMBER_FM4 29u
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u
+#define CYDEV_CHIP_MEMBER_6A 33u
+#define CYDEV_CHIP_MEMBER_FM3 37u
+#define CYDEV_CHIP_MEMBER_FM4 38u
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 34u
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 35u
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 36u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4AA_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4AB_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4AC_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4AD_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4AE_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4W_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4X_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4Y_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4Z_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_ECC_ENABLE 0
#define CYDEV_HEAP_SIZE 0x0400
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
-#define CYDEV_INTR_RISING 0x0000007Fu
+#define CYDEV_INTR_RISING 0x000001FFu
#define CYDEV_IS_EXPORTING_CODE 0
#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 2
#define CYIPBLOCK_S8_SAR_VERSION 0
#define CYIPBLOCK_S8_SIO_VERSION 0
#define CYIPBLOCK_S8_UDB_VERSION 0
-#define DMA_CHANNELS_USED__MASK0 0x0000000Fu
+#define DMA_CHANNELS_USED__MASK0 0x0000003Fu
#define CYDEV_BOOTLOADER_ENABLE 0
#endif /* INCLUDED_CYFITTER_H */
/*******************************************************************************
* File Name: cyfitter_cfg.c
*
-* PSoC Creator 4.2
+* PSoC Creator 4.4
*
* Description:
* This file contains device initialization code.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
+* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
}
#endif
-#define CY_CFG_BASE_ADDR_COUNT 42u
+#define CY_CFG_BASE_ADDR_COUNT 43u
CYPACKED typedef struct
{
uint8 offset;
/* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */
static const uint8 CYCODE BS_IOPINS0_3_VAL[] = {
- 0x08u, 0x00u, 0x01u, 0xFEu, 0xFEu, 0x02u, 0xF6u, 0x00u, 0x00u, 0x01u};
+ 0x08u, 0x00u, 0x01u, 0xFEu, 0xFEu, 0x02u, 0xC6u, 0x00u, 0x00u, 0x01u};
/* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */
static const uint8 CYCODE BS_IOPINS0_4_VAL[] = {
static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = {
0x00u, 0x03u, 0x00u, 0x00u};
+ /* PHUB_CFGMEM4 Address: CYREG_PHUB_CFGMEM4_CFG0 Size (bytes): 4 */
+ static const uint8 CYCODE BS_PHUB_CFGMEM4_VAL[] = {
+ 0x00u, 0x04u, 0x00u, 0x00u};
+
+ /* PHUB_CFGMEM5 Address: CYREG_PHUB_CFGMEM5_CFG0 Size (bytes): 4 */
+ static const uint8 CYCODE BS_PHUB_CFGMEM5_VAL[] = {
+ 0x00u, 0x05u, 0x00u, 0x00u};
+
#ifdef CYGlobalIntDisable
/* Disable interrupts by default. Let user enable if/when they want. */
CYGlobalIntDisable
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x40004501u, /* Base address: 0x40004500 Count: 1 */
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
- 0x4000520Eu, /* Base address: 0x40005200 Count: 14 */
+ 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */
0x40006402u, /* Base address: 0x40006400 Count: 2 */
- 0x40006502u, /* Base address: 0x40006500 Count: 2 */
- 0x40010045u, /* Base address: 0x40010000 Count: 69 */
- 0x4001013Au, /* Base address: 0x40010100 Count: 58 */
- 0x4001024Eu, /* Base address: 0x40010200 Count: 78 */
- 0x4001035Bu, /* Base address: 0x40010300 Count: 91 */
- 0x4001041Bu, /* Base address: 0x40010400 Count: 27 */
- 0x40010545u, /* Base address: 0x40010500 Count: 69 */
- 0x40010651u, /* Base address: 0x40010600 Count: 81 */
- 0x40010751u, /* Base address: 0x40010700 Count: 81 */
+ 0x40006501u, /* Base address: 0x40006500 Count: 1 */
+ 0x4001003Du, /* Base address: 0x40010000 Count: 61 */
+ 0x4001013Fu, /* Base address: 0x40010100 Count: 63 */
+ 0x4001025Au, /* Base address: 0x40010200 Count: 90 */
+ 0x40010354u, /* Base address: 0x40010300 Count: 84 */
+ 0x40010419u, /* Base address: 0x40010400 Count: 25 */
+ 0x40010556u, /* Base address: 0x40010500 Count: 86 */
+ 0x40010653u, /* Base address: 0x40010600 Count: 83 */
+ 0x40010759u, /* Base address: 0x40010700 Count: 89 */
0x4001084Eu, /* Base address: 0x40010800 Count: 78 */
- 0x4001095Fu, /* Base address: 0x40010900 Count: 95 */
- 0x40010A5Cu, /* Base address: 0x40010A00 Count: 92 */
- 0x40010B60u, /* Base address: 0x40010B00 Count: 96 */
- 0x40010C49u, /* Base address: 0x40010C00 Count: 73 */
- 0x40010D54u, /* Base address: 0x40010D00 Count: 84 */
- 0x40010E51u, /* Base address: 0x40010E00 Count: 81 */
- 0x40010F43u, /* Base address: 0x40010F00 Count: 67 */
- 0x40011462u, /* Base address: 0x40011400 Count: 98 */
- 0x40011540u, /* Base address: 0x40011500 Count: 64 */
- 0x40011651u, /* Base address: 0x40011600 Count: 81 */
- 0x4001174Cu, /* Base address: 0x40011700 Count: 76 */
- 0x40011855u, /* Base address: 0x40011800 Count: 85 */
- 0x40011948u, /* Base address: 0x40011900 Count: 72 */
- 0x40011B06u, /* Base address: 0x40011B00 Count: 6 */
- 0x4001401Du, /* Base address: 0x40014000 Count: 29 */
- 0x40014120u, /* Base address: 0x40014100 Count: 32 */
- 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */
- 0x4001430Au, /* Base address: 0x40014300 Count: 10 */
- 0x40014411u, /* Base address: 0x40014400 Count: 17 */
- 0x40014517u, /* Base address: 0x40014500 Count: 23 */
- 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */
- 0x4001470Cu, /* Base address: 0x40014700 Count: 12 */
- 0x4001480Du, /* Base address: 0x40014800 Count: 13 */
- 0x4001491Au, /* Base address: 0x40014900 Count: 26 */
- 0x40014C0Cu, /* Base address: 0x40014C00 Count: 12 */
+ 0x4001095Eu, /* Base address: 0x40010900 Count: 94 */
+ 0x40010A41u, /* Base address: 0x40010A00 Count: 65 */
+ 0x40010B5Cu, /* Base address: 0x40010B00 Count: 92 */
+ 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */
+ 0x40010D61u, /* Base address: 0x40010D00 Count: 97 */
+ 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */
+ 0x40010F41u, /* Base address: 0x40010F00 Count: 65 */
+ 0x40011411u, /* Base address: 0x40011400 Count: 17 */
+ 0x40011550u, /* Base address: 0x40011500 Count: 80 */
+ 0x40011650u, /* Base address: 0x40011600 Count: 80 */
+ 0x40011754u, /* Base address: 0x40011700 Count: 84 */
+ 0x40011848u, /* Base address: 0x40011800 Count: 72 */
+ 0x40011954u, /* Base address: 0x40011900 Count: 84 */
+ 0x40011A4Eu, /* Base address: 0x40011A00 Count: 78 */
+ 0x40011B48u, /* Base address: 0x40011B00 Count: 72 */
+ 0x4001401Cu, /* Base address: 0x40014000 Count: 28 */
+ 0x4001411Fu, /* Base address: 0x40014100 Count: 31 */
+ 0x40014218u, /* Base address: 0x40014200 Count: 24 */
+ 0x40014312u, /* Base address: 0x40014300 Count: 18 */
+ 0x40014412u, /* Base address: 0x40014400 Count: 18 */
+ 0x40014515u, /* Base address: 0x40014500 Count: 21 */
+ 0x4001460Du, /* Base address: 0x40014600 Count: 13 */
+ 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */
+ 0x40014817u, /* Base address: 0x40014800 Count: 23 */
+ 0x40014914u, /* Base address: 0x40014900 Count: 20 */
+ 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */
0x40014D07u, /* Base address: 0x40014D00 Count: 7 */
- 0x40015005u, /* Base address: 0x40015000 Count: 5 */
- 0x40015104u, /* Base address: 0x40015100 Count: 4 */
+ 0x40015006u, /* Base address: 0x40015000 Count: 6 */
+ 0x40015102u, /* Base address: 0x40015100 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x7Eu, 0x02u},
{0x01u, 0x30u},
- {0x0Au, 0x4Bu},
- {0x00u, 0x02u},
- {0x01u, 0x20u},
- {0x10u, 0xA8u},
- {0x11u, 0x2Au},
- {0x18u, 0x62u},
- {0x19u, 0x38u},
+ {0x0Au, 0x36u},
+ {0x00u, 0x22u},
+ {0x10u, 0x0Au},
+ {0x11u, 0x88u},
+ {0x18u, 0xC2u},
+ {0x19u, 0x44u},
{0x1Cu, 0x08u},
{0x20u, 0x01u},
- {0x30u, 0x84u},
- {0x31u, 0x20u},
- {0x61u, 0x20u},
+ {0x31u, 0x84u},
+ {0x60u, 0x20u},
+ {0x61u, 0x22u},
{0x78u, 0x20u},
- {0x79u, 0x20u},
{0x7Cu, 0x40u},
{0x20u, 0x01u},
- {0x88u, 0x0Fu},
- {0x76u, 0x01u},
- {0x85u, 0x0Fu},
- {0x00u, 0x0Au},
- {0x02u, 0x55u},
- {0x06u, 0x7Fu},
- {0x0Cu, 0x8Bu},
- {0x0Eu, 0x74u},
- {0x14u, 0x91u},
- {0x16u, 0x6Cu},
- {0x18u, 0x01u},
- {0x1Cu, 0x40u},
- {0x1Eu, 0x80u},
- {0x22u, 0x10u},
- {0x24u, 0x06u},
- {0x28u, 0x20u},
- {0x2Au, 0x40u},
- {0x30u, 0x3Fu},
- {0x36u, 0xC0u},
- {0x3Au, 0x80u},
- {0x40u, 0x62u},
- {0x41u, 0x04u},
- {0x42u, 0x10u},
- {0x45u, 0xECu},
- {0x46u, 0x2Du},
- {0x47u, 0x0Fu},
+ {0x84u, 0x0Fu},
+ {0x84u, 0x0Fu},
+ {0x01u, 0x06u},
+ {0x02u, 0x03u},
+ {0x05u, 0x02u},
+ {0x06u, 0x04u},
+ {0x07u, 0x01u},
+ {0x0Du, 0x01u},
+ {0x0Eu, 0x24u},
+ {0x0Fu, 0x04u},
+ {0x10u, 0x24u},
+ {0x11u, 0x08u},
+ {0x12u, 0x09u},
+ {0x19u, 0x08u},
+ {0x1Au, 0x18u},
+ {0x28u, 0x24u},
+ {0x29u, 0x10u},
+ {0x2Au, 0x12u},
+ {0x2Du, 0x01u},
+ {0x2Eu, 0x20u},
+ {0x2Fu, 0x02u},
+ {0x30u, 0x07u},
+ {0x31u, 0x07u},
+ {0x33u, 0x10u},
+ {0x34u, 0x38u},
+ {0x35u, 0x08u},
+ {0x39u, 0x22u},
+ {0x3Fu, 0x04u},
+ {0x40u, 0x46u},
+ {0x41u, 0x02u},
+ {0x42u, 0x50u},
+ {0x45u, 0xDCu},
+ {0x46u, 0x2Fu},
+ {0x47u, 0x0Eu},
{0x48u, 0x1Fu},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Fu, 0x2Cu},
{0x56u, 0x01u},
{0x58u, 0x04u},
+ {0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
{0x5Cu, 0x02u},
{0x68u, 0x40u},
{0x69u, 0x40u},
{0x6Eu, 0x08u},
- {0x81u, 0x04u},
- {0x84u, 0x02u},
- {0x86u, 0x01u},
- {0x89u, 0x02u},
- {0x8Du, 0x01u},
- {0x94u, 0x02u},
{0x96u, 0x01u},
- {0x98u, 0x02u},
- {0x9Au, 0x05u},
- {0x9Cu, 0x01u},
- {0x9Eu, 0x02u},
- {0xA0u, 0x02u},
- {0xA2u, 0x09u},
- {0xB1u, 0x04u},
- {0xB2u, 0x08u},
- {0xB4u, 0x04u},
- {0xB5u, 0x02u},
- {0xB6u, 0x03u},
- {0xB7u, 0x01u},
- {0xBAu, 0x80u},
- {0xBFu, 0x50u},
- {0xD6u, 0x08u},
+ {0x97u, 0x01u},
+ {0xAAu, 0x02u},
+ {0xB2u, 0x01u},
+ {0xB3u, 0x01u},
+ {0xB4u, 0x02u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x92u},
- {0xDDu, 0x90u},
+ {0xDCu, 0x22u},
{0xDFu, 0x01u},
- {0x01u, 0x02u},
- {0x03u, 0x12u},
- {0x04u, 0x04u},
- {0x0Au, 0x01u},
- {0x0Bu, 0x28u},
- {0x0Eu, 0x2Au},
- {0x10u, 0xA4u},
- {0x16u, 0x80u},
+ {0x01u, 0x06u},
+ {0x03u, 0x02u},
+ {0x08u, 0x20u},
+ {0x0Au, 0x44u},
+ {0x0Eu, 0x20u},
+ {0x11u, 0x40u},
+ {0x12u, 0x08u},
+ {0x17u, 0x10u},
{0x19u, 0x02u},
- {0x1Au, 0x01u},
- {0x1Cu, 0x04u},
- {0x1Eu, 0x22u},
- {0x1Fu, 0x80u},
- {0x24u, 0x02u},
- {0x25u, 0x02u},
- {0x27u, 0x04u},
- {0x3Du, 0xA2u},
- {0x3Fu, 0x02u},
- {0x40u, 0x08u},
- {0x42u, 0x01u},
+ {0x1Au, 0x04u},
+ {0x1Eu, 0x10u},
+ {0x1Fu, 0x10u},
+ {0x21u, 0x11u},
+ {0x22u, 0x02u},
+ {0x23u, 0x20u},
+ {0x25u, 0x04u},
+ {0x27u, 0x10u},
+ {0x29u, 0x20u},
+ {0x2Bu, 0x01u},
+ {0x31u, 0x22u},
+ {0x36u, 0x04u},
+ {0x39u, 0x02u},
+ {0x3Bu, 0x44u},
+ {0x40u, 0x04u},
{0x43u, 0x02u},
- {0x48u, 0x20u},
- {0x49u, 0x14u},
- {0x4Bu, 0x22u},
- {0x50u, 0x80u},
- {0x51u, 0x60u},
+ {0x48u, 0x04u},
+ {0x49u, 0x84u},
+ {0x4Au, 0x88u},
{0x52u, 0x10u},
- {0x53u, 0x08u},
- {0x59u, 0xA0u},
- {0x5Bu, 0x0Au},
- {0x5Cu, 0x80u},
- {0x60u, 0x60u},
- {0x62u, 0xA0u},
- {0x66u, 0x80u},
- {0x68u, 0x04u},
+ {0x53u, 0x68u},
+ {0x58u, 0x12u},
+ {0x59u, 0x08u},
+ {0x5Au, 0x80u},
+ {0x60u, 0x80u},
+ {0x62u, 0x20u},
+ {0x63u, 0x21u},
+ {0x68u, 0x80u},
{0x69u, 0x44u},
- {0x6Bu, 0x40u},
- {0x70u, 0x50u},
- {0x72u, 0x40u},
- {0x73u, 0x10u},
- {0x81u, 0x60u},
- {0x83u, 0x01u},
- {0x84u, 0x08u},
- {0x85u, 0x46u},
- {0x87u, 0x10u},
- {0x88u, 0xA0u},
- {0x8Cu, 0x41u},
- {0xC0u, 0x2Du},
- {0xC2u, 0xE7u},
- {0xC4u, 0x1Eu},
- {0xCEu, 0xB0u},
- {0xD0u, 0x0Du},
- {0xD2u, 0x04u},
- {0xD6u, 0x1Fu},
- {0xD8u, 0x1Fu},
- {0xE0u, 0x2Du},
- {0xE2u, 0x42u},
- {0xE4u, 0x0Au},
- {0x01u, 0x02u},
- {0x03u, 0x11u},
- {0x05u, 0x02u},
- {0x07u, 0x05u},
- {0x0Cu, 0x02u},
- {0x0Du, 0x02u},
- {0x0Eu, 0x01u},
- {0x0Fu, 0x01u},
- {0x11u, 0x01u},
- {0x13u, 0x02u},
+ {0x6Bu, 0x08u},
+ {0x70u, 0x08u},
+ {0x72u, 0x0Au},
+ {0x73u, 0x80u},
+ {0x81u, 0x04u},
+ {0x84u, 0x02u},
+ {0x86u, 0x88u},
+ {0x87u, 0x80u},
+ {0x8Au, 0x02u},
+ {0x8Bu, 0x40u},
+ {0x8Fu, 0x01u},
+ {0xC0u, 0x0Du},
+ {0xC2u, 0x2Au},
+ {0xC4u, 0x43u},
+ {0xCAu, 0x0Cu},
+ {0xCCu, 0x45u},
+ {0xCEu, 0x0Bu},
+ {0xD0u, 0x05u},
+ {0xD2u, 0x0Cu},
+ {0xD6u, 0x0Fu},
+ {0xD8u, 0x0Fu},
+ {0xE0u, 0x02u},
+ {0xE2u, 0x08u},
+ {0xE4u, 0x09u},
+ {0xE6u, 0x82u},
+ {0x01u, 0x1Cu},
+ {0x04u, 0x01u},
+ {0x05u, 0x14u},
+ {0x06u, 0x02u},
+ {0x07u, 0x08u},
+ {0x08u, 0x02u},
+ {0x09u, 0x24u},
+ {0x0Au, 0x01u},
+ {0x0Bu, 0x10u},
+ {0x0Du, 0x30u},
+ {0x0Fu, 0x0Fu},
+ {0x11u, 0x0Cu},
+ {0x13u, 0x10u},
{0x14u, 0x02u},
- {0x15u, 0x02u},
- {0x16u, 0x11u},
- {0x17u, 0x09u},
- {0x18u, 0x02u},
- {0x1Au, 0x05u},
- {0x1Cu, 0x01u},
- {0x1Eu, 0x02u},
- {0x24u, 0x02u},
- {0x26u, 0x09u},
- {0x30u, 0x04u},
- {0x31u, 0x03u},
- {0x32u, 0x08u},
- {0x33u, 0x08u},
- {0x34u, 0x10u},
- {0x35u, 0x10u},
- {0x36u, 0x03u},
- {0x37u, 0x04u},
- {0x3Au, 0x80u},
- {0x3Bu, 0x02u},
+ {0x15u, 0x21u},
+ {0x16u, 0x01u},
+ {0x17u, 0x1Eu},
+ {0x19u, 0x11u},
+ {0x1Bu, 0x22u},
+ {0x1Cu, 0x02u},
+ {0x1Eu, 0x05u},
+ {0x20u, 0x02u},
+ {0x21u, 0x1Cu},
+ {0x22u, 0x09u},
+ {0x29u, 0x10u},
+ {0x2Bu, 0x0Cu},
+ {0x2Du, 0x08u},
+ {0x32u, 0x04u},
+ {0x33u, 0x0Fu},
+ {0x34u, 0x03u},
+ {0x35u, 0x30u},
+ {0x36u, 0x08u},
+ {0x3Au, 0x20u},
+ {0x3Bu, 0x20u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x22u},
+ {0x5Cu, 0x12u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x78u},
- {0x82u, 0x03u},
- {0x86u, 0x7Fu},
- {0x87u, 0x06u},
- {0x8Cu, 0x20u},
- {0x8Eu, 0x40u},
- {0x8Fu, 0x08u},
- {0x90u, 0x01u},
- {0x92u, 0x6Eu},
- {0x94u, 0x20u},
- {0x96u, 0x40u},
- {0x97u, 0x30u},
- {0x98u, 0x80u},
- {0x9Au, 0x01u},
- {0x9Bu, 0x01u},
- {0x9Cu, 0x03u},
- {0x9Eu, 0x74u},
- {0x9Fu, 0x40u},
- {0xA0u, 0x02u},
- {0xA1u, 0x49u},
- {0xA3u, 0x24u},
+ {0x81u, 0xC0u},
+ {0x83u, 0x02u},
+ {0x85u, 0x7Fu},
+ {0x87u, 0x80u},
+ {0x88u, 0x50u},
+ {0x8Au, 0x0Cu},
+ {0x8Bu, 0x60u},
+ {0x8Cu, 0x5Cu},
+ {0x8Fu, 0xFFu},
+ {0x90u, 0x21u},
+ {0x91u, 0x90u},
+ {0x92u, 0x1Eu},
+ {0x93u, 0x40u},
+ {0x94u, 0x24u},
+ {0x95u, 0xC0u},
+ {0x96u, 0x10u},
+ {0x97u, 0x08u},
+ {0x98u, 0x30u},
+ {0x99u, 0xC0u},
+ {0x9Au, 0x0Fu},
+ {0x9Bu, 0x04u},
+ {0x9Cu, 0x5Cu},
+ {0x9Du, 0xC0u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0x11u},
+ {0xA2u, 0x22u},
+ {0xA3u, 0x9Fu},
+ {0xA4u, 0x54u},
+ {0xA5u, 0x80u},
{0xA6u, 0x08u},
- {0xA8u, 0x64u},
- {0xA9u, 0x01u},
- {0xABu, 0x48u},
- {0xADu, 0x49u},
- {0xAFu, 0x12u},
- {0xB2u, 0x80u},
- {0xB3u, 0x70u},
- {0xB4u, 0x1Fu},
- {0xB5u, 0x0Eu},
- {0xB6u, 0x60u},
- {0xB7u, 0x01u},
- {0xBAu, 0x80u},
- {0xBEu, 0x04u},
- {0xBFu, 0x40u},
+ {0xA8u, 0x08u},
+ {0xACu, 0x0Cu},
+ {0xADu, 0x1Fu},
+ {0xAEu, 0x50u},
+ {0xAFu, 0x20u},
+ {0xB0u, 0x0Fu},
+ {0xB2u, 0x30u},
+ {0xB4u, 0x40u},
+ {0xB5u, 0xFFu},
+ {0xB6u, 0x40u},
+ {0xBAu, 0x08u},
+ {0xBEu, 0x50u},
+ {0xBFu, 0x10u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x22u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x01u, 0x82u},
- {0x03u, 0x10u},
- {0x04u, 0x40u},
- {0x08u, 0x89u},
- {0x0Bu, 0x08u},
- {0x0Du, 0x20u},
+ {0x00u, 0x80u},
+ {0x03u, 0x04u},
+ {0x04u, 0x14u},
+ {0x06u, 0x20u},
+ {0x09u, 0x80u},
+ {0x0Au, 0x20u},
+ {0x0Bu, 0x44u},
{0x0Eu, 0x12u},
- {0x10u, 0x84u},
- {0x12u, 0x10u},
- {0x13u, 0x02u},
- {0x16u, 0x20u},
- {0x18u, 0x28u},
- {0x19u, 0x90u},
- {0x1Cu, 0x42u},
- {0x1Du, 0x20u},
- {0x1Eu, 0x12u},
- {0x20u, 0x24u},
- {0x21u, 0x88u},
- {0x25u, 0x45u},
- {0x26u, 0x02u},
- {0x27u, 0x04u},
- {0x28u, 0x01u},
- {0x29u, 0x12u},
- {0x2Bu, 0x02u},
- {0x2Eu, 0x40u},
+ {0x10u, 0x22u},
+ {0x12u, 0x44u},
+ {0x16u, 0x80u},
+ {0x18u, 0x40u},
+ {0x19u, 0x14u},
+ {0x1Au, 0x22u},
+ {0x1Bu, 0x05u},
+ {0x1Cu, 0x14u},
+ {0x1Eu, 0x22u},
+ {0x21u, 0x20u},
+ {0x24u, 0x08u},
+ {0x25u, 0x18u},
+ {0x27u, 0x20u},
+ {0x29u, 0x05u},
+ {0x2Au, 0x40u},
+ {0x2Bu, 0x01u},
+ {0x2Du, 0x11u},
{0x2Fu, 0x01u},
- {0x30u, 0x20u},
- {0x31u, 0x08u},
- {0x33u, 0x40u},
- {0x36u, 0x02u},
- {0x37u, 0x04u},
- {0x38u, 0x04u},
- {0x39u, 0x40u},
- {0x3Du, 0x88u},
- {0x3Fu, 0x01u},
- {0x40u, 0x20u},
- {0x43u, 0x08u},
- {0x58u, 0x20u},
- {0x59u, 0x04u},
- {0x5Au, 0x40u},
- {0x5Bu, 0x02u},
- {0x5Fu, 0x50u},
- {0x61u, 0x80u},
- {0x66u, 0x20u},
- {0x67u, 0x01u},
- {0x6Bu, 0x01u},
- {0x80u, 0x10u},
- {0x81u, 0x10u},
- {0x84u, 0x54u},
- {0x87u, 0x04u},
- {0x8Bu, 0x50u},
- {0x91u, 0x40u},
- {0x93u, 0x02u},
- {0x97u, 0x08u},
- {0x99u, 0x06u},
- {0x9Au, 0x10u},
- {0x9Bu, 0x40u},
- {0x9Cu, 0x04u},
- {0x9Du, 0x90u},
- {0x9Fu, 0x18u},
- {0xA0u, 0xA4u},
- {0xA2u, 0x10u},
+ {0x30u, 0x22u},
+ {0x31u, 0x80u},
+ {0x33u, 0x04u},
+ {0x34u, 0x04u},
+ {0x37u, 0x21u},
+ {0x39u, 0x22u},
+ {0x3Bu, 0x44u},
+ {0x3Du, 0x20u},
+ {0x3Eu, 0x46u},
+ {0x58u, 0x40u},
+ {0x5Du, 0x40u},
+ {0x60u, 0x02u},
+ {0x66u, 0x80u},
+ {0x82u, 0x20u},
+ {0x89u, 0x02u},
+ {0x8Bu, 0x08u},
+ {0x8Cu, 0x02u},
+ {0x8Eu, 0x08u},
+ {0x8Fu, 0x02u},
+ {0x91u, 0x20u},
+ {0x92u, 0x10u},
+ {0x93u, 0xA0u},
+ {0x96u, 0x80u},
+ {0x97u, 0x44u},
+ {0x98u, 0x61u},
+ {0x99u, 0x02u},
+ {0x9Au, 0x18u},
+ {0x9Du, 0xA0u},
+ {0xA0u, 0x84u},
+ {0xA1u, 0x04u},
+ {0xA2u, 0x80u},
{0xA3u, 0x08u},
- {0xA4u, 0x01u},
- {0xA5u, 0x11u},
- {0xA6u, 0xA4u},
- {0xA7u, 0x02u},
- {0xA8u, 0x10u},
- {0xABu, 0x82u},
- {0xACu, 0x01u},
- {0xADu, 0x22u},
- {0xB3u, 0x01u},
- {0xB4u, 0x40u},
+ {0xA5u, 0x22u},
+ {0xA6u, 0x34u},
+ {0xA7u, 0x13u},
+ {0xA8u, 0x80u},
+ {0xA9u, 0x08u},
+ {0xABu, 0x20u},
+ {0xACu, 0x08u},
+ {0xAFu, 0x08u},
+ {0xB0u, 0x51u},
+ {0xB2u, 0x02u},
+ {0xB4u, 0x04u},
{0xB6u, 0x40u},
- {0xB7u, 0x0Cu},
- {0xC0u, 0x8Du},
- {0xC2u, 0xEFu},
- {0xC4u, 0x2Eu},
- {0xCAu, 0x0Du},
- {0xCCu, 0xCEu},
- {0xCEu, 0xDAu},
- {0xD6u, 0x3Fu},
- {0xD8u, 0x38u},
- {0xE0u, 0x28u},
- {0xE2u, 0x01u},
- {0xE4u, 0x82u},
- {0xE6u, 0x08u},
- {0xE8u, 0x04u},
+ {0xB7u, 0x28u},
+ {0xC0u, 0x63u},
+ {0xC2u, 0xAFu},
+ {0xC4u, 0x1Fu},
+ {0xCAu, 0xBBu},
+ {0xCCu, 0xEFu},
+ {0xCEu, 0xFFu},
+ {0xD6u, 0x18u},
+ {0xD8u, 0x18u},
+ {0xE0u, 0x04u},
+ {0xE4u, 0x04u},
+ {0xE8u, 0x0Au},
{0xEAu, 0x10u},
- {0xECu, 0x0Cu},
- {0xEEu, 0x13u},
- {0x88u, 0x02u},
- {0x8Du, 0x02u},
- {0x8Fu, 0x01u},
- {0x91u, 0x02u},
- {0x93u, 0x05u},
+ {0xEEu, 0x05u},
+ {0x85u, 0x02u},
+ {0x87u, 0x01u},
+ {0x8Du, 0x01u},
+ {0x8Fu, 0x02u},
{0x95u, 0x02u},
- {0x96u, 0x01u},
- {0x97u, 0x09u},
- {0x99u, 0x01u},
- {0x9Bu, 0x02u},
+ {0x97u, 0x01u},
+ {0xA2u, 0x02u},
+ {0xA5u, 0x02u},
+ {0xA7u, 0x01u},
+ {0xACu, 0x01u},
{0xADu, 0x02u},
- {0xAFu, 0x11u},
- {0xB0u, 0x02u},
- {0xB1u, 0x04u},
- {0xB3u, 0x03u},
- {0xB4u, 0x01u},
- {0xB5u, 0x10u},
- {0xB7u, 0x08u},
- {0xBBu, 0x08u},
+ {0xAFu, 0x05u},
+ {0xB0u, 0x01u},
+ {0xB2u, 0x02u},
+ {0xB3u, 0x04u},
+ {0xB7u, 0x03u},
+ {0xBBu, 0x80u},
{0xBEu, 0x01u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xDCu, 0x22u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x18u},
- {0x01u, 0x80u},
- {0x05u, 0x10u},
- {0x08u, 0xA0u},
- {0x09u, 0x88u},
- {0x0Bu, 0x80u},
- {0x0Eu, 0x20u},
- {0x11u, 0xAAu},
- {0x19u, 0x01u},
- {0x1Au, 0x02u},
- {0x1Cu, 0x80u},
- {0x1Eu, 0x08u},
- {0x20u, 0x08u},
- {0x21u, 0x24u},
- {0x23u, 0x01u},
- {0x24u, 0x40u},
- {0x27u, 0x36u},
- {0x28u, 0x20u},
- {0x29u, 0x21u},
- {0x2Au, 0x40u},
+ {0x00u, 0x0Au},
+ {0x01u, 0xA0u},
+ {0x08u, 0x42u},
+ {0x0Bu, 0x08u},
+ {0x12u, 0x99u},
+ {0x14u, 0x01u},
+ {0x17u, 0x02u},
+ {0x19u, 0xA0u},
+ {0x1Au, 0x80u},
+ {0x1Eu, 0x80u},
+ {0x1Fu, 0x08u},
+ {0x20u, 0x20u},
+ {0x21u, 0x04u},
+ {0x22u, 0x20u},
+ {0x25u, 0x40u},
+ {0x26u, 0x04u},
+ {0x28u, 0x04u},
{0x2Eu, 0x80u},
- {0x30u, 0x02u},
- {0x31u, 0xA8u},
- {0x37u, 0x26u},
- {0x38u, 0x90u},
+ {0x2Fu, 0x10u},
+ {0x30u, 0x40u},
+ {0x31u, 0x08u},
+ {0x32u, 0x60u},
+ {0x36u, 0x04u},
+ {0x38u, 0x80u},
{0x39u, 0x08u},
- {0x3Au, 0x01u},
- {0x3Cu, 0x40u},
- {0x40u, 0x81u},
- {0x41u, 0x08u},
- {0x48u, 0x80u},
- {0x49u, 0x08u},
- {0x4Au, 0x0Au},
- {0x4Bu, 0x02u},
- {0x52u, 0x50u},
- {0x53u, 0x48u},
- {0x5Du, 0x40u},
+ {0x3Du, 0x88u},
+ {0x40u, 0x44u},
+ {0x42u, 0x20u},
+ {0x49u, 0x15u},
+ {0x4Bu, 0x40u},
+ {0x50u, 0x01u},
+ {0x51u, 0x20u},
+ {0x52u, 0x04u},
+ {0x53u, 0x80u},
+ {0x5Cu, 0x80u},
+ {0x62u, 0x20u},
{0x66u, 0x80u},
- {0x82u, 0x20u},
- {0x86u, 0x90u},
- {0x87u, 0x08u},
- {0x8Du, 0x40u},
- {0x8Fu, 0x20u},
- {0x90u, 0x04u},
- {0x9Bu, 0x01u},
- {0x9Fu, 0x18u},
- {0xA2u, 0x10u},
- {0xA4u, 0x40u},
- {0xA6u, 0xA4u},
- {0xA7u, 0x02u},
- {0xA8u, 0x08u},
- {0xACu, 0x04u},
- {0xB4u, 0x84u},
- {0xC0u, 0x47u},
- {0xC2u, 0x2Fu},
- {0xC4u, 0x0Fu},
- {0xCAu, 0x1Fu},
- {0xCCu, 0xEFu},
- {0xCEu, 0x1Fu},
- {0xD0u, 0x0Bu},
+ {0x69u, 0x51u},
+ {0x6Au, 0x04u},
+ {0x6Bu, 0x51u},
+ {0x72u, 0x03u},
+ {0x73u, 0x01u},
+ {0x8Au, 0x60u},
+ {0x8Cu, 0x01u},
+ {0x90u, 0x48u},
+ {0x91u, 0x20u},
+ {0x92u, 0x02u},
+ {0x93u, 0xB0u},
+ {0x95u, 0x13u},
+ {0x96u, 0xC4u},
+ {0x97u, 0x46u},
+ {0x98u, 0x23u},
+ {0x99u, 0x12u},
+ {0x9Au, 0x10u},
+ {0x9Bu, 0x20u},
+ {0x9Cu, 0x04u},
+ {0x9Du, 0xA1u},
+ {0x9Eu, 0x06u},
+ {0x9Fu, 0x05u},
+ {0xA0u, 0x84u},
+ {0xA1u, 0x0Cu},
+ {0xA2u, 0x88u},
+ {0xA3u, 0x05u},
+ {0xA4u, 0x62u},
+ {0xA5u, 0x82u},
+ {0xA6u, 0x04u},
+ {0xA7u, 0x10u},
+ {0xAEu, 0x20u},
+ {0xAFu, 0x10u},
+ {0xB5u, 0x40u},
+ {0xB6u, 0x08u},
+ {0xB7u, 0x20u},
+ {0xC0u, 0x0Fu},
+ {0xC2u, 0x0Bu},
+ {0xC4u, 0x9Fu},
+ {0xCAu, 0x54u},
+ {0xCCu, 0x46u},
+ {0xCEu, 0x5Au},
+ {0xD0u, 0x07u},
{0xD2u, 0x0Cu},
{0xD6u, 0x10u},
- {0xD8u, 0x10u},
- {0xE0u, 0x42u},
- {0xE4u, 0x02u},
- {0xE6u, 0x89u},
+ {0xD8u, 0x14u},
+ {0xE2u, 0x21u},
+ {0xE4u, 0x80u},
{0xE8u, 0x40u},
- {0xEAu, 0x08u},
- {0xEEu, 0x04u},
- {0x01u, 0x01u},
- {0x02u, 0x9Fu},
- {0x04u, 0x80u},
- {0x05u, 0x01u},
- {0x08u, 0x1Fu},
- {0x09u, 0x88u},
- {0x0Au, 0x20u},
- {0x0Bu, 0x21u},
- {0x0Cu, 0xC0u},
- {0x0Du, 0xA2u},
- {0x0Eu, 0x01u},
- {0x0Fu, 0x08u},
- {0x10u, 0x7Fu},
- {0x11u, 0x01u},
- {0x12u, 0x80u},
- {0x15u, 0x01u},
- {0x16u, 0xFFu},
- {0x18u, 0xC0u},
- {0x19u, 0x40u},
- {0x1Au, 0x04u},
- {0x1Cu, 0xC0u},
- {0x1Du, 0x04u},
- {0x1Eu, 0x02u},
- {0x21u, 0x10u},
- {0x22u, 0x60u},
- {0x25u, 0x87u},
- {0x27u, 0x18u},
- {0x28u, 0xC0u},
- {0x2Au, 0x08u},
- {0x2Cu, 0x90u},
- {0x2Du, 0x01u},
- {0x2Eu, 0x40u},
- {0x31u, 0x80u},
- {0x32u, 0xFFu},
- {0x33u, 0x40u},
- {0x35u, 0x3Fu},
- {0x37u, 0x08u},
- {0x39u, 0x20u},
- {0x3Eu, 0x04u},
- {0x3Fu, 0x51u},
- {0x54u, 0x09u},
- {0x56u, 0x04u},
+ {0xEEu, 0x02u},
+ {0x00u, 0x04u},
+ {0x02u, 0x02u},
+ {0x0Du, 0x02u},
+ {0x0Fu, 0x01u},
+ {0x11u, 0x02u},
+ {0x13u, 0x09u},
+ {0x14u, 0x02u},
+ {0x15u, 0x02u},
+ {0x16u, 0x04u},
+ {0x17u, 0x01u},
+ {0x18u, 0x04u},
+ {0x19u, 0x01u},
+ {0x1Au, 0x0Au},
+ {0x1Bu, 0x02u},
+ {0x1Cu, 0x04u},
+ {0x1Eu, 0x03u},
+ {0x24u, 0x04u},
+ {0x26u, 0x12u},
+ {0x29u, 0x02u},
+ {0x2Bu, 0x05u},
+ {0x30u, 0x01u},
+ {0x32u, 0x06u},
+ {0x33u, 0x04u},
+ {0x34u, 0x10u},
+ {0x35u, 0x03u},
+ {0x36u, 0x08u},
+ {0x37u, 0x08u},
+ {0x3Au, 0x08u},
+ {0x3Bu, 0x20u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x90u},
- {0x5Du, 0x10u},
+ {0x5Cu, 0x22u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x81u, 0x9Cu},
- {0x84u, 0x01u},
- {0x89u, 0x61u},
- {0x8Bu, 0x1Eu},
+ {0x80u, 0xC6u},
+ {0x81u, 0x10u},
+ {0x84u, 0x42u},
+ {0x85u, 0x22u},
+ {0x87u, 0x08u},
+ {0x88u, 0x39u},
+ {0x89u, 0x04u},
+ {0x8Au, 0x06u},
{0x8Cu, 0x01u},
- {0x8Du, 0xA4u},
- {0x8Eu, 0x02u},
- {0x8Fu, 0x10u},
- {0x91u, 0x8Cu},
- {0x93u, 0x10u},
- {0x95u, 0x30u},
- {0x97u, 0x8Fu},
- {0x98u, 0x02u},
- {0x99u, 0xD1u},
- {0x9Bu, 0x22u},
- {0x9Du, 0x08u},
- {0x9Fu, 0x40u},
- {0xA1u, 0x9Cu},
- {0xA5u, 0x94u},
- {0xA7u, 0x08u},
- {0xADu, 0x10u},
- {0xAFu, 0x8Cu},
- {0xB0u, 0x03u},
- {0xB1u, 0x30u},
- {0xB3u, 0xC1u},
- {0xB7u, 0x0Fu},
- {0xBBu, 0x0Eu},
- {0xBEu, 0x01u},
+ {0x8Du, 0x08u},
+ {0x8Eu, 0x5Eu},
+ {0x8Fu, 0x21u},
+ {0x91u, 0x01u},
+ {0x94u, 0x77u},
+ {0x96u, 0x08u},
+ {0x98u, 0xC2u},
+ {0x99u, 0x01u},
+ {0x9Au, 0x04u},
+ {0x9Cu, 0x04u},
+ {0x9Du, 0x01u},
+ {0x9Eu, 0x20u},
+ {0xA0u, 0xC6u},
+ {0xA1u, 0x01u},
+ {0xA8u, 0x80u},
+ {0xA9u, 0x01u},
+ {0xAAu, 0x46u},
+ {0xACu, 0x46u},
+ {0xADu, 0x07u},
+ {0xAEu, 0x80u},
+ {0xAFu, 0x18u},
+ {0xB0u, 0x70u},
+ {0xB1u, 0x3Fu},
+ {0xB4u, 0x0Fu},
+ {0xB6u, 0x80u},
+ {0xB7u, 0x08u},
+ {0xB8u, 0x20u},
+ {0xB9u, 0x02u},
+ {0xBAu, 0x03u},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x41u},
{0xD4u, 0x09u},
+ {0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
+ {0xDCu, 0x01u},
{0xDFu, 0x01u},
- {0x00u, 0x04u},
- {0x03u, 0x01u},
- {0x05u, 0x16u},
- {0x06u, 0x02u},
- {0x0Au, 0x08u},
- {0x0Eu, 0x56u},
- {0x14u, 0x40u},
- {0x15u, 0x50u},
- {0x19u, 0x01u},
+ {0x00u, 0x40u},
+ {0x01u, 0x20u},
+ {0x02u, 0x10u},
+ {0x03u, 0x40u},
+ {0x04u, 0x08u},
+ {0x05u, 0x01u},
+ {0x06u, 0x10u},
+ {0x09u, 0x08u},
+ {0x0Au, 0x04u},
+ {0x0Bu, 0x02u},
+ {0x0Eu, 0x2Au},
+ {0x11u, 0x50u},
+ {0x13u, 0x01u},
+ {0x16u, 0x20u},
+ {0x18u, 0xC0u},
+ {0x19u, 0x60u},
+ {0x1Au, 0x48u},
+ {0x1Du, 0x01u},
+ {0x1Eu, 0x2Au},
{0x1Fu, 0x04u},
- {0x20u, 0x40u},
- {0x21u, 0x88u},
- {0x26u, 0x44u},
- {0x27u, 0x48u},
- {0x28u, 0xA0u},
- {0x2Au, 0x80u},
- {0x2Du, 0x42u},
- {0x2Fu, 0x20u},
- {0x30u, 0x82u},
- {0x31u, 0x08u},
- {0x32u, 0x20u},
- {0x34u, 0x40u},
- {0x35u, 0x04u},
- {0x36u, 0x81u},
- {0x37u, 0x20u},
- {0x38u, 0xD0u},
- {0x3Au, 0x01u},
- {0x3Cu, 0x80u},
- {0x3Eu, 0x16u},
- {0x44u, 0x01u},
- {0x47u, 0x40u},
- {0x59u, 0x08u},
- {0x5Bu, 0x92u},
- {0x5Cu, 0x02u},
- {0x5Eu, 0x80u},
- {0x5Fu, 0x14u},
- {0x63u, 0x01u},
- {0x64u, 0x01u},
- {0x67u, 0x40u},
- {0x7Cu, 0x40u},
- {0x7Du, 0x80u},
- {0x80u, 0xB0u},
- {0x81u, 0x35u},
- {0x82u, 0x81u},
- {0x84u, 0x02u},
- {0x85u, 0x80u},
- {0x8Au, 0x04u},
- {0x8Bu, 0x40u},
- {0x8Du, 0x81u},
- {0x8Eu, 0x22u},
- {0x90u, 0x04u},
- {0x93u, 0x83u},
- {0x94u, 0x91u},
- {0x99u, 0x08u},
- {0x9Bu, 0x21u},
- {0x9Cu, 0x20u},
- {0x9Du, 0xA0u},
- {0x9Eu, 0x01u},
- {0xA0u, 0x80u},
- {0xA4u, 0x02u},
- {0xA5u, 0xDDu},
- {0xA6u, 0x0Au},
- {0xABu, 0x08u},
- {0xAFu, 0x01u},
- {0xB2u, 0x01u},
- {0xB4u, 0x10u},
- {0xB5u, 0x10u},
- {0xB7u, 0x02u},
- {0xC0u, 0xF5u},
- {0xC2u, 0xF2u},
- {0xC4u, 0xD0u},
- {0xCAu, 0xDBu},
- {0xCCu, 0xFFu},
- {0xCEu, 0xFDu},
- {0xD6u, 0xFFu},
- {0xD8u, 0x98u},
- {0xE2u, 0x2Du},
- {0xE4u, 0x10u},
- {0xE6u, 0x05u},
- {0xE8u, 0x02u},
- {0xEAu, 0x25u},
- {0x00u, 0x11u},
- {0x01u, 0x40u},
- {0x02u, 0x22u},
- {0x03u, 0x03u},
- {0x04u, 0xFFu},
- {0x05u, 0x80u},
- {0x0Au, 0xFFu},
- {0x0Bu, 0x20u},
- {0x0Cu, 0x0Fu},
- {0x0Du, 0x40u},
- {0x0Eu, 0xF0u},
+ {0x21u, 0x02u},
+ {0x22u, 0x40u},
+ {0x25u, 0x40u},
+ {0x26u, 0x28u},
+ {0x27u, 0x0Au},
+ {0x28u, 0x10u},
+ {0x2Au, 0x44u},
+ {0x2Bu, 0x47u},
+ {0x2Fu, 0x08u},
+ {0x30u, 0x26u},
+ {0x31u, 0x80u},
+ {0x32u, 0x04u},
+ {0x34u, 0x02u},
+ {0x36u, 0x28u},
+ {0x38u, 0x02u},
+ {0x39u, 0x20u},
+ {0x3Bu, 0x44u},
+ {0x3Du, 0x80u},
+ {0x58u, 0x10u},
+ {0x59u, 0x04u},
+ {0x5Au, 0x82u},
+ {0x5Du, 0x80u},
+ {0x5Fu, 0x10u},
+ {0x60u, 0x80u},
+ {0x62u, 0x80u},
+ {0x64u, 0x02u},
+ {0x66u, 0x20u},
+ {0x84u, 0x80u},
+ {0x85u, 0x40u},
+ {0x90u, 0x0Au},
+ {0x91u, 0x70u},
+ {0x92u, 0x07u},
+ {0x93u, 0x11u},
+ {0x94u, 0x84u},
+ {0x95u, 0x02u},
+ {0x96u, 0x40u},
+ {0x97u, 0x4Eu},
+ {0x98u, 0x20u},
+ {0x99u, 0x06u},
+ {0x9Au, 0x06u},
+ {0x9Bu, 0x71u},
+ {0x9Cu, 0x04u},
+ {0x9Fu, 0x06u},
+ {0xA0u, 0x10u},
+ {0xA1u, 0x28u},
+ {0xA3u, 0x8Du},
+ {0xA4u, 0x62u},
+ {0xA5u, 0x82u},
+ {0xAAu, 0x01u},
+ {0xABu, 0x10u},
+ {0xACu, 0x81u},
+ {0xAFu, 0x40u},
+ {0xB1u, 0x40u},
+ {0xB3u, 0x01u},
+ {0xB4u, 0x80u},
+ {0xC0u, 0x1Fu},
+ {0xC2u, 0xE7u},
+ {0xC4u, 0x2Bu},
+ {0xCAu, 0x2Du},
+ {0xCCu, 0xEDu},
+ {0xCEu, 0x1Fu},
+ {0xD6u, 0x3Fu},
+ {0xD8u, 0x39u},
+ {0xE2u, 0x04u},
+ {0xE4u, 0x08u},
+ {0xE6u, 0x04u},
+ {0xE8u, 0x08u},
+ {0xEAu, 0x05u},
+ {0xEEu, 0x09u},
+ {0x00u, 0x04u},
+ {0x01u, 0x01u},
+ {0x03u, 0x02u},
+ {0x05u, 0x04u},
+ {0x06u, 0x20u},
+ {0x07u, 0x08u},
+ {0x09u, 0x10u},
+ {0x0Au, 0x07u},
+ {0x0Bu, 0x8Fu},
+ {0x0Cu, 0x01u},
+ {0x0Du, 0x0Fu},
{0x0Fu, 0x80u},
- {0x10u, 0x33u},
- {0x12u, 0xCCu},
- {0x13u, 0x24u},
- {0x14u, 0x48u},
- {0x16u, 0x84u},
- {0x17u, 0x18u},
- {0x18u, 0x12u},
- {0x19u, 0x24u},
- {0x1Au, 0x21u},
- {0x1Bu, 0x09u},
- {0x1Cu, 0xFFu},
- {0x24u, 0x44u},
- {0x26u, 0x88u},
- {0x27u, 0x04u},
- {0x29u, 0x24u},
- {0x2Bu, 0x12u},
- {0x30u, 0xFFu},
- {0x31u, 0x07u},
- {0x33u, 0x38u},
- {0x37u, 0xC0u},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x40u},
- {0x56u, 0x02u},
- {0x57u, 0x2Cu},
+ {0x11u, 0x01u},
+ {0x13u, 0x02u},
+ {0x15u, 0x20u},
+ {0x16u, 0x18u},
+ {0x17u, 0x0Fu},
+ {0x18u, 0x07u},
+ {0x19u, 0x04u},
+ {0x1Bu, 0x08u},
+ {0x1Eu, 0x20u},
+ {0x20u, 0x20u},
+ {0x21u, 0x4Fu},
+ {0x22u, 0x10u},
+ {0x23u, 0x80u},
+ {0x26u, 0x02u},
+ {0x27u, 0x10u},
+ {0x28u, 0x20u},
+ {0x29u, 0x50u},
+ {0x2Au, 0x08u},
+ {0x2Bu, 0x8Fu},
+ {0x31u, 0x03u},
+ {0x32u, 0x38u},
+ {0x33u, 0xF0u},
+ {0x34u, 0x07u},
+ {0x35u, 0x0Cu},
+ {0x39u, 0x08u},
+ {0x3Bu, 0x22u},
+ {0x3Eu, 0x10u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x20u},
+ {0x5Cu, 0x22u},
{0x5Fu, 0x01u},
- {0x80u, 0x0Fu},
- {0x82u, 0xF0u},
- {0x84u, 0xFFu},
- {0x85u, 0x44u},
- {0x87u, 0x88u},
- {0x89u, 0x84u},
- {0x8Bu, 0x48u},
- {0x8Fu, 0xFFu},
- {0x91u, 0x11u},
- {0x92u, 0xFFu},
- {0x93u, 0x22u},
- {0x94u, 0x33u},
- {0x96u, 0xCCu},
- {0x98u, 0xFFu},
- {0x9Bu, 0xFFu},
- {0x9Cu, 0x96u},
- {0x9Eu, 0x69u},
- {0xA0u, 0x55u},
- {0xA1u, 0x33u},
- {0xA2u, 0xAAu},
- {0xA3u, 0xCCu},
- {0xA5u, 0xFFu},
- {0xA6u, 0xFFu},
- {0xA9u, 0x21u},
- {0xABu, 0x12u},
- {0xADu, 0x0Fu},
- {0xAEu, 0xFFu},
- {0xAFu, 0xF0u},
- {0xB0u, 0xFFu},
- {0xB3u, 0xFFu},
- {0xBAu, 0x02u},
- {0xBFu, 0x04u},
+ {0x80u, 0x05u},
+ {0x82u, 0x0Au},
+ {0x85u, 0x08u},
+ {0x88u, 0x06u},
+ {0x89u, 0x20u},
+ {0x8Au, 0x09u},
+ {0x8Cu, 0x0Fu},
+ {0x8Eu, 0xF0u},
+ {0x90u, 0x30u},
+ {0x91u, 0x10u},
+ {0x92u, 0xC0u},
+ {0x94u, 0x03u},
+ {0x95u, 0x04u},
+ {0x96u, 0x0Cu},
+ {0x9Du, 0x01u},
+ {0xA4u, 0x60u},
+ {0xA6u, 0x90u},
+ {0xA8u, 0x50u},
+ {0xA9u, 0x02u},
+ {0xAAu, 0xA0u},
+ {0xADu, 0x15u},
+ {0xAFu, 0x2Au},
+ {0xB1u, 0x30u},
+ {0xB3u, 0x0Cu},
+ {0xB5u, 0x03u},
+ {0xB6u, 0xFFu},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x15u},
+ {0xD4u, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x02u},
+ {0xDDu, 0x20u},
{0xDFu, 0x01u},
- {0x01u, 0x02u},
- {0x02u, 0x20u},
- {0x05u, 0x95u},
- {0x07u, 0xA2u},
- {0x08u, 0x0Au},
- {0x0Bu, 0x09u},
- {0x0Cu, 0x01u},
- {0x0Du, 0x40u},
- {0x0Eu, 0x12u},
- {0x0Fu, 0x98u},
- {0x10u, 0x10u},
- {0x11u, 0x08u},
- {0x12u, 0x42u},
- {0x15u, 0x04u},
- {0x19u, 0x02u},
- {0x1Fu, 0x01u},
- {0x22u, 0x08u},
+ {0x00u, 0x02u},
+ {0x02u, 0x80u},
+ {0x03u, 0x0Au},
+ {0x05u, 0x10u},
+ {0x06u, 0xA2u},
+ {0x0Au, 0x20u},
+ {0x0Bu, 0x40u},
+ {0x0Du, 0x10u},
+ {0x0Eu, 0x22u},
+ {0x10u, 0x04u},
+ {0x13u, 0x14u},
+ {0x14u, 0x20u},
+ {0x15u, 0x01u},
+ {0x17u, 0x10u},
+ {0x1Bu, 0x80u},
+ {0x1Eu, 0x20u},
+ {0x1Fu, 0x18u},
+ {0x20u, 0x08u},
+ {0x21u, 0x06u},
{0x24u, 0x20u},
- {0x25u, 0x01u},
- {0x26u, 0x84u},
- {0x27u, 0x80u},
- {0x29u, 0x84u},
- {0x2Bu, 0x48u},
- {0x2Fu, 0x14u},
- {0x31u, 0x11u},
- {0x34u, 0x12u},
- {0x36u, 0x04u},
- {0x39u, 0x84u},
- {0x3Bu, 0x10u},
- {0x3Cu, 0x20u},
- {0x3Du, 0x86u},
- {0x48u, 0x02u},
- {0x4Au, 0x01u},
- {0x67u, 0x80u},
- {0x68u, 0x05u},
- {0x69u, 0x05u},
- {0x6Au, 0x12u},
- {0x6Cu, 0x01u},
- {0x6Eu, 0x04u},
- {0x6Fu, 0x66u},
- {0x70u, 0x04u},
- {0x71u, 0xA0u},
- {0x72u, 0x01u},
- {0x73u, 0x40u},
- {0x74u, 0x80u},
- {0x76u, 0x01u},
- {0x7Bu, 0x0Cu},
- {0x80u, 0x80u},
- {0x83u, 0x64u},
- {0x87u, 0x02u},
- {0x88u, 0x01u},
- {0x8Cu, 0x82u},
- {0x8Eu, 0x08u},
- {0x91u, 0x20u},
- {0x92u, 0x28u},
- {0x93u, 0xA8u},
- {0x94u, 0x68u},
- {0x95u, 0x01u},
- {0x96u, 0x01u},
- {0x97u, 0x42u},
- {0x98u, 0x0Fu},
- {0x99u, 0x38u},
- {0x9Au, 0x40u},
- {0x9Bu, 0x02u},
- {0x9Du, 0x02u},
- {0x9Eu, 0x0Cu},
- {0x9Fu, 0x08u},
- {0xA0u, 0x10u},
- {0xA1u, 0x44u},
- {0xA2u, 0x22u},
- {0xA3u, 0x08u},
- {0xA4u, 0x04u},
- {0xA5u, 0x20u},
- {0xA6u, 0x08u},
- {0xA8u, 0x04u},
- {0xA9u, 0x10u},
- {0xABu, 0x60u},
- {0xACu, 0x11u},
- {0xADu, 0x40u},
- {0xB4u, 0x80u},
- {0xB5u, 0x44u},
+ {0x26u, 0x2Au},
+ {0x27u, 0x10u},
+ {0x28u, 0x04u},
+ {0x2Bu, 0x02u},
+ {0x2Cu, 0x28u},
+ {0x2Du, 0x01u},
+ {0x2Fu, 0x20u},
+ {0x32u, 0x81u},
+ {0x33u, 0x08u},
+ {0x34u, 0x08u},
+ {0x36u, 0x22u},
+ {0x39u, 0x10u},
+ {0x3Bu, 0x04u},
+ {0x3Du, 0x80u},
+ {0x3Eu, 0x20u},
+ {0x3Fu, 0x0Au},
+ {0x44u, 0x08u},
+ {0x46u, 0x04u},
+ {0x48u, 0x08u},
+ {0x4Au, 0x08u},
+ {0x58u, 0x60u},
+ {0x59u, 0x20u},
+ {0x5Cu, 0x04u},
+ {0x5Eu, 0x40u},
+ {0x5Fu, 0x21u},
+ {0x64u, 0x40u},
+ {0x65u, 0x81u},
+ {0x6Fu, 0x02u},
+ {0x85u, 0x02u},
+ {0x89u, 0x02u},
+ {0x8Eu, 0x04u},
+ {0x8Fu, 0x01u},
+ {0x91u, 0xA1u},
+ {0x92u, 0x62u},
+ {0x93u, 0x08u},
+ {0x94u, 0xA8u},
+ {0x95u, 0x1Cu},
+ {0x97u, 0x40u},
+ {0x98u, 0x80u},
+ {0x99u, 0x01u},
+ {0x9Au, 0x32u},
+ {0x9Bu, 0x28u},
+ {0x9Du, 0x08u},
+ {0x9Eu, 0x04u},
+ {0xA0u, 0x23u},
+ {0xA1u, 0x40u},
+ {0xA2u, 0x05u},
+ {0xA3u, 0x45u},
+ {0xA4u, 0x54u},
+ {0xA5u, 0x01u},
+ {0xA6u, 0x2Au},
+ {0xA7u, 0x82u},
+ {0xAAu, 0x28u},
+ {0xACu, 0x10u},
+ {0xADu, 0x08u},
+ {0xAEu, 0x80u},
+ {0xAFu, 0x10u},
+ {0xB2u, 0x02u},
+ {0xB3u, 0x20u},
{0xB7u, 0x40u},
- {0xC0u, 0xFCu},
- {0xC2u, 0xFFu},
- {0xC4u, 0x2Du},
- {0xCAu, 0x6Fu},
- {0xCCu, 0xE5u},
- {0xCEu, 0xFEu},
- {0xD8u, 0x80u},
- {0xE0u, 0x10u},
- {0xE2u, 0x80u},
- {0xE4u, 0x40u},
- {0xE8u, 0x10u},
- {0xEAu, 0x41u},
- {0xEEu, 0x43u},
- {0x05u, 0x50u},
- {0x06u, 0x04u},
- {0x07u, 0xA0u},
- {0x09u, 0x05u},
- {0x0Au, 0x03u},
- {0x0Bu, 0x0Au},
- {0x0Cu, 0x40u},
- {0x0Du, 0x30u},
- {0x0Fu, 0xC0u},
- {0x11u, 0x06u},
+ {0xC0u, 0xFBu},
+ {0xC2u, 0xECu},
+ {0xC4u, 0x76u},
+ {0xCAu, 0xECu},
+ {0xCCu, 0xEBu},
+ {0xCEu, 0xF6u},
+ {0xD6u, 0xF8u},
+ {0xD8u, 0x10u},
+ {0xE2u, 0x04u},
+ {0xE6u, 0x04u},
+ {0xE8u, 0x82u},
+ {0xEAu, 0x01u},
+ {0xECu, 0x60u},
+ {0xEEu, 0x02u},
+ {0x01u, 0x04u},
+ {0x02u, 0x40u},
+ {0x03u, 0x02u},
+ {0x06u, 0x30u},
+ {0x0Bu, 0x04u},
+ {0x0Du, 0x10u},
+ {0x10u, 0x48u},
+ {0x11u, 0x08u},
{0x12u, 0x24u},
- {0x13u, 0x09u},
- {0x14u, 0x24u},
- {0x15u, 0x03u},
- {0x16u, 0x09u},
- {0x17u, 0x0Cu},
- {0x18u, 0x24u},
- {0x19u, 0x60u},
- {0x1Au, 0x12u},
- {0x1Bu, 0x90u},
- {0x1Cu, 0x40u},
- {0x22u, 0x18u},
- {0x24u, 0x40u},
- {0x28u, 0x40u},
- {0x2Du, 0x0Fu},
- {0x2Eu, 0x20u},
- {0x2Fu, 0xF0u},
- {0x30u, 0x40u},
- {0x32u, 0x07u},
- {0x34u, 0x38u},
- {0x37u, 0xFFu},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x40u},
+ {0x13u, 0x10u},
+ {0x16u, 0x48u},
+ {0x17u, 0x04u},
+ {0x19u, 0x08u},
+ {0x1Au, 0x01u},
+ {0x1Bu, 0x03u},
+ {0x1Eu, 0x06u},
+ {0x22u, 0x08u},
+ {0x28u, 0x48u},
+ {0x29u, 0x04u},
+ {0x2Au, 0x12u},
+ {0x2Bu, 0x01u},
+ {0x30u, 0x01u},
+ {0x33u, 0x18u},
+ {0x34u, 0x70u},
+ {0x35u, 0x07u},
+ {0x36u, 0x0Eu},
+ {0x3Fu, 0x04u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x02u},
+ {0x5Cu, 0x22u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x81u, 0x01u},
- {0x83u, 0x02u},
- {0x84u, 0x04u},
- {0x85u, 0x04u},
- {0x86u, 0x08u},
- {0x87u, 0x08u},
- {0x89u, 0x01u},
- {0x8Au, 0x3Fu},
- {0x8Bu, 0x02u},
- {0x8Cu, 0x3Fu},
- {0x8Du, 0x50u},
- {0x8Fu, 0x8Fu},
- {0x91u, 0x10u},
- {0x92u, 0x3Fu},
- {0x93u, 0x8Fu},
- {0x94u, 0x3Fu},
- {0x95u, 0x20u},
- {0x97u, 0x0Fu},
- {0x98u, 0x01u},
- {0x99u, 0x0Fu},
- {0x9Au, 0x02u},
- {0x9Bu, 0x80u},
- {0x9Cu, 0x10u},
- {0x9Du, 0x04u},
- {0x9Eu, 0x20u},
- {0x9Fu, 0x08u},
- {0xA0u, 0x10u},
- {0xA1u, 0x4Fu},
- {0xA2u, 0x20u},
- {0xA3u, 0x80u},
- {0xA4u, 0x04u},
- {0xA6u, 0x08u},
- {0xA7u, 0x10u},
- {0xA8u, 0x01u},
- {0xAAu, 0x02u},
- {0xAEu, 0x3Fu},
- {0xB1u, 0x03u},
- {0xB2u, 0x0Cu},
- {0xB3u, 0xF0u},
- {0xB4u, 0x03u},
- {0xB6u, 0x30u},
- {0xB7u, 0x0Cu},
- {0xB9u, 0x08u},
- {0xBAu, 0xA8u},
- {0xBBu, 0x82u},
- {0xD4u, 0x01u},
+ {0x82u, 0x70u},
+ {0x84u, 0xC0u},
+ {0x86u, 0x1Fu},
+ {0x88u, 0x90u},
+ {0x8Au, 0x2Fu},
+ {0x8Cu, 0x06u},
+ {0x8Eu, 0x09u},
+ {0x8Fu, 0x04u},
+ {0x94u, 0x03u},
+ {0x96u, 0x0Cu},
+ {0x97u, 0x02u},
+ {0x98u, 0x0Fu},
+ {0x9Cu, 0xA0u},
+ {0x9Eu, 0x4Fu},
+ {0xA0u, 0x05u},
+ {0xA2u, 0x0Au},
+ {0xA6u, 0x80u},
+ {0xA9u, 0x01u},
+ {0xADu, 0x02u},
+ {0xAFu, 0x04u},
+ {0xB0u, 0x7Fu},
+ {0xB5u, 0x01u},
+ {0xB6u, 0x80u},
+ {0xB7u, 0x06u},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x50u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x22u},
- {0xDDu, 0x20u},
+ {0xDCu, 0x02u},
{0xDFu, 0x01u},
- {0x00u, 0x40u},
- {0x01u, 0x04u},
- {0x03u, 0x08u},
- {0x05u, 0x04u},
- {0x06u, 0x02u},
- {0x07u, 0x04u},
- {0x08u, 0x02u},
+ {0x00u, 0x04u},
+ {0x01u, 0x02u},
+ {0x02u, 0x10u},
+ {0x04u, 0xA0u},
+ {0x05u, 0x01u},
+ {0x06u, 0x20u},
{0x09u, 0x04u},
- {0x0Bu, 0x0Au},
- {0x0Eu, 0x28u},
- {0x0Fu, 0x82u},
- {0x10u, 0x42u},
- {0x12u, 0x08u},
- {0x13u, 0x08u},
- {0x14u, 0x02u},
+ {0x0Au, 0x0Au},
+ {0x0Bu, 0x80u},
+ {0x0Cu, 0x60u},
+ {0x0Eu, 0x20u},
+ {0x10u, 0x80u},
+ {0x12u, 0x08u},
{0x15u, 0x02u},
- {0x16u, 0x20u},
- {0x17u, 0x10u},
- {0x1Au, 0x48u},
- {0x1Bu, 0x08u},
- {0x1Cu, 0x04u},
- {0x1Du, 0x04u},
- {0x1Eu, 0x08u},
- {0x1Fu, 0x80u},
- {0x23u, 0x02u},
- {0x25u, 0x05u},
+ {0x17u, 0x04u},
+ {0x18u, 0x04u},
+ {0x1Au, 0x82u},
+ {0x1Du, 0x41u},
+ {0x21u, 0x08u},
+ {0x22u, 0x10u},
+ {0x25u, 0x50u},
{0x26u, 0x80u},
- {0x28u, 0x01u},
- {0x29u, 0x40u},
- {0x2Du, 0x08u},
- {0x2Eu, 0x02u},
- {0x2Fu, 0x20u},
- {0x31u, 0x20u},
- {0x32u, 0x05u},
- {0x34u, 0x02u},
- {0x36u, 0xA0u},
- {0x37u, 0x04u},
- {0x38u, 0x28u},
+ {0x27u, 0x01u},
+ {0x29u, 0x10u},
+ {0x2Cu, 0x40u},
+ {0x2Du, 0x41u},
+ {0x2Fu, 0x08u},
+ {0x30u, 0x08u},
+ {0x32u, 0x10u},
+ {0x33u, 0x02u},
+ {0x37u, 0x08u},
+ {0x39u, 0x01u},
+ {0x3Au, 0x20u},
{0x3Bu, 0x40u},
- {0x3Du, 0x02u},
- {0x3Fu, 0xA8u},
- {0x58u, 0x10u},
- {0x5Bu, 0x40u},
- {0x5Du, 0x80u},
- {0x60u, 0x08u},
- {0x62u, 0x40u},
- {0x63u, 0x08u},
- {0x79u, 0x02u},
- {0x7Bu, 0x80u},
- {0x81u, 0x01u},
- {0x85u, 0x30u},
- {0x87u, 0x80u},
- {0x88u, 0x40u},
- {0x8Au, 0x04u},
- {0x8Cu, 0x20u},
- {0x8Du, 0x08u},
- {0x8Eu, 0x42u},
- {0x8Fu, 0x04u},
- {0x91u, 0x44u},
- {0x92u, 0x22u},
- {0x93u, 0xA8u},
- {0x95u, 0x01u},
- {0x96u, 0x01u},
- {0x98u, 0x06u},
- {0x99u, 0x80u},
- {0x9Au, 0x22u},
- {0x9Bu, 0x10u},
- {0x9Cu, 0x80u},
- {0x9Du, 0x46u},
- {0x9Eu, 0x4Cu},
- {0xA0u, 0x12u},
- {0xA2u, 0x30u},
- {0xA3u, 0x31u},
- {0xA4u, 0x24u},
- {0xA5u, 0x2Cu},
- {0xA6u, 0x80u},
- {0xA7u, 0x48u},
- {0xA8u, 0x40u},
- {0xABu, 0x04u},
- {0xADu, 0x20u},
- {0xAFu, 0x88u},
- {0xB2u, 0x04u},
- {0xB4u, 0x42u},
- {0xC0u, 0xE7u},
- {0xC2u, 0xFFu},
- {0xC4u, 0xFFu},
- {0xCAu, 0xC8u},
- {0xCCu, 0xF7u},
- {0xCEu, 0xFEu},
- {0xD6u, 0x1Cu},
- {0xD8u, 0x0Cu},
- {0xE4u, 0x10u},
- {0xE6u, 0x80u},
- {0xE8u, 0x51u},
- {0xECu, 0x08u},
- {0xEEu, 0x02u},
- {0x01u, 0x02u},
- {0x03u, 0x01u},
- {0x08u, 0x01u},
- {0x0Au, 0x06u},
- {0x0Du, 0x02u},
- {0x0Fu, 0x01u},
- {0x11u, 0x10u},
- {0x13u, 0x20u},
- {0x15u, 0x01u},
- {0x17u, 0x12u},
- {0x1Cu, 0x04u},
- {0x1Eu, 0x03u},
- {0x20u, 0x03u},
- {0x22u, 0x04u},
- {0x25u, 0x02u},
- {0x27u, 0x09u},
- {0x28u, 0x05u},
- {0x2Au, 0x02u},
- {0x2Du, 0x02u},
- {0x2Fu, 0x25u},
- {0x31u, 0x08u},
- {0x33u, 0x03u},
- {0x35u, 0x30u},
- {0x36u, 0x07u},
- {0x37u, 0x04u},
- {0x3Au, 0x80u},
- {0x3Bu, 0x08u},
- {0x3Fu, 0x10u},
- {0x56u, 0x08u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
+ {0x3Eu, 0x80u},
+ {0x49u, 0x10u},
+ {0x4Au, 0x08u},
+ {0x58u, 0x18u},
+ {0x59u, 0x80u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x20u},
- {0x5Du, 0x90u},
- {0x5Fu, 0x01u},
- {0x81u, 0x24u},
- {0x83u, 0x12u},
- {0x84u, 0x40u},
- {0x88u, 0x20u},
- {0x8Bu, 0x18u},
- {0x8Fu, 0x20u},
- {0x90u, 0x29u},
- {0x91u, 0x40u},
- {0x92u, 0x52u},
- {0x93u, 0x03u},
- {0x94u, 0x08u},
- {0x97u, 0x04u},
- {0x99u, 0x80u},
- {0x9Cu, 0x10u},
- {0x9Du, 0x40u},
- {0x9Fu, 0x80u},
- {0xA0u, 0x02u},
- {0xA1u, 0x24u},
- {0xA3u, 0x09u},
- {0xA8u, 0x01u},
- {0xAEu, 0x04u},
- {0xAFu, 0x24u},
- {0xB0u, 0x03u},
- {0xB1u, 0x07u},
- {0xB2u, 0x04u},
- {0xB3u, 0xC0u},
- {0xB4u, 0x60u},
- {0xB5u, 0x38u},
- {0xB6u, 0x18u},
- {0xBEu, 0x51u},
- {0xBFu, 0x04u},
- {0xD6u, 0x08u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x22u},
- {0xDDu, 0x90u},
- {0xDFu, 0x01u},
- {0x00u, 0x08u},
- {0x03u, 0x08u},
- {0x06u, 0x08u},
- {0x0Au, 0xA1u},
- {0x0Eu, 0x02u},
- {0x10u, 0x04u},
- {0x11u, 0x81u},
- {0x14u, 0x80u},
- {0x16u, 0x04u},
- {0x18u, 0x80u},
- {0x19u, 0x18u},
- {0x1Bu, 0x80u},
- {0x1Eu, 0x02u},
- {0x1Fu, 0x40u},
- {0x21u, 0x10u},
- {0x22u, 0x15u},
- {0x25u, 0x41u},
- {0x26u, 0x34u},
- {0x27u, 0x0Cu},
- {0x28u, 0x02u},
- {0x2Bu, 0x40u},
- {0x2Du, 0x08u},
- {0x2Fu, 0x01u},
- {0x31u, 0x60u},
- {0x32u, 0x49u},
- {0x36u, 0x04u},
- {0x37u, 0x01u},
- {0x39u, 0xA0u},
- {0x3Au, 0x02u},
- {0x3Du, 0x82u},
- {0x59u, 0x20u},
- {0x5Au, 0x44u},
- {0x5Cu, 0x50u},
- {0x63u, 0x2Au},
- {0x66u, 0x20u},
- {0x67u, 0x02u},
- {0x6Bu, 0x01u},
- {0x6Du, 0x40u},
- {0x6Eu, 0x10u},
- {0x6Fu, 0x20u},
- {0x80u, 0x10u},
+ {0x5Cu, 0x08u},
+ {0x5Eu, 0x81u},
+ {0x5Fu, 0x10u},
+ {0x63u, 0x0Au},
+ {0x65u, 0x40u},
+ {0x69u, 0x40u},
+ {0x6Cu, 0x22u},
+ {0x6Fu, 0x18u},
+ {0x80u, 0x04u},
{0x81u, 0x10u},
- {0x82u, 0x50u},
{0x84u, 0x04u},
{0x85u, 0x04u},
- {0x87u, 0x20u},
- {0x8Au, 0x04u},
- {0x91u, 0x80u},
- {0x93u, 0x28u},
- {0x99u, 0x80u},
- {0x9Au, 0x02u},
- {0x9Bu, 0x10u},
- {0x9Cu, 0x02u},
- {0x9Du, 0x06u},
- {0x9Eu, 0x60u},
- {0x9Fu, 0x04u},
- {0xA0u, 0x12u},
- {0xA2u, 0x08u},
- {0xA4u, 0x20u},
- {0xA5u, 0x0Cu},
- {0xA6u, 0xA4u},
- {0xA7u, 0x75u},
- {0xA8u, 0x61u},
- {0xA9u, 0x04u},
- {0xAAu, 0x08u},
- {0xADu, 0x10u},
- {0xAFu, 0x08u},
- {0xB1u, 0x08u},
- &n
projects / SCSI2SD.git / commitdiff