Powerbook firmware!
authorMichael McMaster <michael@codesrc.com>
Sat, 22 Mar 2014 22:36:29 +0000 (08:36 +1000)
committerMichael McMaster <michael@codesrc.com>
Sat, 22 Mar 2014 22:36:29 +0000 (08:36 +1000)
Includes updates to the bootloderhost utility to compare the USB device release
number against an expected firmware filename to prevent loading the Powerbook
firmware on the normal board, and vice-versa.

408 files changed:
CHANGELOG
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd
software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
software/SCSI2SD/SCSI2SD.cydsn/bits.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/bits.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/config.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/config.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/diagnostic.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/diagnostic.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/disk.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/disk.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/geometry.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/geometry.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/inquiry.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/inquiry.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/led.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/main.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/mode.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/mode.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/scsi.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/scsi.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/sd.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/sd.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/sense.h [deleted file]
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/ARM_C_FILE.P
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/C_FILE.P
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/GNU_ARM_ASM_FILE.P
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/BL.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/BL.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/Cm3Start.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/Cm3Start.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyDmac.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyDmac.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyFlash.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyFlash.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyLib.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyLib.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CySpc.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CySpc.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dp.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dp.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_boot.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_boot.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cdc.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cdc.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_descr.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_descr.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_hid.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_hid.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_midi.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_midi.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_pm.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_pm.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_std.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_std.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_vnd.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_vnd.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USB_Bootloader-ARM_GCC_473-Release-BUILD.log
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USB_Bootloader.a
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USB_Bootloader.elf
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USB_Bootloader.hex
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USB_Bootloader.map
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyPm.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyPm.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyfitter_cfg.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyfitter_cfg.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cymetadata.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cymetadata.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyutils.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyutils.o
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/library.deps
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/main.lst
software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/main.o
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c [new file with mode: 0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h [new file with mode: 0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h [new file with mode: 0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h [changed mode: 0644->0755]
software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
software/SCSI2SD/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch
software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cycdx
software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cydwr
software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit
software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj
software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000
software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt
software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.ctl
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.cycdx
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.cyfit
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.pci
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.pco
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.plc_log
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.route
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.rpt
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdc
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdf
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.v
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.vh2
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.lib
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.pco
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.vh2
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.lib
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.vh2
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.lib
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.vh2
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_timing.html
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_u.sdc
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/bitstream.txt
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice.h
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice_trm.h
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu.inc
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu_trm.inc
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar.inc
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar_trm.inc
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv.inc
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv_trm.inc
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter.h
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.c
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.h
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfittergnu.inc
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitteriar.inc
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitterrv.inc
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cymetadata.c
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/elab_dependencies.txt
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/generated_files.txt
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/lcpsoc3/index
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/placer.log
software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/project.h
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL.h [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyLib.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyLib.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CySpc.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CySpc.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED.c [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED.h [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyPm.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyPm.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevice.h [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cypins.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cytypes.h [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyutils.c [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/eeprom.hex [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/project.h [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/protect.hex [new file with mode: 0644]
software/SCSI2SD/pbook/bootloader.cydsn/TopDesign/TopDesign.cysch [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cycdx [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cydwr [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cyfit [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cyprj [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/bootloader.svd [new file with mode: 0755]
software/SCSI2SD/pbook/bootloader.cydsn/main.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/.gitignore [new file with mode: 0644]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Bootloadable_1.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Bootloadable_1.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3Iar.icf [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3RealView.scat [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3Start.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyDmac.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyDmac.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyFlash.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyFlash.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyLib.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyLib.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CySpc.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CySpc.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_INT.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_PM.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_PVT.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_audio.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_audio.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_boot.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cls.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_descr.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_drv.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_episr.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_hid.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_hid.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_midi.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_midi.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_pm.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_pvt.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_std.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_vnd.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cm3gcc.ld [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cm3.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cmFunc.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cmInstr.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyPm.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyPm.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cybootloader.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cybootloader.icf [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevice.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevice_trm.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicegnu.inc [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydeviceiar.inc [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicerv.inc [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydisabledsheets.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfittergnu.inc [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitteriar.inc [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitterrv.inc [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cymetadata.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cypins.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cytypes.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyutils.c [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/eeprom.hex [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/project.h [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/protect.hex [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/OddParityGen [new symlink]
software/SCSI2SD/pbook/pbook.cydsn/TopDesign/TopDesign.cysch [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/device.h [new file with mode: 0644]
software/SCSI2SD/pbook/pbook.cydsn/pbook.cycdx [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/pbook.cydwr [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/pbook.cyfit [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/pbook.cyprj [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/pbook.svd [new file with mode: 0755]
software/SCSI2SD/pbook/pbook.cydsn/scsiTarget [new symlink]
software/SCSI2SD/src/bits.c [new file with mode: 0755]
software/SCSI2SD/src/bits.h [new file with mode: 0755]
software/SCSI2SD/src/config.c [new file with mode: 0755]
software/SCSI2SD/src/config.h [new file with mode: 0755]
software/SCSI2SD/src/diagnostic.c [new file with mode: 0755]
software/SCSI2SD/src/diagnostic.h [new file with mode: 0755]
software/SCSI2SD/src/disk.c [new file with mode: 0755]
software/SCSI2SD/src/disk.h [new file with mode: 0755]
software/SCSI2SD/src/geometry.c [new file with mode: 0755]
software/SCSI2SD/src/geometry.h [new file with mode: 0755]
software/SCSI2SD/src/inquiry.c [new file with mode: 0755]
software/SCSI2SD/src/inquiry.h [new file with mode: 0755]
software/SCSI2SD/src/led.h [new file with mode: 0755]
software/SCSI2SD/src/main.c [new file with mode: 0755]
software/SCSI2SD/src/mode.c [new file with mode: 0755]
software/SCSI2SD/src/mode.h [new file with mode: 0755]
software/SCSI2SD/src/scsi.c [new file with mode: 0755]
software/SCSI2SD/src/scsi.h [new file with mode: 0755]
software/SCSI2SD/src/scsiPhy.c [new file with mode: 0755]
software/SCSI2SD/src/scsiPhy.h [new file with mode: 0755]
software/SCSI2SD/src/sd.c [new file with mode: 0755]
software/SCSI2SD/src/sd.h [new file with mode: 0755]
software/SCSI2SD/src/sense.h [new file with mode: 0755]
software/bootloaderhost/main.c

index 81e04ec..ef65147 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -4,6 +4,8 @@
        - Bug fix for Unit Attention Condition, which is now enabled by default.
                - scsi2sd-config can be used to disable it for those systems that
                truely require it (eg. Mac Plus).
+       - Added Linked commands support.
+       - Powerbook firmware added
 
 20140214               3.2
        - Remove hacks around ATN handling, and implement proper select-with-atn
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.h
deleted file mode 100755 (executable)
index fc4e09b..0000000
+++ /dev/null
@@ -1,439 +0,0 @@
-/*******************************************************************************
-* File Name: SCSI_CMD_TIMER.h
-* Version 2.50
-*
-*  Description:
-*     Contains the function prototypes and constants available to the timer
-*     user module.
-*
-*   Note:
-*     None
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-********************************************************************************/
-
-#if !defined(CY_Timer_v2_30_SCSI_CMD_TIMER_H)
-#define CY_Timer_v2_30_SCSI_CMD_TIMER_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */
-
-extern uint8 SCSI_CMD_TIMER_initVar;
-
-/* Check to see if required defines such as CY_PSOC5LP are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5LP)
-    #error Component Timer_v2_50 requires cy_boot v3.0 or later
-#endif /* (CY_ PSOC5LP) */
-
-
-/**************************************
-*           Parameter Defaults
-**************************************/
-
-#define SCSI_CMD_TIMER_Resolution                 16u
-#define SCSI_CMD_TIMER_UsingFixedFunction         1u
-#define SCSI_CMD_TIMER_UsingHWCaptureCounter      0u
-#define SCSI_CMD_TIMER_SoftwareCaptureMode        0u
-#define SCSI_CMD_TIMER_SoftwareTriggerMode        0u
-#define SCSI_CMD_TIMER_UsingHWEnable              0u
-#define SCSI_CMD_TIMER_EnableTriggerMode          0u
-#define SCSI_CMD_TIMER_InterruptOnCaptureCount    0u
-#define SCSI_CMD_TIMER_RunModeUsed                1u
-#define SCSI_CMD_TIMER_ControlRegRemoved          0u
-
-
-/***************************************
-*       Type defines
-***************************************/
-
-
-/**************************************************************************
- * Sleep Wakeup Backup structure for Timer Component
- *************************************************************************/
-typedef struct
-{
-    uint8 TimerEnableState;
-    #if(!SCSI_CMD_TIMER_UsingFixedFunction)
-        #if (CY_UDB_V0)
-            uint16 TimerUdb;                 /* Timer internal counter value */
-            uint16 TimerPeriod;              /* Timer Period value       */
-            uint8 InterruptMaskValue;       /* Timer Compare Value */
-            #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
-                uint8 TimerCaptureCounter;  /* Timer Capture Counter Value */
-            #endif /* variable declaration for backing up Capture Counter value*/
-        #endif /* variables for non retention registers in CY_UDB_V0 */
-
-        #if (CY_UDB_V1)
-            uint16 TimerUdb;
-            uint8 InterruptMaskValue;
-            #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
-                uint8 TimerCaptureCounter;
-            #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
-        #endif /* (CY_UDB_V1) */
-
-        #if (!SCSI_CMD_TIMER_ControlRegRemoved)
-            uint8 TimerControlRegister;
-        #endif /* variable declaration for backing up enable state of the Timer */
-    #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
-}SCSI_CMD_TIMER_backupStruct;
-
-
-/***************************************
-*       Function Prototypes
-***************************************/
-
-void    SCSI_CMD_TIMER_Start(void) ;
-void    SCSI_CMD_TIMER_Stop(void) ;
-
-void    SCSI_CMD_TIMER_SetInterruptMode(uint8 interruptMode) ;
-uint8   SCSI_CMD_TIMER_ReadStatusRegister(void) ;
-/* Deprecated function. Do not use this in future. Retained for backward compatibility */
-#define SCSI_CMD_TIMER_GetInterruptSource() SCSI_CMD_TIMER_ReadStatusRegister()
-
-#if(!SCSI_CMD_TIMER_ControlRegRemoved)
-    uint8   SCSI_CMD_TIMER_ReadControlRegister(void) ;
-    void    SCSI_CMD_TIMER_WriteControlRegister(uint8 control) \
-        ;
-#endif /* (!SCSI_CMD_TIMER_ControlRegRemoved) */
-
-uint16  SCSI_CMD_TIMER_ReadPeriod(void) ;
-void    SCSI_CMD_TIMER_WritePeriod(uint16 period) \
-    ;
-uint16  SCSI_CMD_TIMER_ReadCounter(void) ;
-void    SCSI_CMD_TIMER_WriteCounter(uint16 counter) \
-    ;
-uint16  SCSI_CMD_TIMER_ReadCapture(void) ;
-void    SCSI_CMD_TIMER_SoftwareCapture(void) ;
-
-
-#if(!SCSI_CMD_TIMER_UsingFixedFunction) /* UDB Prototypes */
-    #if (SCSI_CMD_TIMER_SoftwareCaptureMode)
-        void    SCSI_CMD_TIMER_SetCaptureMode(uint8 captureMode) ;
-    #endif /* (!SCSI_CMD_TIMER_UsingFixedFunction) */
-
-    #if (SCSI_CMD_TIMER_SoftwareTriggerMode)
-        void    SCSI_CMD_TIMER_SetTriggerMode(uint8 triggerMode) ;
-    #endif /* (SCSI_CMD_TIMER_SoftwareTriggerMode) */
-    #if (SCSI_CMD_TIMER_EnableTriggerMode)
-        void    SCSI_CMD_TIMER_EnableTrigger(void) ;
-        void    SCSI_CMD_TIMER_DisableTrigger(void) ;
-    #endif /* (SCSI_CMD_TIMER_EnableTriggerMode) */
-
-    #if(SCSI_CMD_TIMER_InterruptOnCaptureCount)
-        #if(!SCSI_CMD_TIMER_ControlRegRemoved)
-            void    SCSI_CMD_TIMER_SetInterruptCount(uint8 interruptCount) \
-                ;
-        #endif /* (!SCSI_CMD_TIMER_ControlRegRemoved) */
-    #endif /* (SCSI_CMD_TIMER_InterruptOnCaptureCount) */
-
-    #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
-        void    SCSI_CMD_TIMER_SetCaptureCount(uint8 captureCount) \
-            ;
-        uint8   SCSI_CMD_TIMER_ReadCaptureCount(void) ;
-    #endif /* (SCSI_CMD_TIMER_UsingHWCaptureCounter) */
-
-    void SCSI_CMD_TIMER_ClearFIFO(void) ;
-#endif /* UDB Prototypes */
-
-/* Sleep Retention APIs */
-void SCSI_CMD_TIMER_Init(void)          ;
-void SCSI_CMD_TIMER_Enable(void)        ;
-void SCSI_CMD_TIMER_SaveConfig(void)    ;
-void SCSI_CMD_TIMER_RestoreConfig(void) ;
-void SCSI_CMD_TIMER_Sleep(void)         ;
-void SCSI_CMD_TIMER_Wakeup(void)        ;
-
-
-/***************************************
-*   Enumerated Types and Parameters
-***************************************/
-
-/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */
-#define SCSI_CMD_TIMER__B_TIMER__CM_NONE 0
-#define SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE 1
-#define SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE 2
-#define SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE 3
-#define SCSI_CMD_TIMER__B_TIMER__CM_SOFTWARE 4
-
-
-
-/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */
-#define SCSI_CMD_TIMER__B_TIMER__TM_NONE 0x00u
-#define SCSI_CMD_TIMER__B_TIMER__TM_RISINGEDGE 0x04u
-#define SCSI_CMD_TIMER__B_TIMER__TM_FALLINGEDGE 0x08u
-#define SCSI_CMD_TIMER__B_TIMER__TM_EITHEREDGE 0x0Cu
-#define SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE 0x10u
-
-
-/***************************************
-*    Initialial Parameter Constants
-***************************************/
-
-#define SCSI_CMD_TIMER_INIT_PERIOD             1199u
-#define SCSI_CMD_TIMER_INIT_CAPTURE_MODE       ((uint8)((uint8)0u << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT))
-#define SCSI_CMD_TIMER_INIT_TRIGGER_MODE       ((uint8)((uint8)0u << SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT))
-#if (SCSI_CMD_TIMER_UsingFixedFunction)
-    #define SCSI_CMD_TIMER_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT)) | \
-                                                  ((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT)))
-#else
-    #define SCSI_CMD_TIMER_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT)) | \
-                                                 ((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT)) | \
-                                                 ((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK_SHIFT)))
-#endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
-#define SCSI_CMD_TIMER_INIT_CAPTURE_COUNT      (2u)
-#define SCSI_CMD_TIMER_INIT_INT_CAPTURE_COUNT  ((uint8)((uint8)(1u - 1u) << SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT))
-
-
-/***************************************
-*           Registers
-***************************************/
-
-#if (SCSI_CMD_TIMER_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */
-
-
-    /***************************************
-    *    Fixed Function Registers
-    ***************************************/
-
-    #define SCSI_CMD_TIMER_STATUS         (*(reg8 *) SCSI_CMD_TIMER_TimerHW__SR0 )
-    /* In Fixed Function Block Status and Mask are the same register */
-    #define SCSI_CMD_TIMER_STATUS_MASK    (*(reg8 *) SCSI_CMD_TIMER_TimerHW__SR0 )
-    #define SCSI_CMD_TIMER_CONTROL        (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG0)
-    #define SCSI_CMD_TIMER_CONTROL2       (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG1)
-    #define SCSI_CMD_TIMER_CONTROL2_PTR   ( (reg8 *) SCSI_CMD_TIMER_TimerHW__CFG1)
-    #define SCSI_CMD_TIMER_RT1            (*(reg8 *) SCSI_CMD_TIMER_TimerHW__RT1)
-    #define SCSI_CMD_TIMER_RT1_PTR        ( (reg8 *) SCSI_CMD_TIMER_TimerHW__RT1)
-
-    #if (CY_PSOC3 || CY_PSOC5LP)
-        #define SCSI_CMD_TIMER_CONTROL3       (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG2)
-        #define SCSI_CMD_TIMER_CONTROL3_PTR   ( (reg8 *) SCSI_CMD_TIMER_TimerHW__CFG2)
-    #endif /* (CY_PSOC3 || CY_PSOC5LP) */
-    #define SCSI_CMD_TIMER_GLOBAL_ENABLE  (*(reg8 *) SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG)
-    #define SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE  (*(reg8 *) SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG)
-
-    #define SCSI_CMD_TIMER_CAPTURE_LSB         (* (reg16 *) SCSI_CMD_TIMER_TimerHW__CAP0 )
-    #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR       ((reg16 *) SCSI_CMD_TIMER_TimerHW__CAP0 )
-    #define SCSI_CMD_TIMER_PERIOD_LSB          (* (reg16 *) SCSI_CMD_TIMER_TimerHW__PER0 )
-    #define SCSI_CMD_TIMER_PERIOD_LSB_PTR        ((reg16 *) SCSI_CMD_TIMER_TimerHW__PER0 )
-    #define SCSI_CMD_TIMER_COUNTER_LSB         (* (reg16 *) SCSI_CMD_TIMER_TimerHW__CNT_CMP0 )
-    #define SCSI_CMD_TIMER_COUNTER_LSB_PTR       ((reg16 *) SCSI_CMD_TIMER_TimerHW__CNT_CMP0 )
-
-
-    /***************************************
-    *    Register Constants
-    ***************************************/
-
-    /* Fixed Function Block Chosen */
-    #define SCSI_CMD_TIMER_BLOCK_EN_MASK                     SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK
-    #define SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK                SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK
-
-    /* Control Register Bit Locations */
-    /* Interrupt Count - Not valid for Fixed Function Block */
-    #define SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT                  0x00u
-    /* Trigger Polarity - Not valid for Fixed Function Block */
-    #define SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT               0x00u
-    /* Trigger Enable - Not valid for Fixed Function Block */
-    #define SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT                 0x00u
-    /* Capture Polarity - Not valid for Fixed Function Block */
-    #define SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT                0x00u
-    /* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */
-    #define SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT                  0x00u
-
-    /* Control Register Bit Masks */
-    #define SCSI_CMD_TIMER_CTRL_ENABLE                        ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT))
-
-    /* Control2 Register Bit Masks */
-    /* As defined in Register Map, Part of the TMRX_CFG1 register */
-    #define SCSI_CMD_TIMER_CTRL2_IRQ_SEL_SHIFT                 0x00u
-    #define SCSI_CMD_TIMER_CTRL2_IRQ_SEL                      ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL2_IRQ_SEL_SHIFT))
-
-    #if (CY_PSOC5A)
-        /* Use CFG1 Mode bits to set run mode */
-        /* As defined by Verilog Implementation */
-        #define SCSI_CMD_TIMER_CTRL_MODE_SHIFT                     0x01u
-        #define SCSI_CMD_TIMER_CTRL_MODE_MASK                     ((uint8)((uint8)0x07u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT))
-    #endif /* (CY_PSOC5A) */
-    #if (CY_PSOC3 || CY_PSOC5LP)
-        /* Control3 Register Bit Locations */
-        #define SCSI_CMD_TIMER_CTRL_RCOD_SHIFT        0x02u
-        #define SCSI_CMD_TIMER_CTRL_ENBL_SHIFT        0x00u
-        #define SCSI_CMD_TIMER_CTRL_MODE_SHIFT        0x00u
-
-        /* Control3 Register Bit Masks */
-        #define SCSI_CMD_TIMER_CTRL_RCOD_MASK  ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */
-        #define SCSI_CMD_TIMER_CTRL_ENBL_MASK  ((uint8)((uint8)0x80u << SCSI_CMD_TIMER_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */
-        #define SCSI_CMD_TIMER_CTRL_MODE_MASK  ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) /* Run mode bit mask */
-
-        #define SCSI_CMD_TIMER_CTRL_RCOD       ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_RCOD_SHIFT))
-        #define SCSI_CMD_TIMER_CTRL_ENBL       ((uint8)((uint8)0x80u << SCSI_CMD_TIMER_CTRL_ENBL_SHIFT))
-    #endif /* (CY_PSOC3 || CY_PSOC5LP) */
-
-    /*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */
-    #define SCSI_CMD_TIMER_RT1_SHIFT                       0x04u
-    /* Sync TC and CMP bit masks */
-    #define SCSI_CMD_TIMER_RT1_MASK                        ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_RT1_SHIFT))
-    #define SCSI_CMD_TIMER_SYNC                            ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_RT1_SHIFT))
-    #define SCSI_CMD_TIMER_SYNCDSI_SHIFT                   0x00u
-    /* Sync all DSI inputs with Mask  */
-    #define SCSI_CMD_TIMER_SYNCDSI_MASK                    ((uint8)((uint8)0x0Fu << SCSI_CMD_TIMER_SYNCDSI_SHIFT))
-    /* Sync all DSI inputs */
-    #define SCSI_CMD_TIMER_SYNCDSI_EN                      ((uint8)((uint8)0x0Fu << SCSI_CMD_TIMER_SYNCDSI_SHIFT))
-
-    #define SCSI_CMD_TIMER_CTRL_MODE_PULSEWIDTH            ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT))
-    #define SCSI_CMD_TIMER_CTRL_MODE_PERIOD                ((uint8)((uint8)0x02u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT))
-    #define SCSI_CMD_TIMER_CTRL_MODE_CONTINUOUS            ((uint8)((uint8)0x00u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT))
-
-    /* Status Register Bit Locations */
-    /* As defined in Register Map, part of TMRX_SR0 register */
-    #define SCSI_CMD_TIMER_STATUS_TC_SHIFT                 0x07u
-    /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
-    #define SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT            0x06u
-    /* As defined in Register Map, part of TMRX_SR0 register */
-    #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT        (SCSI_CMD_TIMER_STATUS_TC_SHIFT - 0x04u)
-    /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
-    #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT   (SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT - 0x04u)
-
-    /* Status Register Bit Masks */
-    #define SCSI_CMD_TIMER_STATUS_TC                       ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT))
-    #define SCSI_CMD_TIMER_STATUS_CAPTURE                  ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT))
-    /* Interrupt Enable Bit-Mask for interrupt on TC */
-    #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK              ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT))
-    /* Interrupt Enable Bit-Mask for interrupt on Capture */
-    #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK         ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT))
-
-#else   /* UDB Registers and Register Constants */
-
-
-    /***************************************
-    *           UDB Registers
-    ***************************************/
-
-    #define SCSI_CMD_TIMER_STATUS              (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__STATUS_REG )
-    #define SCSI_CMD_TIMER_STATUS_MASK         (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__MASK_REG)
-    #define SCSI_CMD_TIMER_STATUS_AUX_CTRL     (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG)
-    #define SCSI_CMD_TIMER_CONTROL             (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG )
-    
-    #if(SCSI_CMD_TIMER_Resolution <= 8u) /* 8-bit Timer */
-        #define SCSI_CMD_TIMER_CAPTURE_LSB         (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
-        #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR       ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
-        #define SCSI_CMD_TIMER_PERIOD_LSB          (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
-        #define SCSI_CMD_TIMER_PERIOD_LSB_PTR        ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
-        #define SCSI_CMD_TIMER_COUNTER_LSB         (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
-        #define SCSI_CMD_TIMER_COUNTER_LSB_PTR       ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
-    #elif(SCSI_CMD_TIMER_Resolution <= 16u) /* 8-bit Timer */
-        #if(CY_PSOC3) /* 8-bit addres space */
-            #define SCSI_CMD_TIMER_CAPTURE_LSB         (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
-            #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR       ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
-            #define SCSI_CMD_TIMER_PERIOD_LSB          (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
-            #define SCSI_CMD_TIMER_PERIOD_LSB_PTR        ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
-            #define SCSI_CMD_TIMER_COUNTER_LSB         (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
-            #define SCSI_CMD_TIMER_COUNTER_LSB_PTR       ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
-        #else /* 16-bit address space */
-            #define SCSI_CMD_TIMER_CAPTURE_LSB         (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
-            #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR       ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
-            #define SCSI_CMD_TIMER_PERIOD_LSB          (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
-            #define SCSI_CMD_TIMER_PERIOD_LSB_PTR        ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
-            #define SCSI_CMD_TIMER_COUNTER_LSB         (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
-            #define SCSI_CMD_TIMER_COUNTER_LSB_PTR       ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
-        #endif /* CY_PSOC3 */
-    #elif(SCSI_CMD_TIMER_Resolution <= 24u)/* 24-bit Timer */
-        #define SCSI_CMD_TIMER_CAPTURE_LSB         (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
-        #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR       ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
-        #define SCSI_CMD_TIMER_PERIOD_LSB          (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
-        #define SCSI_CMD_TIMER_PERIOD_LSB_PTR        ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
-        #define SCSI_CMD_TIMER_COUNTER_LSB         (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
-        #define SCSI_CMD_TIMER_COUNTER_LSB_PTR       ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
-    #else /* 32-bit Timer */
-        #if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */
-            #define SCSI_CMD_TIMER_CAPTURE_LSB         (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
-            #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR       ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
-            #define SCSI_CMD_TIMER_PERIOD_LSB          (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
-            #define SCSI_CMD_TIMER_PERIOD_LSB_PTR        ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
-            #define SCSI_CMD_TIMER_COUNTER_LSB         (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
-            #define SCSI_CMD_TIMER_COUNTER_LSB_PTR       ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
-        #else /* 32-bit address space */
-            #define SCSI_CMD_TIMER_CAPTURE_LSB         (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
-            #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR       ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
-            #define SCSI_CMD_TIMER_PERIOD_LSB          (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
-            #define SCSI_CMD_TIMER_PERIOD_LSB_PTR        ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
-            #define SCSI_CMD_TIMER_COUNTER_LSB         (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
-            #define SCSI_CMD_TIMER_COUNTER_LSB_PTR       ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
-        #endif /* CY_PSOC3 || CY_PSOC5 */ 
-    #endif
-
-    #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
-        #define SCSI_CMD_TIMER_CAP_COUNT              (*(reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__PERIOD_REG )
-        #define SCSI_CMD_TIMER_CAP_COUNT_PTR          ( (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__PERIOD_REG )
-        #define SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL     (*(reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
-        #define SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
-    #endif /* (SCSI_CMD_TIMER_UsingHWCaptureCounter) */
-
-
-    /***************************************
-    *       Register Constants
-    ***************************************/
-
-    /* Control Register Bit Locations */
-    #define SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT              0x00u       /* As defined by Verilog Implementation */
-    #define SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT           0x02u       /* As defined by Verilog Implementation */
-    #define SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT             0x04u       /* As defined by Verilog Implementation */
-    #define SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT            0x05u       /* As defined by Verilog Implementation */
-    #define SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT              0x07u       /* As defined by Verilog Implementation */
-
-    /* Control Register Bit Masks */
-    #define SCSI_CMD_TIMER_CTRL_INTCNT_MASK               ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT))
-    #define SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK            ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT))
-    #define SCSI_CMD_TIMER_CTRL_TRIG_EN                   ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT))
-    #define SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK             ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT))
-    #define SCSI_CMD_TIMER_CTRL_ENABLE                    ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT))
-
-    /* Bit Counter (7-bit) Control Register Bit Definitions */
-    /* As defined by the Register map for the AUX Control Register */
-    #define SCSI_CMD_TIMER_CNTR_ENABLE                    0x20u
-
-    /* Status Register Bit Locations */
-    #define SCSI_CMD_TIMER_STATUS_TC_SHIFT                0x00u  /* As defined by Verilog Implementation */
-    #define SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT           0x01u  /* As defined by Verilog Implementation */
-    #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT       SCSI_CMD_TIMER_STATUS_TC_SHIFT
-    #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT  SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT
-    #define SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT          0x02u  /* As defined by Verilog Implementation */
-    #define SCSI_CMD_TIMER_STATUS_FIFONEMP_SHIFT          0x03u  /* As defined by Verilog Implementation */
-    #define SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT
-
-    /* Status Register Bit Masks */
-    /* Sticky TC Event Bit-Mask */
-    #define SCSI_CMD_TIMER_STATUS_TC                      ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT))
-    /* Sticky Capture Event Bit-Mask */
-    #define SCSI_CMD_TIMER_STATUS_CAPTURE                 ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT))
-    /* Interrupt Enable Bit-Mask */
-    #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK             ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT))
-    /* Interrupt Enable Bit-Mask */
-    #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK        ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT))
-    /* NOT-Sticky FIFO Full Bit-Mask */
-    #define SCSI_CMD_TIMER_STATUS_FIFOFULL                ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT))
-    /* NOT-Sticky FIFO Not Empty Bit-Mask */
-    #define SCSI_CMD_TIMER_STATUS_FIFONEMP                ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFONEMP_SHIFT))
-    /* Interrupt Enable Bit-Mask */
-    #define SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK       ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT))
-
-    #define SCSI_CMD_TIMER_STATUS_ACTL_INT_EN             0x10u   /* As defined for the ACTL Register */
-
-    /* Datapath Auxillary Control Register definitions */
-    #define SCSI_CMD_TIMER_AUX_CTRL_FIFO0_CLR             0x01u   /* As defined by Register map */
-    #define SCSI_CMD_TIMER_AUX_CTRL_FIFO1_CLR             0x02u   /* As defined by Register map */
-    #define SCSI_CMD_TIMER_AUX_CTRL_FIFO0_LVL             0x04u   /* As defined by Register map */
-    #define SCSI_CMD_TIMER_AUX_CTRL_FIFO1_LVL             0x08u   /* As defined by Register map */
-    #define SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK        0x10u   /* As defined for the ACTL Register */
-
-#endif /* Implementation Specific Registers and Register Constants */
-
-#endif  /* CY_Timer_v2_30_SCSI_CMD_TIMER_H */
-
-
-/* [] END OF FILE */
index 9a5677e..7d179bd 100755 (executable)
@@ -3,34 +3,6 @@
 #include <cydevice.h>\r
 #include <cydevice_trm.h>\r
 \r
-/* SCSI_CMD_TIMER_TimerHW */\r
-#define SCSI_CMD_TIMER_TimerHW__CAP0 CYREG_TMR0_CAP0\r
-#define SCSI_CMD_TIMER_TimerHW__CAP1 CYREG_TMR0_CAP1\r
-#define SCSI_CMD_TIMER_TimerHW__CFG0 CYREG_TMR0_CFG0\r
-#define SCSI_CMD_TIMER_TimerHW__CFG1 CYREG_TMR0_CFG1\r
-#define SCSI_CMD_TIMER_TimerHW__CFG2 CYREG_TMR0_CFG2\r
-#define SCSI_CMD_TIMER_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0\r
-#define SCSI_CMD_TIMER_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1\r
-#define SCSI_CMD_TIMER_TimerHW__PER0 CYREG_TMR0_PER0\r
-#define SCSI_CMD_TIMER_TimerHW__PER1 CYREG_TMR0_PER1\r
-#define SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3\r
-#define SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK 0x01u\r
-#define SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3\r
-#define SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK 0x01u\r
-#define SCSI_CMD_TIMER_TimerHW__RT0 CYREG_TMR0_RT0\r
-#define SCSI_CMD_TIMER_TimerHW__RT1 CYREG_TMR0_RT1\r
-#define SCSI_CMD_TIMER_TimerHW__SR0 CYREG_TMR0_SR0\r
-\r
-/* SCSI_CMD_TIMER_ISR */\r
-#define SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_CMD_TIMER_ISR__INTC_MASK 0x01u\r
-#define SCSI_CMD_TIMER_ISR__INTC_NUMBER 0u\r
-#define SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
-#define SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
 /* USBFS_bus_reset */\r
 #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
 #define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
 #define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK\r
 #define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_RxStsReg__4__POS 4\r
 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
 #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
 #define SDCard_BSPIM_RxStsReg__6__POS 6\r
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
 #define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
 #define SDCard_BSPIM_TxStsReg__1__POS 1\r
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_TxStsReg__4__POS 4\r
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0\r
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1\r
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0\r
 /* SCSI_CTL_IO */\r
 #define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
 #define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
 \r
 /* SCSI_In_DBx */\r
 #define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
 /* scsiTarget */\r
 #define scsiTarget_StatusReg__0__MASK 0x01u\r
 #define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST\r
 #define scsiTarget_StatusReg__1__MASK 0x02u\r
 #define scsiTarget_StatusReg__1__POS 1\r
 #define scsiTarget_StatusReg__2__MASK 0x04u\r
 #define scsiTarget_StatusReg__3__MASK 0x08u\r
 #define scsiTarget_StatusReg__3__POS 3\r
 #define scsiTarget_StatusReg__MASK 0x0Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB14_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB14_ST\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB13_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB13_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB13_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB13_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB13_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB13_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB13_MSK\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB13_14_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB13_14_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB13_14_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB13_14_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB13_14_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB13_14_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB13_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB13_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB13_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB13_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB13_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB13_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB13_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB13_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB13_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
 \r
 /* SD_Clk_Ctl */\r
 #define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
 #define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
 \r
 /* USBFS_ep_0 */\r
 #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 /* USBFS_ep_1 */\r
 #define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_1__INTC_MASK 0x02u\r
-#define USBFS_ep_1__INTC_NUMBER 1u\r
+#define USBFS_ep_1__INTC_MASK 0x01u\r
+#define USBFS_ep_1__INTC_NUMBER 0u\r
 #define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
 #define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 /* USBFS_ep_2 */\r
 #define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_2__INTC_MASK 0x04u\r
-#define USBFS_ep_2__INTC_NUMBER 2u\r
+#define USBFS_ep_2__INTC_MASK 0x02u\r
+#define USBFS_ep_2__INTC_NUMBER 1u\r
 #define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
 #define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 #define CYDEV_ECC_ENABLE 0\r
 #define CYDEV_HEAP_SIZE 0x1000\r
 #define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x00000001u\r
+#define CYDEV_INTR_RISING 0x00000000u\r
 #define CYDEV_PROJ_TYPE 2\r
 #define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
 #define CYDEV_PROJ_TYPE_LOADABLE 2\r
index 13e06dc..d3600d7 100755 (executable)
@@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode)
 }\r
 #endif\r
 \r
-#define CY_CFG_BASE_ADDR_COUNT 35u\r
+#define CY_CFG_BASE_ADDR_COUNT 33u\r
 CYPACKED typedef struct\r
 {\r
        uint8 offset;\r
@@ -363,38 +363,36 @@ void cyfitter_cfg(void)
        {\r
                static const uint32 CYCODE cy_cfg_addr_table[] = {\r
                        0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
-                       0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
                        0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
                        0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
-                       0x40010046u, /* Base address: 0x40010000 Count: 70 */\r
-                       0x40010136u, /* Base address: 0x40010100 Count: 54 */\r
-                       0x4001023Eu, /* Base address: 0x40010200 Count: 62 */\r
-                       0x4001035Bu, /* Base address: 0x40010300 Count: 91 */\r
-                       0x40010447u, /* Base address: 0x40010400 Count: 71 */\r
-                       0x40010546u, /* Base address: 0x40010500 Count: 70 */\r
-                       0x4001060Bu, /* Base address: 0x40010600 Count: 11 */\r
-                       0x4001074Au, /* Base address: 0x40010700 Count: 74 */\r
-                       0x40010906u, /* Base address: 0x40010900 Count: 6 */\r
-                       0x40010A04u, /* Base address: 0x40010A00 Count: 4 */\r
-                       0x40010B10u, /* Base address: 0x40010B00 Count: 16 */\r
-                       0x40010C36u, /* Base address: 0x40010C00 Count: 54 */\r
-                       0x40010D36u, /* Base address: 0x40010D00 Count: 54 */\r
-                       0x40010F04u, /* Base address: 0x40010F00 Count: 4 */\r
+                       0x40010101u, /* Base address: 0x40010100 Count: 1 */\r
+                       0x40010308u, /* Base address: 0x40010300 Count: 8 */\r
+                       0x40010442u, /* Base address: 0x40010400 Count: 66 */\r
+                       0x4001053Cu, /* Base address: 0x40010500 Count: 60 */\r
+                       0x40010604u, /* Base address: 0x40010600 Count: 4 */\r
+                       0x40010747u, /* Base address: 0x40010700 Count: 71 */\r
+                       0x40010908u, /* Base address: 0x40010900 Count: 8 */\r
+                       0x40010A44u, /* Base address: 0x40010A00 Count: 68 */\r
+                       0x40010B40u, /* Base address: 0x40010B00 Count: 64 */\r
+                       0x40010C35u, /* Base address: 0x40010C00 Count: 53 */\r
+                       0x40010D49u, /* Base address: 0x40010D00 Count: 73 */\r
+                       0x40010E43u, /* Base address: 0x40010E00 Count: 67 */\r
+                       0x40010F2Fu, /* Base address: 0x40010F00 Count: 47 */\r
                        0x40011504u, /* Base address: 0x40011500 Count: 4 */\r
-                       0x4001164Bu, /* Base address: 0x40011600 Count: 75 */\r
-                       0x40011749u, /* Base address: 0x40011700 Count: 73 */\r
-                       0x40011902u, /* Base address: 0x40011900 Count: 2 */\r
-                       0x4001400Du, /* Base address: 0x40014000 Count: 13 */\r
-                       0x4001410Eu, /* Base address: 0x40014100 Count: 14 */\r
-                       0x4001420Cu, /* Base address: 0x40014200 Count: 12 */\r
-                       0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
-                       0x40014410u, /* Base address: 0x40014400 Count: 16 */\r
-                       0x40014515u, /* Base address: 0x40014500 Count: 21 */\r
-                       0x40014603u, /* Base address: 0x40014600 Count: 3 */\r
-                       0x40014703u, /* Base address: 0x40014700 Count: 3 */\r
-                       0x4001480Eu, /* Base address: 0x40014800 Count: 14 */\r
-                       0x4001490Au, /* Base address: 0x40014900 Count: 10 */\r
-                       0x40014C02u, /* Base address: 0x40014C00 Count: 2 */\r
+                       0x40011648u, /* Base address: 0x40011600 Count: 72 */\r
+                       0x40011740u, /* Base address: 0x40011700 Count: 64 */\r
+                       0x40011904u, /* Base address: 0x40011900 Count: 4 */\r
+                       0x4001400Bu, /* Base address: 0x40014000 Count: 11 */\r
+                       0x4001410Fu, /* Base address: 0x40014100 Count: 15 */\r
+                       0x40014207u, /* Base address: 0x40014200 Count: 7 */\r
+                       0x40014303u, /* Base address: 0x40014300 Count: 3 */\r
+                       0x4001440Cu, /* Base address: 0x40014400 Count: 12 */\r
+                       0x40014516u, /* Base address: 0x40014500 Count: 22 */\r
+                       0x40014608u, /* Base address: 0x40014600 Count: 8 */\r
+                       0x40014708u, /* Base address: 0x40014700 Count: 8 */\r
+                       0x4001480Au, /* Base address: 0x40014800 Count: 10 */\r
+                       0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
+                       0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
                        0x40015006u, /* Base address: 0x40015000 Count: 6 */\r
                        0x40015101u, /* Base address: 0x40015100 Count: 1 */\r
                };\r
@@ -402,188 +400,403 @@ void cyfitter_cfg(void)
                static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
                        {0x36u, 0x02u},\r
                        {0x7Eu, 0x02u},\r
-                       {0x01u, 0x80u},\r
-                       {0x0Au, 0x4Bu},\r
-                       {0x00u, 0x02u},\r
+                       {0x00u, 0x01u},\r
                        {0x01u, 0x03u},\r
-                       {0x18u, 0x08u},\r
+                       {0x18u, 0x04u},\r
                        {0x19u, 0x0Cu},\r
                        {0x1Cu, 0x61u},\r
-                       {0x20u, 0xC0u},\r
-                       {0x21u, 0x90u},\r
-                       {0x30u, 0x0Au},\r
-                       {0x31u, 0x09u},\r
+                       {0x20u, 0x98u},\r
+                       {0x21u, 0x38u},\r
+                       {0x30u, 0x03u},\r
+                       {0x31u, 0x05u},\r
                        {0x7Cu, 0x40u},\r
-                       {0x33u, 0x03u},\r
+                       {0x3Du, 0x03u},\r
                        {0x86u, 0x0Fu},\r
-                       {0x03u, 0x04u},\r
-                       {0x06u, 0x10u},\r
-                       {0x07u, 0x44u},\r
-                       {0x0Bu, 0x40u},\r
-                       {0x0Du, 0x44u},\r
-                       {0x0Eu, 0x0Cu},\r
-                       {0x0Fu, 0x22u},\r
-                       {0x12u, 0x01u},\r
+                       {0xE2u, 0x80u},\r
+                       {0x81u, 0x40u},\r
+                       {0x85u, 0x04u},\r
+                       {0xA0u, 0x04u},\r
+                       {0xACu, 0x04u},\r
+                       {0xE2u, 0x08u},\r
+                       {0xE6u, 0x25u},\r
+                       {0xEAu, 0x01u},\r
+                       {0xEEu, 0x02u},\r
+                       {0x07u, 0x04u},\r
+                       {0x0Bu, 0x04u},\r
+                       {0x0Du, 0x04u},\r
+                       {0x0Fu, 0x02u},\r
                        {0x13u, 0x03u},\r
-                       {0x16u, 0x10u},\r
-                       {0x18u, 0x10u},\r
-                       {0x1Au, 0x04u},\r
-                       {0x1Cu, 0x01u},\r
-                       {0x1Eu, 0x02u},\r
-                       {0x1Fu, 0x30u},\r
-                       {0x21u, 0x08u},\r
-                       {0x22u, 0x02u},\r
-                       {0x24u, 0x20u},\r
-                       {0x29u, 0x44u},\r
-                       {0x2Bu, 0x11u},\r
-                       {0x2Cu, 0x10u},\r
-                       {0x2Eu, 0x08u},\r
-                       {0x30u, 0x1Cu},\r
+                       {0x19u, 0x04u},\r
+                       {0x1Bu, 0x01u},\r
                        {0x31u, 0x07u},\r
-                       {0x32u, 0x03u},\r
-                       {0x33u, 0x08u},\r
-                       {0x36u, 0x20u},\r
-                       {0x37u, 0x70u},\r
-                       {0x3Eu, 0x44u},\r
-                       {0x3Fu, 0x04u},\r
                        {0x56u, 0x08u},\r
+                       {0x59u, 0x04u},\r
+                       {0x5Bu, 0x04u},\r
+                       {0x5Cu, 0x90u},\r
+                       {0x5Du, 0x90u},\r
+                       {0x5Fu, 0x01u},\r
+                       {0x80u, 0xD6u},\r
+                       {0x81u, 0x2Cu},\r
+                       {0x84u, 0x17u},\r
+                       {0x86u, 0x28u},\r
+                       {0x88u, 0xD2u},\r
+                       {0x89u, 0x31u},\r
+                       {0x8Au, 0x04u},\r
+                       {0x8Bu, 0x42u},\r
+                       {0x8Cu, 0xD6u},\r
+                       {0x8Du, 0x2Cu},\r
+                       {0x91u, 0xC0u},\r
+                       {0x94u, 0x29u},\r
+                       {0x96u, 0x46u},\r
+                       {0x97u, 0x2Cu},\r
+                       {0x98u, 0x20u},\r
+                       {0x99u, 0x40u},\r
+                       {0x9Au, 0xD0u},\r
+                       {0x9Bu, 0x2Fu},\r
+                       {0x9Cu, 0x04u},\r
+                       {0x9Du, 0x24u},\r
+                       {0xA0u, 0xD6u},\r
+                       {0xA1u, 0x08u},\r
+                       {0xA3u, 0x10u},\r
+                       {0xA4u, 0xD0u},\r
+                       {0xA5u, 0x24u},\r
+                       {0xA6u, 0x06u},\r
+                       {0xA7u, 0x08u},\r
+                       {0xA8u, 0x21u},\r
+                       {0xA9u, 0x11u},\r
+                       {0xAAu, 0x8Eu},\r
+                       {0xABu, 0x8Eu},\r
+                       {0xACu, 0x02u},\r
+                       {0xADu, 0x2Cu},\r
+                       {0xB0u, 0x01u},\r
+                       {0xB1u, 0xC1u},\r
+                       {0xB2u, 0x0Fu},\r
+                       {0xB3u, 0x31u},\r
+                       {0xB4u, 0xF0u},\r
+                       {0xB5u, 0x0Fu},\r
+                       {0xB6u, 0x08u},\r
+                       {0xB8u, 0x08u},\r
+                       {0xB9u, 0x02u},\r
+                       {0xBAu, 0x20u},\r
+                       {0xBBu, 0x0Cu},\r
+                       {0xBEu, 0x41u},\r
+                       {0xD4u, 0x09u},\r
+                       {0xD8u, 0x0Bu},\r
+                       {0xD9u, 0x0Bu},\r
+                       {0xDBu, 0x0Bu},\r
+                       {0xDCu, 0x99u},\r
+                       {0xDDu, 0x90u},\r
+                       {0xDFu, 0x01u},\r
+                       {0x04u, 0x29u},\r
+                       {0x06u, 0x02u},\r
+                       {0x0Eu, 0x28u},\r
+                       {0x0Fu, 0x02u},\r
+                       {0x17u, 0x65u},\r
+                       {0x1Cu, 0x10u},\r
+                       {0x1Du, 0x48u},\r
+                       {0x1Eu, 0x28u},\r
+                       {0x1Fu, 0x09u},\r
+                       {0x21u, 0x02u},\r
+                       {0x23u, 0x40u},\r
+                       {0x24u, 0x08u},\r
+                       {0x25u, 0x10u},\r
+                       {0x26u, 0x02u},\r
+                       {0x27u, 0x38u},\r
+                       {0x29u, 0xC0u},\r
+                       {0x2Du, 0x02u},\r
+                       {0x2Fu, 0x2Au},\r
+                       {0x31u, 0x02u},\r
+                       {0x32u, 0x10u},\r
+                       {0x34u, 0x01u},\r
+                       {0x36u, 0x02u},\r
+                       {0x37u, 0x54u},\r
+                       {0x39u, 0x48u},\r
+                       {0x3Au, 0x10u},\r
+                       {0x3Cu, 0x81u},\r
+                       {0x3Du, 0x20u},\r
+                       {0x3Eu, 0x01u},\r
+                       {0x58u, 0x80u},\r
+                       {0x5Du, 0x98u},\r
+                       {0x5Eu, 0x02u},\r
+                       {0x60u, 0x02u},\r
+                       {0x62u, 0x80u},\r
+                       {0x65u, 0x08u},\r
+                       {0x66u, 0x04u},\r
+                       {0x67u, 0x02u},\r
+                       {0x7Eu, 0x80u},\r
+                       {0x89u, 0x02u},\r
+                       {0x8Cu, 0x20u},\r
+                       {0x91u, 0x48u},\r
+                       {0x92u, 0x20u},\r
+                       {0x9Au, 0x10u},\r
+                       {0xA0u, 0x04u},\r
+                       {0xA4u, 0x10u},\r
+                       {0xAEu, 0x10u},\r
+                       {0xB0u, 0x10u},\r
+                       {0xB6u, 0x10u},\r
+                       {0xC0u, 0xF0u},\r
+                       {0xC2u, 0xE0u},\r
+                       {0xC4u, 0xF0u},\r
+                       {0xCAu, 0xF0u},\r
+                       {0xCCu, 0xF5u},\r
+                       {0xCEu, 0xBEu},\r
+                       {0xD6u, 0xF8u},\r
+                       {0xD8u, 0x18u},\r
+                       {0xDEu, 0x80u},\r
+                       {0xE2u, 0x40u},\r
+                       {0xE6u, 0x20u},\r
+                       {0xEAu, 0x02u},\r
+                       {0xEEu, 0x08u},\r
+                       {0xD4u, 0x40u},\r
+                       {0xDBu, 0x0Bu},\r
+                       {0xDDu, 0x90u},\r
+                       {0xDFu, 0x01u},\r
+                       {0x04u, 0x20u},\r
+                       {0x06u, 0x02u},\r
+                       {0x07u, 0x60u},\r
+                       {0x0Eu, 0xA1u},\r
+                       {0x0Fu, 0x04u},\r
+                       {0x15u, 0x14u},\r
+                       {0x17u, 0x09u},\r
+                       {0x1Fu, 0x08u},\r
+                       {0x25u, 0x40u},\r
+                       {0x26u, 0x40u},\r
+                       {0x27u, 0x80u},\r
+                       {0x2Cu, 0x80u},\r
+                       {0x2Fu, 0x2Au},\r
+                       {0x36u, 0x02u},\r
+                       {0x37u, 0xA8u},\r
+                       {0x3Cu, 0x10u},\r
+                       {0x3Du, 0x80u},\r
+                       {0x3Eu, 0x01u},\r
+                       {0x3Fu, 0x04u},\r
+                       {0x45u, 0x88u},\r
+                       {0x46u, 0x40u},\r
+                       {0x47u, 0x20u},\r
+                       {0x4Cu, 0x04u},\r
+                       {0x4Du, 0x0Au},\r
+                       {0x4Fu, 0x06u},\r
+                       {0x55u, 0x20u},\r
+                       {0x56u, 0x84u},\r
+                       {0x61u, 0x20u},\r
+                       {0x62u, 0x08u},\r
+                       {0x63u, 0x01u},\r
+                       {0x65u, 0x80u},\r
+                       {0x6Cu, 0x10u},\r
+                       {0x6Du, 0x11u},\r
+                       {0x6Eu, 0x09u},\r
+                       {0x6Fu, 0x27u},\r
+                       {0x74u, 0xC0u},\r
+                       {0x76u, 0x02u},\r
+                       {0x78u, 0x02u},\r
+                       {0x7Eu, 0x80u},\r
+                       {0x81u, 0x48u},\r
+                       {0x90u, 0x18u},\r
+                       {0x92u, 0x80u},\r
+                       {0x93u, 0x40u},\r
+                       {0x94u, 0x20u},\r
+                       {0x96u, 0x01u},\r
+                       {0x98u, 0x23u},\r
+                       {0x9Bu, 0x38u},\r
+                       {0x9Du, 0x02u},\r
+                       {0x9Eu, 0x06u},\r
+                       {0x9Fu, 0x45u},\r
+                       {0xA0u, 0x04u},\r
+                       {0xA1u, 0x08u},\r
+                       {0xA2u, 0x90u},\r
+                       {0xA4u, 0x50u},\r
+                       {0xA6u, 0x01u},\r
+                       {0xA7u, 0x23u},\r
+                       {0xAAu, 0x40u},\r
+                       {0xACu, 0x80u},\r
+                       {0xB1u, 0x12u},\r
+                       {0xC0u, 0xF0u},\r
+                       {0xC2u, 0xF0u},\r
+                       {0xC4u, 0x70u},\r
+                       {0xCAu, 0xF0u},\r
+                       {0xCCu, 0xF0u},\r
+                       {0xCEu, 0xF0u},\r
+                       {0xD0u, 0xF0u},\r
+                       {0xD2u, 0x20u},\r
+                       {0xD8u, 0x1Eu},\r
+                       {0xDEu, 0x81u},\r
+                       {0xE8u, 0x40u},\r
+                       {0xEEu, 0x03u},\r
+                       {0x9Cu, 0x04u},\r
+                       {0xA7u, 0x40u},\r
+                       {0xAEu, 0x11u},\r
+                       {0xB0u, 0x80u},\r
+                       {0xB6u, 0x10u},\r
+                       {0xE8u, 0x40u},\r
+                       {0xEAu, 0x02u},\r
+                       {0xEEu, 0x01u},\r
+                       {0x04u, 0x24u},\r
+                       {0x06u, 0x12u},\r
+                       {0x07u, 0x03u},\r
+                       {0x0Au, 0x24u},\r
+                       {0x0Bu, 0x04u},\r
+                       {0x0Eu, 0x03u},\r
+                       {0x10u, 0x40u},\r
+                       {0x12u, 0x80u},\r
+                       {0x13u, 0x20u},\r
+                       {0x16u, 0x80u},\r
+                       {0x1Au, 0x18u},\r
+                       {0x1Bu, 0x24u},\r
+                       {0x1Fu, 0x18u},\r
+                       {0x21u, 0x40u},\r
+                       {0x22u, 0x20u},\r
+                       {0x25u, 0x24u},\r
+                       {0x26u, 0x04u},\r
+                       {0x27u, 0x12u},\r
+                       {0x29u, 0x80u},\r
+                       {0x2Au, 0x40u},\r
+                       {0x2Cu, 0x24u},\r
+                       {0x2Du, 0x24u},\r
+                       {0x2Eu, 0x09u},\r
+                       {0x2Fu, 0x09u},\r
+                       {0x30u, 0x07u},\r
+                       {0x31u, 0x80u},\r
+                       {0x33u, 0x40u},\r
+                       {0x34u, 0x38u},\r
+                       {0x35u, 0x07u},\r
+                       {0x36u, 0xC0u},\r
+                       {0x37u, 0x38u},\r
+                       {0x3Eu, 0x40u},\r
+                       {0x3Fu, 0x05u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
                        {0x5Cu, 0x99u},\r
-                       {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x81u, 0x33u},\r
-                       {0x82u, 0x02u},\r
-                       {0x83u, 0xCCu},\r
-                       {0x85u, 0x55u},\r
-                       {0x86u, 0x20u},\r
-                       {0x87u, 0xAAu},\r
-                       {0x88u, 0x20u},\r
-                       {0x89u, 0x96u},\r
-                       {0x8Au, 0x08u},\r
-                       {0x8Bu, 0x69u},\r
-                       {0x8Fu, 0xFFu},\r
-                       {0x90u, 0x20u},\r
-                       {0x92u, 0x10u},\r
+                       {0x85u, 0x33u},\r
+                       {0x86u, 0xFFu},\r
+                       {0x87u, 0xCCu},\r
+                       {0x89u, 0xFFu},\r
+                       {0x8Du, 0x0Fu},\r
+                       {0x8Eu, 0xFFu},\r
+                       {0x8Fu, 0xF0u},\r
+                       {0x90u, 0x96u},\r
+                       {0x92u, 0x69u},\r
                        {0x93u, 0xFFu},\r
-                       {0x95u, 0xFFu},\r
-                       {0x96u, 0x20u},\r
-                       {0x9Au, 0x18u},\r
-                       {0x9Eu, 0x07u},\r
-                       {0xA0u, 0x07u},\r
-                       {0xA4u, 0x01u},\r
-                       {0xA5u, 0x0Fu},\r
-                       {0xA7u, 0xF0u},\r
-                       {0xA8u, 0x04u},\r
-                       {0xB2u, 0x07u},\r
-                       {0xB4u, 0x38u},\r
-                       {0xB7u, 0xFFu},\r
+                       {0x94u, 0xFFu},\r
+                       {0x98u, 0x33u},\r
+                       {0x9Au, 0xCCu},\r
+                       {0x9Du, 0x96u},\r
+                       {0x9Fu, 0x69u},\r
+                       {0xA0u, 0x55u},\r
+                       {0xA1u, 0x55u},\r
+                       {0xA2u, 0xAAu},\r
+                       {0xA3u, 0xAAu},\r
+                       {0xA7u, 0xFFu},\r
+                       {0xACu, 0x0Fu},\r
+                       {0xAEu, 0xF0u},\r
+                       {0xB2u, 0xFFu},\r
+                       {0xB3u, 0xFFu},\r
                        {0xBEu, 0x04u},\r
-                       {0xBFu, 0x40u},\r
+                       {0xBFu, 0x04u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
-                       {0xDCu, 0x09u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x40u},\r
-                       {0x03u, 0x10u},\r
-                       {0x05u, 0x10u},\r
-                       {0x06u, 0x80u},\r
-                       {0x07u, 0x20u},\r
-                       {0x09u, 0x08u},\r
-                       {0x0Au, 0x04u},\r
-                       {0x0Bu, 0x82u},\r
-                       {0x0Du, 0x24u},\r
-                       {0x0Eu, 0x01u},\r
-                       {0x0Fu, 0x40u},\r
-                       {0x10u, 0x40u},\r
-                       {0x13u, 0x48u},\r
-                       {0x14u, 0x90u},\r
-                       {0x16u, 0x04u},\r
+                       {0x00u, 0x50u},\r
+                       {0x03u, 0x20u},\r
+                       {0x05u, 0x04u},\r
+                       {0x06u, 0x20u},\r
+                       {0x07u, 0x01u},\r
+                       {0x0Au, 0x64u},\r
+                       {0x0Eu, 0x80u},\r
+                       {0x0Fu, 0xA4u},\r
+                       {0x10u, 0xA5u},\r
+                       {0x13u, 0x40u},\r
+                       {0x14u, 0x40u},\r
+                       {0x15u, 0x40u},\r
                        {0x18u, 0x40u},\r
-                       {0x19u, 0x84u},\r
-                       {0x1Du, 0x20u},\r
-                       {0x1Fu, 0x14u},\r
-                       {0x20u, 0x02u},\r
-                       {0x21u, 0xC0u},\r
-                       {0x22u, 0x03u},\r
-                       {0x23u, 0x10u},\r
-                       {0x25u, 0x40u},\r
-                       {0x29u, 0x10u},\r
-                       {0x2Au, 0x01u},\r
-                       {0x2Fu, 0x20u},\r
-                       {0x31u, 0x80u},\r
-                       {0x32u, 0x01u},\r
-                       {0x36u, 0x06u},\r
-                       {0x39u, 0x18u},\r
-                       {0x3Au, 0x02u},\r
-                       {0x3Bu, 0x40u},\r
-                       {0x3Cu, 0x02u},\r
-                       {0x3Du, 0x60u},\r
-                       {0x3Fu, 0x0Cu},\r
-                       {0x5Bu, 0x40u},\r
-                       {0x60u, 0x02u},\r
-                       {0x6Du, 0x40u},\r
-                       {0x80u, 0x40u},\r
-                       {0x81u, 0x80u},\r
-                       {0x83u, 0x20u},\r
-                       {0x86u, 0x01u},\r
-                       {0x8Bu, 0x08u},\r
-                       {0x8Eu, 0x01u},\r
-                       {0xC0u, 0x75u},\r
-                       {0xC2u, 0xFFu},\r
-                       {0xC4u, 0x7Du},\r
-                       {0xCAu, 0x45u},\r
-                       {0xCCu, 0xC9u},\r
-                       {0xCEu, 0xFFu},\r
-                       {0xD6u, 0x08u},\r
-                       {0xD8u, 0x08u},\r
-                       {0xE4u, 0x05u},\r
-                       {0x01u, 0x03u},\r
-                       {0x03u, 0x0Cu},\r
-                       {0x25u, 0x05u},\r
-                       {0x27u, 0x0Au},\r
-                       {0x29u, 0x06u},\r
-                       {0x2Bu, 0x09u},\r
-                       {0x35u, 0x0Fu},\r
-                       {0x3Fu, 0x10u},\r
-                       {0x59u, 0x04u},\r
-                       {0x5Fu, 0x01u},\r
-                       {0x85u, 0x10u},\r
-                       {0x87u, 0x2Du},\r
+                       {0x1Au, 0x06u},\r
+                       {0x1Bu, 0x10u},\r
+                       {0x1Fu, 0x04u},\r
+                       {0x22u, 0x46u},\r
+                       {0x23u, 0x04u},\r
+                       {0x25u, 0x08u},\r
+                       {0x28u, 0x81u},\r
+                       {0x2Au, 0x10u},\r
+                       {0x2Bu, 0x20u},\r
+                       {0x2Cu, 0x40u},\r
+                       {0x2Eu, 0x04u},\r
+                       {0x30u, 0x42u},\r
+                       {0x31u, 0x20u},\r
+                       {0x32u, 0x40u},\r
+                       {0x36u, 0x40u},\r
+                       {0x37u, 0x01u},\r
+                       {0x39u, 0x10u},\r
+                       {0x3Bu, 0x04u},\r
+                       {0x3Du, 0x40u},\r
+                       {0x3Eu, 0x20u},\r
+                       {0x3Fu, 0x04u},\r
+                       {0x6Au, 0x40u},\r
+                       {0x6Fu, 0x01u},\r
+                       {0x8Cu, 0x40u},\r
+                       {0x90u, 0x10u},\r
+                       {0x91u, 0x50u},\r
+                       {0x93u, 0x40u},\r
+                       {0x96u, 0x08u},\r
+                       {0x97u, 0x0Cu},\r
+                       {0x99u, 0x04u},\r
+                       {0x9Cu, 0x40u},\r
+                       {0x9Fu, 0x01u},\r
+                       {0xA0u, 0xA2u},\r
+                       {0xA1u, 0x20u},\r
+                       {0xA3u, 0x20u},\r
+                       {0xA5u, 0x08u},\r
+                       {0xA6u, 0x02u},\r
+                       {0xA7u, 0x50u},\r
+                       {0xADu, 0x50u},\r
+                       {0xB2u, 0xC0u},\r
+                       {0xB3u, 0x08u},\r
+                       {0xB4u, 0x42u},\r
+                       {0xC0u, 0xA7u},\r
+                       {0xC2u, 0x7Eu},\r
+                       {0xC4u, 0x9Fu},\r
+                       {0xCAu, 0xCFu},\r
+                       {0xCCu, 0x9Du},\r
+                       {0xCEu, 0x76u},\r
+                       {0xE2u, 0x40u},\r
+                       {0xEAu, 0x40u},\r
+                       {0xECu, 0x80u},\r
+                       {0x80u, 0x10u},\r
+                       {0x84u, 0x0Eu},\r
                        {0x89u, 0x01u},\r
-                       {0x8Bu, 0x02u},\r
-                       {0x8Cu, 0x01u},\r
-                       {0x8Du, 0x67u},\r
-                       {0x8Fu, 0x18u},\r
-                       {0x90u, 0x04u},\r
-                       {0x92u, 0x03u},\r
-                       {0x96u, 0x12u},\r
-                       {0x98u, 0x03u},\r
-                       {0x9Au, 0x14u},\r
-                       {0x9Fu, 0x40u},\r
-                       {0xA1u, 0x02u},\r
-                       {0xA4u, 0x08u},\r
-                       {0xA5u, 0x02u},\r
-                       {0xA9u, 0x16u},\r
-                       {0xAAu, 0x07u},\r
-                       {0xABu, 0x48u},\r
-                       {0xAFu, 0x77u},\r
-                       {0xB0u, 0x08u},\r
-                       {0xB1u, 0x07u},\r
-                       {0xB3u, 0x70u},\r
-                       {0xB4u, 0x07u},\r
-                       {0xB5u, 0x08u},\r
-                       {0xB6u, 0x10u},\r
+                       {0x8Au, 0x0Eu},\r
+                       {0x8Bu, 0x92u},\r
+                       {0x8Cu, 0x04u},\r
+                       {0x8Du, 0x19u},\r
+                       {0x8Fu, 0xA4u},\r
+                       {0x90u, 0x0Cu},\r
+                       {0x91u, 0x08u},\r
+                       {0x92u, 0x01u},\r
+                       {0x94u, 0x02u},\r
+                       {0x96u, 0x04u},\r
+                       {0x97u, 0x3Fu},\r
+                       {0x9Au, 0x0Bu},\r
+                       {0xA4u, 0x04u},\r
+                       {0xA7u, 0x04u},\r
+                       {0xA9u, 0x26u},\r
+                       {0xABu, 0x99u},\r
+                       {0xADu, 0x40u},\r
+                       {0xB0u, 0x10u},\r
+                       {0xB1u, 0x38u},\r
+                       {0xB3u, 0x40u},\r
+                       {0xB4u, 0x0Eu},\r
+                       {0xB5u, 0x07u},\r
+                       {0xB6u, 0x01u},\r
+                       {0xB7u, 0x80u},\r
                        {0xBEu, 0x41u},\r
-                       {0xBFu, 0x10u},\r
-                       {0xC0u, 0x34u},\r
-                       {0xC1u, 0x02u},\r
-                       {0xC2u, 0x60u},\r
-                       {0xC5u, 0xCDu},\r
-                       {0xC6u, 0xF2u},\r
-                       {0xC7u, 0x0Eu},\r
+                       {0xBFu, 0x44u},\r
+                       {0xC0u, 0x26u},\r
+                       {0xC1u, 0x04u},\r
+                       {0xC2u, 0x50u},\r
+                       {0xC5u, 0xD2u},\r
+                       {0xC6u, 0xCEu},\r
+                       {0xC7u, 0x0Fu},\r
                        {0xC8u, 0x1Fu},\r
                        {0xC9u, 0xFFu},\r
                        {0xCAu, 0xFFu},\r
@@ -602,743 +815,452 @@ void cyfitter_cfg(void)
                        {0xE8u, 0x40u},\r
                        {0xE9u, 0x40u},\r
                        {0xEEu, 0x08u},\r
-                       {0x01u, 0x40u},\r
-                       {0x03u, 0x01u},\r
-                       {0x09u, 0x08u},\r
-                       {0x0Au, 0x04u},\r
-                       {0x0Bu, 0x40u},\r
-                       {0x12u, 0x08u},\r
+                       {0x00u, 0x80u},\r
+                       {0x02u, 0x80u},\r
+                       {0x03u, 0x28u},\r
+                       {0x04u, 0x08u},\r
+                       {0x07u, 0x10u},\r
+                       {0x09u, 0x20u},\r
+                       {0x0Bu, 0x60u},\r
+                       {0x12u, 0x10u},\r
                        {0x13u, 0x08u},\r
-                       {0x18u, 0x40u},\r
-                       {0x19u, 0x10u},\r
-                       {0x1Au, 0x0Cu},\r
-                       {0x1Bu, 0x40u},\r
-                       {0x20u, 0x28u},\r
-                       {0x21u, 0x0Du},\r
+                       {0x19u, 0x52u},\r
+                       {0x1Bu, 0x20u},\r
+                       {0x20u, 0x42u},\r
+                       {0x21u, 0x31u},\r
+                       {0x22u, 0x08u},\r
                        {0x23u, 0x40u},\r
-                       {0x24u, 0x08u},\r
-                       {0x25u, 0x10u},\r
-                       {0x27u, 0x04u},\r
-                       {0x29u, 0x1Au},\r
-                       {0x2Bu, 0x02u},\r
-                       {0x2Du, 0x20u},\r
-                       {0x2Fu, 0x10u},\r
-                       {0x33u, 0x80u},\r
-                       {0x38u, 0x20u},\r
-                       {0x39u, 0x08u},\r
-                       {0x3Bu, 0x40u},\r
-                       {0x3Fu, 0x01u},\r
-                       {0x41u, 0x05u},\r
-                       {0x42u, 0x04u},\r
-                       {0x48u, 0x84u},\r
-                       {0x49u, 0x0Au},\r
-                       {0x50u, 0x08u},\r
-                       {0x52u, 0x20u},\r
+                       {0x28u, 0x02u},\r
+                       {0x29u, 0x18u},\r
+                       {0x33u, 0x09u},\r
+                       {0x38u, 0x50u},\r
+                       {0x39u, 0x20u},\r
+                       {0x40u, 0x40u},\r
+                       {0x41u, 0x10u},\r
+                       {0x48u, 0x41u},\r
+                       {0x49u, 0x19u},\r
+                       {0x50u, 0x04u},\r
+                       {0x52u, 0x10u},\r
                        {0x53u, 0x80u},\r
-                       {0x58u, 0x24u},\r
-                       {0x59u, 0x80u},\r
-                       {0x5Bu, 0x02u},\r
-                       {0x60u, 0x48u},\r
-                       {0x61u, 0x80u},\r
-                       {0x63u, 0x10u},\r
-                       {0x68u, 0x02u},\r
-                       {0x69u, 0x10u},\r
-                       {0x6Bu, 0x50u},\r
-                       {0x71u, 0x01u},\r
-                       {0x72u, 0x02u},\r
-                       {0x73u, 0x24u},\r
-                       {0x80u, 0x06u},\r
-                       {0x81u, 0x40u},\r
-                       {0x83u, 0x01u},\r
-                       {0x85u, 0x09u},\r
-                       {0x86u, 0x04u},\r
-                       {0x87u, 0x08u},\r
-                       {0x89u, 0x04u},\r
-                       {0x8Au, 0x01u},\r
-                       {0x8Eu, 0x28u},\r
-                       {0x8Fu, 0x02u},\r
-                       {0x90u, 0x20u},\r
-                       {0x91u, 0xC0u},\r
-                       {0x92u, 0x02u},\r
-                       {0x93u, 0x38u},\r
-                       {0x95u, 0x18u},\r
-                       {0x96u, 0x05u},\r
-                       {0x97u, 0xC0u},\r
-                       {0x98u, 0x02u},\r
-                       {0x99u, 0x80u},\r
-                       {0x9Cu, 0xD0u},\r
-                       {0x9Du, 0x10u},\r
-                       {0x9Eu, 0x86u},\r
-                       {0x9Fu, 0x30u},\r
-                       {0xA1u, 0x40u},\r
-                       {0xA3u, 0x24u},\r
-                       {0xA5u, 0x18u},\r
-                       {0xA6u, 0x04u},\r
-                       {0xA8u, 0x10u},\r
-                       {0xB3u, 0x04u},\r
-                       {0xB5u, 0x24u},\r
-                       {0xB7u, 0x41u},\r
-                       {0xC0u, 0x01u},\r
+                       {0x59u, 0x02u},\r
+                       {0x5Au, 0xA8u},\r
+                       {0x60u, 0x04u},\r
+                       {0x62u, 0x4Au},\r
+                       {0x68u, 0x82u},\r
+                       {0x69u, 0x14u},\r
+                       {0x70u, 0x20u},\r
+                       {0x72u, 0x80u},\r
+                       {0x73u, 0x12u},\r
+                       {0x81u, 0x10u},\r
+                       {0x84u, 0x01u},\r
+                       {0x87u, 0x10u},\r
+                       {0x8Bu, 0x11u},\r
+                       {0x90u, 0x04u},\r
+                       {0x91u, 0x40u},\r
+                       {0x92u, 0xA0u},\r
+                       {0x95u, 0x26u},\r
+                       {0x97u, 0x4Cu},\r
+                       {0x99u, 0x04u},\r
+                       {0x9Cu, 0x41u},\r
+                       {0x9Du, 0x11u},\r
+                       {0x9Eu, 0x80u},\r
+                       {0x9Fu, 0x1Bu},\r
+                       {0xA5u, 0x28u},\r
+                       {0xA7u, 0xF0u},\r
+                       {0xA8u, 0x40u},\r
+                       {0xAAu, 0x10u},\r
+                       {0xACu, 0x40u},\r
+                       {0xAEu, 0x01u},\r
+                       {0xAFu, 0x04u},\r
+                       {0xB2u, 0x02u},\r
+                       {0xB7u, 0x10u},\r
+                       {0xC0u, 0x0Fu},\r
                        {0xC2u, 0x0Eu},\r
-                       {0xC4u, 0x06u},\r
-                       {0xCAu, 0x6Fu},\r
-                       {0xCCu, 0x08u},\r
-                       {0xCEu, 0x8Eu},\r
-                       {0xD0u, 0x07u},\r
-                       {0xD2u, 0x04u},\r
+                       {0xC4u, 0x04u},\r
+                       {0xCAu, 0x0Eu},\r
+                       {0xCCu, 0x03u},\r
+                       {0xCEu, 0x0Cu},\r
+                       {0xD0u, 0x05u},\r
+                       {0xD2u, 0x0Cu},\r
                        {0xD6u, 0x0Fu},\r
                        {0xD8u, 0x0Fu},\r
-                       {0xE0u, 0x06u},\r
-                       {0xE2u, 0x08u},\r
-                       {0xE4u, 0x0Fu},\r
-                       {0xEAu, 0x04u},\r
-                       {0xEEu, 0x40u},\r
-                       {0x00u, 0x08u},\r
-                       {0x05u, 0xFFu},\r
-                       {0x06u, 0x03u},\r
-                       {0x0Au, 0x04u},\r
-                       {0x0Du, 0x33u},\r
-                       {0x0Fu, 0xCCu},\r
-                       {0x10u, 0x04u},\r
-                       {0x12u, 0x02u},\r
-                       {0x13u, 0xFFu},\r
-                       {0x15u, 0x96u},\r
-                       {0x17u, 0x69u},\r
-                       {0x18u, 0x04u},\r
-                       {0x1Au, 0x01u},\r
-                       {0x20u, 0x08u},\r
-                       {0x25u, 0x0Fu},\r
-                       {0x26u, 0x04u},\r
-                       {0x27u, 0xF0u},\r
-                       {0x28u, 0x08u},\r
-                       {0x29u, 0x55u},\r
-                       {0x2Bu, 0xAAu},\r
-                       {0x2Cu, 0x08u},\r
-                       {0x2Fu, 0xFFu},\r
-                       {0x30u, 0x08u},\r
-                       {0x33u, 0xFFu},\r
-                       {0x34u, 0x07u},\r
-                       {0x38u, 0x02u},\r
-                       {0x3Eu, 0x01u},\r
-                       {0x3Fu, 0x04u},\r
-                       {0x58u, 0x04u},\r
-                       {0x59u, 0x04u},\r
-                       {0x5Cu, 0x09u},\r
-                       {0x5Fu, 0x01u},\r
-                       {0x81u, 0x02u},\r
-                       {0x83u, 0x0Du},\r
-                       {0x84u, 0x04u},\r
-                       {0x86u, 0x03u},\r
-                       {0x87u, 0x10u},\r
-                       {0x88u, 0x08u},\r
-                       {0x89u, 0x02u},\r
-                       {0x8Au, 0x03u},\r
-                       {0x8Bu, 0x54u},\r
-                       {0x8Du, 0x8Du},\r
-                       {0x91u, 0x8Du},\r
-                       {0x94u, 0x01u},\r
-                       {0x95u, 0x62u},\r
-                       {0x96u, 0x02u},\r
-                       {0x97u, 0x08u},\r
-                       {0x99u, 0x01u},\r
-                       {0x9Au, 0x01u},\r
-                       {0x9Bu, 0x32u},\r
-                       {0x9Eu, 0x0Cu},\r
-                       {0xA3u, 0x80u},\r
-                       {0xA5u, 0x8Du},\r
-                       {0xA9u, 0x8Du},\r
-                       {0xADu, 0x0Du},\r
-                       {0xAEu, 0x12u},\r
-                       {0xAFu, 0x80u},\r
-                       {0xB1u, 0x0Fu},\r
-                       {0xB3u, 0x70u},\r
-                       {0xB4u, 0x10u},\r
-                       {0xB5u, 0x80u},\r
-                       {0xB6u, 0x0Fu},\r
-                       {0xBBu, 0x02u},\r
-                       {0xBFu, 0x10u},\r
-                       {0xD4u, 0x40u},\r
-                       {0xD8u, 0x0Bu},\r
-                       {0xD9u, 0x0Bu},\r
-                       {0xDBu, 0x0Bu},\r
-                       {0xDCu, 0x99u},\r
-                       {0xDDu, 0x90u},\r
-                       {0xDFu, 0x01u},\r
-                       {0x00u, 0x24u},\r
-                       {0x02u, 0x40u},\r
-                       {0x04u, 0x28u},\r
-                       {0x06u, 0x04u},\r
-                       {0x0Au, 0x08u},\r
-                       {0x0Bu, 0x40u},\r
-                       {0x0Eu, 0x25u},\r
-                       {0x10u, 0x80u},\r
-                       {0x11u, 0x80u},\r
-                       {0x13u, 0x24u},\r
-                       {0x16u, 0x02u},\r
-                       {0x18u, 0x04u},\r
-                       {0x19u, 0x20u},\r
-                       {0x1Au, 0x80u},\r
-                       {0x1Eu, 0x05u},\r
-                       {0x23u, 0x20u},\r
-                       {0x25u, 0x25u},\r
-                       {0x2Bu, 0x25u},\r
-                       {0x2Cu, 0x20u},\r
-                       {0x2Du, 0x02u},\r
-                       {0x2Eu, 0x10u},\r
-                       {0x2Fu, 0x02u},\r
-                       {0x33u, 0x05u},\r
-                       {0x34u, 0x10u},\r
-                       {0x36u, 0x19u},\r
-                       {0x39u, 0x84u},\r
-                       {0x3Cu, 0x80u},\r
-                       {0x3Du, 0x2Au},\r
-                       {0x45u, 0x20u},\r
-                       {0x46u, 0x08u},\r
-                       {0x66u, 0x28u},\r
-                       {0x67u, 0x01u},\r
-                       {0x7Cu, 0x02u},\r
-                       {0x80u, 0x80u},\r
-                       {0x8Du, 0x04u},\r
-                       {0x91u, 0x8Cu},\r
-                       {0x92u, 0x08u},\r
-                       {0x93u, 0x4Cu},\r
-                       {0x96u, 0x01u},\r
-                       {0x97u, 0x80u},\r
-                       {0x98u, 0x02u},\r
-                       {0x99u, 0x11u},\r
-                       {0x9Bu, 0x45u},\r
-                       {0x9Cu, 0xD0u},\r
-                       {0x9Du, 0x20u},\r
-                       {0x9Eu, 0x84u},\r
-                       {0xA0u, 0x10u},\r
-                       {0xA1u, 0x40u},\r
-                       {0xA3u, 0x24u},\r
-                       {0xA6u, 0x04u},\r
-                       {0xA8u, 0x80u},\r
-                       {0xACu, 0x0Cu},\r
-                       {0xADu, 0x80u},\r
-                       {0xB1u, 0x04u},\r
-                       {0xB3u, 0x02u},\r
-                       {0xB4u, 0x28u},\r
-                       {0xB7u, 0x40u},\r
-                       {0xC0u, 0x6Eu},\r
-                       {0xC2u, 0xEAu},\r
-                       {0xC4u, 0x8Fu},\r
-                       {0xCAu, 0xFEu},\r
-                       {0xCCu, 0xE3u},\r
-                       {0xCEu, 0xFAu},\r
-                       {0xD8u, 0x70u},\r
-                       {0xDEu, 0x80u},\r
-                       {0xE2u, 0x04u},\r
-                       {0xE6u, 0x40u},\r
-                       {0xE8u, 0x04u},\r
-                       {0xEAu, 0x08u},\r
-                       {0xEEu, 0x4Au},\r
-                       {0x82u, 0x04u},\r
-                       {0x8Au, 0x04u},\r
-                       {0x8Eu, 0x03u},\r
-                       {0x98u, 0x04u},\r
-                       {0x9Au, 0x01u},\r
-                       {0xACu, 0x04u},\r
-                       {0xAEu, 0x02u},\r
-                       {0xB0u, 0x07u},\r
-                       {0xD8u, 0x04u},\r
-                       {0xDCu, 0x09u},\r
-                       {0xDFu, 0x01u},\r
-                       {0x00u, 0x60u},\r
-                       {0x03u, 0x40u},\r
-                       {0x04u, 0x29u},\r
-                       {0x06u, 0x02u},\r
-                       {0x0Au, 0x08u},\r
-                       {0x0Du, 0x20u},\r
-                       {0x0Eu, 0x62u},\r
-                       {0x13u, 0x40u},\r
-                       {0x17u, 0x15u},\r
-                       {0x18u, 0x40u},\r
-                       {0x1Bu, 0x01u},\r
-                       {0x1Eu, 0x01u},\r
-                       {0x24u, 0x2Eu},\r
-                       {0x25u, 0x10u},\r
-                       {0x26u, 0x08u},\r
-                       {0x27u, 0x02u},\r
-                       {0x2Cu, 0x20u},\r
-                       {0x2Eu, 0x10u},\r
-                       {0x36u, 0x59u},\r
-                       {0x39u, 0x04u},\r
-                       {0x3Au, 0x08u},\r
-                       {0x3Cu, 0x81u},\r
-                       {0x3Du, 0x20u},\r
-                       {0x3Fu, 0x08u},\r
-                       {0x45u, 0x1Au},\r
-                       {0x4Cu, 0x01u},\r
-                       {0x4Du, 0x02u},\r
-                       {0x4Eu, 0x08u},\r
-                       {0x4Fu, 0x09u},\r
-                       {0x56u, 0x2Au},\r
-                       {0x65u, 0x20u},\r
-                       {0x6Cu, 0x20u},\r
-                       {0x6Du, 0x03u},\r
-                       {0x6Eu, 0xD2u},\r
-                       {0x6Fu, 0x16u},\r
-                       {0x74u, 0x40u},\r
-                       {0x77u, 0x01u},\r
-                       {0x7Cu, 0x02u},\r
-                       {0x81u, 0x02u},\r
-                       {0x8Cu, 0x40u},\r
-                       {0x8Eu, 0x04u},\r
-                       {0x91u, 0x08u},\r
-                       {0x92u, 0x08u},\r
-                       {0x93u, 0x48u},\r
-                       {0x94u, 0x28u},\r
-                       {0x96u, 0x10u},\r
-                       {0x97u, 0x01u},\r
-                       {0x98u, 0x02u},\r
-                       {0x99u, 0x11u},\r
-                       {0x9Bu, 0x40u},\r
-                       {0x9Cu, 0xC0u},\r
-                       {0x9Du, 0x02u},\r
-                       {0x9Eu, 0x22u},\r
-                       {0xA0u, 0x10u},\r
-                       {0xA4u, 0x60u},\r
-                       {0xA5u, 0x10u},\r
-                       {0xA6u, 0x1Du},\r
-                       {0xA7u, 0x03u},\r
-                       {0xA9u, 0x10u},\r
-                       {0xAAu, 0xC0u},\r
-                       {0xAFu, 0x40u},\r
-                       {0xB2u, 0x40u},\r
-                       {0xB4u, 0x04u},\r
-                       {0xC0u, 0xFBu},\r
-                       {0xC2u, 0xF2u},\r
-                       {0xC4u, 0x71u},\r
-                       {0xCAu, 0x60u},\r
-                       {0xCCu, 0xF0u},\r
-                       {0xCEu, 0xF0u},\r
-                       {0xD0u, 0xE0u},\r
-                       {0xD2u, 0x30u},\r
-                       {0xD8u, 0x20u},\r
-                       {0xDEu, 0x80u},\r
-                       {0xEEu, 0x42u},\r
-                       {0x8Du, 0x40u},\r
-                       {0x95u, 0x40u},\r
-                       {0xAFu, 0x08u},\r
-                       {0xB3u, 0x40u},\r
-                       {0xE0u, 0x40u},\r
-                       {0xEEu, 0x80u},\r
-                       {0x38u, 0x08u},\r
-                       {0x3Eu, 0x04u},\r
-                       {0x58u, 0x04u},\r
-                       {0x5Fu, 0x01u},\r
-                       {0x1Bu, 0x08u},\r
-                       {0x80u, 0x10u},\r
-                       {0x90u, 0x20u},\r
-                       {0x93u, 0x80u},\r
-                       {0x95u, 0x40u},\r
-                       {0xA8u, 0x20u},\r
-                       {0xABu, 0x08u},\r
-                       {0xACu, 0x05u},\r
-                       {0xADu, 0x04u},\r
-                       {0xB0u, 0x04u},\r
-                       {0xB2u, 0x20u},\r
-                       {0xB4u, 0x40u},\r
-                       {0xB7u, 0x90u},\r
-                       {0xEAu, 0x60u},\r
-                       {0xECu, 0x90u},\r
-                       {0xEEu, 0x04u},\r
-                       {0x04u, 0x0Fu},\r
-                       {0x05u, 0x04u},\r
-                       {0x06u, 0xF0u},\r
-                       {0x07u, 0x02u},\r
-                       {0x0Cu, 0x55u},\r
-                       {0x0Du, 0x04u},\r
-                       {0x0Eu, 0xAAu},\r
-                       {0x0Fu, 0x01u},\r
-                       {0x10u, 0x33u},\r
-                       {0x12u, 0xCCu},\r
+                       {0xE2u, 0x02u},\r
+                       {0xE6u, 0x21u},\r
+                       {0xE8u, 0x02u},\r
+                       {0xECu, 0x0Cu},\r
+                       {0x01u, 0x04u},\r
+                       {0x03u, 0x01u},\r
+                       {0x04u, 0x24u},\r
+                       {0x05u, 0x10u},\r
+                       {0x06u, 0x12u},\r
+                       {0x0Bu, 0x04u},\r
+                       {0x0Eu, 0x18u},\r
+                       {0x0Fu, 0x04u},\r
+                       {0x10u, 0x40u},\r
                        {0x13u, 0x03u},\r
-                       {0x17u, 0x04u},\r
-                       {0x19u, 0x08u},\r
-                       {0x1Au, 0xFFu},\r
-                       {0x1Cu, 0x69u},\r
-                       {0x1Eu, 0x96u},\r
-                       {0x20u, 0xFFu},\r
-                       {0x2Bu, 0x04u},\r
-                       {0x2Cu, 0xFFu},\r
+                       {0x15u, 0x10u},\r
+                       {0x16u, 0x03u},\r
+                       {0x19u, 0x04u},\r
+                       {0x1Au, 0x24u},\r
+                       {0x1Bu, 0x02u},\r
+                       {0x1Du, 0x10u},\r
+                       {0x21u, 0x20u},\r
+                       {0x22u, 0x04u},\r
+                       {0x26u, 0x20u},\r
+                       {0x29u, 0x08u},\r
+                       {0x2Cu, 0x24u},\r
+                       {0x2Du, 0x10u},\r
+                       {0x2Eu, 0x09u},\r
+                       {0x30u, 0x38u},\r
+                       {0x31u, 0x07u},\r
+                       {0x32u, 0x07u},\r
+                       {0x33u, 0x10u},\r
+                       {0x34u, 0x40u},\r
                        {0x35u, 0x08u},\r
-                       {0x36u, 0xFFu},\r
-                       {0x37u, 0x07u},\r
-                       {0x3Eu, 0x40u},\r
-                       {0x3Fu, 0x10u},\r
+                       {0x37u, 0x20u},\r
+                       {0x39u, 0x08u},\r
+                       {0x3Eu, 0x10u},\r
+                       {0x3Fu, 0x54u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
-                       {0x5Cu, 0x90u},\r
+                       {0x5Cu, 0x99u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x84u, 0x0Fu},\r
-                       {0x86u, 0xF0u},\r
-                       {0x88u, 0x69u},\r
-                       {0x89u, 0x02u},\r
-                       {0x8Au, 0x96u},\r
-                       {0x8Cu, 0x55u},\r
-                       {0x8Eu, 0xAAu},\r
-                       {0x90u, 0x33u},\r
-                       {0x92u, 0xCCu},\r
-                       {0x95u, 0x01u},\r
-                       {0x9Eu, 0xFFu},\r
-                       {0xA1u, 0x04u},\r
-                       {0xA2u, 0xFFu},\r
-                       {0xA5u, 0x08u},\r
-                       {0xAEu, 0xFFu},\r
-                       {0xB1u, 0x04u},\r
-                       {0xB2u, 0xFFu},\r
-                       {0xB3u, 0x01u},\r
-                       {0xB5u, 0x02u},\r
-                       {0xB7u, 0x08u},\r
-                       {0xBEu, 0x04u},\r
-                       {0xBFu, 0x55u},\r
+                       {0x85u, 0x33u},\r
+                       {0x86u, 0xFFu},\r
+                       {0x87u, 0xCCu},\r
+                       {0x89u, 0xFFu},\r
+                       {0x8Du, 0x0Fu},\r
+                       {0x8Eu, 0xFFu},\r
+                       {0x8Fu, 0xF0u},\r
+                       {0x90u, 0x69u},\r
+                       {0x92u, 0x96u},\r
+                       {0x93u, 0xFFu},\r
+                       {0x96u, 0xFFu},\r
+                       {0x98u, 0x33u},\r
+                       {0x9Au, 0xCCu},\r
+                       {0x9Du, 0x69u},\r
+                       {0x9Fu, 0x96u},\r
+                       {0xA0u, 0x55u},\r
+                       {0xA1u, 0x55u},\r
+                       {0xA2u, 0xAAu},\r
+                       {0xA3u, 0xAAu},\r
+                       {0xA9u, 0xFFu},\r
+                       {0xACu, 0x0Fu},\r
+                       {0xAEu, 0xF0u},\r
+                       {0xB0u, 0xFFu},\r
+                       {0xB7u, 0xFFu},\r
+                       {0xBEu, 0x01u},\r
+                       {0xBFu, 0x40u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x08u},\r
-                       {0x03u, 0x09u},\r
-                       {0x05u, 0x08u},\r
+                       {0x00u, 0x40u},\r
+                       {0x01u, 0x40u},\r
+                       {0x03u, 0x20u},\r
+                       {0x05u, 0x04u},\r
                        {0x07u, 0x01u},\r
-                       {0x08u, 0x81u},\r
-                       {0x0Au, 0x80u},\r
-                       {0x0Cu, 0x01u},\r
-                       {0x0Eu, 0x0Au},\r
-                       {0x11u, 0x40u},\r
-                       {0x12u, 0x80u},\r
-                       {0x14u, 0x80u},\r
+                       {0x08u, 0x01u},\r
+                       {0x09u, 0x20u},\r
+                       {0x0Au, 0x10u},\r
+                       {0x0Cu, 0x08u},\r
+                       {0x0Eu, 0x80u},\r
+                       {0x0Fu, 0xA4u},\r
+                       {0x11u, 0x04u},\r
+                       {0x13u, 0x42u},\r
+                       {0x14u, 0x40u},\r
                        {0x15u, 0x40u},\r
-                       {0x18u, 0x20u},\r
-                       {0x1Fu, 0x40u},\r
-                       {0x20u, 0x4Au},\r
-                       {0x21u, 0x04u},\r
-                       {0x26u, 0x20u},\r
-                       {0x27u, 0x03u},\r
-                       {0x28u, 0x20u},\r
-                       {0x2Bu, 0x80u},\r
-                       {0x2Cu, 0x04u},\r
-                       {0x33u, 0x04u},\r
-                       {0x36u, 0x08u},\r
-                       {0x37u, 0x12u},\r
-                       {0x3Au, 0x20u},\r
-                       {0x3Du, 0x84u},\r
-                       {0x5Du, 0x22u},\r
-                       {0x5Fu, 0x88u},\r
-                       {0x6Cu, 0x01u},\r
-                       {0x82u, 0x8Du},\r
-                       {0x83u, 0x0Cu},\r
-                       {0x85u, 0x46u},\r
-                       {0x88u, 0x80u},\r
-                       {0x8Au, 0x20u},\r
-                       {0x8Bu, 0x80u},\r
-                       {0x8Du, 0x60u},\r
-                       {0x92u, 0x80u},\r
-                       {0x94u, 0x02u},\r
-                       {0x99u, 0x08u},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xB3u, 0x01u},\r
-                       {0xB4u, 0x01u},\r
-                       {0xC0u, 0xA7u},\r
-                       {0xC2u, 0xD9u},\r
-                       {0xC4u, 0x99u},\r
-                       {0xCAu, 0x23u},\r
-                       {0xCCu, 0xE2u},\r
-                       {0xCEu, 0x54u},\r
-                       {0xD6u, 0xF0u},\r
-                       {0xE0u, 0x30u},\r
-                       {0xE2u, 0x09u},\r
-                       {0xE6u, 0x40u},\r
-                       {0xEAu, 0x44u},\r
-                       {0xEEu, 0x20u},\r
-                       {0x81u, 0x08u},\r
-                       {0x82u, 0x40u},\r
-                       {0xE4u, 0x05u},\r
-                       {0xE6u, 0xC0u},\r
-                       {0x87u, 0x04u},\r
-                       {0x93u, 0x08u},\r
-                       {0xA8u, 0x20u},\r
-                       {0xABu, 0x04u},\r
-                       {0x00u, 0x2Cu},\r
-                       {0x01u, 0x01u},\r
-                       {0x04u, 0xC1u},\r
-                       {0x06u, 0x2Eu},\r
-                       {0x08u, 0x60u},\r
-                       {0x09u, 0x48u},\r
-                       {0x0Au, 0x8Fu},\r
-                       {0x0Bu, 0x21u},\r
-                       {0x0Cu, 0x44u},\r
-                       {0x0Du, 0x01u},\r
-                       {0x0Eu, 0x20u},\r
-                       {0x10u, 0x0Cu},\r
-                       {0x12u, 0x20u},\r
-                       {0x14u, 0x21u},\r
-                       {0x15u, 0x62u},\r
-                       {0x16u, 0xC2u},\r
-                       {0x17u, 0x08u},\r
-                       {0x18u, 0x08u},\r
-                       {0x19u, 0x01u},\r
+                       {0x18u, 0x44u},\r
+                       {0x19u, 0x04u},\r
+                       {0x1Au, 0x10u},\r
+                       {0x1Fu, 0x02u},\r
+                       {0x22u, 0x55u},\r
+                       {0x26u, 0x80u},\r
+                       {0x2Au, 0x22u},\r
+                       {0x2Bu, 0x02u},\r
+                       {0x2Cu, 0x48u},\r
+                       {0x31u, 0x18u},\r
+                       {0x32u, 0x81u},\r
+                       {0x36u, 0x40u},\r
+                       {0x37u, 0x01u},\r
+                       {0x39u, 0x22u},\r
+                       {0x3Au, 0x80u},\r
+                       {0x3Bu, 0x08u},\r
+                       {0x3Cu, 0x40u},\r
+                       {0x3Eu, 0x10u},\r
+                       {0x3Fu, 0x04u},\r
+                       {0x43u, 0xC0u},\r
+                       {0x59u, 0x01u},\r
+                       {0x5Bu, 0x58u},\r
+                       {0x86u, 0x20u},\r
+                       {0x8Au, 0x04u},\r
+                       {0xC0u, 0xA5u},\r
+                       {0xC2u, 0x7Eu},\r
+                       {0xC4u, 0x9Du},\r
+                       {0xCAu, 0xADu},\r
+                       {0xCCu, 0x9Fu},\r
+                       {0xCEu, 0x7Fu},\r
+                       {0xD6u, 0x0Fu},\r
+                       {0xE2u, 0x88u},\r
+                       {0x80u, 0x01u},\r
+                       {0x90u, 0x02u},\r
+                       {0xB2u, 0x01u},\r
+                       {0xEAu, 0x20u},\r
+                       {0x01u, 0x05u},\r
+                       {0x02u, 0x01u},\r
+                       {0x05u, 0x09u},\r
+                       {0x06u, 0x0Cu},\r
+                       {0x07u, 0x02u},\r
+                       {0x08u, 0x01u},\r
+                       {0x0Au, 0x02u},\r
+                       {0x0Bu, 0x38u},\r
+                       {0x0Eu, 0x10u},\r
+                       {0x0Fu, 0x04u},\r
+                       {0x13u, 0x05u},\r
+                       {0x14u, 0x04u},\r
+                       {0x15u, 0x05u},\r
+                       {0x16u, 0x03u},\r
+                       {0x18u, 0x10u},\r
+                       {0x19u, 0x23u},\r
                        {0x1Cu, 0x10u},\r
-                       {0x1Du, 0x01u},\r
-                       {0x20u, 0x2Cu},\r
-                       {0x21u, 0x10u},\r
-                       {0x24u, 0x20u},\r
-                       {0x25u, 0x04u},\r
-                       {0x26u, 0x0Cu},\r
-                       {0x28u, 0x24u},\r
-                       {0x29u, 0x47u},\r
-                       {0x2Au, 0x08u},\r
-                       {0x2Bu, 0x18u},\r
-                       {0x2Cu, 0x10u},\r
-                       {0x2Du, 0x01u},\r
-                       {0x30u, 0x80u},\r
-                       {0x31u, 0x3Fu},\r
+                       {0x1Du, 0x02u},\r
+                       {0x1Fu, 0x01u},\r
+                       {0x20u, 0x10u},\r
+                       {0x21u, 0x05u},\r
+                       {0x24u, 0x10u},\r
+                       {0x25u, 0x05u},\r
+                       {0x28u, 0x08u},\r
+                       {0x29u, 0x02u},\r
+                       {0x2Au, 0x03u},\r
+                       {0x2Bu, 0x11u},\r
+                       {0x2Du, 0x38u},\r
+                       {0x2Eu, 0x22u},\r
+                       {0x30u, 0x20u},\r
+                       {0x31u, 0x03u},\r
                        {0x32u, 0x0Fu},\r
-                       {0x34u, 0x10u},\r
-                       {0x36u, 0x60u},\r
-                       {0x37u, 0x40u},\r
-                       {0x38u, 0x20u},\r
-                       {0x39u, 0x02u},\r
-                       {0x3Au, 0x80u},\r
-                       {0x3Eu, 0x01u},\r
-                       {0x3Fu, 0x41u},\r
-                       {0x54u, 0x09u},\r
+                       {0x33u, 0x04u},\r
+                       {0x36u, 0x10u},\r
+                       {0x37u, 0x38u},\r
+                       {0x3Bu, 0x02u},\r
+                       {0x3Eu, 0x40u},\r
+                       {0x3Fu, 0x44u},\r
                        {0x58u, 0x0Bu},\r
-                       {0x59u, 0x04u},\r
-                       {0x5Bu, 0x0Bu},\r
-                       {0x5Cu, 0x09u},\r
-                       {0x5Du, 0x90u},\r
+                       {0x59u, 0x0Bu},\r
+                       {0x5Cu, 0x99u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x84u, 0x19u},\r
-                       {0x86u, 0x24u},\r
-                       {0x87u, 0x04u},\r
-                       {0x8Du, 0x04u},\r
-                       {0x8Fu, 0x02u},\r
-                       {0x93u, 0x03u},\r
-                       {0x94u, 0x09u},\r
-                       {0x96u, 0x32u},\r
-                       {0x98u, 0x20u},\r
-                       {0x9Au, 0x18u},\r
-                       {0x9Cu, 0x06u},\r
-                       {0xA3u, 0x04u},\r
-                       {0xA8u, 0x2Au},\r
-                       {0xA9u, 0x04u},\r
-                       {0xAAu, 0x11u},\r
-                       {0xABu, 0x01u},\r
-                       {0xB1u, 0x07u},\r
-                       {0xB4u, 0x38u},\r
+                       {0x84u, 0x18u},\r
+                       {0x86u, 0x60u},\r
+                       {0x87u, 0x06u},\r
+                       {0x8Cu, 0x04u},\r
+                       {0x8Eu, 0x03u},\r
+                       {0x93u, 0x02u},\r
+                       {0x94u, 0x03u},\r
+                       {0x96u, 0x04u},\r
+                       {0x97u, 0x0Au},\r
+                       {0x98u, 0x30u},\r
+                       {0x99u, 0x0Cu},\r
+                       {0x9Au, 0x48u},\r
+                       {0x9Du, 0x01u},\r
+                       {0xA4u, 0x01u},\r
+                       {0xA6u, 0x06u},\r
+                       {0xA8u, 0x05u},\r
+                       {0xAAu, 0x02u},\r
+                       {0xACu, 0x28u},\r
+                       {0xAEu, 0x50u},\r
+                       {0xB1u, 0x0Eu},\r
+                       {0xB3u, 0x01u},\r
+                       {0xB4u, 0x78u},\r
                        {0xB6u, 0x07u},\r
-                       {0xB8u, 0x80u},\r
-                       {0xBAu, 0x20u},\r
+                       {0xBAu, 0x80u},\r
+                       {0xBEu, 0x10u},\r
+                       {0xBFu, 0x04u},\r
                        {0xD8u, 0x0Bu},\r
-                       {0xD9u, 0x04u},\r
+                       {0xD9u, 0x0Bu},\r
                        {0xDCu, 0x99u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x04u},\r
-                       {0x04u, 0x28u},\r
-                       {0x05u, 0x40u},\r
-                       {0x06u, 0x80u},\r
-                       {0x08u, 0x80u},\r
+                       {0x00u, 0x08u},\r
+                       {0x01u, 0x80u},\r
+                       {0x05u, 0x05u},\r
+                       {0x06u, 0x20u},\r
+                       {0x07u, 0x09u},\r
+                       {0x08u, 0x20u},\r
                        {0x09u, 0x08u},\r
-                       {0x0Au, 0x06u},\r
-                       {0x0Eu, 0xA1u},\r
-                       {0x0Fu, 0x08u},\r
-                       {0x12u, 0x08u},\r
-                       {0x15u, 0x01u},\r
-                       {0x17u, 0x94u},\r
-                       {0x19u, 0x20u},\r
-                       {0x1Au, 0x06u},\r
-                       {0x1Cu, 0x01u},\r
-                       {0x1Du, 0x68u},\r
-                       {0x1Eu, 0x60u},\r
-                       {0x1Fu, 0x28u},\r
-                       {0x21u, 0x02u},\r
+                       {0x0Cu, 0x80u},\r
+                       {0x0Eu, 0x28u},\r
+                       {0x11u, 0x04u},\r
+                       {0x13u, 0x60u},\r
+                       {0x15u, 0x41u},\r
+                       {0x17u, 0x14u},\r
+                       {0x18u, 0x04u},\r
+                       {0x19u, 0x80u},\r
+                       {0x1Du, 0x85u},\r
+                       {0x1Eu, 0x02u},\r
+                       {0x20u, 0x20u},\r
+                       {0x22u, 0x01u},\r
                        {0x24u, 0x02u},\r
-                       {0x27u, 0x80u},\r
-                       {0x29u, 0x11u},\r
-                       {0x2Eu, 0x02u},\r
-                       {0x2Fu, 0x2Au},\r
-                       {0x31u, 0x02u},\r
-                       {0x35u, 0x40u},\r
-                       {0x36u, 0x08u},\r
-                       {0x37u, 0x10u},\r
-                       {0x39u, 0x08u},\r
-                       {0x3Bu, 0x40u},\r
-                       {0x3Cu, 0x80u},\r
-                       {0x3Du, 0x22u},\r
-                       {0x3Eu, 0x80u},\r
-                       {0x4Cu, 0x01u},\r
-                       {0x4Du, 0x80u},\r
-                       {0x5Cu, 0x20u},\r
-                       {0x5Du, 0x04u},\r
-                       {0x5Eu, 0x40u},\r
-                       {0x5Fu, 0x02u},\r
-                       {0x65u, 0x80u},\r
+                       {0x26u, 0x0Au},\r
+                       {0x27u, 0x40u},\r
+                       {0x2Cu, 0x81u},\r
+                       {0x2Fu, 0x28u},\r
+                       {0x31u, 0x08u},\r
+                       {0x32u, 0x41u},\r
+                       {0x33u, 0x18u},\r
+                       {0x37u, 0x65u},\r
+                       {0x38u, 0x08u},\r
+                       {0x3Du, 0x05u},\r
+                       {0x3Eu, 0xA0u},\r
                        {0x78u, 0x02u},\r
-                       {0x7Cu, 0x02u},\r
-                       {0x89u, 0x02u},\r
-                       {0x90u, 0x2Cu},\r
-                       {0x91u, 0x0Du},\r
-                       {0x92u, 0x01u},\r
-                       {0x93u, 0x48u},\r
-                       {0x94u, 0x01u},\r
-                       {0x98u, 0x02u},\r
-                       {0x99u, 0x11u},\r
-                       {0x9Au, 0x02u},\r
-                       {0x9Bu, 0x16u},\r
-                       {0x9Cu, 0x80u},\r
-                       {0x9Du, 0x20u},\r
-                       {0xA0u, 0x40u},\r
-                       {0xA1u, 0x11u},\r
-                       {0xA2u, 0x48u},\r
-                       {0xA3u, 0x06u},\r
-                       {0xA5u, 0x28u},\r
-                       {0xA6u, 0x10u},\r
-                       {0xACu, 0x40u},\r
-                       {0xC0u, 0xF4u},\r
-                       {0xC2u, 0xF7u},\r
-                       {0xC4u, 0xF2u},\r
-                       {0xCAu, 0xF5u},\r
-                       {0xCCu, 0x71u},\r
-                       {0xCEu, 0xBAu},\r
-                       {0xD6u, 0xF0u},\r
-                       {0xD8u, 0x10u},\r
+                       {0x7Eu, 0x80u},\r
+                       {0x90u, 0x08u},\r
+                       {0x91u, 0x45u},\r
+                       {0x92u, 0x80u},\r
+                       {0x93u, 0x40u},\r
+                       {0x94u, 0x04u},\r
+                       {0x98u, 0x23u},\r
+                       {0x9Au, 0x80u},\r
+                       {0x9Bu, 0x3Du},\r
+                       {0x9Du, 0x80u},\r
+                       {0x9Fu, 0x40u},\r
+                       {0xA0u, 0x84u},\r
+                       {0xA1u, 0x08u},\r
+                       {0xA2u, 0x94u},\r
+                       {0xA3u, 0x20u},\r
+                       {0xA4u, 0x10u},\r
+                       {0xA5u, 0x80u},\r
+                       {0xA6u, 0x0Bu},\r
+                       {0xA8u, 0x04u},\r
+                       {0xAEu, 0x40u},\r
+                       {0xB6u, 0x80u},\r
+                       {0xB7u, 0x01u},\r
+                       {0xC0u, 0xF5u},\r
+                       {0xC2u, 0xE6u},\r
+                       {0xC4u, 0xF7u},\r
+                       {0xCAu, 0xF0u},\r
+                       {0xCCu, 0xFFu},\r
+                       {0xCEu, 0xF2u},\r
                        {0xDEu, 0x81u},\r
-                       {0xE6u, 0x20u},\r
-                       {0xEAu, 0x02u},\r
+                       {0xE8u, 0x04u},\r
+                       {0xECu, 0x80u},\r
                        {0xEEu, 0x02u},\r
-                       {0xEAu, 0x02u},\r
+                       {0xABu, 0x40u},\r
+                       {0xB0u, 0x04u},\r
+                       {0xECu, 0x80u},\r
                        {0xEEu, 0x02u},\r
-                       {0x30u, 0x20u},\r
-                       {0x33u, 0x01u},\r
+                       {0x33u, 0x40u},\r
                        {0x36u, 0x40u},\r
-                       {0x53u, 0x08u},\r
-                       {0x5Bu, 0x08u},\r
+                       {0x58u, 0x08u},\r
+                       {0x5Cu, 0x01u},\r
+                       {0x5Du, 0x10u},\r
                        {0x61u, 0x08u},\r
-                       {0x65u, 0xA0u},\r
-                       {0x85u, 0x20u},\r
-                       {0xCCu, 0x70u},\r
-                       {0xD4u, 0x20u},\r
-                       {0xD6u, 0xC0u},\r
+                       {0x64u, 0x10u},\r
+                       {0x89u, 0x10u},\r
+                       {0xCCu, 0x30u},\r
+                       {0xD6u, 0xE0u},\r
                        {0xD8u, 0xC0u},\r
-                       {0xE6u, 0x40u},\r
-                       {0x59u, 0x10u},\r
-                       {0x5Eu, 0x40u},\r
-                       {0x81u, 0x18u},\r
-                       {0x9Du, 0x80u},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA4u, 0x20u},\r
+                       {0x59u, 0x40u},\r
+                       {0x5Fu, 0x20u},\r
+                       {0x83u, 0x40u},\r
+                       {0x8Bu, 0x20u},\r
+                       {0x9Cu, 0x08u},\r
+                       {0x9Fu, 0x40u},\r
                        {0xA5u, 0x08u},\r
                        {0xA6u, 0x40u},\r
-                       {0xA7u, 0x08u},\r
-                       {0xB7u, 0x08u},\r
+                       {0xA8u, 0x01u},\r
+                       {0xACu, 0x10u},\r
                        {0xD4u, 0x80u},\r
                        {0xD6u, 0x20u},\r
-                       {0xE0u, 0x80u},\r
-                       {0xE6u, 0x20u},\r
-                       {0x10u, 0x20u},\r
-                       {0x58u, 0x02u},\r
-                       {0x8Fu, 0x02u},\r
-                       {0x9Du, 0x80u},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA4u, 0x20u},\r
+                       {0xE6u, 0x80u},\r
+                       {0xEAu, 0x80u},\r
+                       {0xEEu, 0x40u},\r
+                       {0x89u, 0x08u},\r
+                       {0x8Cu, 0x08u},\r
+                       {0x9Cu, 0x08u},\r
                        {0xA5u, 0x08u},\r
                        {0xA6u, 0x40u},\r
-                       {0xA7u, 0x08u},\r
-                       {0xB6u, 0x40u},\r
-                       {0xC4u, 0x10u},\r
-                       {0xD6u, 0x40u},\r
-                       {0x80u, 0x01u},\r
-                       {0x97u, 0x10u},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA3u, 0x02u},\r
-                       {0xA5u, 0x08u},\r
+                       {0xADu, 0x40u},\r
+                       {0xEEu, 0x10u},\r
+                       {0x94u, 0x02u},\r
                        {0xA6u, 0x40u},\r
-                       {0xABu, 0x08u},\r
-                       {0xACu, 0x02u},\r
-                       {0xAFu, 0x10u},\r
-                       {0xB5u, 0x80u},\r
-                       {0xE0u, 0x80u},\r
-                       {0xE8u, 0x10u},\r
-                       {0xEEu, 0xC0u},\r
-                       {0x09u, 0x20u},\r
-                       {0x0Fu, 0x80u},\r
-                       {0x13u, 0x08u},\r
-                       {0x52u, 0x20u},\r
-                       {0x53u, 0x01u},\r
-                       {0x57u, 0x20u},\r
-                       {0x5Fu, 0x80u},\r
-                       {0x82u, 0x20u},\r
-                       {0x83u, 0x20u},\r
-                       {0x8Bu, 0x08u},\r
-                       {0x8Eu, 0x01u},\r
+                       {0xB4u, 0x01u},\r
+                       {0x08u, 0x80u},\r
+                       {0x0Fu, 0x40u},\r
+                       {0x12u, 0x80u},\r
+                       {0x53u, 0x04u},\r
+                       {0x57u, 0x80u},\r
+                       {0x5Bu, 0x20u},\r
+                       {0x5Cu, 0x10u},\r
+                       {0x84u, 0x80u},\r
                        {0xC2u, 0x06u},\r
                        {0xC4u, 0x08u},\r
                        {0xD4u, 0x07u},\r
                        {0xD6u, 0x04u},\r
-                       {0xE6u, 0x03u},\r
-                       {0x02u, 0x01u},\r
-                       {0x04u, 0x40u},\r
-                       {0x06u, 0x20u},\r
-                       {0x0Bu, 0x11u},\r
-                       {0x0Fu, 0x82u},\r
-                       {0x83u, 0x01u},\r
-                       {0x86u, 0x20u},\r
-                       {0x8Bu, 0x11u},\r
-                       {0x8Du, 0x20u},\r
-                       {0x8Fu, 0x01u},\r
-                       {0x97u, 0x02u},\r
-                       {0x9Eu, 0x01u},\r
-                       {0xA1u, 0x20u},\r
-                       {0xABu, 0x40u},\r
-                       {0xB3u, 0x80u},\r
+                       {0x01u, 0x20u},\r
+                       {0x06u, 0x80u},\r
+                       {0x07u, 0x01u},\r
+                       {0x09u, 0x01u},\r
+                       {0x0Au, 0x02u},\r
+                       {0x0Cu, 0x80u},\r
+                       {0x0Eu, 0x20u},\r
+                       {0x82u, 0x40u},\r
+                       {0x87u, 0x01u},\r
+                       {0x8Bu, 0x40u},\r
+                       {0x93u, 0x40u},\r
+                       {0x98u, 0x80u},\r
+                       {0xA4u, 0x80u},\r
+                       {0xABu, 0x80u},\r
+                       {0xAFu, 0x24u},\r
+                       {0xB2u, 0x80u},\r
+                       {0xB4u, 0x10u},\r
                        {0xC0u, 0x07u},\r
                        {0xC2u, 0x0Fu},\r
-                       {0xE0u, 0x02u},\r
-                       {0xE2u, 0x01u},\r
-                       {0xE6u, 0x03u},\r
-                       {0xECu, 0x04u},\r
-                       {0xA8u, 0x40u},\r
-                       {0xB7u, 0x40u},\r
-                       {0xEEu, 0x02u},\r
-                       {0x0Bu, 0x40u},\r
-                       {0x0Du, 0x08u},\r
+                       {0xE2u, 0x04u},\r
+                       {0xE8u, 0x08u},\r
+                       {0xEAu, 0x01u},\r
+                       {0x92u, 0x02u},\r
+                       {0x96u, 0x80u},\r
+                       {0x9Au, 0x80u},\r
+                       {0xA1u, 0x01u},\r
+                       {0xB0u, 0x80u},\r
+                       {0xB2u, 0x10u},\r
+                       {0xB5u, 0x20u},\r
+                       {0xEAu, 0x0Du},\r
+                       {0x0Au, 0x80u},\r
+                       {0x0Fu, 0x40u},\r
+                       {0x96u, 0x80u},\r
+                       {0xA9u, 0x01u},\r
+                       {0xAEu, 0x80u},\r
+                       {0xB2u, 0x01u},\r
                        {0xC2u, 0x0Cu},\r
-                       {0x23u, 0x10u},\r
-                       {0x26u, 0x10u},\r
-                       {0x89u, 0x08u},\r
-                       {0x94u, 0x01u},\r
-                       {0x97u, 0x10u},\r
-                       {0xA3u, 0x02u},\r
-                       {0xA5u, 0x08u},\r
-                       {0xA6u, 0x10u},\r
-                       {0xAEu, 0x50u},\r
-                       {0xAFu, 0x01u},\r
+                       {0xEAu, 0x04u},\r
+                       {0x22u, 0x08u},\r
+                       {0x24u, 0x02u},\r
+                       {0x94u, 0x02u},\r
+                       {0x9Eu, 0x20u},\r
+                       {0xA6u, 0x08u},\r
+                       {0xAEu, 0x60u},\r
+                       {0xB2u, 0x08u},\r
                        {0xC8u, 0x60u},\r
-                       {0xEAu, 0x40u},\r
-                       {0xECu, 0x10u},\r
+                       {0xE8u, 0x10u},\r
                        {0xEEu, 0x40u},\r
-                       {0x04u, 0x01u},\r
-                       {0x53u, 0x02u},\r
-                       {0x57u, 0x01u},\r
-                       {0x87u, 0x01u},\r
-                       {0x94u, 0x01u},\r
-                       {0xA3u, 0x02u},\r
+                       {0x06u, 0x20u},\r
+                       {0x53u, 0x01u},\r
+                       {0x5Du, 0x20u},\r
+                       {0x83u, 0x01u},\r
+                       {0x99u, 0x20u},\r
+                       {0x9Eu, 0x20u},\r
+                       {0xB1u, 0x20u},\r
                        {0xC0u, 0x20u},\r
                        {0xD4u, 0x80u},\r
                        {0xD6u, 0x20u},\r
-                       {0xE6u, 0x10u},\r
-                       {0xADu, 0x08u},\r
+                       {0xE6u, 0x20u},\r
                        {0xAFu, 0x40u},\r
                        {0x01u, 0x01u},\r
-                       {0x09u, 0x01u},\r
                        {0x0Bu, 0x01u},\r
+                       {0x0Du, 0x01u},\r
                        {0x0Fu, 0x01u},\r
                        {0x11u, 0x01u},\r
                        {0x1Bu, 0x01u},\r
-                       {0x00u, 0x2Bu},\r
+                       {0x00u, 0x0Au},\r
                };\r
 \r
 \r
@@ -1357,7 +1279,6 @@ void cyfitter_cfg(void)
 \r
                static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
                        /* address, size */\r
-                       {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
                        {(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
                        {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},\r
                        {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},\r
@@ -1369,12 +1290,12 @@ void cyfitter_cfg(void)
 \r
                /* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */\r
                static const uint8 CYCODE BS_UDB_1_2_1_CONFIG_VAL[] = {\r
-                       0x80u, 0x42u, 0x00u, 0x00u, 0x00u, 0x04u, 0xFFu, 0x20u, 0x7Fu, 0x39u, 0x80u, 0x06u, 0x00u, 0xC6u, 0x9Fu, 0x00u, \r
-                       0x90u, 0xC6u, 0x40u, 0x00u, 0x1Fu, 0x01u, 0x20u, 0x5Eu, 0x00u, 0x77u, 0x60u, 0x08u, 0xC0u, 0x46u, 0x02u, 0x80u, \r
-                       0xC0u, 0x00u, 0x01u, 0x00u, 0xC0u, 0xC2u, 0x08u, 0x04u, 0xC0u, 0x80u, 0x04u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, \r
-                       0x00u, 0x00u, 0x00u, 0x70u, 0x00u, 0x0Fu, 0xFFu, 0x80u, 0x00u, 0x20u, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x40u, 0x40u, \r
-                       0x26u, 0x03u, 0x50u, 0x00u, 0x04u, 0xDCu, 0xF0u, 0xBEu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
-                       0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, \r
+                       0x80u, 0x01u, 0x00u, 0x00u, 0x7Fu, 0x10u, 0x80u, 0x00u, 0xC0u, 0x08u, 0x04u, 0x21u, 0xC0u, 0x04u, 0x01u, 0x00u, \r
+                       0x00u, 0x01u, 0x60u, 0x00u, 0x00u, 0x07u, 0xFFu, 0x18u, 0x00u, 0x22u, 0x9Fu, 0x08u, 0xC0u, 0x40u, 0x02u, 0x00u, \r
+                       0x90u, 0x01u, 0x40u, 0x00u, 0x1Fu, 0x01u, 0x20u, 0x00u, 0xC0u, 0x40u, 0x08u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, \r
+                       0x00u, 0x3Fu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u, \r
+                       0x32u, 0x06u, 0x10u, 0x00u, 0x04u, 0xCBu, 0xFDu, 0x0Eu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+                       0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, \r
                        0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
                        0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
 \r
index 0765235..25148f4 100755 (executable)
@@ -3,34 +3,6 @@
 .include "cydevicegnu.inc"\r
 .include "cydevicegnu_trm.inc"\r
 \r
-/* SCSI_CMD_TIMER_TimerHW */\r
-.set SCSI_CMD_TIMER_TimerHW__CAP0, CYREG_TMR0_CAP0\r
-.set SCSI_CMD_TIMER_TimerHW__CAP1, CYREG_TMR0_CAP1\r
-.set SCSI_CMD_TIMER_TimerHW__CFG0, CYREG_TMR0_CFG0\r
-.set SCSI_CMD_TIMER_TimerHW__CFG1, CYREG_TMR0_CFG1\r
-.set SCSI_CMD_TIMER_TimerHW__CFG2, CYREG_TMR0_CFG2\r
-.set SCSI_CMD_TIMER_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0\r
-.set SCSI_CMD_TIMER_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1\r
-.set SCSI_CMD_TIMER_TimerHW__PER0, CYREG_TMR0_PER0\r
-.set SCSI_CMD_TIMER_TimerHW__PER1, CYREG_TMR0_PER1\r
-.set SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3\r
-.set SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK, 0x01\r
-.set SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3\r
-.set SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK, 0x01\r
-.set SCSI_CMD_TIMER_TimerHW__RT0, CYREG_TMR0_RT0\r
-.set SCSI_CMD_TIMER_TimerHW__RT1, CYREG_TMR0_RT1\r
-.set SCSI_CMD_TIMER_TimerHW__SR0, CYREG_TMR0_SR0\r
-\r
-/* SCSI_CMD_TIMER_ISR */\r
-.set SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_CMD_TIMER_ISR__INTC_MASK, 0x01\r
-.set SCSI_CMD_TIMER_ISR__INTC_NUMBER, 0\r
-.set SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
-.set SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
 /* USBFS_bus_reset */\r
 .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
 .set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
 .set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK\r
 .set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
 .set SDCard_BSPIM_RxStsReg__4__POS, 4\r
 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
 .set SDCard_BSPIM_RxStsReg__6__POS, 6\r
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
 .set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
 .set SDCard_BSPIM_TxStsReg__1__POS, 1\r
 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
 .set SDCard_BSPIM_TxStsReg__4__POS, 4\r
 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0\r
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1\r
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0\r
 /* SCSI_CTL_IO */\r
 .set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
 .set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
 \r
 /* SCSI_In_DBx */\r
 .set SCSI_In_DBx__0__AG, CYREG_PRT12_AG\r
 /* scsiTarget */\r
 .set scsiTarget_StatusReg__0__MASK, 0x01\r
 .set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST\r
 .set scsiTarget_StatusReg__1__MASK, 0x02\r
 .set scsiTarget_StatusReg__1__POS, 1\r
 .set scsiTarget_StatusReg__2__MASK, 0x04\r
 .set scsiTarget_StatusReg__3__MASK, 0x08\r
 .set scsiTarget_StatusReg__3__POS, 3\r
 .set scsiTarget_StatusReg__MASK, 0x0F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK\r
-.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK\r
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL\r
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL\r
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK\r
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0\r
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1\r
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0\r
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1\r
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0\r
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1\r
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1\r
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0\r
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1\r
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1\r
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0\r
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1\r
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1\r
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0\r
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1\r
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB14_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB14_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB13_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB13_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB13_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB13_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB13_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB13_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB13_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB13_14_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB13_14_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB13_14_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB13_14_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB13_14_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB13_14_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB13_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB13_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB13_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB13_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB13_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB13_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB13_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB13_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB13_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
 \r
 /* SD_Clk_Ctl */\r
 .set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
 .set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
 \r
 /* USBFS_ep_0 */\r
 .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 /* USBFS_ep_1 */\r
 .set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_1__INTC_MASK, 0x02\r
-.set USBFS_ep_1__INTC_NUMBER, 1\r
+.set USBFS_ep_1__INTC_MASK, 0x01\r
+.set USBFS_ep_1__INTC_NUMBER, 0\r
 .set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
 .set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* USBFS_ep_2 */\r
 .set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_2__INTC_MASK, 0x04\r
-.set USBFS_ep_2__INTC_NUMBER, 2\r
+.set USBFS_ep_2__INTC_MASK, 0x02\r
+.set USBFS_ep_2__INTC_NUMBER, 1\r
 .set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 .set CYDEV_ECC_ENABLE, 0\r
 .set CYDEV_HEAP_SIZE, 0x1000\r
 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
-.set CYDEV_INTR_RISING, 0x00000001\r
+.set CYDEV_INTR_RISING, 0x00000000\r
 .set CYDEV_PROJ_TYPE, 2\r
 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1\r
 .set CYDEV_PROJ_TYPE_LOADABLE, 2\r
index 7e0fb10..9483441 100755 (executable)
@@ -3,34 +3,6 @@
     INCLUDE cydeviceiar.inc\r
     INCLUDE cydeviceiar_trm.inc\r
 \r
-/* SCSI_CMD_TIMER_TimerHW */\r
-SCSI_CMD_TIMER_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
-SCSI_CMD_TIMER_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
-SCSI_CMD_TIMER_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
-SCSI_CMD_TIMER_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
-SCSI_CMD_TIMER_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
-SCSI_CMD_TIMER_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
-SCSI_CMD_TIMER_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
-SCSI_CMD_TIMER_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
-SCSI_CMD_TIMER_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
-SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
-SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK EQU 0x01\r
-SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
-SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK EQU 0x01\r
-SCSI_CMD_TIMER_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
-SCSI_CMD_TIMER_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
-SCSI_CMD_TIMER_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
-\r
-/* SCSI_CMD_TIMER_ISR */\r
-SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_CMD_TIMER_ISR__INTC_MASK EQU 0x01\r
-SCSI_CMD_TIMER_ISR__INTC_NUMBER EQU 0\r
-SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
 /* USBFS_bus_reset */\r
 USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
@@ -532,8 +504,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
 SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
 SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
 SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
@@ -541,13 +513,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
 SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
 SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
 SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
@@ -557,9 +529,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
@@ -593,24 +565,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 /* SCSI_CTL_IO */\r
 SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
 SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
 \r
 /* SCSI_In_DBx */\r
 SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
@@ -1069,8 +1041,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02
 /* scsiTarget */\r
 scsiTarget_StatusReg__0__MASK EQU 0x01\r
 scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST\r
 scsiTarget_StatusReg__1__MASK EQU 0x02\r
 scsiTarget_StatusReg__1__POS EQU 1\r
 scsiTarget_StatusReg__2__MASK EQU 0x04\r
@@ -1078,80 +1050,76 @@ scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08\r
 scsiTarget_StatusReg__3__POS EQU 3\r
 scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL\r
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
 \r
 /* SD_Clk_Ctl */\r
 SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
 SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
 \r
 /* USBFS_ep_0 */\r
 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
@@ -1166,20 +1134,20 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 /* USBFS_ep_1 */\r
 USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x02\r
-USBFS_ep_1__INTC_NUMBER EQU 1\r
+USBFS_ep_1__INTC_MASK EQU 0x01\r
+USBFS_ep_1__INTC_NUMBER EQU 0\r
 USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
 \r
 /* USBFS_ep_2 */\r
 USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x04\r
-USBFS_ep_2__INTC_NUMBER EQU 2\r
+USBFS_ep_2__INTC_MASK EQU 0x02\r
+USBFS_ep_2__INTC_NUMBER EQU 1\r
 USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
 \r
@@ -2754,7 +2722,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0\r
 CYDEV_HEAP_SIZE EQU 0x1000\r
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000001\r
+CYDEV_INTR_RISING EQU 0x00000000\r
 CYDEV_PROJ_TYPE EQU 2\r
 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
 CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
index 257ff86..d206801 100755 (executable)
@@ -3,34 +3,6 @@ INCLUDED_CYFITTERRV_INC EQU 1
     GET cydevicerv.inc\r
     GET cydevicerv_trm.inc\r
 \r
-; SCSI_CMD_TIMER_TimerHW\r
-SCSI_CMD_TIMER_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
-SCSI_CMD_TIMER_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
-SCSI_CMD_TIMER_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
-SCSI_CMD_TIMER_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
-SCSI_CMD_TIMER_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
-SCSI_CMD_TIMER_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
-SCSI_CMD_TIMER_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
-SCSI_CMD_TIMER_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
-SCSI_CMD_TIMER_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
-SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
-SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK EQU 0x01\r
-SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
-SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK EQU 0x01\r
-SCSI_CMD_TIMER_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
-SCSI_CMD_TIMER_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
-SCSI_CMD_TIMER_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
-\r
-; SCSI_CMD_TIMER_ISR\r
-SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_CMD_TIMER_ISR__INTC_MASK EQU 0x01\r
-SCSI_CMD_TIMER_ISR__INTC_NUMBER EQU 0\r
-SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
 ; USBFS_bus_reset\r
 USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
@@ -532,8 +504,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
 SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
 SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
 SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
@@ -541,13 +513,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
 SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
 SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
 SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
@@ -557,9 +529,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
@@ -593,24 +565,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 ; SCSI_CTL_IO\r
 SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
 SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
 \r
 ; SCSI_In_DBx\r
 SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
@@ -1069,8 +1041,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02
 ; scsiTarget\r
 scsiTarget_StatusReg__0__MASK EQU 0x01\r
 scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST\r
 scsiTarget_StatusReg__1__MASK EQU 0x02\r
 scsiTarget_StatusReg__1__POS EQU 1\r
 scsiTarget_StatusReg__2__MASK EQU 0x04\r
@@ -1078,80 +1050,76 @@ scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08\r
 scsiTarget_StatusReg__3__POS EQU 3\r
 scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL\r
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
 \r
 ; SD_Clk_Ctl\r
 SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
 SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
 \r
 ; USBFS_ep_0\r
 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
@@ -1166,20 +1134,20 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 ; USBFS_ep_1\r
 USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x02\r
-USBFS_ep_1__INTC_NUMBER EQU 1\r
+USBFS_ep_1__INTC_MASK EQU 0x01\r
+USBFS_ep_1__INTC_NUMBER EQU 0\r
 USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
 \r
 ; USBFS_ep_2\r
 USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x04\r
-USBFS_ep_2__INTC_NUMBER EQU 2\r
+USBFS_ep_2__INTC_MASK EQU 0x02\r
+USBFS_ep_2__INTC_NUMBER EQU 1\r
 USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
 \r
@@ -2754,7 +2722,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0\r
 CYDEV_HEAP_SIZE EQU 0x1000\r
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000001\r
+CYDEV_INTR_RISING EQU 0x00000000\r
 CYDEV_PROJ_TYPE EQU 2\r
 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
 CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
index 1252396..92a14ac 100755 (executable)
@@ -58,8 +58,6 @@
 #include <USBFS_midi.h>\r
 #include <USBFS_pvt.h>\r
 #include <Bootloadable_1.h>\r
-#include <SCSI_CMD_TIMER.h>\r
-#include <SCSI_CMD_TIMER_ISR.h>\r
 #include <USBFS_Dm_aliases.h>\r
 #include <USBFS_Dm.h>\r
 #include <USBFS_Dp_aliases.h>\r
index 4575072..ad440cf 100755 (executable)
@@ -1,79 +1,12 @@
 <?xml version="1.0" encoding="utf-8"?>\r
 <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
-  <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
-    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  </block>\r
-  <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SCSI_CMD_TIMER_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SCSI_CMD_TIMER" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
-    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <register name="SCSI_CMD_TIMER_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">\r
-      <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
-    </register>\r
-    <register name="SCSI_CMD_TIMER_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">\r
-      <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
-      <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
-        <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
-        <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
-      </field>\r
-      <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
-      <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
-      <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
-      <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
-        <value name="Timer" value="0" desc="CMP and TC are output." />\r
-        <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
-      </field>\r
-      <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
-    </register>\r
-    <register name="SCSI_CMD_TIMER_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">\r
-      <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
-      <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
-        <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
-        <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
-      </field>\r
-      <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
-      <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
-      <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
-      <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
-    </register>\r
-    <register name="SCSI_CMD_TIMER_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">\r
-      <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
-        <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
-        <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
-        <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
-        <value name="Irq" value="11" desc="Timer runs until IRQ." />\r
-      </field>\r
-      <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
-      <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
-      <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
-        <value name="Equal" value="0" desc="Compare Equal " />\r
-        <value name="Less than" value="1" desc="Compare Less Than " />\r
-        <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
-        <value name="Greater" value="11" desc="Compare Greater Than ." />\r
-        <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
-      </field>\r
-      <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
-    </register>\r
-    <register name="SCSI_CMD_TIMER_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
-    <register name="SCSI_CMD_TIMER_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
-  </block>\r
+  <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
     <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
     <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
   </block>\r
   <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+    <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  </block>\r
+  <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
-    <register name="SD_Clk_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />\r
+    <register name="SD_Clk_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />\r
   </block>\r
-  <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_CTL_IO" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
-    <register name="SCSI_CTL_IO_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />\r
+    <register name="SCSI_CTL_IO_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />\r
   </block>\r
-  <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
 </blockRegMap>
\ No newline at end of file
index f94969f..e8e530b 100755 (executable)
Binary files a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit differ
index 2ee5808..5b2500f 100755 (executable)
 <CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
 <dependencies>\r
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="main.c" persistent=".\main.c">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="main.c" persistent="..\src\main.c">\r
 <Hidden v="False" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <build_action v="C_FILE" />\r
 <PropertyDeltas />\r
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="diagnostic.c" persistent=".\diagnostic.c">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="diagnostic.c" persistent="..\src\diagnostic.c">\r
 <Hidden v="False" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <build_action v="C_FILE" />\r
 <PropertyDeltas />\r
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="disk.c" persistent=".\disk.c">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="disk.c" persistent="..\src\disk.c">\r
 <Hidden v="False" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <build_action v="C_FILE" />\r
 <PropertyDeltas />\r
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="geometry.c" persistent=".\geometry.c">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="geometry.c" persistent="..\src\geometry.c">\r
 <Hidden v="False" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <build_action v="C_FILE" />\r
 <PropertyDeltas />\r
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="inquiry.c" persistent=".\inquiry.c">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="inquiry.c" persistent="..\src\inquiry.c">\r
 <Hidden v="False" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <build_action v="C_FILE" />\r
 <PropertyDeltas />\r
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="mode.c" persistent=".\mode.c">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="mode.c" persistent="..\src\mode.c">\r
 <Hidden v="False" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <build_action v="C_FILE" />\r
 <PropertyDeltas />\r
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="scsi.c" persistent=".\scsi.c">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="scsi.c" persistent="..\src\scsi.c">\r
 <Hidden v="False" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <build_action v="C_FILE" />\r
 <PropertyDeltas />\r
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="scsiPhy.c" persistent=".\scsiPhy.c">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" versio