Fix USB ID to identify V5.2 boards
authorMichael McMaster <michael@codesrc.com>
Mon, 12 Oct 2020 01:09:06 +0000 (11:09 +1000)
committerMichael McMaster <michael@codesrc.com>
Mon, 12 Oct 2020 01:09:06 +0000 (11:09 +1000)
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c
software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit
software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c
software/SCSI2SD/v5.2/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch
software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyfit
software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.rpt
software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader_timing.html

index 638f491..ab6eca2 100644 (file)
@@ -43,7 +43,7 @@ const uint8 CYCODE USBFS_DEVICE0_DESCR[18u] = {
 /* bMaxPacketSize0                         */ 0x08u,
 /* idVendor                                */ 0xB4u, 0x04u,
 /* idProduct                               */ 0x37u, 0x13u,
-/* bcdDevice                               */ 0x03u, 0x30u,
+/* bcdDevice                               */ 0x04u, 0x30u,
 /* iManufacturer                           */ 0x02u,
 /* iProduct                                */ 0x01u,
 /* iSerialNumber                           */ 0x80u,
index 3012ade..8ad4f7e 100644 (file)
@@ -1104,7 +1104,7 @@ const uint8 cy_bootloader[] = {
     0x10u, 0xBDu, 0x03u, 0x46u, 0x02u, 0x44u, 0x93u, 0x42u,
     0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u,
     0x70u, 0x47u, 0x00u, 0x00u, 0x00u, 0x25u, 0x00u, 0x00u,
-    0xE6u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0xE5u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x50u, 0x51u, 0x00u, 0x40u, 0x10u, 0x00u, 0x00u, 0x00u,
     0x01u, 0x40u, 0x00u, 0x10u, 0x00u, 0x14u, 0x01u, 0x40u,
     0x00u, 0x08u, 0x00u, 0x40u, 0x01u, 0x40u, 0x00u, 0x0Au,
@@ -1173,7 +1173,7 @@ const uint8 cy_bootloader[] = {
     0x07u, 0x05u, 0x01u, 0x03u, 0x40u, 0x00u, 0x01u, 0x07u,
     0x05u, 0x82u, 0x03u, 0x40u, 0x00u, 0x01u, 0x12u, 0x01u,
     0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x08u, 0xB4u, 0x04u,
-    0x1Du, 0xB7u, 0x03u, 0x30u, 0x01u, 0x02u, 0x80u, 0x01u,
+    0x1Du, 0xB7u, 0x04u, 0x30u, 0x01u, 0x02u, 0x80u, 0x01u,
     0xF8u, 0xB5u, 0x00u, 0xBFu, 0xF8u, 0xBCu, 0x08u, 0xBCu,
     0x9Eu, 0x46u, 0x70u, 0x47u, 0x51u, 0x00u, 0x00u, 0x00u,
     0xE9u, 0x03u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x00u, 0xBFu,
index cb211a9..c125153 100644 (file)
Binary files a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit differ
index aec23a1..fbbca47 100644 (file)
Binary files a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ
index 67c28b3..ba28a23 100644 (file)
@@ -45,7 +45,7 @@ const uint8 CYCODE USBFS_DEVICE0_DESCR[18u] = {
 /* bMaxPacketSize0                         */ 0x08u,
 /* idVendor                                */ 0xB4u, 0x04u,
 /* idProduct                               */ 0x1Du, 0xB7u,
-/* bcdDevice                               */ 0x03u, 0x30u,
+/* bcdDevice                               */ 0x04u, 0x30u,
 /* iManufacturer                           */ 0x01u,
 /* iProduct                                */ 0x02u,
 /* iSerialNumber                           */ 0x80u,
index 4925ad2..51e3e9c 100644 (file)
Binary files a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch differ
index 2d60b76..d467eea 100644 (file)
Binary files a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyfit and b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyfit differ
index 3ca2f53..92ea60e 100644 (file)
@@ -1,13 +1,13 @@
-Loading plugins phase: Elapsed time ==> 0s.111ms
+Loading plugins phase: Elapsed time ==> 0s.109ms
 <CYPRESSTAG name="CyDsfit arguments...">
 cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
 </CYPRESSTAG>
 <CYPRESSTAG name="Design elaboration results...">
 </CYPRESSTAG>
-Elaboration phase: Elapsed time ==> 1s.455ms
+Elaboration phase: Elapsed time ==> 1s.465ms
 <CYPRESSTAG name="HDL generation results...">
 </CYPRESSTAG>
-HDL generation phase: Elapsed time ==> 0s.042ms
+HDL generation phase: Elapsed time ==> 0s.041ms
 <CYPRESSTAG name="Synthesis results...">
 
      | | | | | | |
@@ -41,7 +41,7 @@ Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Micha
 ======================================================================
 
 vlogfe V6.3 IR 41:  Verilog parser
-Tue Sep 29 22:08:40 2020
+Mon Oct 12 10:51:56 2020
 
 
 ======================================================================
@@ -51,7 +51,7 @@ Options  :    -yv2 -q10 USB_Bootloader.v
 ======================================================================
 
 vpp V6.3 IR 41:  Verilog Pre-Processor
-Tue Sep 29 22:08:40 2020
+Mon Oct 12 10:51:56 2020
 
 Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'
 Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'
@@ -82,7 +82,7 @@ Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Micha
 ======================================================================
 
 tovif V6.3 IR 41:  High-level synthesis
-Tue Sep 29 22:08:40 2020
+Mon Oct 12 10:51:56 2020
 
 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'.
 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'.
@@ -108,7 +108,7 @@ Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Micha
 ======================================================================
 
 topld V6.3 IR 41:  Synthesis and optimization
-Tue Sep 29 22:08:40 2020
+Mon Oct 12 10:51:56 2020
 
 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'.
 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'.
@@ -243,14 +243,14 @@ CYPRESS_DIR    : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\wa
 Warp Program   : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe
 Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog
 </CYPRESSTAG>
-Warp synthesis phase: Elapsed time ==> 0s.454ms
+Warp synthesis phase: Elapsed time ==> 0s.471ms
 <CYPRESSTAG name="Fitter results...">
 <CYPRESSTAG name="Fitter startup details...">
-cyp3fit: V4.2.0.641, Family: PSoC3, Started at: Tuesday, 29 September 2020 22:08:40
+cyp3fit: V4.2.0.641, Family: PSoC3, Started at: Monday, 12 October 2020 10:51:56
 Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog
 </CYPRESSTAG>
 <CYPRESSTAG name="Design parsing">
-Design parsing phase: Elapsed time ==> 0s.010ms
+Design parsing phase: Elapsed time ==> 0s.009ms
 </CYPRESSTAG>
 <CYPRESSTAG name="Tech Mapping">
 <CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">
@@ -1659,8 +1659,8 @@ SAR ADC                       :    0 :    1 :    1 :  0.00 %
 DAC                           :      :      :      :        
   VIDAC                       :    0 :    1 :    1 :  0.00 %
 </CYPRESSTAG>
-Technology Mapping: Elapsed time ==> 0s.071ms
-Tech Mapping phase: Elapsed time ==> 0s.129ms
+Technology Mapping: Elapsed time ==> 0s.073ms
+Tech Mapping phase: Elapsed time ==> 0s.130ms
 </CYPRESSTAG>
 <CYPRESSTAG name="Analog Placement">
 Initial Analog Placement Results:
@@ -1697,7 +1697,7 @@ IO_3@[IOP=(15)][IoId=(3)] : TERM_EN(0) (fixed)
 IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed)
 IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed)
 USB[0]@[FFB(USB,0)] : \USBFS:USB\
-Analog Placement phase: Elapsed time ==> 0s.049ms
+Analog Placement phase: Elapsed time ==> 0s.053ms
 </CYPRESSTAG>
 <CYPRESSTAG name="Analog Routing">
 Analog Routing phase: Elapsed time ==> 0s.000ms
@@ -1715,7 +1715,7 @@ Dump of CyP35AnalogRoutingResultsDB
 IsVddaHalfUsedForComp = False
 IsVddaHalfUsedForSar0 = False
 IsVddaHalfUsedForSar1 = False
-Analog Code Generation phase: Elapsed time ==> 0s.253ms
+Analog Code Generation phase: Elapsed time ==> 0s.328ms
 </CYPRESSTAG>
 <CYPRESSTAG name="Digital Placement">
 <CYPRESSTAG name="Detailed placement messages">
@@ -1734,7 +1734,7 @@ PLD Packing: Elapsed time ==> 0s.000ms
 Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
 <CYPRESSTAG name="Final Partitioning Summary">
 Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
-Partitioning: Elapsed time ==> 0s.029ms
+Partitioning: Elapsed time ==> 0s.028ms
 </CYPRESSTAG>
 <CYPRESSTAG name="Final Placement Summary">
 
@@ -3336,33 +3336,33 @@ Port | Pin | Fixed |      Type |       Drive Mode |            Name | Connection
 </CYPRESSTAG>
 </CYPRESSTAG>
 </CYPRESSTAG>
-Digital component placer commit/Report: Elapsed time ==> 0s.047ms
-Digital Placement phase: Elapsed time ==> 0s.979ms
+Digital component placer commit/Report: Elapsed time ==> 0s.048ms
+Digital Placement phase: Elapsed time ==> 0s.964ms
 </CYPRESSTAG>
 <CYPRESSTAG name="Digital Routing">
 "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\bin/sjrouter.exe" --xml-path "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\psoc5/psoc5lp/route_arch-rrg.cydata" --vh2-path "USB_Bootloader_r.vh2" --pcf-path "USB_Bootloader.pco" --des-name "USB_Bootloader" --dsf-path "USB_Bootloader.dsf" --sdc-path "USB_Bootloader.sdc" --lib-path "USB_Bootloader_r.lib"
 Routing successful.
-Digital Routing phase: Elapsed time ==> 1s.052ms
+Digital Routing phase: Elapsed time ==> 1s.346ms
 </CYPRESSTAG>
 <CYPRESSTAG name="Bitstream Generation">
-Bitstream Generation phase: Elapsed time ==> 0s.154ms
+Bitstream Generation phase: Elapsed time ==> 0s.136ms
 </CYPRESSTAG>
 <CYPRESSTAG name="Bitstream Verification">
 Bitstream Verification phase: Elapsed time ==> 0s.030ms
 </CYPRESSTAG>
 <CYPRESSTAG name="Static timing analysis">
 Timing report is in USB_Bootloader_timing.html.
-Static timing analysis phase: Elapsed time ==> 0s.224ms
+Static timing analysis phase: Elapsed time ==> 0s.229ms
 </CYPRESSTAG>
 <CYPRESSTAG name="Data reporting">
 Data reporting phase: Elapsed time ==> 0s.000ms
 </CYPRESSTAG>
 <CYPRESSTAG name="Database update...">
-Design database save phase: Elapsed time ==> 0s.163ms
+Design database save phase: Elapsed time ==> 0s.159ms
 </CYPRESSTAG>
-cydsfit: Elapsed time ==> 3s.066ms
+cydsfit: Elapsed time ==> 3s.406ms
 </CYPRESSTAG>
-Fitter phase: Elapsed time ==> 3s.068ms
-API generation phase: Elapsed time ==> 1s.280ms
-Dependency generation phase: Elapsed time ==> 0s.006ms
+Fitter phase: Elapsed time ==> 3s.407ms
+API generation phase: Elapsed time ==> 1s.335ms
+Dependency generation phase: Elapsed time ==> 0s.009ms
 Cleanup phase: Elapsed time ==> 0s.000ms
index a6b325d..cca1641 100644 (file)
@@ -539,7 +539,7 @@ function getElementsByClass(rootNode, elemName, className)
 <tr> <td class="prop"> Project :</td>
 <td class="proptext"> USB_Bootloader</td></tr>
 <tr> <td class="prop"> Build Time :</td>
-<td class="proptext"> 09/29/20 22:08:43</td></tr>
+<td class="proptext"> 10/12/20 10:51:59</td></tr>
 <tr> <td class="prop"> Device :</td>
 <td class="proptext"> CY8C5267AXI-LP051</td></tr>
 <tr> <td class="prop"> Temperature :</td>