SCSI data read/write implemented using the PSoC datapath
authorMichael McMaster <michael@codesrc.com>
Sun, 20 Oct 2013 08:27:57 +0000 (18:27 +1000)
committerMichael McMaster <michael@codesrc.com>
Sun, 20 Oct 2013 08:27:57 +0000 (18:27 +1000)
Moved some configuration parameters into EEPROM

58 files changed:
STATUS
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c [new file with mode: 0644]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h [new file with mode: 0644]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN_aliases.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c [new file with mode: 0644]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h [new file with mode: 0644]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ID_aliases.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_INT.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PM.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PVT.h [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/config.hex
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.c [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/eeprom.hex
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/post_link.bat [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml [deleted file]
software/SCSI2SD/SCSI2SD.cydsn/OddParityGen/OddParityGen.cysym [new file with mode: 0755]
software/SCSI2SD/SCSI2SD.cydsn/OddParityGen/OddParityGen.v [new file with mode: 0755]
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx [new file with mode: 0644]
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd [new file with mode: 0644]
software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
software/SCSI2SD/SCSI2SD.cydsn/config.c [new file with mode: 0755]
software/SCSI2SD/SCSI2SD.cydsn/config.h [new file with mode: 0755]
software/SCSI2SD/SCSI2SD.cydsn/disk.c
software/SCSI2SD/SCSI2SD.cydsn/inquiry.c
software/SCSI2SD/SCSI2SD.cydsn/main.c
software/SCSI2SD/SCSI2SD.cydsn/scsi.c
software/SCSI2SD/SCSI2SD.cydsn/scsi.h
software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c
software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h
software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym [new file with mode: 0755]
software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v [new file with mode: 0755]
software/SCSI2SD/SCSI2SD.cydsn/sd.c
software/SCSI2SD/SCSI2SD.cydsn/sd.h

diff --git a/STATUS b/STATUS
index dc2d8ce..ab682ae 100644 (file)
--- a/STATUS
+++ b/STATUS
@@ -3,11 +3,12 @@ assignments are incorrect.
 
 - USB bootloader is not implemented yet.
 
-- Configuration options are not yet loaded from EEPROM.
 - Configuration options cannot be set via USB.
        - SCSI ID hardcoded to 0
        - Partity checking is on
        - Unit Attention Condition is off
+       - SPI overclock to 32MHz off.
 
 - DMA is not used for SPI transfers
+- Parity checking not implemented for the PSoC Datapath implementation
 
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c
new file mode 100644 (file)
index 0000000..0668305
--- /dev/null
@@ -0,0 +1,511 @@
+/*******************************************************************************\r
+* File Name: CFG_EEPROM.c\r
+* Version 2.10\r
+*\r
+* Description:\r
+*  Provides the source code to the API for the EEPROM component.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "CFG_EEPROM.h"\r
+\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+\r
+    /*******************************************************************************\r
+    * Function Name: CFG_EEPROM_Enable\r
+    ********************************************************************************\r
+    *\r
+    * Summary:\r
+    *  Enable the EEPROM.\r
+    *\r
+    * Parameters:\r
+    *  None\r
+    *\r
+    * Return:\r
+    *  None\r
+    *\r
+    *******************************************************************************/\r
+    void CFG_EEPROM_Enable(void) \r
+    {\r
+        CyEEPROM_Start();\r
+    }\r
+\r
+\r
+    /*******************************************************************************\r
+    * Function Name: CFG_EEPROM_Start\r
+    ********************************************************************************\r
+    *\r
+    * Summary:\r
+    *  Starts EEPROM.\r
+    *\r
+    * Parameters:\r
+    *  None\r
+    *\r
+    * Return:\r
+    *  None\r
+    *\r
+    *******************************************************************************/\r
+    void CFG_EEPROM_Start(void) \r
+    {\r
+        /* Enable the EEPROM */\r
+        CFG_EEPROM_Enable();\r
+    }\r
+\r
+\r
+    /*******************************************************************************\r
+    * Function Name: CFG_EEPROM_Stop\r
+    ********************************************************************************\r
+    *\r
+    * Summary:\r
+    *  Stops and powers down EEPROM.\r
+    *\r
+    * Parameters:\r
+    *  None\r
+    *\r
+    * Return:\r
+    *  None\r
+    *\r
+    *******************************************************************************/\r
+    void CFG_EEPROM_Stop (void) \r
+    {\r
+        /* Disable EEPROM */\r
+        CyEEPROM_Stop();\r
+    }\r
+\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_EraseSector\r
+********************************************************************************\r
+*\r
+* Summary:\r
+*  Erases a sector of memory. This function blocks until the operation is\r
+*  complete.\r
+*\r
+* Parameters:\r
+*  sectorNumber:  Sector number to erase.\r
+*\r
+* Return:\r
+*  CYRET_SUCCESS, if the operation was successful.\r
+*  CYRET_BAD_PARAM, if the parameter sectorNumber out of range.\r
+*  CYRET_LOCKED, if the spc is being used.\r
+*  CYRET_UNKNOWN, if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) \r
+{\r
+    cystatus status;\r
+\r
+    /* Start the SPC */\r
+    CySpcStart();\r
+\r
+    if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)\r
+    {\r
+        /* See if we can get the SPC. */\r
+        if(CySpcLock() == CYRET_SUCCESS)\r
+        {\r
+            #if(CY_PSOC5A)\r
+\r
+                /* Plan for failure */\r
+                status = CYRET_UNKNOWN;\r
+\r
+                /* Command to load a row of data */\r
+                if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, 0, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)\r
+                {\r
+                    while(CY_SPC_BUSY)\r
+                    {\r
+                        /* Wait until SPC becomes idle */\r
+                    }\r
+\r
+                    /* SPC is idle now */\r
+                    if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+                    {\r
+                        status = CYRET_SUCCESS;\r
+                    }\r
+                }\r
+\r
+                /* Command to erase a sector */\r
+                if(status == CYRET_SUCCESS)\r
+                {\r
+\r
+            #endif /* (CY_PSOC5A) */\r
+\r
+                    if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)\r
+                    {\r
+                        /* Plan for failure */\r
+                        status = CYRET_UNKNOWN;\r
+\r
+                        while(CY_SPC_BUSY)\r
+                        {\r
+                            /* Wait until SPC becomes idle */\r
+                        }\r
+\r
+                        /* SPC is idle now */\r
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+                        {\r
+                            status = CYRET_SUCCESS;\r
+                        }\r
+                    }\r
+                    else\r
+                    {\r
+                        status = CYRET_UNKNOWN;\r
+                    }\r
+\r
+            #if(CY_PSOC5A)\r
+\r
+                }\r
+                else\r
+                {\r
+                    status = CYRET_UNKNOWN;\r
+                }\r
+\r
+            #endif /* (CY_PSOC5A) */\r
+\r
+                /* Unlock the SPC so someone else can use it. */\r
+                CySpcUnlock();\r
+        }\r
+        else\r
+        {\r
+            status = CYRET_LOCKED;\r
+        }\r
+    }\r
+    else\r
+    {\r
+        status = CYRET_BAD_PARAM;\r
+    }\r
+\r
+    return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+*  Writes a row, CYDEV_EEPROM_ROW_SIZE of data to the EEPROM. This is\r
+*  a blocking call. It will not return until the function succeeds or fails.\r
+*\r
+* Parameters:\r
+*  rowData:  Address of the data to write to the EEPROM.\r
+*  rowNumber:  EEPROM row number to program.\r
+*\r
+* Return:\r
+*  CYRET_SUCCESS, if the operation was successful.\r
+*  CYRET_BAD_PARAM, if the parameter rowNumber out of range.\r
+*  CYRET_LOCKED, if the spc is being used.\r
+*  CYRET_UNKNOWN, if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) \r
+{\r
+    cystatus status;\r
+\r
+    /* Start the SPC */\r
+    CySpcStart();\r
+\r
+    if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)\r
+    {\r
+        /* See if we can get the SPC. */\r
+        if(CySpcLock() == CYRET_SUCCESS)\r
+        {\r
+            /* Plan for failure */\r
+            status = CYRET_UNKNOWN;\r
+\r
+            /* Command to load a row of data */\r
+            if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)\r
+            {\r
+                while(CY_SPC_BUSY)\r
+                {\r
+                    /* Wait until SPC becomes idle */\r
+                }\r
+\r
+                /* SPC is idle now */\r
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+                {\r
+                    status = CYRET_SUCCESS;\r
+                }\r
+\r
+                /* Command to erase and program the row. */\r
+                if(status == CYRET_SUCCESS)\r
+                {\r
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],\r
+                    dieTemperature[1]) == CYRET_STARTED)\r
+                    {\r
+                        /* Plan for failure */\r
+                        status = CYRET_UNKNOWN;\r
+\r
+                        while(CY_SPC_BUSY)\r
+                        {\r
+                            /* Wait until SPC becomes idle */\r
+                        }\r
+\r
+                        /* SPC is idle now */\r
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+                        {\r
+                            status = CYRET_SUCCESS;\r
+                        }\r
+                    }\r
+                    else\r
+                    {\r
+                        status = CYRET_UNKNOWN;\r
+                    }\r
+                }\r
+                else\r
+                {\r
+                    status = CYRET_UNKNOWN;\r
+                }\r
+            }\r
+\r
+            /* Unlock the SPC so someone else can use it. */\r
+            CySpcUnlock();\r
+        }\r
+        else\r
+        {\r
+            status = CYRET_LOCKED;\r
+        }\r
+    }\r
+    else\r
+    {\r
+        status = CYRET_BAD_PARAM;\r
+    }\r
+\r
+    return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_StartWrite\r
+********************************************************************************\r
+*\r
+* Summary:\r
+*  Starts the SPC write function. This function does not block, it returns\r
+*  once the command has begun the SPC write function. This function must be used\r
+*  in combination with CFG_EEPROM_QueryWrite(). Once this function has\r
+*  been called the SPC will be locked until CFG_EEPROM_QueryWrite()\r
+*  returns CYRET_SUCCESS.\r
+*\r
+* Parameters:\r
+*  rowData:  Address of buffer containing a row of data to write to the EEPROM.\r
+*  rowNumber:  EEPROM row number to program.\r
+*\r
+* Return:\r
+*  CYRET_STARTED, if the spc command to write was successfuly started.\r
+*  CYRET_BAD_PARAM, if the parameter rowNumber out of range.\r
+*  CYRET_LOCKED, if the spc is being used.\r
+*  CYRET_UNKNOWN, if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \\r
+\r
+{\r
+    cystatus status;\r
+\r
+    if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)\r
+    {\r
+        /* See if we can get the SPC. */\r
+        if(CySpcLock() == CYRET_SUCCESS)\r
+        {\r
+            /* Plan for failure */\r
+            status = CYRET_UNKNOWN;\r
+\r
+            /* Command to load a row of data */\r
+            if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)\r
+            {\r
+                while(CY_SPC_BUSY)\r
+                {\r
+                    /* Wait until SPC becomes idle */\r
+                }\r
+\r
+                /* SPC is idle now */\r
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+                {\r
+                    status = CYRET_SUCCESS;\r
+                }\r
+\r
+                /* Command to erase and program the row. */\r
+                if(status == CYRET_SUCCESS)\r
+                {\r
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],\r
+                    dieTemperature[1]) == CYRET_STARTED)\r
+                    {\r
+                        status = CYRET_STARTED;\r
+                    }\r
+                    else\r
+                    {\r
+                        status = CYRET_UNKNOWN;\r
+                    }\r
+                }\r
+                else\r
+                {\r
+                    status = CYRET_UNKNOWN;\r
+                }\r
+            }\r
+        }\r
+        else\r
+        {\r
+            status = CYRET_LOCKED;\r
+        }\r
+    }\r
+    else\r
+    {\r
+        status = CYRET_BAD_PARAM;\r
+    }\r
+\r
+    return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_QueryWrite\r
+********************************************************************************\r
+*\r
+* Summary:\r
+*  Checks the state of write to EEPROM. This function must be called until\r
+*  the return value is not CYRET_STARTED.\r
+*\r
+* Parameters:\r
+*  None\r
+*\r
+* Return:\r
+*  CYRET_STARTED, if the spc command is still processing.\r
+*  CYRET_SUCCESS, if the operation was successful.\r
+*  CYRET_UNKNOWN, if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CFG_EEPROM_QueryWrite(void) \r
+{\r
+    cystatus status;\r
+\r
+    /* Check if SPC is idle */\r
+    if(CY_SPC_IDLE)\r
+    {\r
+        /* SPC is idle now */\r
+        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+        {\r
+            status = CYRET_SUCCESS;\r
+        }\r
+        else\r
+        {\r
+            status = CYRET_UNKNOWN;\r
+        }\r
+\r
+        /* Unlock the SPC so someone else can use it. */\r
+        CySpcUnlock();\r
+    }\r
+    else\r
+    {\r
+        status = CYRET_STARTED;\r
+    }\r
+\r
+    return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_ByteWrite\r
+********************************************************************************\r
+*\r
+* Summary:\r
+*  Writes a byte of data to the EEPROM. This is a blocking call. It will not\r
+*  return until the function succeeds or fails.\r
+*\r
+* Parameters:\r
+*  dataByte:  Byte of data to write to the EEPROM.\r
+*  rowNumber:  EEPROM row number to program.\r
+*  byteNumber:  Byte number within the row to program.\r
+*\r
+* Return:\r
+*  CYRET_SUCCESS, if the operation was successful.\r
+*  CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber out of range.\r
+*  CYRET_LOCKED, if the spc is being used.\r
+*  CYRET_UNKNOWN, if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \\r
+\r
+{\r
+    cystatus status;\r
+\r
+    /* Start the SPC */\r
+    CySpcStart();\r
+\r
+    if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW))\r
+    {\r
+        /* See if we can get the SPC. */\r
+        if(CySpcLock() == CYRET_SUCCESS)\r
+        {\r
+            /* Plan for failure */\r
+            status = CYRET_UNKNOWN;\r
+\r
+            /* Command to load a byte of data */\r
+            if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\\r
+                                                                CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED)\r
+            {\r
+                while(CY_SPC_BUSY)\r
+                {\r
+                    /* Wait until SPC becomes idle */\r
+                }\r
+\r
+                /* SPC is idle now */\r
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+                {\r
+                    status = CYRET_SUCCESS;\r
+                }\r
+\r
+                /* Command to erase and program the row. */\r
+                if(status == CYRET_SUCCESS)\r
+                {\r
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],\r
+                    dieTemperature[1]) == CYRET_STARTED)\r
+                    {\r
+                        /* Plan for failure */\r
+                        status = CYRET_UNKNOWN;\r
+\r
+                        while(CY_SPC_BUSY)\r
+                        {\r
+                            /* Wait until SPC becomes idle */\r
+                        }\r
+\r
+                        /* SPC is idle now */\r
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+                        {\r
+                            status = CYRET_SUCCESS;\r
+                        }\r
+                    }\r
+                    else\r
+                    {\r
+                        status = CYRET_UNKNOWN;\r
+                    }\r
+                }\r
+                else\r
+                {\r
+                    status = CYRET_UNKNOWN;\r
+                }\r
+            }\r
+\r
+            /* Unlock the SPC so someone else can use it. */\r
+            CySpcUnlock();\r
+        }\r
+        else\r
+        {\r
+            status = CYRET_LOCKED;\r
+        }\r
+    }\r
+    else\r
+    {\r
+        status = CYRET_BAD_PARAM;\r
+    }\r
+\r
+    return(status);\r
+}\r
+\r
+\r
+/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h
new file mode 100644 (file)
index 0000000..e6a5f0f
--- /dev/null
@@ -0,0 +1,60 @@
+/*******************************************************************************\r
+* File Name: CFG_EEPROM.h\r
+* Version 2.10\r
+*\r
+* Description:\r
+*  Provides the function definitions for the EEPROM APIs.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_EEPROM_CFG_EEPROM_H)\r
+#define CY_EEPROM_CFG_EEPROM_H\r
+\r
+#include "cydevice_trm.h"\r
+#include "CyFlash.h"\r
+\r
+#if !defined(CY_PSOC5LP)\r
+    #error Component EEPROM_v2_10 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5LP) */\r
+\r
+\r
+/***************************************\r
+*        Function Prototypes\r
+***************************************/\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP) \r
+    void CFG_EEPROM_Enable(void) ;\r
+    void CFG_EEPROM_Start(void); \r
+    void CFG_EEPROM_Stop(void) ;\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ;\r
+cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ;\r
+cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \\r
+            ;\r
+cystatus CFG_EEPROM_QueryWrite(void) ;\r
+cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \\r
+            ;\r
+\r
+\r
+/****************************************\r
+*           API Constants\r
+****************************************/\r
+\r
+#define CFG_EEPROM_EEPROM_SIZE                 CYDEV_EE_SIZE\r
+#define CFG_EEPROM_SPC_BYTE_WRITE_SIZE    (0x01u)\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from EEPROM 2.10\r
+*******************************************************************************/\r
+#define SPC_BYTE_WRITE_SIZE             (CFG_EEPROM_SPC_BYTE_WRITE_SIZE)\r
+\r
+#endif /* CY_EEPROM_CFG_EEPROM_H */\r
+\r
+/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.c
deleted file mode 100644 (file)
index d5642c3..0000000
+++ /dev/null
@@ -1,137 +0,0 @@
-/*******************************************************************************\r
-* File Name: PARITY_EN.c  \r
-* Version 1.90\r
-*\r
-* Description:\r
-*  This file contains API to enable firmware control of a Pins component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "cytypes.h"\r
-#include "PARITY_EN.h"\r
-\r
-/* APIs are not generated for P15[7:6] on PSoC 5 */\r
-#if !(CY_PSOC5A &&\\r
-        PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0))\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: PARITY_EN_Write\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Assign a new value to the digital port's data output register.  \r
-*\r
-* Parameters:  \r
-*  prtValue:  The value to be assigned to the Digital Port. \r
-*\r
-* Return: \r
-*  None\r
-*  \r
-*******************************************************************************/\r
-void PARITY_EN_Write(uint8 value) \r
-{\r
-    uint8 staticBits = (PARITY_EN_DR & (uint8)(~PARITY_EN_MASK));\r
-    PARITY_EN_DR = staticBits | ((uint8)(value << PARITY_EN_SHIFT) & PARITY_EN_MASK);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: PARITY_EN_SetDriveMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Change the drive mode on the pins of the port.\r
-* \r
-* Parameters:  \r
-*  mode:  Change the pins to this drive mode.\r
-*\r
-* Return: \r
-*  None\r
-*\r
-*******************************************************************************/\r
-void PARITY_EN_SetDriveMode(uint8 mode) \r
-{\r
-       CyPins_SetPinDriveMode(PARITY_EN_0, mode);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: PARITY_EN_Read\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Read the current value on the pins of the Digital Port in right justified \r
-*  form.\r
-*\r
-* Parameters:  \r
-*  None\r
-*\r
-* Return: \r
-*  Returns the current value of the Digital Port as a right justified number\r
-*  \r
-* Note:\r
-*  Macro PARITY_EN_ReadPS calls this function. \r
-*  \r
-*******************************************************************************/\r
-uint8 PARITY_EN_Read(void) \r
-{\r
-    return (PARITY_EN_PS & PARITY_EN_MASK) >> PARITY_EN_SHIFT;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: PARITY_EN_ReadDataReg\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Read the current value assigned to a Digital Port's data output register\r
-*\r
-* Parameters:  \r
-*  None \r
-*\r
-* Return: \r
-*  Returns the current value assigned to the Digital Port's data output register\r
-*  \r
-*******************************************************************************/\r
-uint8 PARITY_EN_ReadDataReg(void) \r
-{\r
-    return (PARITY_EN_DR & PARITY_EN_MASK) >> PARITY_EN_SHIFT;\r
-}\r
-\r
-\r
-/* If Interrupts Are Enabled for this Pins component */ \r
-#if defined(PARITY_EN_INTSTAT) \r
-\r
-    /*******************************************************************************\r
-    * Function Name: PARITY_EN_ClearInterrupt\r
-    ********************************************************************************\r
-    * Summary:\r
-    *  Clears any active interrupts attached to port and returns the value of the \r
-    *  interrupt status register.\r
-    *\r
-    * Parameters:  \r
-    *  None \r
-    *\r
-    * Return: \r
-    *  Returns the value of the interrupt status register\r
-    *  \r
-    *******************************************************************************/\r
-    uint8 PARITY_EN_ClearInterrupt(void) \r
-    {\r
-        return (PARITY_EN_INTSTAT & PARITY_EN_MASK) >> PARITY_EN_SHIFT;\r
-    }\r
-\r
-#endif /* If Interrupts Are Enabled for this Pins component */ \r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
-    \r
-/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.h
deleted file mode 100644 (file)
index 75953b0..0000000
+++ /dev/null
@@ -1,130 +0,0 @@
-/*******************************************************************************\r
-* File Name: PARITY_EN.h  \r
-* Version 1.90\r
-*\r
-* Description:\r
-*  This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_PARITY_EN_H) /* Pins PARITY_EN_H */\r
-#define CY_PINS_PARITY_EN_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-#include "cypins.h"\r
-#include "PARITY_EN_aliases.h"\r
-\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
-/* APIs are not generated for P15[7:6] */\r
-#if !(CY_PSOC5A &&\\r
-        PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0))\r
-\r
-\r
-/***************************************\r
-*        Function Prototypes             \r
-***************************************/    \r
-\r
-void    PARITY_EN_Write(uint8 value) ;\r
-void    PARITY_EN_SetDriveMode(uint8 mode) ;\r
-uint8   PARITY_EN_ReadDataReg(void) ;\r
-uint8   PARITY_EN_Read(void) ;\r
-uint8   PARITY_EN_ClearInterrupt(void) ;\r
-\r
-\r
-/***************************************\r
-*           API Constants        \r
-***************************************/\r
-\r
-/* Drive Modes */\r
-#define PARITY_EN_DM_ALG_HIZ         PIN_DM_ALG_HIZ\r
-#define PARITY_EN_DM_DIG_HIZ         PIN_DM_DIG_HIZ\r
-#define PARITY_EN_DM_RES_UP          PIN_DM_RES_UP\r
-#define PARITY_EN_DM_RES_DWN         PIN_DM_RES_DWN\r
-#define PARITY_EN_DM_OD_LO           PIN_DM_OD_LO\r
-#define PARITY_EN_DM_OD_HI           PIN_DM_OD_HI\r
-#define PARITY_EN_DM_STRONG          PIN_DM_STRONG\r
-#define PARITY_EN_DM_RES_UPDWN       PIN_DM_RES_UPDWN\r
-\r
-/* Digital Port Constants */\r
-#define PARITY_EN_MASK               PARITY_EN__MASK\r
-#define PARITY_EN_SHIFT              PARITY_EN__SHIFT\r
-#define PARITY_EN_WIDTH              1u\r
-\r
-\r
-/***************************************\r
-*             Registers        \r
-***************************************/\r
-\r
-/* Main Port Registers */\r
-/* Pin State */\r
-#define PARITY_EN_PS                     (* (reg8 *) PARITY_EN__PS)\r
-/* Data Register */\r
-#define PARITY_EN_DR                     (* (reg8 *) PARITY_EN__DR)\r
-/* Port Number */\r
-#define PARITY_EN_PRT_NUM                (* (reg8 *) PARITY_EN__PRT) \r
-/* Connect to Analog Globals */                                                  \r
-#define PARITY_EN_AG                     (* (reg8 *) PARITY_EN__AG)                       \r
-/* Analog MUX bux enable */\r
-#define PARITY_EN_AMUX                   (* (reg8 *) PARITY_EN__AMUX) \r
-/* Bidirectional Enable */                                                        \r
-#define PARITY_EN_BIE                    (* (reg8 *) PARITY_EN__BIE)\r
-/* Bit-mask for Aliased Register Access */\r
-#define PARITY_EN_BIT_MASK               (* (reg8 *) PARITY_EN__BIT_MASK)\r
-/* Bypass Enable */\r
-#define PARITY_EN_BYP                    (* (reg8 *) PARITY_EN__BYP)\r
-/* Port wide control signals */                                                   \r
-#define PARITY_EN_CTL                    (* (reg8 *) PARITY_EN__CTL)\r
-/* Drive Modes */\r
-#define PARITY_EN_DM0                    (* (reg8 *) PARITY_EN__DM0) \r
-#define PARITY_EN_DM1                    (* (reg8 *) PARITY_EN__DM1)\r
-#define PARITY_EN_DM2                    (* (reg8 *) PARITY_EN__DM2) \r
-/* Input Buffer Disable Override */\r
-#define PARITY_EN_INP_DIS                (* (reg8 *) PARITY_EN__INP_DIS)\r
-/* LCD Common or Segment Drive */\r
-#define PARITY_EN_LCD_COM_SEG            (* (reg8 *) PARITY_EN__LCD_COM_SEG)\r
-/* Enable Segment LCD */\r
-#define PARITY_EN_LCD_EN                 (* (reg8 *) PARITY_EN__LCD_EN)\r
-/* Slew Rate Control */\r
-#define PARITY_EN_SLW                    (* (reg8 *) PARITY_EN__SLW)\r
-\r
-/* DSI Port Registers */\r
-/* Global DSI Select Register */\r
-#define PARITY_EN_PRTDSI__CAPS_SEL       (* (reg8 *) PARITY_EN__PRTDSI__CAPS_SEL) \r
-/* Double Sync Enable */\r
-#define PARITY_EN_PRTDSI__DBL_SYNC_IN    (* (reg8 *) PARITY_EN__PRTDSI__DBL_SYNC_IN) \r
-/* Output Enable Select Drive Strength */\r
-#define PARITY_EN_PRTDSI__OE_SEL0        (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL0) \r
-#define PARITY_EN_PRTDSI__OE_SEL1        (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL1) \r
-/* Port Pin Output Select Registers */\r
-#define PARITY_EN_PRTDSI__OUT_SEL0       (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL0) \r
-#define PARITY_EN_PRTDSI__OUT_SEL1       (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL1) \r
-/* Sync Output Enable Registers */\r
-#define PARITY_EN_PRTDSI__SYNC_OUT       (* (reg8 *) PARITY_EN__PRTDSI__SYNC_OUT) \r
-\r
-\r
-#if defined(PARITY_EN__INTSTAT)  /* Interrupt Registers */\r
-\r
-    #define PARITY_EN_INTSTAT                (* (reg8 *) PARITY_EN__INTSTAT)\r
-    #define PARITY_EN_SNAP                   (* (reg8 *) PARITY_EN__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
-#endif /*  CY_PINS_PARITY_EN_H */\r
-\r
-\r
-/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN_aliases.h
deleted file mode 100644 (file)
index 04919da..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-/*******************************************************************************\r
-* File Name: PARITY_EN.h  \r
-* Version 1.90\r
-*\r
-* Description:\r
-*  This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_PARITY_EN_ALIASES_H) /* Pins PARITY_EN_ALIASES_H */\r
-#define CY_PINS_PARITY_EN_ALIASES_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-\r
-\r
-\r
-/***************************************\r
-*              Constants        \r
-***************************************/\r
-#define PARITY_EN_0            PARITY_EN__0__PC\r
-\r
-#endif /* End Pins PARITY_EN_ALIASES_H */\r
-\r
-/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c
new file mode 100644 (file)
index 0000000..34503f1
--- /dev/null
@@ -0,0 +1,63 @@
+/*******************************************************************************\r
+* File Name: SCSI_CTL_IO.c  \r
+* Version 1.70\r
+*\r
+* Description:\r
+*  This file contains API to enable firmware control of a Control Register.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "SCSI_CTL_IO.h"\r
+\r
+#if !defined(SCSI_CTL_IO_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_CTL_IO_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+*  Write a byte to the Control Register.\r
+*\r
+* Parameters:\r
+*  control:  The value to be assigned to the Control Register.\r
+*\r
+* Return:\r
+*  None.\r
+*\r
+*******************************************************************************/\r
+void SCSI_CTL_IO_Write(uint8 control) \r
+{\r
+    SCSI_CTL_IO_Control = control;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_CTL_IO_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+*  Reads the current value assigned to the Control Register.\r
+*\r
+* Parameters:\r
+*  None.\r
+*\r
+* Return:\r
+*  Returns the current value in the Control Register.\r
+*\r
+*******************************************************************************/\r
+uint8 SCSI_CTL_IO_Read(void) \r
+{\r
+    return SCSI_CTL_IO_Control;\r
+}\r
+\r
+#endif /* End check for removal by optimization */\r
+\r
+\r
+/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h
new file mode 100644 (file)
index 0000000..849b8e2
--- /dev/null
@@ -0,0 +1,42 @@
+/*******************************************************************************\r
+* File Name: SCSI_CTL_IO.h  \r
+* Version 1.70\r
+*\r
+* Description:\r
+*  This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_CONTROL_REG_SCSI_CTL_IO_H) /* CY_CONTROL_REG_SCSI_CTL_IO_H */\r
+#define CY_CONTROL_REG_SCSI_CTL_IO_H\r
+\r
+#include "cytypes.h"\r
+\r
+\r
+/***************************************\r
+*         Function Prototypes \r
+***************************************/\r
+\r
+void    SCSI_CTL_IO_Write(uint8 control) ;\r
+uint8   SCSI_CTL_IO_Read(void) ;\r
+\r
+\r
+/***************************************\r
+*            Registers        \r
+***************************************/\r
+\r
+/* Control Register */\r
+#define SCSI_CTL_IO_Control        (* (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )\r
+#define SCSI_CTL_IO_Control_PTR    (  (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )\r
+\r
+#endif /* End CY_CONTROL_REG_SCSI_CTL_IO_H */\r
+\r
+\r
+/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ID_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ID_aliases.h
deleted file mode 100644 (file)
index 0cdbb60..0000000
+++ /dev/null
@@ -1,34 +0,0 @@
-/*******************************************************************************\r
-* File Name: SCSI_ID.h  \r
-* Version 1.90\r
-*\r
-* Description:\r
-*  This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_SCSI_ID_ALIASES_H) /* Pins SCSI_ID_ALIASES_H */\r
-#define CY_PINS_SCSI_ID_ALIASES_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-\r
-\r
-\r
-/***************************************\r
-*              Constants        \r
-***************************************/\r
-#define SCSI_ID_0              SCSI_ID__0__PC\r
-#define SCSI_ID_1              SCSI_ID__1__PC\r
-#define SCSI_ID_2              SCSI_ID__2__PC\r
-\r
-#endif /* End Pins SCSI_ID_ALIASES_H */\r
-\r
-/* [] END OF FILE */\r
index cc35e5b..e8aa91f 100644 (file)
@@ -36,7 +36,7 @@
 #define SCSI_Out_8             SCSI_Out__8__PC\r
 #define SCSI_Out_9             SCSI_Out__9__PC\r
 \r
-#define SCSI_Out_DBP           SCSI_Out__DBP__PC\r
+#define SCSI_Out_DBP_raw               SCSI_Out__DBP_raw__PC\r
 #define SCSI_Out_ATN           SCSI_Out__ATN__PC\r
 #define SCSI_Out_BSY           SCSI_Out__BSY__PC\r
 #define SCSI_Out_ACK           SCSI_Out__ACK__PC\r
@@ -45,7 +45,7 @@
 #define SCSI_Out_SEL           SCSI_Out__SEL__PC\r
 #define SCSI_Out_CD            SCSI_Out__CD__PC\r
 #define SCSI_Out_REQ           SCSI_Out__REQ__PC\r
-#define SCSI_Out_IO            SCSI_Out__IO__PC\r
+#define SCSI_Out_IO_raw                SCSI_Out__IO_raw__PC\r
 \r
 #endif /* End Pins SCSI_Out_ALIASES_H */\r
 \r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.c
deleted file mode 100644 (file)
index c1d6394..0000000
+++ /dev/null
@@ -1,1155 +0,0 @@
-/*******************************************************************************\r
-* File Name: SD.c\r
-* Version 2.40\r
-*\r
-* Description:\r
-*  This file provides all API functionality of the SPI Master component.\r
-*\r
-* Note:\r
-*  None.\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "SD_PVT.h"\r
-\r
-#if(SD_TX_SOFTWARE_BUF_ENABLED)\r
-    volatile uint8 SD_txBuffer[SD_TX_BUFFER_SIZE] = {0u};\r
-    volatile uint8 SD_txBufferFull;\r
-    volatile uint8 SD_txBufferRead;\r
-    volatile uint8 SD_txBufferWrite;\r
-#endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
-#if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-    volatile uint8 SD_rxBuffer[SD_RX_BUFFER_SIZE] = {0u};\r
-    volatile uint8 SD_rxBufferFull;\r
-    volatile uint8 SD_rxBufferRead;\r
-    volatile uint8 SD_rxBufferWrite;\r
-#endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
-uint8 SD_initVar = 0u;\r
-\r
-volatile uint8 SD_swStatusTx;\r
-volatile uint8 SD_swStatusRx;\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Inits/Restores default SPIM configuration provided with customizer.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Side Effects:\r
-*  When this function is called it initializes all of the necessary parameters\r
-*  for execution. i.e. setting the initial interrupt mask, configuring the\r
-*  interrupt service routine, configuring the bit-counter parameters and\r
-*  clearing the FIFO and Status Register.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-void SD_Init(void) \r
-{\r
-    /* Initialize the Bit counter */\r
-    SD_COUNTER_PERIOD_REG = SD_BITCTR_INIT;\r
-\r
-    /* Init TX ISR  */\r
-    #if(0u != SD_INTERNAL_TX_INT_ENABLED)\r
-        CyIntDisable         (SD_TX_ISR_NUMBER);\r
-        CyIntSetPriority     (SD_TX_ISR_NUMBER,  SD_TX_ISR_PRIORITY);\r
-        (void) CyIntSetVector(SD_TX_ISR_NUMBER, &SD_TX_ISR);\r
-    #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */\r
-\r
-    /* Init RX ISR  */\r
-    #if(0u != SD_INTERNAL_RX_INT_ENABLED)\r
-        CyIntDisable         (SD_RX_ISR_NUMBER);\r
-        CyIntSetPriority     (SD_RX_ISR_NUMBER,  SD_RX_ISR_PRIORITY);\r
-        (void) CyIntSetVector(SD_RX_ISR_NUMBER, &SD_RX_ISR);\r
-    #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */\r
-\r
-    /* Clear any stray data from the RX and TX FIFO */\r
-    SD_ClearFIFO();\r
-\r
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-        SD_rxBufferFull  = 0u;\r
-        SD_rxBufferRead  = 0u;\r
-        SD_rxBufferWrite = 0u;\r
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
-        SD_txBufferFull  = 0u;\r
-        SD_txBufferRead  = 0u;\r
-        SD_txBufferWrite = 0u;\r
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    (void) SD_ReadTxStatus(); /* Clear Tx status and swStatusTx */\r
-    (void) SD_ReadRxStatus(); /* Clear Rx status and swStatusRx */\r
-\r
-    /* Configure TX and RX interrupt mask */\r
-    SD_TX_STATUS_MASK_REG = SD_TX_INIT_INTERRUPTS_MASK;\r
-    SD_RX_STATUS_MASK_REG = SD_RX_INIT_INTERRUPTS_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Enable\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Enable SPIM component.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-*******************************************************************************/\r
-void SD_Enable(void) \r
-{\r
-    uint8 enableInterrupts;\r
-\r
-    enableInterrupts = CyEnterCriticalSection();\r
-    SD_COUNTER_CONTROL_REG |= SD_CNTR_ENABLE;\r
-    SD_TX_STATUS_ACTL_REG  |= SD_INT_ENABLE;\r
-    SD_RX_STATUS_ACTL_REG  |= SD_INT_ENABLE;\r
-    CyExitCriticalSection(enableInterrupts);\r
-\r
-    #if(0u != SD_INTERNAL_CLOCK)\r
-        SD_IntClock_Enable();\r
-    #endif /* (0u != SD_INTERNAL_CLOCK) */\r
-\r
-    SD_EnableTxInt();\r
-    SD_EnableRxInt();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Start\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Initialize and Enable the SPI Master component.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Global variables:\r
-*  SD_initVar - used to check initial configuration, modified on\r
-*  first function call.\r
-*\r
-* Theory:\r
-*  Enable the clock input to enable operation.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-void SD_Start(void) \r
-{\r
-    if(0u == SD_initVar)\r
-    {\r
-        SD_Init();\r
-        SD_initVar = 1u;\r
-    }\r
-\r
-    SD_Enable();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Stop\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Disable the SPI Master component.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Theory:\r
-*  Disable the clock input to enable operation.\r
-*\r
-*******************************************************************************/\r
-void SD_Stop(void) \r
-{\r
-    uint8 enableInterrupts;\r
-\r
-    enableInterrupts = CyEnterCriticalSection();\r
-    SD_TX_STATUS_ACTL_REG &= ((uint8) ~SD_INT_ENABLE);\r
-    SD_RX_STATUS_ACTL_REG &= ((uint8) ~SD_INT_ENABLE);\r
-    CyExitCriticalSection(enableInterrupts);\r
-\r
-    #if(0u != SD_INTERNAL_CLOCK)\r
-        SD_IntClock_Disable();\r
-    #endif /* (0u != SD_INTERNAL_CLOCK) */\r
-\r
-    SD_DisableTxInt();\r
-    SD_DisableRxInt();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_EnableTxInt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Enable internal Tx interrupt generation.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Theory:\r
-*  Enable the internal Tx interrupt output -or- the interrupt component itself.\r
-*\r
-*******************************************************************************/\r
-void SD_EnableTxInt(void) \r
-{\r
-    #if(0u != SD_INTERNAL_TX_INT_ENABLED)\r
-        CyIntEnable(SD_TX_ISR_NUMBER);\r
-    #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_EnableRxInt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Enable internal Rx interrupt generation.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Theory:\r
-*  Enable the internal Rx interrupt output -or- the interrupt component itself.\r
-*\r
-*******************************************************************************/\r
-void SD_EnableRxInt(void) \r
-{\r
-    #if(0u != SD_INTERNAL_RX_INT_ENABLED)\r
-        CyIntEnable(SD_RX_ISR_NUMBER);\r
-    #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_DisableTxInt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Disable internal Tx interrupt generation.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Theory:\r
-*  Disable the internal Tx interrupt output -or- the interrupt component itself.\r
-*\r
-*******************************************************************************/\r
-void SD_DisableTxInt(void) \r
-{\r
-    #if(0u != SD_INTERNAL_TX_INT_ENABLED)\r
-        CyIntDisable(SD_TX_ISR_NUMBER);\r
-    #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_DisableRxInt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Disable internal Rx interrupt generation.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Theory:\r
-*  Disable the internal Rx interrupt output -or- the interrupt component itself.\r
-*\r
-*******************************************************************************/\r
-void SD_DisableRxInt(void) \r
-{\r
-    #if(0u != SD_INTERNAL_RX_INT_ENABLED)\r
-        CyIntDisable(SD_RX_ISR_NUMBER);\r
-    #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_SetTxInterruptMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Configure which status bits trigger an interrupt event.\r
-*\r
-* Parameters:\r
-*  intSrc: An or'd combination of the desired status bit masks (defined in the\r
-*  header file).\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Theory:\r
-*  Enables the output of specific status bits to the interrupt controller.\r
-*\r
-*******************************************************************************/\r
-void SD_SetTxInterruptMode(uint8 intSrc) \r
-{\r
-    SD_TX_STATUS_MASK_REG = intSrc;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_SetRxInterruptMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Configure which status bits trigger an interrupt event.\r
-*\r
-* Parameters:\r
-*  intSrc: An or'd combination of the desired status bit masks (defined in the\r
-*  header file).\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Theory:\r
-*  Enables the output of specific status bits to the interrupt controller.\r
-*\r
-*******************************************************************************/\r
-void SD_SetRxInterruptMode(uint8 intSrc) \r
-{\r
-    SD_RX_STATUS_MASK_REG  = intSrc;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ReadTxStatus\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Read the Tx status register for the component.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  Contents of the Tx status register.\r
-*\r
-* Global variables:\r
-*  SD_swStatusTx - used to store in software status register,\r
-*  modified every function call - resets to zero.\r
-*\r
-* Theory:\r
-*  Allows the user and the API to read the Tx status register for error\r
-*  detection and flow control.\r
-*\r
-* Side Effects:\r
-*  Clear Tx status register of the component.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_ReadTxStatus(void) \r
-{\r
-    uint8 tmpStatus;\r
-\r
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
-        /* Disable TX interrupt to protect global veriables */\r
-        SD_DisableTxInt();\r
-\r
-        tmpStatus = SD_GET_STATUS_TX(SD_swStatusTx);\r
-        SD_swStatusTx = 0u;\r
-\r
-        SD_EnableTxInt();\r
-\r
-    #else\r
-\r
-        tmpStatus = SD_TX_STATUS_REG;\r
-\r
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    return(tmpStatus);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ReadRxStatus\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Read the Rx status register for the component.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  Contents of the Rx status register.\r
-*\r
-* Global variables:\r
-*  SD_swStatusRx - used to store in software Rx status register,\r
-*  modified every function call - resets to zero.\r
-*\r
-* Theory:\r
-*  Allows the user and the API to read the Rx status register for error\r
-*  detection and flow control.\r
-*\r
-* Side Effects:\r
-*  Clear Rx status register of the component.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_ReadRxStatus(void) \r
-{\r
-    uint8 tmpStatus;\r
-\r
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-        /* Disable RX interrupt to protect global veriables */\r
-        SD_DisableRxInt();\r
-\r
-        tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);\r
-        SD_swStatusRx = 0u;\r
-\r
-        SD_EnableRxInt();\r
-\r
-    #else\r
-\r
-        tmpStatus = SD_RX_STATUS_REG;\r
-\r
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    return(tmpStatus);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_WriteTxData\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Write a byte of data to be sent across the SPI.\r
-*\r
-* Parameters:\r
-*  txDataByte: The data value to send across the SPI.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Global variables:\r
-*  SD_txBufferWrite - used for the account of the bytes which\r
-*  have been written down in the TX software buffer, modified every function\r
-*  call if TX Software Buffer is used.\r
-*  SD_txBufferRead - used for the account of the bytes which\r
-*  have been read from the TX software buffer.\r
-*  SD_txBuffer[SD_TX_BUFFER_SIZE] - used to store\r
-*  data to sending, modified every function call if TX Software Buffer is used.\r
-*\r
-* Theory:\r
-*  Allows the user to transmit any byte of data in a single transfer.\r
-*\r
-* Side Effects:\r
-*  If this function is called again before the previous byte is finished then\r
-*  the next byte will be appended to the transfer with no time between\r
-*  the byte transfers. Clear Tx status register of the component.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-void SD_WriteTxData(uint8 txData) \r
-{\r
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
-\r
-        uint8 tempStatus;\r
-        uint8 tmpTxBufferRead;\r
-\r
-        /* Block if TX buffer is FULL: don't overwrite */\r
-        do\r
-        {\r
-            tmpTxBufferRead = SD_txBufferRead;\r
-            if(0u == tmpTxBufferRead)\r
-            {\r
-                tmpTxBufferRead = (SD_TX_BUFFER_SIZE - 1u);\r
-            }\r
-            else\r
-            {\r
-                tmpTxBufferRead--;\r
-            }\r
-\r
-        }while(tmpTxBufferRead == SD_txBufferWrite);\r
-\r
-        /* Disable TX interrupt to protect global veriables */\r
-        SD_DisableTxInt();\r
-\r
-        tempStatus = SD_GET_STATUS_TX(SD_swStatusTx);\r
-        SD_swStatusTx = tempStatus;\r
-\r
-\r
-        if((SD_txBufferRead == SD_txBufferWrite) &&\r
-           (0u != (SD_swStatusTx & SD_STS_TX_FIFO_NOT_FULL)))\r
-        {\r
-            /* Add directly to the TX FIFO */\r
-            CY_SET_REG8(SD_TXDATA_PTR, txData);\r
-        }\r
-        else\r
-        {\r
-            /* Add to the TX software buffer */\r
-            SD_txBufferWrite++;\r
-            if(SD_txBufferWrite >= SD_TX_BUFFER_SIZE)\r
-            {\r
-                SD_txBufferWrite = 0u;\r
-            }\r
-\r
-            if(SD_txBufferWrite == SD_txBufferRead)\r
-            {\r
-                SD_txBufferRead++;\r
-                if(SD_txBufferRead >= SD_TX_BUFFER_SIZE)\r
-                {\r
-                    SD_txBufferRead = 0u;\r
-                }\r
-                SD_txBufferFull = 1u;\r
-            }\r
-\r
-            SD_txBuffer[SD_txBufferWrite] = txData;\r
-\r
-            SD_TX_STATUS_MASK_REG |= SD_STS_TX_FIFO_NOT_FULL;\r
-        }\r
-\r
-        SD_EnableTxInt();\r
-\r
-    #else\r
-\r
-        while(0u == (SD_TX_STATUS_REG & SD_STS_TX_FIFO_NOT_FULL))\r
-        {\r
-            ; /* Wait for room in FIFO */\r
-        }\r
-\r
-        /* Put byte in TX FIFO */\r
-        CY_SET_REG8(SD_TXDATA_PTR, txData);\r
-\r
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ReadRxData\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Read the next byte of data received across the SPI.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  The next byte of data read from the FIFO.\r
-*\r
-* Global variables:\r
-*  SD_rxBufferWrite - used for the account of the bytes which\r
-*  have been written down in the RX software buffer.\r
-*  SD_rxBufferRead - used for the account of the bytes which\r
-*  have been read from the RX software buffer, modified every function\r
-*  call if RX Software Buffer is used.\r
-*  SD_rxBuffer[SD_RX_BUFFER_SIZE] - used to store\r
-*  received data.\r
-*\r
-* Theory:\r
-*  Allows the user to read a byte of data received.\r
-*\r
-* Side Effects:\r
-*  Will return invalid data if the FIFO is empty. The user should Call\r
-*  GetRxBufferSize() and if it returns a non-zero value then it is safe to call\r
-*  ReadByte() function.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_ReadRxData(void) \r
-{\r
-    uint8 rxData;\r
-\r
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-\r
-        /* Disable RX interrupt to protect global veriables */\r
-        SD_DisableRxInt();\r
-\r
-        if(SD_rxBufferRead != SD_rxBufferWrite)\r
-        {\r
-            if(0u == SD_rxBufferFull)\r
-            {\r
-                SD_rxBufferRead++;\r
-                if(SD_rxBufferRead >= SD_RX_BUFFER_SIZE)\r
-                {\r
-                    SD_rxBufferRead = 0u;\r
-                }\r
-            }\r
-            else\r
-            {\r
-                SD_rxBufferFull = 0u;\r
-            }\r
-        }\r
-\r
-        rxData = SD_rxBuffer[SD_rxBufferRead];\r
-\r
-        SD_EnableRxInt();\r
-\r
-    #else\r
-\r
-        rxData = CY_GET_REG8(SD_RXDATA_PTR);\r
-\r
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    return(rxData);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_GetRxBufferSize\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Returns the number of bytes/words of data currently held in the RX buffer.\r
-*  If RX Software Buffer not used then function return 0 if FIFO empty or 1 if\r
-*  FIFO not empty. In another case function return size of RX Software Buffer.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  Integer count of the number of bytes/words in the RX buffer.\r
-*\r
-* Global variables:\r
-*  SD_rxBufferWrite - used for the account of the bytes which\r
-*  have been written down in the RX software buffer.\r
-*  SD_rxBufferRead - used for the account of the bytes which\r
-*  have been read from the RX software buffer.\r
-*\r
-* Side Effects:\r
-*  Clear status register of the component.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_GetRxBufferSize(void) \r
-{\r
-    uint8 size;\r
-\r
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-\r
-        /* Disable RX interrupt to protect global veriables */\r
-        SD_DisableRxInt();\r
-\r
-        if(SD_rxBufferRead == SD_rxBufferWrite)\r
-        {\r
-            size = 0u;\r
-        }\r
-        else if(SD_rxBufferRead < SD_rxBufferWrite)\r
-        {\r
-            size = (SD_rxBufferWrite - SD_rxBufferRead);\r
-        }\r
-        else\r
-        {\r
-            size = (SD_RX_BUFFER_SIZE - SD_rxBufferRead) + SD_rxBufferWrite;\r
-        }\r
-\r
-        SD_EnableRxInt();\r
-\r
-    #else\r
-\r
-        /* We can only know if there is data in the RX FIFO */\r
-        size = (0u != (SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY)) ? 1u : 0u;\r
-\r
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    return(size);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_GetTxBufferSize\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Returns the number of bytes/words of data currently held in the TX buffer.\r
-*  If TX Software Buffer not used then function return 0 - if FIFO empty, 1 - if\r
-*  FIFO not full, 4 - if FIFO full. In another case function return size of TX\r
-*  Software Buffer.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  Integer count of the number of bytes/words in the TX buffer.\r
-*\r
-* Global variables:\r
-*  SD_txBufferWrite - used for the account of the bytes which\r
-*  have been written down in the TX software buffer.\r
-*  SD_txBufferRead - used for the account of the bytes which\r
-*  have been read from the TX software buffer.\r
-*\r
-* Side Effects:\r
-*  Clear status register of the component.\r
-*\r
-*******************************************************************************/\r
-uint8  SD_GetTxBufferSize(void) \r
-{\r
-    uint8 size;\r
-\r
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
-        /* Disable TX interrupt to protect global veriables */\r
-        SD_DisableTxInt();\r
-\r
-        if(SD_txBufferRead == SD_txBufferWrite)\r
-        {\r
-            size = 0u;\r
-        }\r
-        else if(SD_txBufferRead < SD_txBufferWrite)\r
-        {\r
-            size = (SD_txBufferWrite - SD_txBufferRead);\r
-        }\r
-        else\r
-        {\r
-            size = (SD_TX_BUFFER_SIZE - SD_txBufferRead) + SD_txBufferWrite;\r
-        }\r
-\r
-        SD_EnableTxInt();\r
-\r
-    #else\r
-\r
-        size = SD_TX_STATUS_REG;\r
-\r
-        if(0u != (size & SD_STS_TX_FIFO_EMPTY))\r
-        {\r
-            size = 0u;\r
-        }\r
-        else if(0u != (size & SD_STS_TX_FIFO_NOT_FULL))\r
-        {\r
-            size = 1u;\r
-        }\r
-        else\r
-        {\r
-            size = SD_FIFO_SIZE;\r
-        }\r
-\r
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    return(size);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ClearRxBuffer\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Clear the RX RAM buffer by setting the read and write pointers both to zero.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Global variables:\r
-*  SD_rxBufferWrite - used for the account of the bytes which\r
-*  have been written down in the RX software buffer, modified every function\r
-*  call - resets to zero.\r
-*  SD_rxBufferRead - used for the account of the bytes which\r
-*  have been read from the RX software buffer, modified every function call -\r
-*  resets to zero.\r
-*\r
-* Theory:\r
-*  Setting the pointers to zero makes the system believe there is no data to\r
-*  read and writing will resume at address 0 overwriting any data that may have\r
-*  remained in the RAM.\r
-*\r
-* Side Effects:\r
-*  Any received data not read from the RAM buffer will be lost when overwritten.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-void SD_ClearRxBuffer(void) \r
-{\r
-    /* Clear Hardware RX FIFO */\r
-    while(0u !=(SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY))\r
-    {\r
-        (void) CY_GET_REG8(SD_RXDATA_PTR);\r
-    }\r
-\r
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-        /* Disable RX interrupt to protect global veriables */\r
-        SD_DisableRxInt();\r
-\r
-        SD_rxBufferFull  = 0u;\r
-        SD_rxBufferRead  = 0u;\r
-        SD_rxBufferWrite = 0u;\r
-\r
-        SD_EnableRxInt();\r
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ClearTxBuffer\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Clear the TX RAM buffer by setting the read and write pointers both to zero.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Global variables:\r
-*  SD_txBufferWrite - used for the account of the bytes which\r
-*  have been written down in the TX software buffer, modified every function\r
-*  call - resets to zero.\r
-*  SD_txBufferRead - used for the account of the bytes which\r
-*  have been read from the TX software buffer, modified every function call -\r
-*  resets to zero.\r
-*\r
-* Theory:\r
-*  Setting the pointers to zero makes the system believe there is no data to\r
-*  read and writing will resume at address 0 overwriting any data that may have\r
-*  remained in the RAM.\r
-*\r
-* Side Effects:\r
-*  Any data not yet transmitted from the RAM buffer will be lost when\r
-*  overwritten.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-void SD_ClearTxBuffer(void) \r
-{\r
-    uint8 enableInterrupts;\r
-\r
-    enableInterrupts = CyEnterCriticalSection();\r
-    /* Clear TX FIFO */\r
-    SD_AUX_CONTROL_DP0_REG |= ((uint8)  SD_TX_FIFO_CLR);\r
-    SD_AUX_CONTROL_DP0_REG &= ((uint8) ~SD_TX_FIFO_CLR);\r
-\r
-    #if(SD_USE_SECOND_DATAPATH)\r
-        /* Clear TX FIFO for 2nd Datapath */\r
-        SD_AUX_CONTROL_DP1_REG |= ((uint8)  SD_TX_FIFO_CLR);\r
-        SD_AUX_CONTROL_DP1_REG &= ((uint8) ~SD_TX_FIFO_CLR);\r
-    #endif /* (SD_USE_SECOND_DATAPATH) */\r
-    CyExitCriticalSection(enableInterrupts);\r
-\r
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
-        /* Disable TX interrupt to protect global veriables */\r
-        SD_DisableTxInt();\r
-\r
-        SD_txBufferFull  = 0u;\r
-        SD_txBufferRead  = 0u;\r
-        SD_txBufferWrite = 0u;\r
-\r
-        /* Buffer is EMPTY: disable TX FIFO NOT FULL interrupt */\r
-        SD_TX_STATUS_MASK_REG &= ((uint8) ~SD_STS_TX_FIFO_NOT_FULL);\r
-\r
-        SD_EnableTxInt();\r
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-}\r
-\r
-\r
-#if(0u != SD_BIDIRECTIONAL_MODE)\r
-    /*******************************************************************************\r
-    * Function Name: SD_TxEnable\r
-    ********************************************************************************\r
-    *\r
-    * Summary:\r
-    *  If the SPI master is configured to use a single bi-directional pin then this\r
-    *  will set the bi-directional pin to transmit.\r
-    *\r
-    * Parameters:\r
-    *  None.\r
-    *\r
-    * Return:\r
-    *  None.\r
-    *\r
-    *******************************************************************************/\r
-    void SD_TxEnable(void) \r
-    {\r
-        SD_CONTROL_REG |= SD_CTRL_TX_SIGNAL_EN;\r
-    }\r
-\r
-\r
-    /*******************************************************************************\r
-    * Function Name: SD_TxDisable\r
-    ********************************************************************************\r
-    *\r
-    * Summary:\r
-    *  If the SPI master is configured to use a single bi-directional pin then this\r
-    *  will set the bi-directional pin to receive.\r
-    *\r
-    * Parameters:\r
-    *  None.\r
-    *\r
-    * Return:\r
-    *  None.\r
-    *\r
-    *******************************************************************************/\r
-    void SD_TxDisable(void) \r
-    {\r
-        SD_CONTROL_REG &= ((uint8) ~SD_CTRL_TX_SIGNAL_EN);\r
-    }\r
-\r
-#endif /* (0u != SD_BIDIRECTIONAL_MODE) */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_PutArray\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Write available data from ROM/RAM to the TX buffer while space is available\r
-*  in the TX buffer. Keep trying until all data is passed to the TX buffer.\r
-*\r
-* Parameters:\r
-*  *buffer: Pointer to the location in RAM containing the data to send\r
-*  byteCount: The number of bytes to move to the transmit buffer.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Side Effects:\r
-*  Will stay in this routine until all data has been sent.  May get locked in\r
-*  this loop if data is not being initiated by the master if there is not\r
-*  enough room in the TX FIFO.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-void SD_PutArray(const uint8 buffer[], uint8 byteCount)\r
-                                                                          \r
-{\r
-    uint8 bufIndex;\r
-\r
-    bufIndex = 0u;\r
-\r
-    while(byteCount > 0u)\r
-    {\r
-        SD_WriteTxData(buffer[bufIndex]);\r
-        bufIndex++;\r
-        byteCount--;\r
-    }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ClearFIFO\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Clear the RX and TX FIFO's of all data for a fresh start.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Side Effects:\r
-*  Clear status register of the component.\r
-*\r
-*******************************************************************************/\r
-void SD_ClearFIFO(void) \r
-{\r
-    uint8 enableInterrupts;\r
-\r
-    /* Clear Hardware RX FIFO */\r
-    while(0u !=(SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY))\r
-    {\r
-        (void) CY_GET_REG8(SD_RXDATA_PTR);\r
-    }\r
-\r
-    enableInterrupts = CyEnterCriticalSection();\r
-    /* Clear TX FIFO */\r
-    SD_AUX_CONTROL_DP0_REG |= ((uint8)  SD_TX_FIFO_CLR);\r
-    SD_AUX_CONTROL_DP0_REG &= ((uint8) ~SD_TX_FIFO_CLR);\r
-\r
-    #if(SD_USE_SECOND_DATAPATH)\r
-        /* Clear TX FIFO for 2nd Datapath */\r
-        SD_AUX_CONTROL_DP1_REG |= ((uint8)  SD_TX_FIFO_CLR);\r
-        SD_AUX_CONTROL_DP1_REG &= ((uint8) ~SD_TX_FIFO_CLR);\r
-    #endif /* (SD_USE_SECOND_DATAPATH) */\r
-    CyExitCriticalSection(enableInterrupts);\r
-}\r
-\r
-\r
-/* Following functions are for version Compatibility, they are obsolete.\r
-*  Please do not use it in new projects.\r
-*/\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_EnableInt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Enable internal interrupt generation.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Theory:\r
-*  Enable the internal interrupt output -or- the interrupt component itself.\r
-*\r
-*******************************************************************************/\r
-void SD_EnableInt(void) \r
-{\r
-    SD_EnableRxInt();\r
-    SD_EnableTxInt();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_DisableInt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Disable internal interrupt generation.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Theory:\r
-*  Disable the internal interrupt output -or- the interrupt component itself.\r
-*\r
-*******************************************************************************/\r
-void SD_DisableInt(void) \r
-{\r
-    SD_DisableTxInt();\r
-    SD_DisableRxInt();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_SetInterruptMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Configure which status bits trigger an interrupt event.\r
-*\r
-* Parameters:\r
-*  intSrc: An or'd combination of the desired status bit masks (defined in the\r
-*  header file).\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Theory:\r
-*  Enables the output of specific status bits to the interrupt controller.\r
-*\r
-*******************************************************************************/\r
-void SD_SetInterruptMode(uint8 intSrc) \r
-{\r
-    SD_TX_STATUS_MASK_REG  = (intSrc & ((uint8) ~SD_STS_SPI_IDLE));\r
-    SD_RX_STATUS_MASK_REG  =  intSrc;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ReadStatus\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Read the status register for the component.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  Contents of the status register.\r
-*\r
-* Global variables:\r
-*  SD_swStatus - used to store in software status register,\r
-*  modified every function call - resets to zero.\r
-*\r
-* Theory:\r
-*  Allows the user and the API to read the status register for error detection\r
-*  and flow control.\r
-*\r
-* Side Effects:\r
-*  Clear status register of the component.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_ReadStatus(void) \r
-{\r
-    uint8 tmpStatus;\r
-\r
-    #if(SD_TX_SOFTWARE_BUF_ENABLED || SD_RX_SOFTWARE_BUF_ENABLED)\r
-\r
-        SD_DisableInt();\r
-\r
-        tmpStatus  = SD_GET_STATUS_RX(SD_swStatusRx);\r
-        tmpStatus |= SD_GET_STATUS_TX(SD_swStatusTx);\r
-        tmpStatus &= ((uint8) ~SD_STS_SPI_IDLE);\r
-\r
-        SD_swStatusTx = 0u;\r
-        SD_swStatusRx = 0u;\r
-\r
-        SD_EnableInt();\r
-\r
-    #else\r
-\r
-        tmpStatus  = SD_RX_STATUS_REG;\r
-        tmpStatus |= SD_TX_STATUS_REG;\r
-        tmpStatus &= ((uint8) ~SD_STS_SPI_IDLE);\r
-\r
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED || SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    return(tmpStatus);\r
-}\r
-\r
-\r
-/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.h
deleted file mode 100644 (file)
index 0f99abf..0000000
+++ /dev/null
@@ -1,389 +0,0 @@
-/*******************************************************************************\r
-* File Name: SD.h\r
-* Version 2.40\r
-*\r
-* Description:\r
-*  Contains the function prototypes, constants and register definition\r
-*  of the SPI Master Component.\r
-*\r
-* Note:\r
-*  None\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_SPIM_SD_H)\r
-#define CY_SPIM_SD_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-#include "CyLib.h"\r
-\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
-    #error Component SPI_Master_v2_40 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
-\r
-/***************************************\r
-*   Conditional Compilation Parameters\r
-***************************************/\r
-\r
-#define SD_INTERNAL_CLOCK             (0u)\r
-\r
-#if(0u != SD_INTERNAL_CLOCK)\r
-    #include "SD_IntClock.h"\r
-#endif /* (0u != SD_INTERNAL_CLOCK) */\r
-\r
-#define SD_MODE                       (1u)\r
-#define SD_DATA_WIDTH                 (8u)\r
-#define SD_MODE_USE_ZERO              (1u)\r
-#define SD_BIDIRECTIONAL_MODE         (0u)\r
-\r
-/* Internal interrupt handling */\r
-#define SD_TX_BUFFER_SIZE             (4u)\r
-#define SD_RX_BUFFER_SIZE             (4u)\r
-#define SD_INTERNAL_TX_INT_ENABLED    (0u)\r
-#define SD_INTERNAL_RX_INT_ENABLED    (0u)\r
-\r
-#define SD_SINGLE_REG_SIZE            (8u)\r
-#define SD_USE_SECOND_DATAPATH        (SD_DATA_WIDTH > SD_SINGLE_REG_SIZE)\r
-\r
-#define SD_FIFO_SIZE                  (4u)\r
-#define SD_TX_SOFTWARE_BUF_ENABLED    ((0u != SD_INTERNAL_TX_INT_ENABLED) && \\r
-                                                     (SD_TX_BUFFER_SIZE > SD_FIFO_SIZE))\r
-\r
-#define SD_RX_SOFTWARE_BUF_ENABLED    ((0u != SD_INTERNAL_RX_INT_ENABLED) && \\r
-                                                     (SD_RX_BUFFER_SIZE > SD_FIFO_SIZE))\r
-\r
-\r
-/***************************************\r
-*        Data Struct Definition\r
-***************************************/\r
-\r
-/* Sleep Mode API Support */\r
-typedef struct\r
-{\r
-    uint8 enableState;\r
-    uint8 cntrPeriod;\r
-    #if(CY_UDB_V0)\r
-        uint8 saveSrTxIntMask;\r
-        uint8 saveSrRxIntMask;\r
-    #endif /* (CY_UDB_V0) */\r
-\r
-} SD_BACKUP_STRUCT;\r
-\r
-\r
-/***************************************\r
-*        Function Prototypes\r
-***************************************/\r
-\r
-void  SD_Init(void)                           ;\r
-void  SD_Enable(void)                         ;\r
-void  SD_Start(void)                          ;\r
-void  SD_Stop(void)                           ;\r
-\r
-void  SD_EnableTxInt(void)                    ;\r
-void  SD_EnableRxInt(void)                    ;\r
-void  SD_DisableTxInt(void)                   ;\r
-void  SD_DisableRxInt(void)                   ;\r
-\r
-void  SD_Sleep(void)                          ;\r
-void  SD_Wakeup(void)                         ;\r
-void  SD_SaveConfig(void)                     ;\r
-void  SD_RestoreConfig(void)                  ;\r
-\r
-void  SD_SetTxInterruptMode(uint8 intSrc)     ;\r
-void  SD_SetRxInterruptMode(uint8 intSrc)     ;\r
-uint8 SD_ReadTxStatus(void)                   ;\r
-uint8 SD_ReadRxStatus(void)                   ;\r
-void  SD_WriteTxData(uint8 txData)  \\r
-                                                            ;\r
-uint8 SD_ReadRxData(void) \\r
-                                                            ;\r
-uint8 SD_GetRxBufferSize(void)                ;\r
-uint8 SD_GetTxBufferSize(void)                ;\r
-void  SD_ClearRxBuffer(void)                  ;\r
-void  SD_ClearTxBuffer(void)                  ;\r
-void  SD_ClearFIFO(void)                              ;\r
-void  SD_PutArray(const uint8 buffer[], uint8 byteCount) \\r
-                                                            ;\r
-\r
-#if(0u != SD_BIDIRECTIONAL_MODE)\r
-    void  SD_TxEnable(void)                   ;\r
-    void  SD_TxDisable(void)                  ;\r
-#endif /* (0u != SD_BIDIRECTIONAL_MODE) */\r
-\r
-CY_ISR_PROTO(SD_TX_ISR);\r
-CY_ISR_PROTO(SD_RX_ISR);\r
-\r
-\r
-/**********************************\r
-*   Variable with external linkage\r
-**********************************/\r
-\r
-extern uint8 SD_initVar;\r
-\r
-\r
-/***************************************\r
-*           API Constants\r
-***************************************/\r
-\r
-#define SD_TX_ISR_NUMBER     ((uint8) (SD_TxInternalInterrupt__INTC_NUMBER))\r
-#define SD_RX_ISR_NUMBER     ((uint8) (SD_RxInternalInterrupt__INTC_NUMBER))\r
-\r
-#define SD_TX_ISR_PRIORITY   ((uint8) (SD_TxInternalInterrupt__INTC_PRIOR_NUM))\r
-#define SD_RX_ISR_PRIORITY   ((uint8) (SD_RxInternalInterrupt__INTC_PRIOR_NUM))\r
-\r
-\r
-/***************************************\r
-*    Initial Parameter Constants\r
-***************************************/\r
-\r
-#define SD_INT_ON_SPI_DONE    ((uint8) (0u   << SD_STS_SPI_DONE_SHIFT))\r
-#define SD_INT_ON_TX_EMPTY    ((uint8) (0u   << SD_STS_TX_FIFO_EMPTY_SHIFT))\r
-#define SD_INT_ON_TX_NOT_FULL ((uint8) (0u << \\r
-                                                                           SD_STS_TX_FIFO_NOT_FULL_SHIFT))\r
-#define SD_INT_ON_BYTE_COMP   ((uint8) (0u  << SD_STS_BYTE_COMPLETE_SHIFT))\r
-#define SD_INT_ON_SPI_IDLE    ((uint8) (0u   << SD_STS_SPI_IDLE_SHIFT))\r
-\r
-/* Disable TX_NOT_FULL if software buffer is used */\r
-#define SD_INT_ON_TX_NOT_FULL_DEF ((SD_TX_SOFTWARE_BUF_ENABLED) ? \\r
-                                                                        (0u) : (SD_INT_ON_TX_NOT_FULL))\r
-\r
-/* TX interrupt mask */\r
-#define SD_TX_INIT_INTERRUPTS_MASK    (SD_INT_ON_SPI_DONE  | \\r
-                                                     SD_INT_ON_TX_EMPTY  | \\r
-                                                     SD_INT_ON_TX_NOT_FULL_DEF | \\r
-                                                     SD_INT_ON_BYTE_COMP | \\r
-                                                     SD_INT_ON_SPI_IDLE)\r
-\r
-#define SD_INT_ON_RX_FULL         ((uint8) (0u << \\r
-                                                                          SD_STS_RX_FIFO_FULL_SHIFT))\r
-#define SD_INT_ON_RX_NOT_EMPTY    ((uint8) (0u << \\r
-                                                                          SD_STS_RX_FIFO_NOT_EMPTY_SHIFT))\r
-#define SD_INT_ON_RX_OVER         ((uint8) (0u << \\r
-                                                                          SD_STS_RX_FIFO_OVERRUN_SHIFT))\r
-\r
-/* RX interrupt mask */\r
-#define SD_RX_INIT_INTERRUPTS_MASK    (SD_INT_ON_RX_FULL      | \\r
-                                                     SD_INT_ON_RX_NOT_EMPTY | \\r
-                                                     SD_INT_ON_RX_OVER)\r
-/* Nubmer of bits to receive/transmit */\r
-#define SD_BITCTR_INIT            (((uint8) (SD_DATA_WIDTH << 1u)) - 1u)\r
-\r
-\r
-/***************************************\r
-*             Registers\r
-***************************************/\r
-\r
-#if(CY_PSOC3 || CY_PSOC5)\r
-    #define SD_TXDATA_REG (* (reg8 *) \\r
-                                                SD_BSPIM_sR8_Dp_u0__F0_REG)\r
-    #define SD_TXDATA_PTR (  (reg8 *) \\r
-                                                SD_BSPIM_sR8_Dp_u0__F0_REG)\r
-    #define SD_RXDATA_REG (* (reg8 *) \\r
-                                                SD_BSPIM_sR8_Dp_u0__F1_REG)\r
-    #define SD_RXDATA_PTR (  (reg8 *) \\r
-                                                SD_BSPIM_sR8_Dp_u0__F1_REG)\r
-#else   /* PSOC4 */\r
-    #if(SD_USE_SECOND_DATAPATH)\r
-        #define SD_TXDATA_REG (* (reg16 *) \\r
-                                          SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG)\r
-        #define SD_TXDATA_PTR (  (reg16 *) \\r
-                                          SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG)\r
-        #define SD_RXDATA_REG (* (reg16 *) \\r
-                                          SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG)\r
-        #define SD_RXDATA_PTR         (  (reg16 *) \\r
-                                          SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG)\r
-    #else\r
-        #define SD_TXDATA_REG (* (reg8 *) \\r
-                                                SD_BSPIM_sR8_Dp_u0__F0_REG)\r
-        #define SD_TXDATA_PTR (  (reg8 *) \\r
-                                                SD_BSPIM_sR8_Dp_u0__F0_REG)\r
-        #define SD_RXDATA_REG (* (reg8 *) \\r
-                                                SD_BSPIM_sR8_Dp_u0__F1_REG)\r
-        #define SD_RXDATA_PTR (  (reg8 *) \\r
-                                                SD_BSPIM_sR8_Dp_u0__F1_REG)\r
-    #endif /* (SD_USE_SECOND_DATAPATH) */\r
-#endif     /* (CY_PSOC3 || CY_PSOC5) */\r
-\r
-#define SD_AUX_CONTROL_DP0_REG (* (reg8 *) \\r
-                                        SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)\r
-#define SD_AUX_CONTROL_DP0_PTR (  (reg8 *) \\r
-                                        SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)\r
-\r
-#if(SD_USE_SECOND_DATAPATH)\r
-    #define SD_AUX_CONTROL_DP1_REG  (* (reg8 *) \\r
-                                        SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)\r
-    #define SD_AUX_CONTROL_DP1_PTR  (  (reg8 *) \\r
-                                        SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)\r
-#endif /* (SD_USE_SECOND_DATAPATH) */\r
-\r
-#define SD_COUNTER_PERIOD_REG     (* (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG)\r
-#define SD_COUNTER_PERIOD_PTR     (  (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG)\r
-#define SD_COUNTER_CONTROL_REG    (* (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)\r
-#define SD_COUNTER_CONTROL_PTR    (  (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)\r
-\r
-#define SD_TX_STATUS_REG          (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG)\r
-#define SD_TX_STATUS_PTR          (  (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG)\r
-#define SD_RX_STATUS_REG          (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG)\r
-#define SD_RX_STATUS_PTR          (  (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG)\r
-\r
-#define SD_CONTROL_REG            (* (reg8 *) \\r
-                                      SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)\r
-#define SD_CONTROL_PTR            (  (reg8 *) \\r
-                                      SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)\r
-\r
-#define SD_TX_STATUS_MASK_REG     (* (reg8 *) SD_BSPIM_TxStsReg__MASK_REG)\r
-#define SD_TX_STATUS_MASK_PTR     (  (reg8 *) SD_BSPIM_TxStsReg__MASK_REG)\r
-#define SD_RX_STATUS_MASK_REG     (* (reg8 *) SD_BSPIM_RxStsReg__MASK_REG)\r
-#define SD_RX_STATUS_MASK_PTR     (  (reg8 *) SD_BSPIM_RxStsReg__MASK_REG)\r
-\r
-#define SD_TX_STATUS_ACTL_REG     (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)\r
-#define SD_TX_STATUS_ACTL_PTR     (  (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)\r
-#define SD_RX_STATUS_ACTL_REG     (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)\r
-#define SD_RX_STATUS_ACTL_PTR     (  (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)\r
-\r
-#if(SD_USE_SECOND_DATAPATH)\r
-    #define SD_AUX_CONTROLDP1     (SD_AUX_CONTROL_DP1_REG)\r
-#endif /* (SD_USE_SECOND_DATAPATH) */\r
-\r
-\r
-/***************************************\r
-*       Register Constants\r
-***************************************/\r
-\r
-/* Status Register Definitions */\r
-#define SD_STS_SPI_DONE_SHIFT             (0x00u)\r
-#define SD_STS_TX_FIFO_EMPTY_SHIFT        (0x01u)\r
-#define SD_STS_TX_FIFO_NOT_FULL_SHIFT     (0x02u)\r
-#define SD_STS_BYTE_COMPLETE_SHIFT        (0x03u)\r
-#define SD_STS_SPI_IDLE_SHIFT             (0x04u)\r
-#define SD_STS_RX_FIFO_FULL_SHIFT         (0x04u)\r
-#define SD_STS_RX_FIFO_NOT_EMPTY_SHIFT    (0x05u)\r
-#define SD_STS_RX_FIFO_OVERRUN_SHIFT      (0x06u)\r
-\r
-#define SD_STS_SPI_DONE           ((uint8) (0x01u << SD_STS_SPI_DONE_SHIFT))\r
-#define SD_STS_TX_FIFO_EMPTY      ((uint8) (0x01u << SD_STS_TX_FIFO_EMPTY_SHIFT))\r
-#define SD_STS_TX_FIFO_NOT_FULL   ((uint8) (0x01u << SD_STS_TX_FIFO_NOT_FULL_SHIFT))\r
-#define SD_STS_BYTE_COMPLETE      ((uint8) (0x01u << SD_STS_BYTE_COMPLETE_SHIFT))\r
-#define SD_STS_SPI_IDLE           ((uint8) (0x01u << SD_STS_SPI_IDLE_SHIFT))\r
-#define SD_STS_RX_FIFO_FULL       ((uint8) (0x01u << SD_STS_RX_FIFO_FULL_SHIFT))\r
-#define SD_STS_RX_FIFO_NOT_EMPTY  ((uint8) (0x01u << SD_STS_RX_FIFO_NOT_EMPTY_SHIFT))\r
-#define SD_STS_RX_FIFO_OVERRUN    ((uint8) (0x01u << SD_STS_RX_FIFO_OVERRUN_SHIFT))\r
-\r
-/* TX and RX masks for clear on read bits */\r
-#define SD_TX_STS_CLR_ON_RD_BYTES_MASK    (0x09u)\r
-#define SD_RX_STS_CLR_ON_RD_BYTES_MASK    (0x40u)\r
-\r
-/* StatusI Register Interrupt Enable Control Bits */\r
-/* As defined by the Register map for the AUX Control Register */\r
-#define SD_INT_ENABLE     (0x10u) /* Enable interrupt from statusi */\r
-#define SD_TX_FIFO_CLR    (0x01u) /* F0 - TX FIFO */\r
-#define SD_RX_FIFO_CLR    (0x02u) /* F1 - RX FIFO */\r
-#define SD_FIFO_CLR       (SD_TX_FIFO_CLR | SD_RX_FIFO_CLR)\r
-\r
-/* Bit Counter (7-bit) Control Register Bit Definitions */\r
-/* As defined by the Register map for the AUX Control Register */\r
-#define SD_CNTR_ENABLE    (0x20u) /* Enable CNT7 */\r
-\r
-/* Bi-Directional mode control bit */\r
-#define SD_CTRL_TX_SIGNAL_EN  (0x01u)\r
-\r
-/* Datapath Auxillary Control Register definitions */\r
-#define SD_AUX_CTRL_FIFO0_CLR         (0x01u)\r
-#define SD_AUX_CTRL_FIFO1_CLR         (0x02u)\r
-#define SD_AUX_CTRL_FIFO0_LVL         (0x04u)\r
-#define SD_AUX_CTRL_FIFO1_LVL         (0x08u)\r
-#define SD_STATUS_ACTL_INT_EN_MASK    (0x10u)\r
-\r
-/* Component disabled */\r
-#define SD_DISABLED   (0u)\r
-\r
-\r
-/***************************************\r
-*       Macros\r
-***************************************/\r
-\r
-/* Returns true if componentn enabled */\r
-#define SD_IS_ENABLED (0u != (SD_TX_STATUS_ACTL_REG & SD_INT_ENABLE))\r
-\r
-/* Retuns TX status register */\r
-#define SD_GET_STATUS_TX(swTxSts) ( (uint8)(SD_TX_STATUS_REG | \\r
-                                                          ((swTxSts) & SD_TX_STS_CLR_ON_RD_BYTES_MASK)) )\r
-/* Retuns RX status register */\r
-#define SD_GET_STATUS_RX(swRxSts) ( (uint8)(SD_RX_STATUS_REG | \\r
-                                                          ((swRxSts) & SD_RX_STS_CLR_ON_RD_BYTES_MASK)) )\r
-\r
-\r
-/***************************************\r
-*       Obsolete definitions\r
-***************************************/\r
-\r
-/* Following definitions are for version compatibility.\r
-*  They are obsolete in SPIM v2_30.\r
-*  Please do not use it in new projects\r
-*/\r
-\r
-#define SD_WriteByte   SD_WriteTxData\r
-#define SD_ReadByte    SD_ReadRxData\r
-void  SD_SetInterruptMode(uint8 intSrc)       ;\r
-uint8 SD_ReadStatus(void)                     ;\r
-void  SD_EnableInt(void)                      ;\r
-void  SD_DisableInt(void)                     ;\r
-\r
-/* Obsolete register names. Not to be used in new designs */\r
-#define SD_TXDATA                 (SD_TXDATA_REG)\r
-#define SD_RXDATA                 (SD_RXDATA_REG)\r
-#define SD_AUX_CONTROLDP0         (SD_AUX_CONTROL_DP0_REG)\r
-#define SD_TXBUFFERREAD           (SD_txBufferRead)\r
-#define SD_TXBUFFERWRITE          (SD_txBufferWrite)\r
-#define SD_RXBUFFERREAD           (SD_rxBufferRead)\r
-#define SD_RXBUFFERWRITE          (SD_rxBufferWrite)\r
-\r
-#define SD_COUNTER_PERIOD         (SD_COUNTER_PERIOD_REG)\r
-#define SD_COUNTER_CONTROL        (SD_COUNTER_CONTROL_REG)\r
-#define SD_STATUS                 (SD_TX_STATUS_REG)\r
-#define SD_CONTROL                (SD_CONTROL_REG)\r
-#define SD_STATUS_MASK            (SD_TX_STATUS_MASK_REG)\r
-#define SD_STATUS_ACTL            (SD_TX_STATUS_ACTL_REG)\r
-\r
-#define SD_INIT_INTERRUPTS_MASK  (SD_INT_ON_SPI_DONE     | \\r
-                                                SD_INT_ON_TX_EMPTY     | \\r
-                                                SD_INT_ON_TX_NOT_FULL_DEF  | \\r
-                                                SD_INT_ON_RX_FULL      | \\r
-                                                SD_INT_ON_RX_NOT_EMPTY | \\r
-                                                SD_INT_ON_RX_OVER      | \\r
-                                                SD_INT_ON_BYTE_COMP)\r
-                                                \r
-/* Following definitions are for version Compatibility.\r
-*  They are obsolete in SPIM v2_40.\r
-*  Please do not use it in new projects\r
-*/\r
-\r
-#define SD_DataWidth                  (SD_DATA_WIDTH)\r
-#define SD_InternalClockUsed          (SD_INTERNAL_CLOCK)\r
-#define SD_InternalTxInterruptEnabled (SD_INTERNAL_TX_INT_ENABLED)\r
-#define SD_InternalRxInterruptEnabled (SD_INTERNAL_RX_INT_ENABLED)\r
-#define SD_ModeUseZero                (SD_MODE_USE_ZERO)\r
-#define SD_BidirectionalMode          (SD_BIDIRECTIONAL_MODE)\r
-#define SD_Mode                       (SD_MODE)\r
-#define SD_DATAWIDHT                  (SD_DATA_WIDTH)\r
-#define SD_InternalInterruptEnabled   (0u)\r
-\r
-#define SD_TXBUFFERSIZE   (SD_TX_BUFFER_SIZE)\r
-#define SD_RXBUFFERSIZE   (SD_RX_BUFFER_SIZE)\r
-\r
-#define SD_TXBUFFER       SD_txBuffer\r
-#define SD_RXBUFFER       SD_rxBuffer\r
-\r
-#endif /* (CY_SPIM_SD_H) */\r
-\r
-\r
-/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_INT.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_INT.c
deleted file mode 100644 (file)
index b9bb216..0000000
+++ /dev/null
@@ -1,189 +0,0 @@
-/*******************************************************************************\r
-* File Name: SD_INT.c\r
-* Version 2.40\r
-*\r
-* Description:\r
-*  This file provides all Interrupt Service Routine (ISR) for the SPI Master\r
-*  component.\r
-*\r
-* Note:\r
-*  None.\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "SD_PVT.h"\r
-\r
-/* User code required at start of ISR */\r
-/* `#START SD_ISR_START_DEF` */\r
-\r
-/* `#END` */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_TX_ISR\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Interrupt Service Routine for TX portion of the SPI Master.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Global variables:\r
-*  SD_txBufferWrite - used for the account of the bytes which\r
-*  have been written down in the TX software buffer.\r
-*  SD_txBufferRead - used for the account of the bytes which\r
-*  have been read from the TX software buffer, modified when exist data to\r
-*  sending and FIFO Not Full.\r
-*  SD_txBuffer[SD_TX_BUFFER_SIZE] - used to store\r
-*  data to sending.\r
-*  All described above Global variables are used when Software Buffer is used.\r
-*\r
-*******************************************************************************/\r
-CY_ISR(SD_TX_ISR)\r
-{\r
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
-        uint8 tmpStatus;\r
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    /* User code required at start of ISR */\r
-    /* `#START SD_TX_ISR_START` */\r
-\r
-    /* `#END` */\r
-\r
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
-        /* Check if TX data buffer is not empty and there is space in TX FIFO */\r
-        while(SD_txBufferRead != SD_txBufferWrite)\r
-        {\r
-            tmpStatus = SD_GET_STATUS_TX(SD_swStatusTx);\r
-            SD_swStatusTx = tmpStatus;\r
-\r
-            if(0u != (SD_swStatusTx & SD_STS_TX_FIFO_NOT_FULL))\r
-            {\r
-                if(0u == SD_txBufferFull)\r
-                {\r
-                   SD_txBufferRead++;\r
-\r
-                    if(SD_txBufferRead >= SD_TX_BUFFER_SIZE)\r
-                    {\r
-                        SD_txBufferRead = 0u;\r
-                    }\r
-                }\r
-                else\r
-                {\r
-                    SD_txBufferFull = 0u;\r
-                }\r
-\r
-                /* Move data from the Buffer to the FIFO */\r
-                CY_SET_REG8(SD_TXDATA_PTR,\r
-                    SD_txBuffer[SD_txBufferRead]);\r
-            }\r
-            else\r
-            {\r
-                break;\r
-            }\r
-        }\r
-\r
-        if(SD_txBufferRead == SD_txBufferWrite)\r
-        {\r
-            /* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */\r
-            SD_TX_STATUS_MASK_REG &= ((uint8) ~SD_STS_TX_FIFO_NOT_FULL);\r
-        }\r
-\r
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    /* User code required at end of ISR (Optional) */\r
-    /* `#START SD_TX_ISR_END` */\r
-\r
-    /* `#END` */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_RX_ISR\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Interrupt Service Routine for RX portion of the SPI Master.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Global variables:\r
-*  SD_rxBufferWrite - used for the account of the bytes which\r
-*  have been written down in the RX software buffer modified when FIFO contains\r
-*  new data.\r
-*  SD_rxBufferRead - used for the account of the bytes which\r
-*  have been read from the RX software buffer, modified when overflow occurred.\r
-*  SD_rxBuffer[SD_RX_BUFFER_SIZE] - used to store\r
-*  received data, modified when FIFO contains new data.\r
-*  All described above Global variables are used when Software Buffer is used.\r
-*\r
-*******************************************************************************/\r
-CY_ISR(SD_RX_ISR)\r
-{\r
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-        uint8 tmpStatus;\r
-        uint8 rxData;\r
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    /* User code required at start of ISR */\r
-    /* `#START SD_RX_ISR_START` */\r
-\r
-    /* `#END` */\r
-\r
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-\r
-        tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);\r
-        SD_swStatusRx = tmpStatus;\r
-\r
-        /* Check if RX data FIFO has some data to be moved into the RX Buffer */\r
-        while(0u != (SD_swStatusRx & SD_STS_RX_FIFO_NOT_EMPTY))\r
-        {\r
-            rxData = CY_GET_REG8(SD_RXDATA_PTR);\r
-\r
-            /* Set next pointer. */\r
-            SD_rxBufferWrite++;\r
-            if(SD_rxBufferWrite >= SD_RX_BUFFER_SIZE)\r
-            {\r
-                SD_rxBufferWrite = 0u;\r
-            }\r
-\r
-            if(SD_rxBufferWrite == SD_rxBufferRead)\r
-            {\r
-                SD_rxBufferRead++;\r
-                if(SD_rxBufferRead >= SD_RX_BUFFER_SIZE)\r
-                {\r
-                    SD_rxBufferRead = 0u;\r
-                }\r
-\r
-                SD_rxBufferFull = 1u;\r
-            }\r
-\r
-            /* Move data from the FIFO to the Buffer */\r
-            SD_rxBuffer[SD_rxBufferWrite] = rxData;\r
-\r
-            tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);\r
-            SD_swStatusRx = tmpStatus;\r
-        }\r
-\r
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    /* User code required at end of ISR (Optional) */\r
-    /* `#START SD_RX_ISR_END` */\r
-\r
-    /* `#END` */\r
-}\r
-\r
-/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.c
deleted file mode 100644 (file)
index 8848744..0000000
+++ /dev/null
@@ -1,521 +0,0 @@
-/*******************************************************************************\r
-* File Name: SD_IntClock.c\r
-* Version 2.0\r
-*\r
-*  Description:\r
-*   This file provides the source code to the API for the clock component.\r
-*\r
-*  Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include <cydevice_trm.h>\r
-#include "SD_IntClock.h"\r
-\r
-/* Clock Distribution registers. */\r
-#define CLK_DIST_LD              (* (reg8 *) CYREG_CLKDIST_LD)\r
-#define CLK_DIST_BCFG2           (* (reg8 *) CYREG_CLKDIST_BCFG2)\r
-#define BCFG2_MASK               (0x80u)\r
-#define CLK_DIST_DMASK           (* (reg8 *) CYREG_CLKDIST_DMASK)\r
-#define CLK_DIST_AMASK           (* (reg8 *) CYREG_CLKDIST_AMASK)\r
-\r
-#define HAS_CLKDIST_LD_DISABLE   (CY_PSOC3 || CY_PSOC5LP)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_Start\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Starts the clock. Note that on startup, clocks may be already running if the\r
-*  "Start on Reset" option is enabled in the DWR.\r
-*\r
-* Parameters:\r
-*  None\r
-*\r
-* Returns:\r
-*  None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_Start(void) \r
-{\r
-    /* Set the bit to enable the clock. */\r
-    SD_IntClock_CLKEN |= SD_IntClock_CLKEN_MASK;\r
-       SD_IntClock_CLKSTBY |= SD_IntClock_CLKSTBY_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_Stop\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Stops the clock and returns immediately. This API does not require the\r
-*  source clock to be running but may return before the hardware is actually\r
-*  disabled. If the settings of the clock are changed after calling this\r
-*  function, the clock may glitch when it is started. To avoid the clock\r
-*  glitch, use the StopBlock function.\r
-*\r
-* Parameters:\r
-*  None\r
-*\r
-* Returns:\r
-*  None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_Stop(void) \r
-{\r
-    /* Clear the bit to disable the clock. */\r
-    SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK);\r
-       SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK);\r
-}\r
-\r
-\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_StopBlock\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Stops the clock and waits for the hardware to actually be disabled before\r
-*  returning. This ensures that the clock is never truncated (high part of the\r
-*  cycle will terminate before the clock is disabled and the API returns).\r
-*  Note that the source clock must be running or this API will never return as\r
-*  a stopped clock cannot be disabled.\r
-*\r
-* Parameters:\r
-*  None\r
-*\r
-* Returns:\r
-*  None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_StopBlock(void) \r
-{\r
-    if ((SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK) != 0u)\r
-    {\r
-#if HAS_CLKDIST_LD_DISABLE\r
-        uint16 oldDivider;\r
-\r
-        CLK_DIST_LD = 0u;\r
-\r
-        /* Clear all the mask bits except ours. */\r
-#if defined(SD_IntClock__CFG3)\r
-        CLK_DIST_AMASK = SD_IntClock_CLKEN_MASK;\r
-        CLK_DIST_DMASK = 0x00u;\r
-#else\r
-        CLK_DIST_DMASK = SD_IntClock_CLKEN_MASK;\r
-        CLK_DIST_AMASK = 0x00u;\r
-#endif /* SD_IntClock__CFG3 */\r
-\r
-        /* Clear mask of bus clock. */\r
-        CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
-\r
-        oldDivider = CY_GET_REG16(SD_IntClock_DIV_PTR);\r
-        CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
-        CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;\r
-\r
-        /* Wait for clock to be disabled */\r
-        while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
-\r
-        /* Clear the bit to disable the clock. */\r
-        SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK);\r
-        SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK);\r
-\r
-#if HAS_CLKDIST_LD_DISABLE\r
-        /* Clear the disable bit */\r
-        CLK_DIST_LD = 0x00u;\r
-        CY_SET_REG16(SD_IntClock_DIV_PTR, oldDivider);\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
-    }\r
-}\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_StandbyPower\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Sets whether the clock is active in standby mode.\r
-*\r
-* Parameters:\r
-*  state:  0 to disable clock during standby, nonzero to enable.\r
-*\r
-* Returns:\r
-*  None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_StandbyPower(uint8 state) \r
-{\r
-    if(state == 0u)\r
-    {\r
-        SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK);\r
-    }\r
-    else\r
-    {\r
-        SD_IntClock_CLKSTBY |= SD_IntClock_CLKSTBY_MASK;\r
-    }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_SetDividerRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Modifies the clock divider and, thus, the frequency. When the clock divider\r
-*  register is set to zero or changed from zero, the clock will be temporarily\r
-*  disabled in order to change the SSS mode bit. If the clock is enabled when\r
-*  SetDividerRegister is called, then the source clock must be running.\r
-*\r
-* Parameters:\r
-*  clkDivider:  Divider register value (0-65,535). This value is NOT the\r
-*    divider; the clock hardware divides by clkDivider plus one. For example,\r
-*    to divide the clock by 2, this parameter should be set to 1.\r
-*  restart:  If nonzero, restarts the clock divider: the current clock cycle\r
-*   will be truncated and the new divide value will take effect immediately. If\r
-*   zero, the new divide value will take effect at the end of the current clock\r
-*   cycle.\r
-*\r
-* Returns:\r
-*  None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_SetDividerRegister(uint16 clkDivider, uint8 restart)\r
-                                \r
-{\r
-    uint8 enabled;\r
-\r
-    uint8 currSrc = SD_IntClock_GetSourceRegister();\r
-    uint16 oldDivider = SD_IntClock_GetDividerRegister();\r
-\r
-    if (clkDivider != oldDivider)\r
-    {\r
-        enabled = SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK;\r
-\r
-        if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))\r
-        {\r
-            /* Moving to/from SSS requires correct ordering to prevent halting the clock    */\r
-            if (oldDivider == 0u)\r
-            {\r
-                /* Moving away from SSS, set the divider first so when SSS is cleared we    */\r
-                /* don't halt the clock.  Using the shadow load isn't required as the       */\r
-                /* divider is ignored while SSS is set.                                     */\r
-                CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider);\r
-                SD_IntClock_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
-            }\r
-            else\r
-            {\r
-                /* Moving to SSS, set SSS which then ignores the divider and we can set     */\r
-                /* it without bothering with the shadow load.                               */\r
-                SD_IntClock_MOD_SRC |= CYCLK_SSS;\r
-                CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider);\r
-            }\r
-        }\r
-        else\r
-        {\r
-                       \r
-            if (enabled != 0u)\r
-            {\r
-                CLK_DIST_LD = 0x00u;\r
-\r
-                /* Clear all the mask bits except ours. */\r
-#if defined(SD_IntClock__CFG3)\r
-                CLK_DIST_AMASK = SD_IntClock_CLKEN_MASK;\r
-                CLK_DIST_DMASK = 0x00u;\r
-#else\r
-                CLK_DIST_DMASK = SD_IntClock_CLKEN_MASK;\r
-                CLK_DIST_AMASK = 0x00u;\r
-#endif /* SD_IntClock__CFG3 */\r
-                /* Clear mask of bus clock. */\r
-                CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
-\r
-                /* If clock is currently enabled, disable it if async or going from N-to-1*/\r
-                if (((SD_IntClock_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))\r
-                {\r
-#if HAS_CLKDIST_LD_DISABLE\r
-                    CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
-                    CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;\r
-\r
-                    /* Wait for clock to be disabled */\r
-                    while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
-\r
-                    SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK);\r
-\r
-#if HAS_CLKDIST_LD_DISABLE\r
-                    /* Clear the disable bit */\r
-                    CLK_DIST_LD = 0x00u;\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
-                }\r
-            }\r
-\r
-            /* Load divide value. */\r
-            if ((SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK) != 0u)\r
-            {\r
-                /* If the clock is still enabled, use the shadow registers */\r
-                CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);\r
-\r
-                CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));\r
-                while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
-            }\r
-            else\r
-            {\r
-                /* If the clock is disabled, set the divider directly */\r
-                CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider);\r
-                               SD_IntClock_CLKEN |= enabled;\r
-            }\r
-        }\r
-    }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_GetDividerRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Gets the clock divider register value.\r
-*\r
-* Parameters:\r
-*  None\r
-*\r
-* Returns:\r
-*  Divide value of the clock minus 1. For example, if the clock is set to\r
-*  divide by 2, the return value will be 1.\r
-*\r
-*******************************************************************************/\r
-uint16 SD_IntClock_GetDividerRegister(void) \r
-{\r
-    return CY_GET_REG16(SD_IntClock_DIV_PTR);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_SetModeRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Sets flags that control the operating mode of the clock. This function only\r
-*  changes flags from 0 to 1; flags that are already 1 will remain unchanged.\r
-*  To clear flags, use the ClearModeRegister function. The clock must be\r
-*  disabled before changing the mode.\r
-*\r
-* Parameters:\r
-*  clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,\r
-*   clkMode should be a set of the following optional bits or'ed together.\r
-*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
-*                 occur when the divider count reaches half of the divide\r
-*                 value.\r
-*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock\r
-*                 is asserted for approximately half of its period. When\r
-*                 disabled, the output clock is asserted for one period of the\r
-*                 source clock.\r
-*   - CYCLK_SYNC  Enable output synchronization to master clock. This should\r
-*                 be enabled for all synchronous clocks.\r
-*   See the Technical Reference Manual for details about setting the mode of\r
-*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
-*\r
-* Returns:\r
-*  None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_SetModeRegister(uint8 modeBitMask) \r
-{\r
-    SD_IntClock_MOD_SRC |= modeBitMask & (uint8)SD_IntClock_MODE_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_ClearModeRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Clears flags that control the operating mode of the clock. This function\r
-*  only changes flags from 1 to 0; flags that are already 0 will remain\r
-*  unchanged. To set flags, use the SetModeRegister function. The clock must be\r
-*  disabled before changing the mode.\r
-*\r
-* Parameters:\r
-*  clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,\r
-*   clkMode should be a set of the following optional bits or'ed together.\r
-*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
-*                 occur when the divider count reaches half of the divide\r
-*                 value.\r
-*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock\r
-*                 is asserted for approximately half of its period. When\r
-*                 disabled, the output clock is asserted for one period of the\r
-*                 source clock.\r
-*   - CYCLK_SYNC  Enable output synchronization to master clock. This should\r
-*                 be enabled for all synchronous clocks.\r
-*   See the Technical Reference Manual for details about setting the mode of\r
-*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
-*\r
-* Returns:\r
-*  None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_ClearModeRegister(uint8 modeBitMask) \r
-{\r
-    SD_IntClock_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_IntClock_MODE_MASK));\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_GetModeRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Gets the clock mode register value.\r
-*\r
-* Parameters:\r
-*  None\r
-*\r
-* Returns:\r
-*  Bit mask representing the enabled mode bits. See the SetModeRegister and\r
-*  ClearModeRegister descriptions for details about the mode bits.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_IntClock_GetModeRegister(void) \r
-{\r
-    return SD_IntClock_MOD_SRC & (uint8)(SD_IntClock_MODE_MASK);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_SetSourceRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Sets the input source of the clock. The clock must be disabled before\r
-*  changing the source. The old and new clock sources must be running.\r
-*\r
-* Parameters:\r
-*  clkSource:  For PSoC 3 and PSoC 5 devices, clkSource should be one of the\r
-*   following input sources:\r
-*   - CYCLK_SRC_SEL_SYNC_DIG\r
-*   - CYCLK_SRC_SEL_IMO\r
-*   - CYCLK_SRC_SEL_XTALM\r
-*   - CYCLK_SRC_SEL_ILO\r
-*   - CYCLK_SRC_SEL_PLL\r
-*   - CYCLK_SRC_SEL_XTALK\r
-*   - CYCLK_SRC_SEL_DSI_G\r
-*   - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A\r
-*   See the Technical Reference Manual for details on clock sources.\r
-*\r
-* Returns:\r
-*  None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_SetSourceRegister(uint8 clkSource) \r
-{\r
-    uint16 currDiv = SD_IntClock_GetDividerRegister();\r
-    uint8 oldSrc = SD_IntClock_GetSourceRegister();\r
-\r
-    if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
-        (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
-    {\r
-        /* Switching to Master and divider is 1, set SSS, which will output master, */\r
-        /* then set the source so we are consistent.                                */\r
-        SD_IntClock_MOD_SRC |= CYCLK_SSS;\r
-        SD_IntClock_MOD_SRC =\r
-            (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource;\r
-    }\r
-    else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
-            (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
-    {\r
-        /* Switching from Master to not and divider is 1, set source, so we don't   */\r
-        /* lock when we clear SSS.                                                  */\r
-        SD_IntClock_MOD_SRC =\r
-            (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource;\r
-        SD_IntClock_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
-    }\r
-    else\r
-    {\r
-        SD_IntClock_MOD_SRC =\r
-            (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource;\r
-    }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_GetSourceRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Gets the input source of the clock.\r
-*\r
-* Parameters:\r
-*  None\r
-*\r
-* Returns:\r
-*  The input source of the clock. See SetSourceRegister for details.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_IntClock_GetSourceRegister(void) \r
-{\r
-    return SD_IntClock_MOD_SRC & SD_IntClock_SRC_SEL_MSK;\r
-}\r
-\r
-\r
-#if defined(SD_IntClock__CFG3)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_SetPhaseRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Sets the phase delay of the analog clock. This function is only available\r
-*  for analog clocks. The clock must be disabled before changing the phase\r
-*  delay to avoid glitches.\r
-*\r
-* Parameters:\r
-*  clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.\r
-*   clkPhase must be from 1 to 11 inclusive. Other values, including 0,\r
-*   disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 \r
-*   produces a 10ns delay.\r
-*\r
-* Returns:\r
-*  None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_SetPhaseRegister(uint8 clkPhase) \r
-{\r
-    SD_IntClock_PHASE = clkPhase & SD_IntClock_PHASE_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_GetPhase\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Gets the phase delay of the analog clock. This function is only available\r
-*  for analog clocks.\r
-*\r
-* Parameters:\r
-*  None\r
-*\r
-* Returns:\r
-*  Phase of the analog clock. See SetPhaseRegister for details.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_IntClock_GetPhaseRegister(void) \r
-{\r
-    return SD_IntClock_PHASE & SD_IntClock_PHASE_MASK;\r
-}\r
-\r
-#endif /* SD_IntClock__CFG3 */\r
-\r
-\r
-/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.h
deleted file mode 100644 (file)
index df76982..0000000
+++ /dev/null
@@ -1,124 +0,0 @@
-/*******************************************************************************\r
-* File Name: SD_IntClock.h\r
-* Version 2.0\r
-*\r
-*  Description:\r
-*   Provides the function and constant definitions for the clock component.\r
-*\r
-*  Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_CLOCK_SD_IntClock_H)\r
-#define CY_CLOCK_SD_IntClock_H\r
-\r
-#include <cytypes.h>\r
-#include <cyfitter.h>\r
-\r
-\r
-/***************************************\r
-* Conditional Compilation Parameters\r
-***************************************/\r
-\r
-/* Check to see if required defines such as CY_PSOC5LP are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5LP)\r
-    #error Component cy_clock_v2_0 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5LP) */\r
-\r
-\r
-/***************************************\r
-*        Function Prototypes\r
-***************************************/\r
-\r
-void SD_IntClock_Start(void) ;\r
-void SD_IntClock_Stop(void) ;\r
-\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
-void SD_IntClock_StopBlock(void) ;\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
-void SD_IntClock_StandbyPower(uint8 state) ;\r
-void SD_IntClock_SetDividerRegister(uint16 clkDivider, uint8 restart) \r
-                                ;\r
-uint16 SD_IntClock_GetDividerRegister(void) ;\r
-void SD_IntClock_SetModeRegister(uint8 modeBitMask) ;\r
-void SD_IntClock_ClearModeRegister(uint8 modeBitMask) ;\r
-uint8 SD_IntClock_GetModeRegister(void) ;\r
-void SD_IntClock_SetSourceRegister(uint8 clkSource) ;\r
-uint8 SD_IntClock_GetSourceRegister(void) ;\r
-#if defined(SD_IntClock__CFG3)\r
-void SD_IntClock_SetPhaseRegister(uint8 clkPhase) ;\r
-uint8 SD_IntClock_GetPhaseRegister(void) ;\r
-#endif /* defined(SD_IntClock__CFG3) */\r
-\r
-#define SD_IntClock_Enable()                       SD_IntClock_Start()\r
-#define SD_IntClock_Disable()                      SD_IntClock_Stop()\r
-#define SD_IntClock_SetDivider(clkDivider)         SD_IntClock_SetDividerRegister(clkDivider, 1)\r
-#define SD_IntClock_SetDividerValue(clkDivider)    SD_IntClock_SetDividerRegister((clkDivider) - 1, 1)\r
-#define SD_IntClock_SetMode(clkMode)               SD_IntClock_SetModeRegister(clkMode)\r
-#define SD_IntClock_SetSource(clkSource)           SD_IntClock_SetSourceRegister(clkSource)\r
-#if defined(SD_IntClock__CFG3)\r
-#define SD_IntClock_SetPhase(clkPhase)             SD_IntClock_SetPhaseRegister(clkPhase)\r
-#define SD_IntClock_SetPhaseValue(clkPhase)        SD_IntClock_SetPhaseRegister((clkPhase) + 1)\r
-#endif /* defined(SD_IntClock__CFG3) */\r
-\r
-\r
-/***************************************\r
-*             Registers\r
-***************************************/\r
-\r
-/* Register to enable or disable the clock */\r
-#define SD_IntClock_CLKEN              (* (reg8 *) SD_IntClock__PM_ACT_CFG)\r
-#define SD_IntClock_CLKEN_PTR          ((reg8 *) SD_IntClock__PM_ACT_CFG)\r
-\r
-/* Register to enable or disable the clock */\r
-#define SD_IntClock_CLKSTBY            (* (reg8 *) SD_IntClock__PM_STBY_CFG)\r
-#define SD_IntClock_CLKSTBY_PTR        ((reg8 *) SD_IntClock__PM_STBY_CFG)\r
-\r
-/* Clock LSB divider configuration register. */\r
-#define SD_IntClock_DIV_LSB            (* (reg8 *) SD_IntClock__CFG0)\r
-#define SD_IntClock_DIV_LSB_PTR        ((reg8 *) SD_IntClock__CFG0)\r
-#define SD_IntClock_DIV_PTR            ((reg16 *) SD_IntClock__CFG0)\r
-\r
-/* Clock MSB divider configuration register. */\r
-#define SD_IntClock_DIV_MSB            (* (reg8 *) SD_IntClock__CFG1)\r
-#define SD_IntClock_DIV_MSB_PTR        ((reg8 *) SD_IntClock__CFG1)\r
-\r
-/* Mode and source configuration register */\r
-#define SD_IntClock_MOD_SRC            (* (reg8 *) SD_IntClock__CFG2)\r
-#define SD_IntClock_MOD_SRC_PTR        ((reg8 *) SD_IntClock__CFG2)\r
-\r
-#if defined(SD_IntClock__CFG3)\r
-/* Analog clock phase configuration register */\r
-#define SD_IntClock_PHASE              (* (reg8 *) SD_IntClock__CFG3)\r
-#define SD_IntClock_PHASE_PTR          ((reg8 *) SD_IntClock__CFG3)\r
-#endif /* defined(SD_IntClock__CFG3) */\r
-\r
-\r
-/**************************************\r
-*       Register Constants\r
-**************************************/\r
-\r
-/* Power manager register masks */\r
-#define SD_IntClock_CLKEN_MASK         SD_IntClock__PM_ACT_MSK\r
-#define SD_IntClock_CLKSTBY_MASK       SD_IntClock__PM_STBY_MSK\r
-\r
-/* CFG2 field masks */\r
-#define SD_IntClock_SRC_SEL_MSK        SD_IntClock__CFG2_SRC_SEL_MASK\r
-#define SD_IntClock_MODE_MASK          (~(SD_IntClock_SRC_SEL_MSK))\r
-\r
-#if defined(SD_IntClock__CFG3)\r
-/* CFG3 phase mask */\r
-#define SD_IntClock_PHASE_MASK         SD_IntClock__CFG3_PHASE_DLY_MASK\r
-#endif /* defined(SD_IntClock__CFG3) */\r
-\r
-#endif /* CY_CLOCK_SD_IntClock_H */\r
-\r
-\r
-/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PM.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PM.c
deleted file mode 100644 (file)
index d2388e6..0000000
+++ /dev/null
@@ -1,180 +0,0 @@
-/*******************************************************************************\r
-* File Name: SD_PM.c\r
-* Version 2.40\r
-*\r
-* Description:\r
-*  This file contains the setup, control and status commands to support\r
-*  component operations in low power mode.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "SD_PVT.h"\r
-\r
-static SD_BACKUP_STRUCT SD_backup =\r
-{\r
-    SD_DISABLED,\r
-    SD_BITCTR_INIT,\r
-    #if(CY_UDB_V0)\r
-        SD_TX_INIT_INTERRUPTS_MASK,\r
-        SD_RX_INIT_INTERRUPTS_MASK\r
-    #endif /* CY_UDB_V0 */\r
-};\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_SaveConfig\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Saves SPIM configuration.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Global Variables:\r
-*  SD_backup - modified when non-retention registers are saved.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-void SD_SaveConfig(void) \r
-{\r
-    /* Store Status Mask registers */\r
-    #if(CY_UDB_V0)\r
-       SD_backup.cntrPeriod      = SD_COUNTER_PERIOD_REG;\r
-       SD_backup.saveSrTxIntMask = SD_TX_STATUS_MASK_REG;\r
-       SD_backup.saveSrRxIntMask = SD_RX_STATUS_MASK_REG;\r
-    #endif /* (CY_UDB_V0) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_RestoreConfig\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Restores SPIM configuration.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Global Variables:\r
-*  SD_backup - used when non-retention registers are restored.\r
-*\r
-* Side Effects:\r
-*  If this API is called without first calling SaveConfig then in the following\r
-*  registers will be default values from Customizer:\r
-*  SD_STATUS_MASK_REG and SD_COUNTER_PERIOD_REG.\r
-*\r
-*******************************************************************************/\r
-void SD_RestoreConfig(void) \r
-{\r
-    /* Restore the data, saved by SaveConfig() function */\r
-    #if(CY_UDB_V0)\r
-        SD_COUNTER_PERIOD_REG = SD_backup.cntrPeriod;\r
-        SD_TX_STATUS_MASK_REG = ((uint8) SD_backup.saveSrTxIntMask);\r
-        SD_RX_STATUS_MASK_REG = ((uint8) SD_backup.saveSrRxIntMask);\r
-    #endif /* (CY_UDB_V0) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Sleep\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Prepare SPIM Component goes to sleep.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Global Variables:\r
-*  SD_backup - modified when non-retention registers are saved.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-void SD_Sleep(void) \r
-{\r
-    /* Save components enable state */\r
-    SD_backup.enableState = ((uint8) SD_IS_ENABLED);\r
-\r
-    SD_Stop();\r
-    SD_SaveConfig();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Wakeup\r
-********************************************************************************\r
-*\r
-* Summary:\r
-*  Prepare SPIM Component to wake up.\r
-*\r
-* Parameters:\r
-*  None.\r
-*\r
-* Return:\r
-*  None.\r
-*\r
-* Global Variables:\r
-*  SD_backup - used when non-retention registers are restored.\r
-*  SD_txBufferWrite - modified every function call - resets to\r
-*  zero.\r
-*  SD_txBufferRead - modified every function call - resets to\r
-*  zero.\r
-*  SD_rxBufferWrite - modified every function call - resets to\r
-*  zero.\r
-*  SD_rxBufferRead - modified every function call - resets to\r
-*  zero.\r
-*\r
-* Reentrant:\r
-*  No.\r
-*\r
-*******************************************************************************/\r
-void SD_Wakeup(void) \r
-{\r
-    SD_RestoreConfig();\r
-\r
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-        SD_rxBufferFull  = 0u;\r
-        SD_rxBufferRead  = 0u;\r
-        SD_rxBufferWrite = 0u;\r
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
-        SD_txBufferFull  = 0u;\r
-        SD_txBufferRead  = 0u;\r
-        SD_txBufferWrite = 0u;\r
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
-    /* Clear any data from the RX and TX FIFO */\r
-    SD_ClearFIFO();\r
-\r
-    /* Restore components block enable state */\r
-    if(0u != SD_backup.enableState)\r
-    {\r
-        SD_Enable();\r
-    }\r
-}\r
-\r
-\r
-/* [] END OF FILE */\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PVT.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PVT.h
deleted file mode 100644 (file)
index cadc78e..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************\r
-* File Name: .h\r
-* Version 2.40\r
-*\r
-* Description:\r
-*  This private header file contains internal definitions for the SPIM\r
-*  component. Do not use these definitions directly in your application.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_SPIM_PVT_SD_H)\r
-#define CY_SPIM_PVT_SD_H\r
-\r
-#include "SD.h"\r
-\r
-\r
-/**********************************\r
-*   Functions with external linkage\r
-**********************************/\r
-\r
-\r
-/**********************************\r
-*   Variables with external linkage\r
-**********************************/\r
-\r
-extern volatile uint8 SD_swStatusTx;\r
-extern volatile uint8 SD_swStatusRx;\r
-\r
-#if(SD_TX_SOFTWARE_BUF_ENABLED)\r
-    extern volatile uint8 SD_txBuffer[SD_TX_BUFFER_SIZE];\r
-    extern volatile uint8 SD_txBufferRead;\r
-    extern volatile uint8 SD_txBufferWrite;\r
-    extern volatile uint8 SD_txBufferFull;\r
-#endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
-#if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-    extern volatile uint8 SD_rxBuffer[SD_RX_BUFFER_SIZE];\r
-    extern volatile uint8 SD_rxBufferRead;\r
-    extern volatile uint8 SD_rxBufferWrite;\r
-    extern volatile uint8 SD_rxBufferFull;\r
-#endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
-#endif /* CY_SPIM_PVT_SD_H */\r
-\r
-\r
-/* [] END OF FILE */\r
index 3d388ee..d1bb893 100644 (file)
@@ -1,33 +1,69 @@
-:20000000014500400752004001640040020301403F0401402A05014003060140410701400F\r
-:20002000010D014009150140431601403A17014002400140014101400142014002430140D6\r
-:200040000244014002450140044801400E4901400450014001510140360214FF1804190CB8\r
-:200060001CE12CFF34F06410860F9840B04000011D012D013001310139023E01560858047F\r
-:20008000590B5B045C905D905F01806C814184688604886C89818B408D41910492029410DC\r
-:2000A00095E296689708981099889AC59B619C6C9D479F98A06CA110A404A541A893A94076\r
-:2000C000AA20AC0FAD01AE90AF40B278B407B5C0B680B73FB980BA38BB20BE40BF40D4095A\r
-:2000E000D80BD90BDB0BDC99DD90DF010001042806800C020D010E2917691A801D301E28DE\r
-:200100001F40210222022590270829402FAA3180360637603C803D203E814BC058405D2493\r
-:200120005E025F406001664078027C029840C078C2F0C4F0CAF8CCF8CEB0D6F8D818DE812A\r
-:20014000D608DB04DD9000010240051007610D020E210F08171A1D402401250C26022760CD\r
-:200160002A022B802C022E012F2836463C803D28448045A84C804D044E02540256105784A2\r
-:200180005980600266206C146EA16F3B744077027C0294289504960199109B089C029D4007\r
-:2001A0009E409F61A132A204A442A601A7AAAA40AD21C0F0C2F0C470CAF0CCD0CE70D0F068\r
-:2001C000D210D608D828DE80EA80848089409C80A140AA40AD01B085B210E620000402082A\r
-:2001E00004100518060C0725082009200A0C0B180E030F011108120413331403192E1A30C8\r
-:200200001B101C032003260128032E4830403201343C3538360237073B203E445440580BDF\r
-:20022000590B5B0B5C995D905F018001820288068B078E1091019208970298029A01A1074D\r
-:20024000A801A904AA04AC08AE10B007B107B207B618B80ABE40BF01D80BD904DB04DC092E\r
-:20026000DF010010014003400510076109200A800E691002120813201612171218101981F1\r
-:200280001D841E4A1F102101254027082911320A351036023B203D883E20462047086405E1\r
-:2002A0006504680278027C028D409201980299109A129B739C809D809E20A080A124A21286\r
-:2002C000A580A601C0FBC2FAC4F3CA05CCA3CE74D870DE81E0403340CC109F409F40AB40E5\r
-:2002E000EE801440C404B040EA01201026808E80C86008025B205F4084028B209340A810AD\r
-:20030000AF40C210D480D620E440EC80EE4001010B0111011B0100031F0020000091FF6E98\r
-:200320007F248000906C400000716082C01008EF00009F00C06C0200C06C0100802400485E\r
-:20034000C000046C00480000000F00F00000FF1000080000000040403205100004FEDBCBA0\r
-:200360003FFFFFFF2200F0080400000000000224040B0B0B909900010000C000400110118C\r
-:20038000C0010011400140010000000000000000000000000000000000FFFF00000000000B\r
-:2003A0000800300008000000000000000000000010000000FF000000000000010200F10EEC\r
-:2003C0000E000C000000000000FCFC0000000000F0000FF00000000000010000F00F0F000D\r
-:2003E0000000000100000000000000000000000000000000000000000000000000000000FC\r
+:20000000024500400852004002640040450001403201014044020140540301403D0401407E\r
+:200020005B0501400B0601404E070140100901403C0A01403F0B01400A0D0140020F014021\r
+:2000400003150140481601404317014003190140021B0140074001401041014008420140AD\r
+:20006000054301400844014013450140064601400147014008480140094901400650014000\r
+:200080003602650200C9019C180819041CE12104300431083403820F0140060C07180A60EB\r
+:2000A0000C020F201090124814901624172419241A101B091F03230426802A902C012D243E\r
+:2000C0002F1230013140321C333834E0360237073E413F01580459045B045C995F01850148\r
+:2000E000872C880889328B018F089004920296039740980499069A019E04A008A408A501D5\r
+:20010000A71AAA04AB40AC08B207B307B408B540B738B820B908BE10BF10D804D90BDC9953\r
+:20012000DF010128030205100A780C800D100E60120C1348149016041740184019A81B2021\r
+:200140001E201F14218422012540271429012B012E14318032183608371039483A083B01AF\r
+:200160003D803F1469806B017E808180830485408B108F01C047C2FEC4F7CA69CC6ECE7B6C\r
+:20018000DE80E001E220040F055506F007AA0BFF0EFF10FF13FF150F16FF17F01D691F9657\r
+:2001A0002433253326CC27CC28552AAA2BFF2C962E6931FF34FF3E103F015602572C5804AF\r
+:2001C00059045B0B5D905F01843885108A458E38900792409406964098089C029D039F0CC7\r
+:2001E000A002A105A30AA610A820A906AB09AC01AE02B007B10FB240B510B638BE44BF11DE\r
+:20020000D440D804D904DB0BDC09DD90DF01020A0310050807010A640B020C020E201001FD\r
+:20022000124013141504160817801A501B411D10200423802740284029202D042F24318070\r
+:20024000350837813A043C203E086120632167806C206D916F027602770278027A037E80FC\r
+:200260008120820483408480861088108E4090409180920293089560966C97149801998828\r
+:200280009A089B119C909D119F48A180A210A320A480A688A701AF01B001B340B702C0A74B\r
+:2002A000C23FC4EFCA65CCD8CE62D88EDE81E201E408E603E80200030A010F081528174463\r
+:2002C000192C1B811E031F0320032403278028032B042DD42F22300233E03401351836025E\r
+:2002E00037073B303E5140644102423045E2460D47CF483749FF4AFF4BFF4F2C5601580455\r
+:2003000059045A045B045C905D095F0162C06680684069406E0888018A069405960298035D\r
+:200320009A049C049E03B607BA80D80BDC09DF0101010204051009400E010F141020111056\r
+:20034000130219421B101E011F4021102258232029042A202B01304032583980411042505D\r
+:20036000484049044A0851085240530159A85A026064618069406A086B8870907101722003\r
+:200380007E80810883018580882089108C108E409044919192529560962C979799809A022E\r
+:2003A0009B029C429D019E409F08A020A140A323A490A520A689A710AB80AF20B012B508E0\r
+:2003C000B608C04AC2E1C40ECA0ECC0ECE08D007D204D60FD80FDE80E001E210E404E602DE\r
+:2003E000E801EA50EE8010041202160318041A012A042E04320758045C095F010008010130\r
+:20040000030A09080A840D100E6010221112130217A018201C201E202040210422402A823F\r
+:200420002B16302231083240386039013B044108420443014804494850425120524558804B\r
+:200440006002628078029131924096049714988099429A029BA29C029D109E04A020A140AB\r
+:20046000A302A410A520A681A880A908AA04AB01AC50AD20B240B540B608B720C00FC27EB0\r
+:20048000C4CFCA0FCC0FCE0FD007D20CD608D808DE01E440E80AEE078E019E41A402A841DE\r
+:2004A000AB08AE09AF82B201B441B510B620B704E440E840EA01ECD00001013303CC0802A2\r
+:2004C0000FFF1196136917FF1D551FAA21FF290F2BF0340135FF36023E503F1058045904F0\r
+:2004E0005F0182028533868087CC88808A408BFF8E0891FF92049406950F960897F0988074\r
+:200500009A209D559E609FAAA002A204A410A969AA80AB96AC01ADFFB001B20EB410B6E04B\r
+:20052000B7FFBE15BF40D804D904DB04DC09DF0100010120066107080C020E220F04158058\r
+:20054000161017111A0A1C481E021F0822202640280829022C082F023102320833403408FA\r
+:200560003502374038823D203F085D085E015FA06E206F018128832084048A048B048D40F0\r
+:200580008F10980899029A109B48A008A102A661A808A902B408B740C0FAC2F0C4F0CA3575\r
+:2005A000CCDBCE69D6F0E280E460E601E8508201850286308A408F08E223E440E802EA2094\r
+:2005C000EE60E001E610A840AB20EC8000D00424064308110A220CD0102012D0142816838E\r
+:2005E00018D01E0C20D0260128D02E0230F0360F3A02580B5C095F018038814684438539DD\r
+:20060000863C870688488A208B468D048F20903894619501961E975E982399429A449B04F1\r
+:200620009C189E20A010A146A428A542A610A820A977AA18AB08AD46B108B260B370B41E38\r
+:20064000B50FB601B920BA08BB0CBE40BF01D409D80BD90BDB0BDC99DD90DF0100080101A9\r
+:200660000308040405100680070209490A040C200E420F1010201110124015191601195473\r
+:200680001A041B1C1E42200C2108239429142A022B0230203108388039113B04590A5BA0DB\r
+:2006A000614078027E808B0190809119960497149802990A9AC39B029D109F01A020A14170\r
+:2006C000A280A302A404A508A601A71CC0FEC2FFC4FECA0FCC06CE0FD60FD808DE81E420A3\r
+:2006E000EC80A402B240EC80B002EC805810808086808810D480E240E6805381570A5904F8\r
+:200700005C026008648081048240840898809A80D4E0D6E0D8C0E220E6908C0292409A8036\r
+:200720009C02AF80B302B709EE1023088F0892409A80C8100C015102542080208C40C204ED\r
+:20074000D403E608020403100480074009020B010C188008850294809C109F10AD02B011C7\r
+:20076000B710C00FC20FEA04EE0683408E0493019A049B40E608AB01231027088801924077\r
+:2007800097109A80B310C860080156805A4092409A809C01B308C210D4C0010109010B0172\r
+:2007A0000D0111011B010000C00102000008FF218040000090404000001060807F22800829\r
+:2007C0001F01200000040000C0010100C0070418C001080000019F00003FFF8000000040C9\r
+:2007E000008200000000040163025000040EFCBD3DFFFFFF2200F008040000000000080092\r
+:20080000040B0B04909900010000C00040011011C00100114001400100000000000000001A\r
+:20082000000000000000000000FFFF00FF000000080030000800000000000000000000007B\r
+:2008400010000000FF000000000000010200F10E0E000C000000000000FCFC000400000071\r
+:200860000F00000000000001F00F0F000C000001000000000000000000000000000000004D\r
 :00000001FF\r
diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.c
deleted file mode 100644 (file)
index 56fddc5..0000000
+++ /dev/null
@@ -1,784 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_cm3.c\r
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
- * @version  V1.30\r
- * @date     30. October 2009\r
- *\r
- * @note\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
- * processor based microcontrollers.  This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#include <stdint.h>\r
-\r
-/* define compiler specific symbols */\r
-#if defined ( __CC_ARM   )\r
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */\r
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */\r
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
-\r
-#elif defined   (  __GNUC__  )\r
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */\r
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */\r
-\r
-#elif defined   (  __TASKING__  )\r
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */\r
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */\r
-\r
-#endif\r
-\r
-\r
-/* ###################  Compiler specific Intrinsics  ########################### */\r
-\r
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-/**\r
- * @brief  Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-__ASM uint32_t __get_PSP(void)\r
-{\r
-  mrs r0, psp\r
-  bx lr\r
-}\r
-\r
-/**\r
- * @brief  Set the Process Stack Pointer\r
- *\r
- * @param  topOfProcStack  Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-__ASM void __set_PSP(uint32_t topOfProcStack)\r
-{\r
-  msr psp, r0\r
-  bx lr\r
-}\r
-\r
-/**\r
- * @brief  Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-__ASM uint32_t __get_MSP(void)\r
-{\r
-  mrs r0, msp\r
-  bx lr\r
-}\r
-\r
-/**\r
- * @brief  Set the Main Stack Pointer\r
- *\r
- * @param  topOfMainStack  Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-__ASM void __set_MSP(uint32_t mainStackPointer)\r
-{\r
-  msr msp, r0\r
-  bx lr\r
-}\r
-\r
-/**\r
- * @brief  Reverse byte order in unsigned short value\r
- *\r
- * @param   value  value to reverse\r
- * @return         reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-__ASM uint32_t __REV16(uint16_t value)\r
-{\r
-  rev16 r0, r0\r
-  bx lr\r
-}\r
-\r
-/**\r
- * @brief  Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param   value  value to reverse\r
- * @return         reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-__ASM int32_t __REVSH(int16_t value)\r
-{\r
-  revsh r0, r0\r
-  bx lr\r
-}\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief  Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-__ASM void __CLREX(void)\r
-{\r
-  clrex\r
-}\r
-\r
-/**\r
- * @brief  Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-__ASM uint32_t  __get_BASEPRI(void)\r
-{\r
-  mrs r0, basepri\r
-  bx lr\r
-}\r
-\r
-/**\r
- * @brief  Set the Base Priority value\r
- *\r
- * @param  basePri  BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-__ASM void __set_BASEPRI(uint32_t basePri)\r
-{\r
-  msr basepri, r0\r
-  bx lr\r
-}\r
-\r
-/**\r
- * @brief  Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-__ASM uint32_t __get_PRIMASK(void)\r
-{\r
-  mrs r0, primask\r
-  bx lr\r
-}\r
-\r
-/**\r
- * @brief  Set the Priority Mask value\r
- *\r
- * @param  priMask  PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-__ASM void __set_PRIMASK(uint32_t priMask)\r
-{\r
-  msr primask, r0\r
-  bx lr\r
-}\r
-\r
-/**\r
- * @brief  Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-__ASM uint32_t  __get_FAULTMASK(void)\r
-{\r
-  mrs r0, faultmask\r
-  bx lr\r
-}\r
-\r
-/**\r
- * @brief  Set the Fault Mask value\r
- *\r
- * @param  faultMask  faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-__ASM void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
-  msr faultmask, r0\r
-  bx lr\r
-}\r
-\r
-/**\r
- * @brief  Return the Control Register value\r
- * \r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-__ASM uint32_t __get_CONTROL(void)\r
-{\r
-  mrs r0, control\r
-  bx lr\r
-}\r
-\r
-/**\r
- * @brief  Set the Control Register value\r
- *\r
- * @param  control  Control value\r
- *\r
- * Set the control register\r
- */\r
-__ASM void __set_CONTROL(uint32_t control)\r
-{\r
-  msr control, r0\r
-  bx lr\r
-}\r
-\r
-#endif /* __ARMCC_VERSION  */ \r
-\r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-#pragma diag_suppress=Pe940\r
-\r
-/**\r
- * @brief  Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-uint32_t __get_PSP(void)\r
-{\r
-  __ASM("mrs r0, psp");\r
-  __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief  Set the Process Stack Pointer\r
- *\r
- * @param  topOfProcStack  Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-void __set_PSP(uint32_t topOfProcStack)\r
-{\r
-  __ASM("msr psp, r0");\r
-  __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief  Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-uint32_t __get_MSP(void)\r
-{\r
-  __ASM("mrs r0, msp");\r
-  __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief  Set the Main Stack Pointer\r
- *\r
- * @param  topOfMainStack  Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-void __set_MSP(uint32_t topOfMainStack)\r
-{\r
-  __ASM("msr msp, r0");\r
-  __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief  Reverse byte order in unsigned short value\r
- *\r
- * @param  value  value to reverse\r
- * @return        reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-uint32_t __REV16(uint16_t value)\r
-{\r
-  __ASM("rev16 r0, r0");\r
-  __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief  Reverse bit order of value\r
- *\r
- * @param  value  value to reverse\r
- * @return        reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-uint32_t __RBIT(uint32_t value)\r
-{\r
-  __ASM("rbit r0, r0");\r
-  __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief  LDR Exclusive (8 bit)\r
- *\r
- * @param  *addr  address pointer\r
- * @return        value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit values)\r
- */\r
-uint8_t __LDREXB(uint8_t *addr)\r
-{\r
-  __ASM("ldrexb r0, [r0]");\r
-  __ASM("bx lr"); \r
-}\r
-\r
-/**\r
- * @brief  LDR Exclusive (16 bit)\r
- *\r
- * @param  *addr  address pointer\r
- * @return        value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-uint16_t __LDREXH(uint16_t *addr)\r
-{\r
-  __ASM("ldrexh r0, [r0]");\r
-  __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief  LDR Exclusive (32 bit)\r
- *\r
- * @param  *addr  address pointer\r
- * @return        value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-uint32_t __LDREXW(uint32_t *addr)\r
-{\r
-  __ASM("ldrex r0, [r0]");\r
-  __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief  STR Exclusive (8 bit)\r
- *\r
- * @param  value  value to store\r
- * @param  *addr  address pointer\r
- * @return        successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
-{\r
-  __ASM("strexb r0, r0, [r1]");\r
-  __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief  STR Exclusive (16 bit)\r
- *\r
- * @param  value  value to store\r
- * @param  *addr  address pointer\r
- * @return        successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
-{\r
-  __ASM("strexh r0, r0, [r1]");\r
-  __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief  STR Exclusive (32 bit)\r
- *\r
- * @param  value  value to store\r
- * @param  *addr  address pointer\r
- * @return        successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
-{\r
-  __ASM("strex r0, r0, [r1]");\r
-  __ASM("bx lr");\r
-}\r
-\r
-#pragma diag_default=Pe940\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/**\r
- * @brief  Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
-uint32_t __get_PSP(void)\r
-{\r
-  uint32_t result=0;\r
-\r
-  __ASM volatile ("MRS %0, psp\n\t" \r
-                  "MOV r0, %0 \n\t"\r
-                  "BX  lr     \n\t"  : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-/**\r
- * @brief  Set the Process Stack Pointer\r
- *\r
- * @param  topOfProcStack  Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
-void __set_PSP(uint32_t topOfProcStack)\r
-{\r
-  __ASM volatile ("MSR psp, %0\n\t"\r
-                  "BX  lr     \n\t" : : "r" (topOfProcStack) );\r
-}\r
-\r
-/**\r
- * @brief  Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
-uint32_t __get_MSP(void)\r
-{\r
-  uint32_t result=0;\r
-\r
-  __ASM volatile ("MRS %0, msp\n\t" \r
-                  "MOV r0, %0 \n\t"\r
-                  "BX  lr     \n\t"  : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-/**\r
- * @brief  Set the Main Stack Pointer\r
- *\r
- * @param  topOfMainStack  Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
-void __set_MSP(uint32_t topOfMainStack)\r
-{\r
-  __ASM volatile ("MSR msp, %0\n\t"\r
-                  "BX  lr     \n\t" : : "r" (topOfMainStack) );\r
-}\r
-\r
-/**\r
- * @brief  Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-uint32_t __get_BASEPRI(void)\r
-{\r
-  uint32_t result=0;\r
-  \r
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-/**\r
- * @brief  Set the Base Priority value\r
- *\r
- * @param  basePri  BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-void __set_BASEPRI(uint32_t value)\r
-{\r
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
-}\r
-\r
-/**\r
- * @brief  Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-uint32_t __get_PRIMASK(void)\r
-{\r
-  uint32_t result=0;\r
-\r
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-/**\r
- * @brief  Set the Priority Mask value\r
- *\r
- * @param  priMask  PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-void __set_PRIMASK(uint32_t priMask)\r
-{\r
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
-}\r
-\r
-/**\r
- * @brief  Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-uint32_t __get_FAULTMASK(void)\r
-{\r
-  uint32_t result=0;\r
-  \r
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-/**\r
- * @brief  Set the Fault Mask value\r
- *\r
- * @param  faultMask  faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
-}\r
-\r
-/**\r
- * @brief  Return the Control Register value\r
-* \r
-*  @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-uint32_t __get_CONTROL(void)\r
-{\r
-  uint32_t result=0;\r
-\r
-  __ASM volatile ("MRS %0, control" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-/**\r
- * @brief  Set the Control Register value\r
- *\r
- * @param  control  Control value\r
- *\r
- * Set the control register\r
- */\r
-void __set_CONTROL(uint32_t control)\r
-{\r
-  __ASM volatile ("MSR control, %0" : : "r" (control) );\r
-}\r
-\r
-\r
-/**\r
- * @brief  Reverse byte order in integer value\r
- *\r
- * @param  value  value to reverse\r
- * @return        reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-uint32_t __REV(uint32_t value)\r
-{\r
-  uint32_t result=0;\r
-  \r
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
-  return(result);\r
-}\r
-\r
-/**\r
- * @brief  Reverse byte order in unsigned short value\r
- *\r
- * @param  value  value to reverse\r
- * @return        reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-uint32_t __REV16(uint16_t value)\r
-{\r
-  uint32_t result=0;\r
-  \r
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
-  return(result);\r
-}\r
-\r
-/**\r
- * @brief  Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param  value  value to reverse\r
- * @return        reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-int32_t __REVSH(int16_t value)\r
-{\r
-  uint32_t result=0;\r
-  \r
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
-  return(result);\r
-}\r
-\r
-/**\r
- * @brief  Reverse bit order of value\r
- *\r
- * @param  value  value to reverse\r
- * @return        reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-uint32_t __RBIT(uint32_t value)\r
-{\r
-  uint32_t result=0;\r
-  \r
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
-   return(result);\r
-}\r
-\r
-/**\r
- * @brief  LDR Exclusive (8 bit)\r
- *\r
- * @param  *addr  address pointer\r
- * @return        value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit value\r
- */\r
-uint8_t __LDREXB(uint8_t *addr)\r
-{\r
-    uint8_t result=0;\r
-  \r
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
-   return(result);\r
-}\r
-\r
-/**\r
- * @brief  LDR Exclusive (16 bit)\r
- *\r
- * @param  *addr  address pointer\r
- * @return        value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-uint16_t __LDREXH(uint16_t *addr)\r
-{\r
-    uint16_t result=0;\r
-  \r
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
-   return(result);\r
-}\r
-\r
-/**\r
- * @brief  LDR Exclusive (32 bit)\r
- *\r
- * @param  *addr  address pointer\r
- * @return        value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-uint32_t __LDREXW(uint32_t *addr)\r
-{\r
-    uint32_t result=0;\r
-  \r
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
-   return(result);\r
-}\r
-\r
-/**\r
- * @brief  STR Exclusive (8 bit)\r
- *\r
- * @param  value  value to store\r
- * @param  *addr  address pointer\r
- * @return        successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
-{\r
-   uint32_t result=0;\r
-  \r
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
-   return(result);\r
-}\r
-\r
-/**\r
- * @brief  STR Exclusive (16 bit)\r
- *\r
- * @param  value  value to store\r
- * @param  *addr  address pointer\r
- * @return        successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
-{\r
-   uint32_t result=0;\r
-  \r
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
-   return(result);\r
-}\r
-\r
-/**\r
- * @brief  STR Exclusive (32 bit)\r
- *\r
- * @param  value  value to store\r
- * @param  *addr  address pointer\r
- * @return        successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
-{\r
-   uint32_t result=0;\r
-  \r
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
-   return(result);\r
-}\r
-\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
index e82bc00..b9e0788 100644 (file)
 #define CYDEV_ECC_BASE CYDEV_FLSECC_BASE\r
 #define CYDEV_FLS_SECTOR_SIZE 0x00010000u\r
 #define CYDEV_FLS_ROW_SIZE 0x00000100u\r
+#define CYDEV_ALLOCATE_EEPROM 0x00000001u\r
 #define CYDEV_ECC_SECTOR_SIZE 0x00002000u\r
 #define CYDEV_ECC_ROW_SIZE 0x00000020u\r
 #define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u\r
index d98ec4d..1fbd788 100644 (file)
 #define CYDEV_ECC_BASE CYDEV_FLSECC_BASE\r
 #define CYDEV_FLS_SECTOR_SIZE 0x00010000u\r
 #define CYDEV_FLS_ROW_SIZE 0x00000100u\r
+#define CYDEV_ALLOCATE_EEPROM 0x00000001u\r
 #define CYDEV_ECC_SECTOR_SIZE 0x00002000u\r
 #define CYDEV_ECC_ROW_SIZE 0x00000020u\r
 #define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u\r
index 3175b08..88db2ec 100644 (file)
 .set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE\r
 .set CYDEV_FLS_SECTOR_SIZE, 0x00010000\r
 .set CYDEV_FLS_ROW_SIZE, 0x00000100\r
+.set CYDEV_ALLOCATE_EEPROM, 0x00000001\r
 .set CYDEV_ECC_SECTOR_SIZE, 0x00002000\r
 .set CYDEV_ECC_ROW_SIZE, 0x00000020\r
 .set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400\r
index 54bd325..f7aaccf 100644 (file)
 .set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE\r
 .set CYDEV_FLS_SECTOR_SIZE, 0x00010000\r
 .set CYDEV_FLS_ROW_SIZE, 0x00000100\r
+.set CYDEV_ALLOCATE_EEPROM, 0x00000001\r
 .set CYDEV_ECC_SECTOR_SIZE, 0x00002000\r
 .set CYDEV_ECC_ROW_SIZE, 0x00000020\r
 .set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400\r
index 260c34e..84d3a34 100644 (file)
 #define CYDEV_ECC_BASE CYDEV_FLSECC_BASE\r
 #define CYDEV_FLS_SECTOR_SIZE 0x00010000\r
 #define CYDEV_FLS_ROW_SIZE 0x00000100\r
+#define CYDEV_ALLOCATE_EEPROM 0x00000001\r
 #define CYDEV_ECC_SECTOR_SIZE 0x00002000\r
 #define CYDEV_ECC_ROW_SIZE 0x00000020\r
 #define CYDEV_EEPROM_SECTOR_SIZE 0x00000400\r
index d5a03cf..ed08149 100644 (file)
 #define CYDEV_ECC_BASE CYDEV_FLSECC_BASE\r
 #define CYDEV_FLS_SECTOR_SIZE 0x00010000\r
 #define CYDEV_FLS_ROW_SIZE 0x00000100\r
+#define CYDEV_ALLOCATE_EEPROM 0x00000001\r
 #define CYDEV_ECC_SECTOR_SIZE 0x00002000\r
 #define CYDEV_ECC_ROW_SIZE 0x00000020\r
 #define CYDEV_EEPROM_SECTOR_SIZE 0x00000400\r
index 437e604..27c28f5 100644 (file)
@@ -15957,6 +15957,9 @@ CYDEV_FLS_SECTOR_SIZE EQU 0x00010000
     ENDIF\r
     IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE\r
 CYDEV_FLS_ROW_SIZE EQU 0x00000100\r
+    ENDIF\r
+    IF :LNOT::DEF:CYDEV_ALLOCATE_EEPROM\r
+CYDEV_ALLOCATE_EEPROM EQU 0x00000001\r
     ENDIF\r
     IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE\r
 CYDEV_ECC_SECTOR_SIZE EQU 0x00002000\r
index c632e72..ac134b9 100644 (file)
@@ -15957,6 +15957,9 @@ CYDEV_FLS_SECTOR_SIZE EQU 0x00010000
     ENDIF\r
     IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE\r
 CYDEV_FLS_ROW_SIZE EQU 0x00000100\r
+    ENDIF\r
+    IF :LNOT::DEF:CYDEV_ALLOCATE_EEPROM\r
+CYDEV_ALLOCATE_EEPROM EQU 0x00000001\r
     ENDIF\r
     IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE\r
 CYDEV_ECC_SECTOR_SIZE EQU 0x00002000\r
index 17c6d84..2bdffa5 100644 (file)
@@ -6,10 +6,10 @@
 /* SCSI_ATN_ISR */\r
 #define SCSI_ATN_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
 #define SCSI_ATN_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_ATN_ISR__INTC_MASK 0x01u\r
-#define SCSI_ATN_ISR__INTC_NUMBER 0u\r
+#define SCSI_ATN_ISR__INTC_MASK 0x800u\r
+#define SCSI_ATN_ISR__INTC_NUMBER 11u\r
 #define SCSI_ATN_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_ATN_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define SCSI_ATN_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_11\r
 #define SCSI_ATN_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
 #define SCSI_ATN_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
 \r
 /* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB02_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB02_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_RxStsReg__4__POS 4\r
 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
 #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
 #define SDCard_BSPIM_RxStsReg__6__POS 6\r
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB03_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB03_ST\r
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
 #define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
 #define SDCard_BSPIM_TxStsReg__1__POS 1\r
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
 #define SDCard_BSPIM_TxStsReg__4__POS 4\r
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1\r
+\r
+/* SCSI_CTL_IO */\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
 \r
 /* SCSI_In_DBx */\r
 #define SCSI_In_DBx__0__MASK 0x01u\r
 #define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
 #define SD_Init_Clk__PM_STBY_MSK 0x02u\r
 \r
+/* scsiTarget */\r
+#define scsiTarget_StatusReg__0__MASK 0x01u\r
+#define scsiTarget_StatusReg__0__POS 0\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
+#define scsiTarget_StatusReg__1__MASK 0x02u\r
+#define scsiTarget_StatusReg__1__POS 1\r
+#define scsiTarget_StatusReg__2__MASK 0x04u\r
+#define scsiTarget_StatusReg__2__POS 2\r
+#define scsiTarget_StatusReg__3__MASK 0x08u\r
+#define scsiTarget_StatusReg__3__POS 3\r
+#define scsiTarget_StatusReg__MASK 0x0Fu\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB04_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB04_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB04_MSK\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB04_05_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB04_05_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB04_05_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB04_05_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB04_05_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB04_05_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB04_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB04_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB04_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB04_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB04_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB04_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB04_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB04_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB04_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+\r
 /* SD_Clk_Ctl */\r
 #define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
 #define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-\r
-/* PARITY_EN */\r
-#define PARITY_EN__0__MASK 0x10u\r
-#define PARITY_EN__0__PC CYREG_PRT5_PC4\r
-#define PARITY_EN__0__PORT 5u\r
-#define PARITY_EN__0__SHIFT 4\r
-#define PARITY_EN__AG CYREG_PRT5_AG\r
-#define PARITY_EN__AMUX CYREG_PRT5_AMUX\r
-#define PARITY_EN__BIE CYREG_PRT5_BIE\r
-#define PARITY_EN__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define PARITY_EN__BYP CYREG_PRT5_BYP\r
-#define PARITY_EN__CTL CYREG_PRT5_CTL\r
-#define PARITY_EN__DM0 CYREG_PRT5_DM0\r
-#define PARITY_EN__DM1 CYREG_PRT5_DM1\r
-#define PARITY_EN__DM2 CYREG_PRT5_DM2\r
-#define PARITY_EN__DR CYREG_PRT5_DR\r
-#define PARITY_EN__INP_DIS CYREG_PRT5_INP_DIS\r
-#define PARITY_EN__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define PARITY_EN__LCD_EN CYREG_PRT5_LCD_EN\r
-#define PARITY_EN__MASK 0x10u\r
-#define PARITY_EN__PORT 5u\r
-#define PARITY_EN__PRT CYREG_PRT5_PRT\r
-#define PARITY_EN__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define PARITY_EN__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define PARITY_EN__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define PARITY_EN__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define PARITY_EN__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define PARITY_EN__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define PARITY_EN__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define PARITY_EN__PS CYREG_PRT5_PS\r
-#define PARITY_EN__SHIFT 4\r
-#define PARITY_EN__SLW CYREG_PRT5_SLW\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__1__POS 1\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x03u\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
 \r
 /* SCSI_ATN */\r
 #define SCSI_ATN__0__MASK 0x20u\r
 #define SCSI_ATN__DM2 CYREG_PRT12_DM2\r
 #define SCSI_ATN__DR CYREG_PRT12_DR\r
 #define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_ATN__INTSTAT CYREG_PICU12_INTSTAT\r
 #define SCSI_ATN__INT__MASK 0x20u\r
 #define SCSI_ATN__INT__PC CYREG_PRT12_PC5\r
 #define SCSI_ATN__INT__PORT 12u\r
 #define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
 #define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
 #define SCSI_ATN__SLW CYREG_PRT12_SLW\r
+#define SCSI_ATN__SNAP CYREG_PICU12_SNAP\r
 \r
 /* SCSI_Out */\r
 #define SCSI_Out__0__AG CYREG_PRT4_AG\r
 #define SCSI_Out__CD__PS CYREG_PRT6_PS\r
 #define SCSI_Out__CD__SHIFT 1\r
 #define SCSI_Out__CD__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out__DBP__AG CYREG_PRT4_AG\r
-#define SCSI_Out__DBP__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__DBP__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__DBP__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__DBP__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__DBP__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__DBP__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__DBP__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__DBP__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__DBP__DR CYREG_PRT4_DR\r
-#define SCSI_Out__DBP__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__DBP__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__DBP__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__DBP__MASK 0x04u\r
-#define SCSI_Out__DBP__PC CYREG_PRT4_PC2\r
-#define SCSI_Out__DBP__PORT 4u\r
-#define SCSI_Out__DBP__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__DBP__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__DBP__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__DBP__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__DBP__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__DBP__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__DBP__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__DBP__PS CYREG_PRT4_PS\r
-#define SCSI_Out__DBP__SHIFT 2\r
-#define SCSI_Out__DBP__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__IO__AG CYREG_PRT6_AG\r
-#define SCSI_Out__IO__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out__IO__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out__IO__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out__IO__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out__IO__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out__IO__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out__IO__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out__IO__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out__IO__DR CYREG_PRT6_DR\r
-#define SCSI_Out__IO__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out__IO__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out__IO__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out__IO__MASK 0x08u\r
-#define SCSI_Out__IO__PC CYREG_PRT6_PC3\r
-#define SCSI_Out__IO__PORT 6u\r
-#define SCSI_Out__IO__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out__IO__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out__IO__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out__IO__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out__IO__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out__IO__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out__IO__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out__IO__PS CYREG_PRT6_PS\r
-#define SCSI_Out__IO__SHIFT 3\r
-#define SCSI_Out__IO__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG\r
+#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR\r
+#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__DBP_raw__MASK 0x04u\r
+#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC2\r
+#define SCSI_Out__DBP_raw__PORT 4u\r
+#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS\r
+#define SCSI_Out__DBP_raw__SHIFT 2\r
+#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__IO_raw__AG CYREG_PRT6_AG\r
+#define SCSI_Out__IO_raw__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__IO_raw__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__IO_raw__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__IO_raw__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__IO_raw__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__IO_raw__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__IO_raw__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__IO_raw__DR CYREG_PRT6_DR\r
+#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__IO_raw__MASK 0x08u\r
+#define SCSI_Out__IO_raw__PC CYREG_PRT6_PC3\r
+#define SCSI_Out__IO_raw__PORT 6u\r
+#define SCSI_Out__IO_raw__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__IO_raw__PS CYREG_PRT6_PS\r
+#define SCSI_Out__IO_raw__SHIFT 3\r
+#define SCSI_Out__IO_raw__SLW CYREG_PRT6_SLW\r
 #define SCSI_Out__MSG__AG CYREG_PRT4_AG\r
 #define SCSI_Out__MSG__AMUX CYREG_PRT4_AMUX\r
 #define SCSI_Out__MSG__BIE CYREG_PRT4_BIE\r
 #define SCSI_RST__SLW CYREG_PRT6_SLW\r
 #define SCSI_RST__SNAP CYREG_PICU6_SNAP\r
 \r
-/* SCSI_ID */\r
-#define SCSI_ID__0__MASK 0x80u\r
-#define SCSI_ID__0__PC CYREG_PRT5_PC7\r
-#define SCSI_ID__0__PORT 5u\r
-#define SCSI_ID__0__SHIFT 7\r
-#define SCSI_ID__1__MASK 0x40u\r
-#define SCSI_ID__1__PC CYREG_PRT5_PC6\r
-#define SCSI_ID__1__PORT 5u\r
-#define SCSI_ID__1__SHIFT 6\r
-#define SCSI_ID__2__MASK 0x20u\r
-#define SCSI_ID__2__PC CYREG_PRT5_PC5\r
-#define SCSI_ID__2__PORT 5u\r
-#define SCSI_ID__2__SHIFT 5\r
-#define SCSI_ID__AG CYREG_PRT5_AG\r
-#define SCSI_ID__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_ID__BIE CYREG_PRT5_BIE\r
-#define SCSI_ID__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_ID__BYP CYREG_PRT5_BYP\r
-#define SCSI_ID__CTL CYREG_PRT5_CTL\r
-#define SCSI_ID__DM0 CYREG_PRT5_DM0\r
-#define SCSI_ID__DM1 CYREG_PRT5_DM1\r
-#define SCSI_ID__DM2 CYREG_PRT5_DM2\r
-#define SCSI_ID__DR CYREG_PRT5_DR\r
-#define SCSI_ID__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_ID__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_ID__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_ID__PORT 5u\r
-#define SCSI_ID__PRT CYREG_PRT5_PRT\r
-#define SCSI_ID__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_ID__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_ID__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_ID__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_ID__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_ID__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_ID__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_ID__PS CYREG_PRT5_PS\r
-#define SCSI_ID__SLW CYREG_PRT5_SLW\r
-\r
 /* SCSI_In */\r
 #define SCSI_In__0__AG CYREG_PRT12_AG\r
 #define SCSI_In__0__BIE CYREG_PRT12_BIE\r
 #define CYDEV_ECC_ENABLE 0\r
 #define CYDEV_HEAP_SIZE 0x1000\r
 #define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x00000001u\r
+#define CYDEV_INTR_RISING 0x00000000u\r
 #define CYDEV_PROJ_TYPE 0\r
 #define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
 #define CYDEV_PROJ_TYPE_LOADABLE 2\r
index 32faaac..bbee0d7 100644 (file)
@@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode)
 }\r
 #endif\r
 \r
-#define CY_CFG_BASE_ADDR_COUNT 22u\r
+#define CY_CFG_BASE_ADDR_COUNT 32u\r
 CYPACKED typedef struct\r
 {\r
        uint8 offset;\r
@@ -129,34 +129,34 @@ CYPACKED typedef struct
 } CYPACKED_ATTR cy_cfg_addrvalue_t;\r
 \r
 #define cy_cfg_addr_table ((const uint32 CYFAR *)0x48000000u)\r
-#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000058u)\r
+#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000080u)\r
 \r
-/* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */\r
-#define BS_UDB_1_2_1_CONFIG_VAL ((const uint8 CYFAR *)0x48000318u)\r
+/* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */\r
+#define BS_UDB_1_2_0_CONFIG_VAL ((const uint8 CYFAR *)0x480007A8u)\r
 \r
 /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */\r
-#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000398u)\r
+#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000828u)\r
 \r
 /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */\r
-#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x480003A0u)\r
+#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x48000830u)\r
 \r
 /* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */\r
-#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x480003ACu)\r
+#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x4800083Cu)\r
 \r
 /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */\r
-#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x480003B4u)\r
+#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x48000844u)\r
 \r
 /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */\r
-#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x480003BCu)\r
+#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x4800084Cu)\r
 \r
 /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */\r
-#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x480003C8u)\r
+#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x48000858u)\r
 \r
-/* IOPINS0_5 Address: CYREG_PRT5_DR Size (bytes): 10 */\r
-#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x480003D0u)\r
+/* IOPINS0_5 Address: CYREG_PRT5_DM0 Size (bytes): 8 */\r
+#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x48000860u)\r
 \r
 /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */\r
-#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x480003DCu)\r
+#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x48000868u)\r
 \r
 \r
 /*******************************************************************************\r
@@ -369,8 +369,8 @@ void cyfitter_cfg(void)
                        /* address, size */\r
                        {(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
                        {(void CYFAR *)(CYREG_PRT15_DR), 16u},\r
-                       {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},\r
-                       {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},\r
+                       {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1664u},\r
+                       {(void CYFAR *)(CYDEV_UCFG_B0_P3_ROUTE_BASE), 2304u},\r
                        {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
                        {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
                        {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
@@ -379,7 +379,7 @@ void cyfitter_cfg(void)
 \r
                static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
                        /* dest, src, size */\r
-                       {(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u},\r
+                       {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), BS_UDB_1_2_0_CONFIG_VAL, 128u},\r
                };\r
 \r
                uint8 CYDATA i;\r
@@ -419,7 +419,7 @@ void cyfitter_cfg(void)
        CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DM0), (const void CYFAR *)(BS_IOPINS0_2_VAL), 8u);\r
        CYCONFIGCPY((void CYFAR *)(CYREG_PRT3_DR), (const void CYFAR *)(BS_IOPINS0_3_VAL), 10u);\r
        CYCONFIGCPY((void CYFAR *)(CYREG_PRT4_DM0), (const void CYFAR *)(BS_IOPINS0_4_VAL), 8u);\r
-       CYCONFIGCPY((void CYFAR *)(CYREG_PRT5_DR), (const void CYFAR *)(BS_IOPINS0_5_VAL), 10u);\r
+       CYCONFIGCPY((void CYFAR *)(CYREG_PRT5_DM0), (const void CYFAR *)(BS_IOPINS0_5_VAL), 8u);\r
        CYCONFIGCPY((void CYFAR *)(CYREG_PRT6_DM0), (const void CYFAR *)(BS_IOPINS0_6_VAL), 8u);\r
 \r
        /* Switch Boost to the precision bandgap reference from its internal reference */\r
index 34d8afa..e0aa8c4 100644 (file)
@@ -6,10 +6,10 @@
 /* SCSI_ATN_ISR */\r
 .set SCSI_ATN_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set SCSI_ATN_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_ATN_ISR__INTC_MASK, 0x01\r
-.set SCSI_ATN_ISR__INTC_NUMBER, 0\r
+.set SCSI_ATN_ISR__INTC_MASK, 0x800\r
+.set SCSI_ATN_ISR__INTC_NUMBER, 11\r
 .set SCSI_ATN_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_ATN_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set SCSI_ATN_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_11\r
 .set SCSI_ATN_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set SCSI_ATN_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB02_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB02_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB02_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB02_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
 .set SDCard_BSPIM_RxStsReg__4__POS, 4\r
 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
 .set SDCard_BSPIM_RxStsReg__6__POS, 6\r
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB03_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB03_ST\r
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
 .set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
 .set SDCard_BSPIM_TxStsReg__1__POS, 1\r
 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
 .set SDCard_BSPIM_TxStsReg__4__POS, 4\r
 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB07_08_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB07_08_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB07_08_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB07_08_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB07_08_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB07_08_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB07_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB07_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB07_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB07_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB07_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB07_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB07_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB07_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB07_F1\r
+\r
+/* SCSI_CTL_IO */\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
 \r
 /* SCSI_In_DBx */\r
 .set SCSI_In_DBx__0__MASK, 0x01\r
 .set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
 .set SD_Init_Clk__PM_STBY_MSK, 0x02\r
 \r
+/* scsiTarget */\r
+.set scsiTarget_StatusReg__0__MASK, 0x01\r
+.set scsiTarget_StatusReg__0__POS, 0\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
+.set scsiTarget_StatusReg__1__MASK, 0x02\r
+.set scsiTarget_StatusReg__1__POS, 1\r
+.set scsiTarget_StatusReg__2__MASK, 0x04\r
+.set scsiTarget_StatusReg__2__POS, 2\r
+.set scsiTarget_StatusReg__3__MASK, 0x08\r
+.set scsiTarget_StatusReg__3__POS, 3\r
+.set scsiTarget_StatusReg__MASK, 0x0F\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK\r
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB04_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB04_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB04_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB04_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB04_05_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB04_05_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB04_05_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB04_05_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB04_05_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB04_05_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB04_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB04_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB04_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB04_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB04_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB04_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB04_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB04_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB04_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+\r
 /* SD_Clk_Ctl */\r
 .set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-\r
-/* PARITY_EN */\r
-.set PARITY_EN__0__MASK, 0x10\r
-.set PARITY_EN__0__PC, CYREG_PRT5_PC4\r
-.set PARITY_EN__0__PORT, 5\r
-.set PARITY_EN__0__SHIFT, 4\r
-.set PARITY_EN__AG, CYREG_PRT5_AG\r
-.set PARITY_EN__AMUX, CYREG_PRT5_AMUX\r
-.set PARITY_EN__BIE, CYREG_PRT5_BIE\r
-.set PARITY_EN__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set PARITY_EN__BYP, CYREG_PRT5_BYP\r
-.set PARITY_EN__CTL, CYREG_PRT5_CTL\r
-.set PARITY_EN__DM0, CYREG_PRT5_DM0\r
-.set PARITY_EN__DM1, CYREG_PRT5_DM1\r
-.set PARITY_EN__DM2, CYREG_PRT5_DM2\r
-.set PARITY_EN__DR, CYREG_PRT5_DR\r
-.set PARITY_EN__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set PARITY_EN__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set PARITY_EN__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set PARITY_EN__MASK, 0x10\r
-.set PARITY_EN__PORT, 5\r
-.set PARITY_EN__PRT, CYREG_PRT5_PRT\r
-.set PARITY_EN__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set PARITY_EN__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set PARITY_EN__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set PARITY_EN__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set PARITY_EN__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set PARITY_EN__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set PARITY_EN__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set PARITY_EN__PS, CYREG_PRT5_PS\r
-.set PARITY_EN__SHIFT, 4\r
-.set PARITY_EN__SLW, CYREG_PRT5_SLW\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__1__MASK, 0x02\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__1__POS, 1\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x03\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
 \r
 /* SCSI_ATN */\r
 .set SCSI_ATN__0__MASK, 0x20\r
 .set SCSI_ATN__DM2, CYREG_PRT12_DM2\r
 .set SCSI_ATN__DR, CYREG_PRT12_DR\r
 .set SCSI_ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_ATN__INTSTAT, CYREG_PICU12_INTSTAT\r
 .set SCSI_ATN__INT__MASK, 0x20\r
 .set SCSI_ATN__INT__PC, CYREG_PRT12_PC5\r
 .set SCSI_ATN__INT__PORT, 12\r
 .set SCSI_ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
 .set SCSI_ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
 .set SCSI_ATN__SLW, CYREG_PRT12_SLW\r
+.set SCSI_ATN__SNAP, CYREG_PICU12_SNAP\r
 \r
 /* SCSI_Out */\r
 .set SCSI_Out__0__AG, CYREG_PRT4_AG\r
 .set SCSI_Out__CD__PS, CYREG_PRT6_PS\r
 .set SCSI_Out__CD__SHIFT, 1\r
 .set SCSI_Out__CD__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out__DBP__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__DBP__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__DBP__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__DBP__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__DBP__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__DBP__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__DBP__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__DBP__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__DBP__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__DBP__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__DBP__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__DBP__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__DBP__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__DBP__MASK, 0x04\r
-.set SCSI_Out__DBP__PC, CYREG_PRT4_PC2\r
-.set SCSI_Out__DBP__PORT, 4\r
-.set SCSI_Out__DBP__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__DBP__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__DBP__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__DBP__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__DBP__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__DBP__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__DBP__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__DBP__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__DBP__SHIFT, 2\r
-.set SCSI_Out__DBP__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__IO__AG, CYREG_PRT6_AG\r
-.set SCSI_Out__IO__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out__IO__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out__IO__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out__IO__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out__IO__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out__IO__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out__IO__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out__IO__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out__IO__DR, CYREG_PRT6_DR\r
-.set SCSI_Out__IO__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out__IO__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out__IO__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out__IO__MASK, 0x08\r
-.set SCSI_Out__IO__PC, CYREG_PRT6_PC3\r
-.set SCSI_Out__IO__PORT, 6\r
-.set SCSI_Out__IO__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out__IO__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out__IO__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out__IO__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out__IO__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out__IO__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out__IO__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out__IO__PS, CYREG_PRT6_PS\r
-.set SCSI_Out__IO__SHIFT, 3\r
-.set SCSI_Out__IO__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__DBP_raw__MASK, 0x04\r
+.set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC2\r
+.set SCSI_Out__DBP_raw__PORT, 4\r
+.set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__DBP_raw__SHIFT, 2\r
+.set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__IO_raw__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__IO_raw__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__IO_raw__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__IO_raw__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__IO_raw__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__IO_raw__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__IO_raw__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__IO_raw__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__IO_raw__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__IO_raw__MASK, 0x08\r
+.set SCSI_Out__IO_raw__PC, CYREG_PRT6_PC3\r
+.set SCSI_Out__IO_raw__PORT, 6\r
+.set SCSI_Out__IO_raw__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__IO_raw__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__IO_raw__SHIFT, 3\r
+.set SCSI_Out__IO_raw__SLW, CYREG_PRT6_SLW\r
 .set SCSI_Out__MSG__AG, CYREG_PRT4_AG\r
 .set SCSI_Out__MSG__AMUX, CYREG_PRT4_AMUX\r
 .set SCSI_Out__MSG__BIE, CYREG_PRT4_BIE\r
 .set SCSI_RST__SLW, CYREG_PRT6_SLW\r
 .set SCSI_RST__SNAP, CYREG_PICU6_SNAP\r
 \r
-/* SCSI_ID */\r
-.set SCSI_ID__0__MASK, 0x80\r
-.set SCSI_ID__0__PC, CYREG_PRT5_PC7\r
-.set SCSI_ID__0__PORT, 5\r
-.set SCSI_ID__0__SHIFT, 7\r
-.set SCSI_ID__1__MASK, 0x40\r
-.set SCSI_ID__1__PC, CYREG_PRT5_PC6\r
-.set SCSI_ID__1__PORT, 5\r
-.set SCSI_ID__1__SHIFT, 6\r
-.set SCSI_ID__2__MASK, 0x20\r
-.set SCSI_ID__2__PC, CYREG_PRT5_PC5\r
-.set SCSI_ID__2__PORT, 5\r
-.set SCSI_ID__2__SHIFT, 5\r
-.set SCSI_ID__AG, CYREG_PRT5_AG\r
-.set SCSI_ID__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_ID__BIE, CYREG_PRT5_BIE\r
-.set SCSI_ID__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_ID__BYP, CYREG_PRT5_BYP\r
-.set SCSI_ID__CTL, CYREG_PRT5_CTL\r
-.set SCSI_ID__DM0, CYREG_PRT5_DM0\r
-.set SCSI_ID__DM1, CYREG_PRT5_DM1\r
-.set SCSI_ID__DM2, CYREG_PRT5_DM2\r
-.set SCSI_ID__DR, CYREG_PRT5_DR\r
-.set SCSI_ID__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_ID__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_ID__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_ID__PORT, 5\r
-.set SCSI_ID__PRT, CYREG_PRT5_PRT\r
-.set SCSI_ID__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_ID__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_ID__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_ID__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_ID__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_ID__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_ID__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_ID__PS, CYREG_PRT5_PS\r
-.set SCSI_ID__SLW, CYREG_PRT5_SLW\r
-\r
 /* SCSI_In */\r
 .set SCSI_In__0__AG, CYREG_PRT12_AG\r
 .set SCSI_In__0__BIE, CYREG_PRT12_BIE\r
 .set CYDEV_ECC_ENABLE, 0\r
 .set CYDEV_HEAP_SIZE, 0x1000\r
 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
-.set CYDEV_INTR_RISING, 0x00000001\r
+.set CYDEV_INTR_RISING, 0x00000000\r
 .set CYDEV_PROJ_TYPE, 0\r
 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1\r
 .set CYDEV_PROJ_TYPE_LOADABLE, 2\r
index cac69a6..5523e00 100644 (file)
@@ -6,10 +6,10 @@
 /* SCSI_ATN_ISR */\r
 SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
 SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_ATN_ISR__INTC_MASK EQU 0x01\r
-SCSI_ATN_ISR__INTC_NUMBER EQU 0\r
+SCSI_ATN_ISR__INTC_MASK EQU 0x800\r
+SCSI_ATN_ISR__INTC_NUMBER EQU 11\r
 SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11\r
 SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
 SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
 \r
@@ -116,34 +116,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
 \r
 /* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
@@ -151,13 +151,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
 SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
 SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
 SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
@@ -167,28 +167,48 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1\r
+\r
+/* SCSI_CTL_IO */\r
+SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
 \r
 /* SCSI_In_DBx */\r
 SCSI_In_DBx__0__MASK EQU 0x01\r
@@ -304,59 +324,94 @@ SD_Init_Clk__PM_ACT_MSK EQU 0x02
 SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
 SD_Init_Clk__PM_STBY_MSK EQU 0x02\r
 \r
+/* scsiTarget */\r
+scsiTarget_StatusReg__0__MASK EQU 0x01\r
+scsiTarget_StatusReg__0__POS EQU 0\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+scsiTarget_StatusReg__1__MASK EQU 0x02\r
+scsiTarget_StatusReg__1__POS EQU 1\r
+scsiTarget_StatusReg__2__MASK EQU 0x04\r
+scsiTarget_StatusReg__2__POS EQU 2\r
+scsiTarget_StatusReg__3__MASK EQU 0x08\r
+scsiTarget_StatusReg__3__POS EQU 3\r
+scsiTarget_StatusReg__MASK EQU 0x0F\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+\r
 /* SD_Clk_Ctl */\r
 SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-\r
-/* PARITY_EN */\r
-PARITY_EN__0__MASK EQU 0x10\r
-PARITY_EN__0__PC EQU CYREG_PRT5_PC4\r
-PARITY_EN__0__PORT EQU 5\r
-PARITY_EN__0__SHIFT EQU 4\r
-PARITY_EN__AG EQU CYREG_PRT5_AG\r
-PARITY_EN__AMUX EQU CYREG_PRT5_AMUX\r
-PARITY_EN__BIE EQU CYREG_PRT5_BIE\r
-PARITY_EN__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-PARITY_EN__BYP EQU CYREG_PRT5_BYP\r
-PARITY_EN__CTL EQU CYREG_PRT5_CTL\r
-PARITY_EN__DM0 EQU CYREG_PRT5_DM0\r
-PARITY_EN__DM1 EQU CYREG_PRT5_DM1\r
-PARITY_EN__DM2 EQU CYREG_PRT5_DM2\r
-PARITY_EN__DR EQU CYREG_PRT5_DR\r
-PARITY_EN__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-PARITY_EN__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-PARITY_EN__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-PARITY_EN__MASK EQU 0x10\r
-PARITY_EN__PORT EQU 5\r
-PARITY_EN__PRT EQU CYREG_PRT5_PRT\r
-PARITY_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-PARITY_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-PARITY_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-PARITY_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-PARITY_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-PARITY_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-PARITY_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-PARITY_EN__PS EQU CYREG_PRT5_PS\r
-PARITY_EN__SHIFT EQU 4\r
-PARITY_EN__SLW EQU CYREG_PRT5_SLW\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SD_Clk_Ctl_Sync_ctrl_reg__1__POS EQU 1\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x03\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
 \r
 /* SCSI_ATN */\r
 SCSI_ATN__0__MASK EQU 0x20\r
@@ -372,6 +427,7 @@ SCSI_ATN__DM1 EQU CYREG_PRT12_DM1
 SCSI_ATN__DM2 EQU CYREG_PRT12_DM2\r
 SCSI_ATN__DR EQU CYREG_PRT12_DR\r
 SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_ATN__INTSTAT EQU CYREG_PICU12_INTSTAT\r
 SCSI_ATN__INT__MASK EQU 0x20\r
 SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5\r
 SCSI_ATN__INT__PORT EQU 12\r
@@ -392,6 +448,7 @@ SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
 SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
 SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
 SCSI_ATN__SLW EQU CYREG_PRT12_SLW\r
+SCSI_ATN__SNAP EQU CYREG_PICU12_SNAP\r
 \r
 /* SCSI_Out */\r
 SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
@@ -772,60 +829,60 @@ SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
 SCSI_Out__CD__PS EQU CYREG_PRT6_PS\r
 SCSI_Out__CD__SHIFT EQU 1\r
 SCSI_Out__CD__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out__DBP__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__DBP__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__DBP__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__DBP__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__DBP__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__DBP__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__DBP__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__DBP__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__DBP__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__DBP__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__DBP__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__DBP__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__DBP__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__DBP__MASK EQU 0x04\r
-SCSI_Out__DBP__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__DBP__PORT EQU 4\r
-SCSI_Out__DBP__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__DBP__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__DBP__SHIFT EQU 2\r
-SCSI_Out__DBP__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__IO__AG EQU CYREG_PRT6_AG\r
-SCSI_Out__IO__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out__IO__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out__IO__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out__IO__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out__IO__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out__IO__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out__IO__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out__IO__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out__IO__DR EQU CYREG_PRT6_DR\r
-SCSI_Out__IO__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out__IO__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out__IO__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out__IO__MASK EQU 0x08\r
-SCSI_Out__IO__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out__IO__PORT EQU 6\r
-SCSI_Out__IO__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out__IO__PS EQU CYREG_PRT6_PS\r
-SCSI_Out__IO__SHIFT EQU 3\r
-SCSI_Out__IO__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__DBP_raw__MASK EQU 0x04\r
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__DBP_raw__PORT EQU 4\r
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__DBP_raw__SHIFT EQU 2\r
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__IO_raw__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__IO_raw__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__IO_raw__MASK EQU 0x08\r
+SCSI_Out__IO_raw__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out__IO_raw__PORT EQU 6\r
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__IO_raw__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__IO_raw__SHIFT EQU 3\r
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT6_SLW\r
 SCSI_Out__MSG__AG EQU CYREG_PRT4_AG\r
 SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX\r
 SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE\r
@@ -973,44 +1030,6 @@ SCSI_RST__SHIFT EQU 6
 SCSI_RST__SLW EQU CYREG_PRT6_SLW\r
 SCSI_RST__SNAP EQU CYREG_PICU6_SNAP\r
 \r
-/* SCSI_ID */\r
-SCSI_ID__0__MASK EQU 0x80\r
-SCSI_ID__0__PC EQU CYREG_PRT5_PC7\r
-SCSI_ID__0__PORT EQU 5\r
-SCSI_ID__0__SHIFT EQU 7\r
-SCSI_ID__1__MASK EQU 0x40\r
-SCSI_ID__1__PC EQU CYREG_PRT5_PC6\r
-SCSI_ID__1__PORT EQU 5\r
-SCSI_ID__1__SHIFT EQU 6\r
-SCSI_ID__2__MASK EQU 0x20\r
-SCSI_ID__2__PC EQU CYREG_PRT5_PC5\r
-SCSI_ID__2__PORT EQU 5\r
-SCSI_ID__2__SHIFT EQU 5\r
-SCSI_ID__AG EQU CYREG_PRT5_AG\r
-SCSI_ID__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_ID__BIE EQU CYREG_PRT5_BIE\r
-SCSI_ID__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_ID__BYP EQU CYREG_PRT5_BYP\r
-SCSI_ID__CTL EQU CYREG_PRT5_CTL\r
-SCSI_ID__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_ID__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_ID__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_ID__DR EQU CYREG_PRT5_DR\r
-SCSI_ID__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_ID__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_ID__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_ID__PORT EQU 5\r
-SCSI_ID__PRT EQU CYREG_PRT5_PRT\r
-SCSI_ID__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_ID__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_ID__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_ID__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_ID__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_ID__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_ID__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_ID__PS EQU CYREG_PRT5_PS\r
-SCSI_ID__SLW EQU CYREG_PRT5_SLW\r
-\r
 /* SCSI_In */\r
 SCSI_In__0__AG EQU CYREG_PRT12_AG\r
 SCSI_In__0__BIE EQU CYREG_PRT12_BIE\r
@@ -1805,7 +1824,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0\r
 CYDEV_HEAP_SIZE EQU 0x1000\r
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000001\r
+CYDEV_INTR_RISING EQU 0x00000000\r
 CYDEV_PROJ_TYPE EQU 0\r
 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
 CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
index d108744..0023a23 100644 (file)
@@ -6,10 +6,10 @@ INCLUDED_CYFITTERRV_INC EQU 1
 ; SCSI_ATN_ISR\r
 SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
 SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_ATN_ISR__INTC_MASK EQU 0x01\r
-SCSI_ATN_ISR__INTC_NUMBER EQU 0\r
+SCSI_ATN_ISR__INTC_MASK EQU 0x800\r
+SCSI_ATN_ISR__INTC_NUMBER EQU 11\r
 SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11\r
 SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
 SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
 \r
@@ -116,34 +116,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
 \r
 ; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
@@ -151,13 +151,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
 SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
 SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
 SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
@@ -167,28 +167,48 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
 SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1\r
+\r
+; SCSI_CTL_IO\r
+SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
 \r
 ; SCSI_In_DBx\r
 SCSI_In_DBx__0__MASK EQU 0x01\r
@@ -304,59 +324,94 @@ SD_Init_Clk__PM_ACT_MSK EQU 0x02
 SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
 SD_Init_Clk__PM_STBY_MSK EQU 0x02\r
 \r
+; scsiTarget\r
+scsiTarget_StatusReg__0__MASK EQU 0x01\r
+scsiTarget_StatusReg__0__POS EQU 0\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+scsiTarget_StatusReg__1__MASK EQU 0x02\r
+scsiTarget_StatusReg__1__POS EQU 1\r
+scsiTarget_StatusReg__2__MASK EQU 0x04\r
+scsiTarget_StatusReg__2__POS EQU 2\r
+scsiTarget_StatusReg__3__MASK EQU 0x08\r
+scsiTarget_StatusReg__3__POS EQU 3\r
+scsiTarget_StatusReg__MASK EQU 0x0F\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+\r
 ; SD_Clk_Ctl\r
 SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-\r
-; PARITY_EN\r
-PARITY_EN__0__MASK EQU 0x10\r
-PARITY_EN__0__PC EQU CYREG_PRT5_PC4\r
-PARITY_EN__0__PORT EQU 5\r
-PARITY_EN__0__SHIFT EQU 4\r
-PARITY_EN__AG EQU CYREG_PRT5_AG\r
-PARITY_EN__AMUX EQU CYREG_PRT5_AMUX\r
-PARITY_EN__BIE EQU CYREG_PRT5_BIE\r
-PARITY_EN__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-PARITY_EN__BYP EQU CYREG_PRT5_BYP\r
-PARITY_EN__CTL EQU CYREG_PRT5_CTL\r
-PARITY_EN__DM0 EQU CYREG_PRT5_DM0\r
-PARITY_EN__DM1 EQU CYREG_PRT5_DM1\r
-PARITY_EN__DM2 EQU CYREG_PRT5_DM2\r
-PARITY_EN__DR EQU CYREG_PRT5_DR\r
-PARITY_EN__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-PARITY_EN__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-PARITY_EN__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-PARITY_EN__MASK EQU 0x10\r
-PARITY_EN__PORT EQU 5\r
-PARITY_EN__PRT EQU CYREG_PRT5_PRT\r
-PARITY_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-PARITY_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-PARITY_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-PARITY_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-PARITY_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-PARITY_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-PARITY_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-PARITY_EN__PS EQU CYREG_PRT5_PS\r
-PARITY_EN__SHIFT EQU 4\r
-PARITY_EN__SLW EQU CYREG_PRT5_SLW\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SD_Clk_Ctl_Sync_ctrl_reg__1__POS EQU 1\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x03\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
 \r
 ; SCSI_ATN\r
 SCSI_ATN__0__MASK EQU 0x20\r
@@ -372,6 +427,7 @@ SCSI_ATN__DM1 EQU CYREG_PRT12_DM1
 SCSI_ATN__DM2 EQU CYREG_PRT12_DM2\r
 SCSI_ATN__DR EQU CYREG_PRT12_DR\r
 SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_ATN__INTSTAT EQU CYREG_PICU12_INTSTAT\r
 SCSI_ATN__INT__MASK EQU 0x20\r
 SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5\r
 SCSI_ATN__INT__PORT EQU 12\r
@@ -392,6 +448,7 @@ SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
 SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
 SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
 SCSI_ATN__SLW EQU CYREG_PRT12_SLW\r
+SCSI_ATN__SNAP EQU CYREG_PICU12_SNAP\r
 \r
 ; SCSI_Out\r
 SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
@@ -772,60 +829,60 @@ SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
 SCSI_Out__CD__PS EQU CYREG_PRT6_PS\r
 SCSI_Out__CD__SHIFT EQU 1\r
 SCSI_Out__CD__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out__DBP__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__DBP__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__DBP__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__DBP__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__DBP__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__DBP__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__DBP__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__DBP__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__DBP__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__DBP__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__DBP__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__DBP__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__DBP__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__DBP__MASK EQU 0x04\r
-SCSI_Out__DBP__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__DBP__PORT EQU 4\r
-SCSI_Out__DBP__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__DBP__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__DBP__SHIFT EQU 2\r
-SCSI_Out__DBP__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__IO__AG EQU CYREG_PRT6_AG\r
-SCSI_Out__IO__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out__IO__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out__IO__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out__IO__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out__IO__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out__IO__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out__IO__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out__IO__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out__IO__DR EQU CYREG_PRT6_DR\r
-SCSI_Out__IO__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out__IO__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out__IO__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out__IO__MASK EQU 0x08\r
-SCSI_Out__IO__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out__IO__PORT EQU 6\r
-SCSI_Out__IO__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out__IO__PS EQU CYREG_PRT6_PS\r
-SCSI_Out__IO__SHIFT EQU 3\r
-SCSI_Out__IO__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__DBP_raw__MASK EQU 0x04\r
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__DBP_raw__PORT EQU 4\r
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__DBP_raw__SHIFT EQU 2\r
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__IO_raw__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__IO_raw__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__IO_raw__MASK EQU 0x08\r
+SCSI_Out__IO_raw__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out__IO_raw__PORT EQU 6\r
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__IO_raw__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__IO_raw__SHIFT EQU 3\r
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT6_SLW\r
 SCSI_Out__MSG__AG EQU CYREG_PRT4_AG\r
 SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX\r
 SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE\r
@@ -973,44 +1030,6 @@ SCSI_RST__SHIFT EQU 6
 SCSI_RST__SLW EQU CYREG_PRT6_SLW\r
 SCSI_RST__SNAP EQU CYREG_PICU6_SNAP\r
 \r
-; SCSI_ID\r
-SCSI_ID__0__MASK EQU 0x80\r
-SCSI_ID__0__PC EQU CYREG_PRT5_PC7\r
-SCSI_ID__0__PORT EQU 5\r
-SCSI_ID__0__SHIFT EQU 7\r
-SCSI_ID__1__MASK EQU 0x40\r
-SCSI_ID__1__PC EQU CYREG_PRT5_PC6\r
-SCSI_ID__1__PORT EQU 5\r
-SCSI_ID__1__SHIFT EQU 6\r
-SCSI_ID__2__MASK EQU 0x20\r
-SCSI_ID__2__PC EQU CYREG_PRT5_PC5\r
-SCSI_ID__2__PORT EQU 5\r
-SCSI_ID__2__SHIFT EQU 5\r
-SCSI_ID__AG EQU CYREG_PRT5_AG\r
-SCSI_ID__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_ID__BIE EQU CYREG_PRT5_BIE\r
-SCSI_ID__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_ID__BYP EQU CYREG_PRT5_BYP\r
-SCSI_ID__CTL EQU CYREG_PRT5_CTL\r
-SCSI_ID__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_ID__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_ID__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_ID__DR EQU CYREG_PRT5_DR\r
-SCSI_ID__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_ID__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_ID__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_ID__PORT EQU 5\r
-SCSI_ID__PRT EQU CYREG_PRT5_PRT\r
-SCSI_ID__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_ID__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_ID__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_ID__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_ID__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_ID__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_ID__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_ID__PS EQU CYREG_PRT5_PS\r
-SCSI_ID__SLW EQU CYREG_PRT5_SLW\r
-\r
 ; SCSI_In\r
 SCSI_In__0__AG EQU CYREG_PRT12_AG\r
 SCSI_In__0__BIE EQU CYREG_PRT12_BIE\r
@@ -1805,7 +1824,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0\r
 CYDEV_HEAP_SIZE EQU 0x1000\r
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000001\r
+CYDEV_INTR_RISING EQU 0x00000000\r
 CYDEV_PROJ_TYPE EQU 0\r
 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
 CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
index 6fd46ba..2f14425 100644 (file)
@@ -26,131 +26,276 @@ __attribute__ ((__section__(".cyconfigecc"), used))
 #error "Unsupported toolchain"\r
 #endif\r
 const uint8 cy_meta_configecc[] = {\r
-    0x01u, 0x45u, 0x00u, 0x40u, 0x07u, 0x52u, 0x00u, 0x40u,\r
-    0x01u, 0x64u, 0x00u, 0x40u, 0x02u, 0x03u, 0x01u, 0x40u,\r
-    0x3Fu, 0x04u, 0x01u, 0x40u, 0x2Au, 0x05u, 0x01u, 0x40u,\r
-    0x03u, 0x06u, 0x01u, 0x40u, 0x41u, 0x07u, 0x01u, 0x40u,\r
-    0x01u, 0x0Du, 0x01u, 0x40u, 0x09u, 0x15u, 0x01u, 0x40u,\r
-    0x43u, 0x16u, 0x01u, 0x40u, 0x3Au, 0x17u, 0x01u, 0x40u,\r
-    0x02u, 0x40u, 0x01u, 0x40u, 0x01u, 0x41u, 0x01u, 0x40u,\r
-    0x01u, 0x42u, 0x01u, 0x40u, 0x02u, 0x43u, 0x01u, 0x40u,\r
-    0x02u, 0x44u, 0x01u, 0x40u, 0x02u, 0x45u, 0x01u, 0x40u,\r
-    0x04u, 0x48u, 0x01u, 0x40u, 0x0Eu, 0x49u, 0x01u, 0x40u,\r
-    0x04u, 0x50u, 0x01u, 0x40u, 0x01u, 0x51u, 0x01u, 0x40u,\r
-    0x36u, 0x02u, 0x14u, 0xFFu, 0x18u, 0x04u, 0x19u, 0x0Cu,\r
-    0x1Cu, 0xE1u, 0x2Cu, 0xFFu, 0x34u, 0xF0u, 0x64u, 0x10u,\r
-    0x86u, 0x0Fu, 0x98u, 0x40u, 0xB0u, 0x40u, 0x00u, 0x01u,\r
-    0x1Du, 0x01u, 0x2Du, 0x01u, 0x30u, 0x01u, 0x31u, 0x01u,\r
-    0x39u, 0x02u, 0x3Eu, 0x01u, 0x56u, 0x08u, 0x58u, 0x04u,\r
-    0x59u, 0x0Bu, 0x5Bu, 0x04u, 0x5Cu, 0x90u, 0x5Du, 0x90u,\r
-    0x5Fu, 0x01u, 0x80u, 0x6Cu, 0x81u, 0x41u, 0x84u, 0x68u,\r
-    0x86u, 0x04u, 0x88u, 0x6Cu, 0x89u, 0x81u, 0x8Bu, 0x40u,\r
-    0x8Du, 0x41u, 0x91u, 0x04u, 0x92u, 0x02u, 0x94u, 0x10u,\r
-    0x95u, 0xE2u, 0x96u, 0x68u, 0x97u, 0x08u, 0x98u, 0x10u,\r
-    0x99u, 0x88u, 0x9Au, 0xC5u, 0x9Bu, 0x61u, 0x9Cu, 0x6Cu,\r
-    0x9Du, 0x47u, 0x9Fu, 0x98u, 0xA0u, 0x6Cu, 0xA1u, 0x10u,\r
-    0xA4u, 0x04u, 0xA5u, 0x41u, 0xA8u, 0x93u, 0xA9u, 0x40u,\r
-    0xAAu, 0x20u, 0xACu, 0x0Fu, 0xADu, 0x01u, 0xAEu, 0x90u,\r
-    0xAFu, 0x40u, 0xB2u, 0x78u, 0xB4u, 0x07u, 0xB5u, 0xC0u,\r
-    0xB6u, 0x80u, 0xB7u, 0x3Fu, 0xB9u, 0x80u, 0xBAu, 0x38u,\r
-    0xBBu, 0x20u, 0xBEu, 0x40u, 0xBFu, 0x40u, 0xD4u, 0x09u,\r
+    0x02u, 0x45u, 0x00u, 0x40u, 0x08u, 0x52u, 0x00u, 0x40u,\r
+    0x02u, 0x64u, 0x00u, 0x40u, 0x45u, 0x00u, 0x01u, 0x40u,\r
+    0x32u, 0x01u, 0x01u, 0x40u, 0x44u, 0x02u, 0x01u, 0x40u,\r
+    0x54u, 0x03u, 0x01u, 0x40u, 0x3Du, 0x04u, 0x01u, 0x40u,\r
+    0x5Bu, 0x05u, 0x01u, 0x40u, 0x0Bu, 0x06u, 0x01u, 0x40u,\r
+    0x4Eu, 0x07u, 0x01u, 0x40u, 0x10u, 0x09u, 0x01u, 0x40u,\r
+    0x3Cu, 0x0Au, 0x01u, 0x40u, 0x3Fu, 0x0Bu, 0x01u, 0x40u,\r
+    0x0Au, 0x0Du, 0x01u, 0x40u, 0x02u, 0x0Fu, 0x01u, 0x40u,\r
+    0x03u, 0x15u, 0x01u, 0x40u, 0x48u, 0x16u, 0x01u, 0x40u,\r
+    0x43u, 0x17u, 0x01u, 0x40u, 0x03u, 0x19u, 0x01u, 0x40u,\r
+    0x02u, 0x1Bu, 0x01u, 0x40u, 0x07u, 0x40u, 0x01u, 0x40u,\r
+    0x10u, 0x41u, 0x01u, 0x40u, 0x08u, 0x42u, 0x01u, 0x40u,\r
+    0x05u, 0x43u, 0x01u, 0x40u, 0x08u, 0x44u, 0x01u, 0x40u,\r
+    0x13u, 0x45u, 0x01u, 0x40u, 0x06u, 0x46u, 0x01u, 0x40u,\r
+    0x01u, 0x47u, 0x01u, 0x40u, 0x08u, 0x48u, 0x01u, 0x40u,\r
+    0x09u, 0x49u, 0x01u, 0x40u, 0x06u, 0x50u, 0x01u, 0x40u,\r
+    0x36u, 0x02u, 0x65u, 0x02u, 0x00u, 0xC9u, 0x01u, 0x9Cu,\r
+    0x18u, 0x08u, 0x19u, 0x04u, 0x1Cu, 0xE1u, 0x21u, 0x04u,\r
+    0x30u, 0x04u, 0x31u, 0x08u, 0x34u, 0x03u, 0x82u, 0x0Fu,\r
+    0x01u, 0x40u, 0x06u, 0x0Cu, 0x07u, 0x18u, 0x0Au, 0x60u,\r
+    0x0Cu, 0x02u, 0x0Fu, 0x20u, 0x10u, 0x90u, 0x12u, 0x48u,\r
+    0x14u, 0x90u, 0x16u, 0x24u, 0x17u, 0x24u, 0x19u, 0x24u,\r
+    0x1Au, 0x10u, 0x1Bu, 0x09u, 0x1Fu, 0x03u, 0x23u, 0x04u,\r
+    0x26u, 0x80u, 0x2Au, 0x90u, 0x2Cu, 0x01u, 0x2Du, 0x24u,\r
+    0x2Fu, 0x12u, 0x30u, 0x01u, 0x31u, 0x40u, 0x32u, 0x1Cu,\r
+    0x33u, 0x38u, 0x34u, 0xE0u, 0x36u, 0x02u, 0x37u, 0x07u,\r
+    0x3Eu, 0x41u, 0x3Fu, 0x01u, 0x58u, 0x04u, 0x59u, 0x04u,\r
+    0x5Bu, 0x04u, 0x5Cu, 0x99u, 0x5Fu, 0x01u, 0x85u, 0x01u,\r
+    0x87u, 0x2Cu, 0x88u, 0x08u, 0x89u, 0x32u, 0x8Bu, 0x01u,\r
+    0x8Fu, 0x08u, 0x90u, 0x04u, 0x92u, 0x02u, 0x96u, 0x03u,\r
+    0x97u, 0x40u, 0x98u, 0x04u, 0x99u, 0x06u, 0x9Au, 0x01u,\r
+    0x9Eu, 0x04u, 0xA0u, 0x08u, 0xA4u, 0x08u, 0xA5u, 0x01u,\r
+    0xA7u, 0x1Au, 0xAAu, 0x04u, 0xABu, 0x40u, 0xACu, 0x08u,\r
+    0xB2u, 0x07u, 0xB3u, 0x07u, 0xB4u, 0x08u, 0xB5u, 0x40u,\r
+    0xB7u, 0x38u, 0xB8u, 0x20u, 0xB9u, 0x08u, 0xBEu, 0x10u,\r
+    0xBFu, 0x10u, 0xD8u, 0x04u, 0xD9u, 0x0Bu, 0xDCu, 0x99u,\r
+    0xDFu, 0x01u, 0x01u, 0x28u, 0x03u, 0x02u, 0x05u, 0x10u,\r
+    0x0Au, 0x78u, 0x0Cu, 0x80u, 0x0Du, 0x10u, 0x0Eu, 0x60u,\r
+    0x12u, 0x0Cu, 0x13u, 0x48u, 0x14u, 0x90u, 0x16u, 0x04u,\r
+    0x17u, 0x40u, 0x18u, 0x40u, 0x19u, 0xA8u, 0x1Bu, 0x20u,\r
+    0x1Eu, 0x20u, 0x1Fu, 0x14u, 0x21u, 0x84u, 0x22u, 0x01u,\r
+    0x25u, 0x40u, 0x27u, 0x14u, 0x29u, 0x01u, 0x2Bu, 0x01u,\r
+    0x2Eu, 0x14u, 0x31u, 0x80u, 0x32u, 0x18u, 0x36u, 0x08u,\r
+    0x37u, 0x10u, 0x39u, 0x48u, 0x3Au, 0x08u, 0x3Bu, 0x01u,\r
+    0x3Du, 0x80u, 0x3Fu, 0x14u, 0x69u, 0x80u, 0x6Bu, 0x01u,\r
+    0x7Eu, 0x80u, 0x81u, 0x80u, 0x83u, 0x04u, 0x85u, 0x40u,\r
+    0x8Bu, 0x10u, 0x8Fu, 0x01u, 0xC0u, 0x47u, 0xC2u, 0xFEu,\r
+    0xC4u, 0xF7u, 0xCAu, 0x69u, 0xCCu, 0x6Eu, 0xCEu, 0x7Bu,\r
+    0xDEu, 0x80u, 0xE0u, 0x01u, 0xE2u, 0x20u, 0x04u, 0x0Fu,\r
+    0x05u, 0x55u, 0x06u, 0xF0u, 0x07u, 0xAAu, 0x0Bu, 0xFFu,\r
+    0x0Eu, 0xFFu, 0x10u, 0xFFu, 0x13u, 0xFFu, 0x15u, 0x0Fu,\r
+    0x16u, 0xFFu, 0x17u, 0xF0u, 0x1Du, 0x69u, 0x1Fu, 0x96u,\r
+    0x24u, 0x33u, 0x25u, 0x33u, 0x26u, 0xCCu, 0x27u, 0xCCu,\r
+    0x28u, 0x55u, 0x2Au, 0xAAu, 0x2Bu, 0xFFu, 0x2Cu, 0x96u,\r
+    0x2Eu, 0x69u, 0x31u, 0xFFu, 0x34u, 0xFFu, 0x3Eu, 0x10u,\r
+    0x3Fu, 0x01u, 0x56u, 0x02u, 0x57u, 0x2Cu, 0x58u, 0x04u,\r
+    0x59u, 0x04u, 0x5Bu, 0x0Bu, 0x5Du, 0x90u, 0x5Fu, 0x01u,\r
+    0x84u, 0x38u, 0x85u, 0x10u, 0x8Au, 0x45u, 0x8Eu, 0x38u,\r
+    0x90u, 0x07u, 0x92u, 0x40u, 0x94u, 0x06u, 0x96u, 0x40u,\r
+    0x98u, 0x08u, 0x9Cu, 0x02u, 0x9Du, 0x03u, 0x9Fu, 0x0Cu,\r
+    0xA0u, 0x02u, 0xA1u, 0x05u, 0xA3u, 0x0Au, 0xA6u, 0x10u,\r
+    0xA8u, 0x20u, 0xA9u, 0x06u, 0xABu, 0x09u, 0xACu, 0x01u,\r
+    0xAEu, 0x02u, 0xB0u, 0x07u, 0xB1u, 0x0Fu, 0xB2u, 0x40u,\r
+    0xB5u, 0x10u, 0xB6u, 0x38u, 0xBEu, 0x44u, 0xBFu, 0x11u,\r
+    0xD4u, 0x40u, 0xD8u, 0x04u, 0xD9u, 0x04u, 0xDBu, 0x0Bu,\r
+    0xDCu, 0x09u, 0xDDu, 0x90u, 0xDFu, 0x01u, 0x02u, 0x0Au,\r
+    0x03u, 0x10u, 0x05u, 0x08u, 0x07u, 0x01u, 0x0Au, 0x64u,\r
+    0x0Bu, 0x02u, 0x0Cu, 0x02u, 0x0Eu, 0x20u, 0x10u, 0x01u,\r
+    0x12u, 0x40u, 0x13u, 0x14u, 0x15u, 0x04u, 0x16u, 0x08u,\r
+    0x17u, 0x80u, 0x1Au, 0x50u, 0x1Bu, 0x41u, 0x1Du, 0x10u,\r
+    0x20u, 0x04u, 0x23u, 0x80u, 0x27u, 0x40u, 0x28u, 0x40u,\r
+    0x29u, 0x20u, 0x2Du, 0x04u, 0x2Fu, 0x24u, 0x31u, 0x80u,\r
+    0x35u, 0x08u, 0x37u, 0x81u, 0x3Au, 0x04u, 0x3Cu, 0x20u,\r
+    0x3Eu, 0x08u, 0x61u, 0x20u, 0x63u, 0x21u, 0x67u, 0x80u,\r
+    0x6Cu, 0x20u, 0x6Du, 0x91u, 0x6Fu, 0x02u, 0x76u, 0x02u,\r
+    0x77u, 0x02u, 0x78u, 0x02u, 0x7Au, 0x03u, 0x7Eu, 0x80u,\r
+    0x81u, 0x20u, 0x82u, 0x04u, 0x83u, 0x40u, 0x84u, 0x80u,\r
+    0x86u, 0x10u, 0x88u, 0x10u, 0x8Eu, 0x40u, 0x90u, 0x40u,\r
+    0x91u, 0x80u, 0x92u, 0x02u, 0x93u, 0x08u, 0x95u, 0x60u,\r
+    0x96u, 0x6Cu, 0x97u, 0x14u, 0x98u, 0x01u, 0x99u, 0x88u,\r
+    0x9Au, 0x08u, 0x9Bu, 0x11u, 0x9Cu, 0x90u, 0x9Du, 0x11u,\r
+    0x9Fu, 0x48u, 0xA1u, 0x80u, 0xA2u, 0x10u, 0xA3u, 0x20u,\r
+    0xA4u, 0x80u, 0xA6u, 0x88u, 0xA7u, 0x01u, 0xAFu, 0x01u,\r
+    0xB0u, 0x01u, 0xB3u, 0x40u, 0xB7u, 0x02u, 0xC0u, 0xA7u,\r
+    0xC2u, 0x3Fu, 0xC4u, 0xEFu, 0xCAu, 0x65u, 0xCCu, 0xD8u,\r
+    0xCEu, 0x62u, 0xD8u, 0x8Eu, 0xDEu, 0x81u, 0xE2u, 0x01u,\r
+    0xE4u, 0x08u, 0xE6u, 0x03u, 0xE8u, 0x02u, 0x00u, 0x03u,\r
+    0x0Au, 0x01u, 0x0Fu, 0x08u, 0x15u, 0x28u, 0x17u, 0x44u,\r
+    0x19u, 0x2Cu, 0x1Bu, 0x81u, 0x1Eu, 0x03u, 0x1Fu, 0x03u,\r
+    0x20u, 0x03u, 0x24u, 0x03u, 0x27u, 0x80u, 0x28u, 0x03u,\r
+    0x2Bu, 0x04u, 0x2Du, 0xD4u, 0x2Fu, 0x22u, 0x30u, 0x02u,\r
+    0x33u, 0xE0u, 0x34u, 0x01u, 0x35u, 0x18u, 0x36u, 0x02u,\r
+    0x37u, 0x07u, 0x3Bu, 0x30u, 0x3Eu, 0x51u, 0x40u, 0x64u,\r
+    0x41u, 0x02u, 0x42u, 0x30u, 0x45u, 0xE2u, 0x46u, 0x0Du,\r
+    0x47u, 0xCFu, 0x48u, 0x37u, 0x49u, 0xFFu, 0x4Au, 0xFFu,\r
+    0x4Bu, 0xFFu, 0x4Fu, 0x2Cu, 0x56u, 0x01u, 0x58u, 0x04u,\r
+    0x59u, 0x04u, 0x5Au, 0x04u, 0x5Bu, 0x04u, 0x5Cu, 0x90u,\r
+    0x5Du, 0x09u, 0x5Fu, 0x01u, 0x62u, 0xC0u, 0x66u, 0x80u,\r
+    0x68u, 0x40u, 0x69u, 0x40u, 0x6Eu, 0x08u, 0x88u, 0x01u,\r
+    0x8Au, 0x06u, 0x94u, 0x05u, 0x96u, 0x02u, 0x98u, 0x03u,\r
+    0x9Au, 0x04u, 0x9Cu, 0x04u, 0x9Eu, 0x03u, 0xB6u, 0x07u,\r
+    0xBAu, 0x80u, 0xD8u, 0x0Bu, 0xDCu, 0x09u, 0xDFu, 0x01u,\r
+    0x01u, 0x01u, 0x02u, 0x04u, 0x05u, 0x10u, 0x09u, 0x40u,\r
+    0x0Eu, 0x01u, 0x0Fu, 0x14u, 0x10u, 0x20u, 0x11u, 0x10u,\r
+    0x13u, 0x02u, 0x19u, 0x42u, 0x1Bu, 0x10u, 0x1Eu, 0x01u,\r
+    0x1Fu, 0x40u, 0x21u, 0x10u, 0x22u, 0x58u, 0x23u, 0x20u,\r
+    0x29u, 0x04u, 0x2Au, 0x20u, 0x2Bu, 0x01u, 0x30u, 0x40u,\r
+    0x32u, 0x58u, 0x39u, 0x80u, 0x41u, 0x10u, 0x42u, 0x50u,\r
+    0x48u, 0x40u, 0x49u, 0x04u, 0x4Au, 0x08u, 0x51u, 0x08u,\r
+    0x52u, 0x40u, 0x53u, 0x01u, 0x59u, 0xA8u, 0x5Au, 0x02u,\r
+    0x60u, 0x64u, 0x61u, 0x80u, 0x69u, 0x40u, 0x6Au, 0x08u,\r
+    0x6Bu, 0x88u, 0x70u, 0x90u, 0x71u, 0x01u, 0x72u, 0x20u,\r
+    0x7Eu, 0x80u, 0x81u, 0x08u, 0x83u, 0x01u, 0x85u, 0x80u,\r
+    0x88u, 0x20u, 0x89u, 0x10u, 0x8Cu, 0x10u, 0x8Eu, 0x40u,\r
+    0x90u, 0x44u, 0x91u, 0x91u, 0x92u, 0x52u, 0x95u, 0x60u,\r
+    0x96u, 0x2Cu, 0x97u, 0x97u, 0x99u, 0x80u, 0x9Au, 0x02u,\r
+    0x9Bu, 0x02u, 0x9Cu, 0x42u, 0x9Du, 0x01u, 0x9Eu, 0x40u,\r
+    0x9Fu, 0x08u, 0xA0u, 0x20u, 0xA1u, 0x40u, 0xA3u, 0x23u,\r
+    0xA4u, 0x90u, 0xA5u, 0x20u, 0xA6u, 0x89u, 0xA7u, 0x10u,\r
+    0xABu, 0x80u, 0xAFu, 0x20u, 0xB0u, 0x12u, 0xB5u, 0x08u,\r
+    0xB6u, 0x08u, 0xC0u, 0x4Au, 0xC2u, 0xE1u, 0xC4u, 0x0Eu,\r
+    0xCAu, 0x0Eu, 0xCCu, 0x0Eu, 0xCEu, 0x08u, 0xD0u, 0x07u,\r
+    0xD2u, 0x04u, 0xD6u, 0x0Fu, 0xD8u, 0x0Fu, 0xDEu, 0x80u,\r
+    0xE0u, 0x01u, 0xE2u, 0x10u, 0xE4u, 0x04u, 0xE6u, 0x02u,\r
+    0xE8u, 0x01u, 0xEAu, 0x50u, 0xEEu, 0x80u, 0x10u, 0x04u,\r
+    0x12u, 0x02u, 0x16u, 0x03u, 0x18u, 0x04u, 0x1Au, 0x01u,\r
+    0x2Au, 0x04u, 0x2Eu, 0x04u, 0x32u, 0x07u, 0x58u, 0x04u,\r
+    0x5Cu, 0x09u, 0x5Fu, 0x01u, 0x00u, 0x08u, 0x01u, 0x01u,\r
+    0x03u, 0x0Au, 0x09u, 0x08u, 0x0Au, 0x84u, 0x0Du, 0x10u,\r
+    0x0Eu, 0x60u, 0x10u, 0x22u, 0x11u, 0x12u, 0x13u, 0x02u,\r
+    0x17u, 0xA0u, 0x18u, 0x20u, 0x1Cu, 0x20u, 0x1Eu, 0x20u,\r
+    0x20u, 0x40u, 0x21u, 0x04u, 0x22u, 0x40u, 0x2Au, 0x82u,\r
+    0x2Bu, 0x16u, 0x30u, 0x22u, 0x31u, 0x08u, 0x32u, 0x40u,\r
+    0x38u, 0x60u, 0x39u, 0x01u, 0x3Bu, 0x04u, 0x41u, 0x08u,\r
+    0x42u, 0x04u, 0x43u, 0x01u, 0x48u, 0x04u, 0x49u, 0x48u,\r
+    0x50u, 0x42u, 0x51u, 0x20u, 0x52u, 0x45u, 0x58u, 0x80u,\r
+    0x60u, 0x02u, 0x62u, 0x80u, 0x78u, 0x02u, 0x91u, 0x31u,\r
+    0x92u, 0x40u, 0x96u, 0x04u, 0x97u, 0x14u, 0x98u, 0x80u,\r
+    0x99u, 0x42u, 0x9Au, 0x02u, 0x9Bu, 0xA2u, 0x9Cu, 0x02u,\r
+    0x9Du, 0x10u, 0x9Eu, 0x04u, 0xA0u, 0x20u, 0xA1u, 0x40u,\r
+    0xA3u, 0x02u, 0xA4u, 0x10u, 0xA5u, 0x20u, 0xA6u, 0x81u,\r
+    0xA8u, 0x80u, 0xA9u, 0x08u, 0xAAu, 0x04u, 0xABu, 0x01u,\r
+    0xACu, 0x50u, 0xADu, 0x20u, 0xB2u, 0x40u, 0xB5u, 0x40u,\r
+    0xB6u, 0x08u, 0xB7u, 0x20u, 0xC0u, 0x0Fu, 0xC2u, 0x7Eu,\r
+    0xC4u, 0xCFu, 0xCAu, 0x0Fu, 0xCCu, 0x0Fu, 0xCEu, 0x0Fu,\r
+    0xD0u, 0x07u, 0xD2u, 0x0Cu, 0xD6u, 0x08u, 0xD8u, 0x08u,\r
+    0xDEu, 0x01u, 0xE4u, 0x40u, 0xE8u, 0x0Au, 0xEEu, 0x07u,\r
+    0x8Eu, 0x01u, 0x9Eu, 0x41u, 0xA4u, 0x02u, 0xA8u, 0x41u,\r
+    0xABu, 0x08u, 0xAEu, 0x09u, 0xAFu, 0x82u, 0xB2u, 0x01u,\r
+    0xB4u, 0x41u, 0xB5u, 0x10u, 0xB6u, 0x20u, 0xB7u, 0x04u,\r
+    0xE4u, 0x40u, 0xE8u, 0x40u, 0xEAu, 0x01u, 0xECu, 0xD0u,\r
+    0x00u, 0x01u, 0x01u, 0x33u, 0x03u, 0xCCu, 0x08u, 0x02u,\r
+    0x0Fu, 0xFFu, 0x11u, 0x96u, 0x13u, 0x69u, 0x17u, 0xFFu,\r
+    0x1Du, 0x55u, 0x1Fu, 0xAAu, 0x21u, 0xFFu, 0x29u, 0x0Fu,\r
+    0x2Bu, 0xF0u, 0x34u, 0x01u, 0x35u, 0xFFu, 0x36u, 0x02u,\r
+    0x3Eu, 0x50u, 0x3Fu, 0x10u, 0x58u, 0x04u, 0x59u, 0x04u,\r
+    0x5Fu, 0x01u, 0x82u, 0x02u, 0x85u, 0x33u, 0x86u, 0x80u,\r
+    0x87u, 0xCCu, 0x88u, 0x80u, 0x8Au, 0x40u, 0x8Bu, 0xFFu,\r
+    0x8Eu, 0x08u, 0x91u, 0xFFu, 0x92u, 0x04u, 0x94u, 0x06u,\r
+    0x95u, 0x0Fu, 0x96u, 0x08u, 0x97u, 0xF0u, 0x98u, 0x80u,\r
+    0x9Au, 0x20u, 0x9Du, 0x55u, 0x9Eu, 0x60u, 0x9Fu, 0xAAu,\r
+    0xA0u, 0x02u, 0xA2u, 0x04u, 0xA4u, 0x10u, 0xA9u, 0x69u,\r
+    0xAAu, 0x80u, 0xABu, 0x96u, 0xACu, 0x01u, 0xADu, 0xFFu,\r
+    0xB0u, 0x01u, 0xB2u, 0x0Eu, 0xB4u, 0x10u, 0xB6u, 0xE0u,\r
+    0xB7u, 0xFFu, 0xBEu, 0x15u, 0xBFu, 0x40u, 0xD8u, 0x04u,\r
+    0xD9u, 0x04u, 0xDBu, 0x04u, 0xDCu, 0x09u, 0xDFu, 0x01u,\r
+    0x00u, 0x01u, 0x01u, 0x20u, 0x06u, 0x61u, 0x07u, 0x08u,\r
+    0x0Cu, 0x02u, 0x0Eu, 0x22u, 0x0Fu, 0x04u, 0x15u, 0x80u,\r
+    0x16u, 0x10u, 0x17u, 0x11u, 0x1Au, 0x0Au, 0x1Cu, 0x48u,\r
+    0x1Eu, 0x02u, 0x1Fu, 0x08u, 0x22u, 0x20u, 0x26u, 0x40u,\r
+    0x28u, 0x08u, 0x29u, 0x02u, 0x2Cu, 0x08u, 0x2Fu, 0x02u,\r
+    0x31u, 0x02u, 0x32u, 0x08u, 0x33u, 0x40u, 0x34u, 0x08u,\r
+    0x35u, 0x02u, 0x37u, 0x40u, 0x38u, 0x82u, 0x3Du, 0x20u,\r
+    0x3Fu, 0x08u, 0x5Du, 0x08u, 0x5Eu, 0x01u, 0x5Fu, 0xA0u,\r
+    0x6Eu, 0x20u, 0x6Fu, 0x01u, 0x81u, 0x28u, 0x83u, 0x20u,\r
+    0x84u, 0x04u, 0x8Au, 0x04u, 0x8Bu, 0x04u, 0x8Du, 0x40u,\r
+    0x8Fu, 0x10u, 0x98u, 0x08u, 0x99u, 0x02u, 0x9Au, 0x10u,\r
+    0x9Bu, 0x48u, 0xA0u, 0x08u, 0xA1u, 0x02u, 0xA6u, 0x61u,\r
+    0xA8u, 0x08u, 0xA9u, 0x02u, 0xB4u, 0x08u, 0xB7u, 0x40u,\r
+    0xC0u, 0xFAu, 0xC2u, 0xF0u, 0xC4u, 0xF0u, 0xCAu, 0x35u,\r
+    0xCCu, 0xDBu, 0xCEu, 0x69u, 0xD6u, 0xF0u, 0xE2u, 0x80u,\r
+    0xE4u, 0x60u, 0xE6u, 0x01u, 0xE8u, 0x50u, 0x82u, 0x01u,\r
+    0x85u, 0x02u, 0x86u, 0x30u, 0x8Au, 0x40u, 0x8Fu, 0x08u,\r
+    0xE2u, 0x23u, 0xE4u, 0x40u, 0xE8u, 0x02u, 0xEAu, 0x20u,\r
+    0xEEu, 0x60u, 0xE0u, 0x01u, 0xE6u, 0x10u, 0xA8u, 0x40u,\r
+    0xABu, 0x20u, 0xECu, 0x80u, 0x00u, 0xD0u, 0x04u, 0x24u,\r
+    0x06u, 0x43u, 0x08u, 0x11u, 0x0Au, 0x22u, 0x0Cu, 0xD0u,\r
+    0x10u, 0x20u, 0x12u, 0xD0u, 0x14u, 0x28u, 0x16u, 0x83u,\r
+    0x18u, 0xD0u, 0x1Eu, 0x0Cu, 0x20u, 0xD0u, 0x26u, 0x01u,\r
+    0x28u, 0xD0u, 0x2Eu, 0x02u, 0x30u, 0xF0u, 0x36u, 0x0Fu,\r
+    0x3Au, 0x02u, 0x58u, 0x0Bu, 0x5Cu, 0x09u, 0x5Fu, 0x01u,\r
+    0x80u, 0x38u, 0x81u, 0x46u, 0x84u, 0x43u, 0x85u, 0x39u,\r
+    0x86u, 0x3Cu, 0x87u, 0x06u, 0x88u, 0x48u, 0x8Au, 0x20u,\r
+    0x8Bu, 0x46u, 0x8Du, 0x04u, 0x8Fu, 0x20u, 0x90u, 0x38u,\r
+    0x94u, 0x61u, 0x95u, 0x01u, 0x96u, 0x1Eu, 0x97u, 0x5Eu,\r
+    0x98u, 0x23u, 0x99u, 0x42u, 0x9Au, 0x44u, 0x9Bu, 0x04u,\r
+    0x9Cu, 0x18u, 0x9Eu, 0x20u, 0xA0u, 0x10u, 0xA1u, 0x46u,\r
+    0xA4u, 0x28u, 0xA5u, 0x42u, 0xA6u, 0x10u, 0xA8u, 0x20u,\r
+    0xA9u, 0x77u, 0xAAu, 0x18u, 0xABu, 0x08u, 0xADu, 0x46u,\r
+    0xB1u, 0x08u, 0xB2u, 0x60u, 0xB3u, 0x70u, 0xB4u, 0x1Eu,\r
+    0xB5u, 0x0Fu, 0xB6u, 0x01u, 0xB9u, 0x20u, 0xBAu, 0x08u,\r
+    0xBBu, 0x0Cu, 0xBEu, 0x40u, 0xBFu, 0x01u, 0xD4u, 0x09u,\r
     0xD8u, 0x0Bu, 0xD9u, 0x0Bu, 0xDBu, 0x0Bu, 0xDCu, 0x99u,\r
-    0xDDu, 0x90u, 0xDFu, 0x01u, 0x00u, 0x01u, 0x04u, 0x28u,\r
-    0x06u, 0x80u, 0x0Cu, 0x02u, 0x0Du, 0x01u, 0x0Eu, 0x29u,\r
-    0x17u, 0x69u, 0x1Au, 0x80u, 0x1Du, 0x30u, 0x1Eu, 0x28u,\r
-    0x1Fu, 0x40u, 0x21u, 0x02u, 0x22u, 0x02u, 0x25u, 0x90u,\r
-    0x27u, 0x08u, 0x29u, 0x40u, 0x2Fu, 0xAAu, 0x31u, 0x80u,\r
-    0x36u, 0x06u, 0x37u, 0x60u, 0x3Cu, 0x80u, 0x3Du, 0x20u,\r
-    0x3Eu, 0x81u, 0x4Bu, 0xC0u, 0x58u, 0x40u, 0x5Du, 0x24u,\r
-    0x5Eu, 0x02u, 0x5Fu, 0x40u, 0x60u, 0x01u, 0x66u, 0x40u,\r
-    0x78u, 0x02u, 0x7Cu, 0x02u, 0x98u, 0x40u, 0xC0u, 0x78u,\r
-    0xC2u, 0xF0u, 0xC4u, 0xF0u, 0xCAu, 0xF8u, 0xCCu, 0xF8u,\r
-    0xCEu, 0xB0u, 0xD6u, 0xF8u, 0xD8u, 0x18u, 0xDEu, 0x81u,\r
-    0xD6u, 0x08u, 0xDBu, 0x04u, 0xDDu, 0x90u, 0x00u, 0x01u,\r
-    0x02u, 0x40u, 0x05u, 0x10u, 0x07u, 0x61u, 0x0Du, 0x02u,\r
-    0x0Eu, 0x21u, 0x0Fu, 0x08u, 0x17u, 0x1Au, 0x1Du, 0x40u,\r
-    0x24u, 0x01u, 0x25u, 0x0Cu, 0x26u, 0x02u, 0x27u, 0x60u,\r
-    0x2Au, 0x02u, 0x2Bu, 0x80u, 0x2Cu, 0x02u, 0x2Eu, 0x01u,\r
-    0x2Fu, 0x28u, 0x36u, 0x46u, 0x3Cu, 0x80u, 0x3Du, 0x28u,\r
-    0x44u, 0x80u, 0x45u, 0xA8u, 0x4Cu, 0x80u, 0x4Du, 0x04u,\r
-    0x4Eu, 0x02u, 0x54u, 0x02u, 0x56u, 0x10u, 0x57u, 0x84u,\r
-    0x59u, 0x80u, 0x60u, 0x02u, 0x66u, 0x20u, 0x6Cu, 0x14u,\r
-    0x6Eu, 0xA1u, 0x6Fu, 0x3Bu, 0x74u, 0x40u, 0x77u, 0x02u,\r
-    0x7Cu, 0x02u, 0x94u, 0x28u, 0x95u, 0x04u, 0x96u, 0x01u,\r
-    0x99u, 0x10u, 0x9Bu, 0x08u, 0x9Cu, 0x02u, 0x9Du, 0x40u,\r
-    0x9Eu, 0x40u, 0x9Fu, 0x61u, 0xA1u, 0x32u, 0xA2u, 0x04u,\r
-    0xA4u, 0x42u, 0xA6u, 0x01u, 0xA7u, 0xAAu, 0xAAu, 0x40u,\r
-    0xADu, 0x21u, 0xC0u, 0xF0u, 0xC2u, 0xF0u, 0xC4u, 0x70u,\r
-    0xCAu, 0xF0u, 0xCCu, 0xD0u, 0xCEu, 0x70u, 0xD0u, 0xF0u,\r
-    0xD2u, 0x10u, 0xD6u, 0x08u, 0xD8u, 0x28u, 0xDEu, 0x80u,\r
-    0xEAu, 0x80u, 0x84u, 0x80u, 0x89u, 0x40u, 0x9Cu, 0x80u,\r
-    0xA1u, 0x40u, 0xAAu, 0x40u, 0xADu, 0x01u, 0xB0u, 0x85u,\r
-    0xB2u, 0x10u, 0xE6u, 0x20u, 0x00u, 0x04u, 0x02u, 0x08u,\r
-    0x04u, 0x10u, 0x05u, 0x18u, 0x06u, 0x0Cu, 0x07u, 0x25u,\r
-    0x08u, 0x20u, 0x09u, 0x20u, 0x0Au, 0x0Cu, 0x0Bu, 0x18u,\r
-    0x0Eu, 0x03u, 0x0Fu, 0x01u, 0x11u, 0x08u, 0x12u, 0x04u,\r
-    0x13u, 0x33u, 0x14u, 0x03u, 0x19u, 0x2Eu, 0x1Au, 0x30u,\r
-    0x1Bu, 0x10u, 0x1Cu, 0x03u, 0x20u, 0x03u, 0x26u, 0x01u,\r
-    0x28u, 0x03u, 0x2Eu, 0x48u, 0x30u, 0x40u, 0x32u, 0x01u,\r
-    0x34u, 0x3Cu, 0x35u, 0x38u, 0x36u, 0x02u, 0x37u, 0x07u,\r
-    0x3Bu, 0x20u, 0x3Eu, 0x44u, 0x54u, 0x40u, 0x58u, 0x0Bu,\r
-    0x59u, 0x0Bu, 0x5Bu, 0x0Bu, 0x5Cu, 0x99u, 0x5Du, 0x90u,\r
-    0x5Fu, 0x01u, 0x80u, 0x01u, 0x82u, 0x02u, 0x88u, 0x06u,\r
-    0x8Bu, 0x07u, 0x8Eu, 0x10u, 0x91u, 0x01u, 0x92u, 0x08u,\r
-    0x97u, 0x02u, 0x98u, 0x02u, 0x9Au, 0x01u, 0xA1u, 0x07u,\r
-    0xA8u, 0x01u, 0xA9u, 0x04u, 0xAAu, 0x04u, 0xACu, 0x08u,\r
-    0xAEu, 0x10u, 0xB0u, 0x07u, 0xB1u, 0x07u, 0xB2u, 0x07u,\r
-    0xB6u, 0x18u, 0xB8u, 0x0Au, 0xBEu, 0x40u, 0xBFu, 0x01u,\r
-    0xD8u, 0x0Bu, 0xD9u, 0x04u, 0xDBu, 0x04u, 0xDCu, 0x09u,\r
-    0xDFu, 0x01u, 0x00u, 0x10u, 0x01u, 0x40u, 0x03u, 0x40u,\r
-    0x05u, 0x10u, 0x07u, 0x61u, 0x09u, 0x20u, 0x0Au, 0x80u,\r
-    0x0Eu, 0x69u, 0x10u, 0x02u, 0x12u, 0x08u, 0x13u, 0x20u,\r
-    0x16u, 0x12u, 0x17u, 0x12u, 0x18u, 0x10u, 0x19u, 0x81u,\r
-    0x1Du, 0x84u, 0x1Eu, 0x4Au, 0x1Fu, 0x10u, 0x21u, 0x01u,\r
-    0x25u, 0x40u, 0x27u, 0x08u, 0x29u, 0x11u, 0x32u, 0x0Au,\r
-    0x35u, 0x10u, 0x36u, 0x02u, 0x3Bu, 0x20u, 0x3Du, 0x88u,\r
-    0x3Eu, 0x20u, 0x46u, 0x20u, 0x47u, 0x08u, 0x64u, 0x05u,\r
-    0x65u, 0x04u, 0x68u, 0x02u, 0x78u, 0x02u, 0x7Cu, 0x02u,\r
-    0x8Du, 0x40u, 0x92u, 0x01u, 0x98u, 0x02u, 0x99u, 0x10u,\r
-    0x9Au, 0x12u, 0x9Bu, 0x73u, 0x9Cu, 0x80u, 0x9Du, 0x80u,\r
-    0x9Eu, 0x20u, 0xA0u, 0x80u, 0xA1u, 0x24u, 0xA2u, 0x12u,\r
-    0xA5u, 0x80u, 0xA6u, 0x01u, 0xC0u, 0xFBu, 0xC2u, 0xFAu,\r
-    0xC4u, 0xF3u, 0xCAu, 0x05u, 0xCCu, 0xA3u, 0xCEu, 0x74u,\r
-    0xD8u, 0x70u, 0xDEu, 0x81u, 0xE0u, 0x40u, 0x33u, 0x40u,\r
-    0xCCu, 0x10u, 0x9Fu, 0x40u, 0x9Fu, 0x40u, 0xABu, 0x40u,\r
-    0xEEu, 0x80u, 0x14u, 0x40u, 0xC4u, 0x04u, 0xB0u, 0x40u,\r
-    0xEAu, 0x01u, 0x20u, 0x10u, 0x26u, 0x80u, 0x8Eu, 0x80u,\r
-    0xC8u, 0x60u, 0x08u, 0x02u, 0x5Bu, 0x20u, 0x5Fu, 0x40u,\r
-    0x84u, 0x02u, 0x8Bu, 0x20u, 0x93u, 0x40u, 0xA8u, 0x10u,\r
-    0xAFu, 0x40u, 0xC2u, 0x10u, 0xD4u, 0x80u, 0xD6u, 0x20u,\r
-    0xE4u, 0x40u, 0xECu, 0x80u, 0xEEu, 0x40u, 0x01u, 0x01u,\r
-    0x0Bu, 0x01u, 0x11u, 0x01u, 0x1Bu, 0x01u, 0x00u, 0x03u,\r
-    0x1Fu, 0x00u, 0x20u, 0x00u, 0x00u, 0x91u, 0xFFu, 0x6Eu,\r
-    0x7Fu, 0x24u, 0x80u, 0x00u, 0x90u, 0x6Cu, 0x40u, 0x00u,\r
-    0x00u, 0x71u, 0x60u, 0x82u, 0xC0u, 0x10u, 0x08u, 0xEFu,\r
-    0x00u, 0x00u, 0x9Fu, 0x00u, 0xC0u, 0x6Cu, 0x02u, 0x00u,\r
-    0xC0u, 0x6Cu, 0x01u, 0x00u, 0x80u, 0x24u, 0x00u, 0x48u,\r
-    0xC0u, 0x00u, 0x04u, 0x6Cu, 0x00u, 0x48u, 0x00u, 0x00u,\r
-    0x00u, 0x0Fu, 0x00u, 0xF0u, 0x00u, 0x00u, 0xFFu, 0x10u,\r
-    0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x40u,\r
-    0x32u, 0x05u, 0x10u, 0x00u, 0x04u, 0xFEu, 0xDBu, 0xCBu,\r
-    0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,\r
-    0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u,\r
-    0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u,\r
+    0xDDu, 0x90u, 0xDFu, 0x01u, 0x00u, 0x08u, 0x01u, 0x01u,\r
+    0x03u, 0x08u, 0x04u, 0x04u, 0x05u, 0x10u, 0x06u, 0x80u,\r
+    0x07u, 0x02u, 0x09u, 0x49u, 0x0Au, 0x04u, 0x0Cu, 0x20u,\r
+    0x0Eu, 0x42u, 0x0Fu, 0x10u, 0x10u, 0x20u, 0x11u, 0x10u,\r
+    0x12u, 0x40u, 0x15u, 0x19u, 0x16u, 0x01u, 0x19u, 0x54u,\r
+    0x1Au, 0x04u, 0x1Bu, 0x1Cu, 0x1Eu, 0x42u, 0x20u, 0x0Cu,\r
+    0x21u, 0x08u, 0x23u, 0x94u, 0x29u, 0x14u, 0x2Au, 0x02u,\r
+    0x2Bu, 0x02u, 0x30u, 0x20u, 0x31u, 0x08u, 0x38u, 0x80u,\r
+    0x39u, 0x11u, 0x3Bu, 0x04u, 0x59u, 0x0Au, 0x5Bu, 0xA0u,\r
+    0x61u, 0x40u, 0x78u, 0x02u, 0x7Eu, 0x80u, 0x8Bu, 0x01u,\r
+    0x90u, 0x80u, 0x91u, 0x19u, 0x96u, 0x04u, 0x97u, 0x14u,\r
+    0x98u, 0x02u, 0x99u, 0x0Au, 0x9Au, 0xC3u, 0x9Bu, 0x02u,\r
+    0x9Du, 0x10u, 0x9Fu, 0x01u, 0xA0u, 0x20u, 0xA1u, 0x41u,\r
+    0xA2u, 0x80u, 0xA3u, 0x02u, 0xA4u, 0x04u, 0xA5u, 0x08u,\r
+    0xA6u, 0x01u, 0xA7u, 0x1Cu, 0xC0u, 0xFEu, 0xC2u, 0xFFu,\r
+    0xC4u, 0xFEu, 0xCAu, 0x0Fu, 0xCCu, 0x06u, 0xCEu, 0x0Fu,\r
+    0xD6u, 0x0Fu, 0xD8u, 0x08u, 0xDEu, 0x81u, 0xE4u, 0x20u,\r
+    0xECu, 0x80u, 0xA4u, 0x02u, 0xB2u, 0x40u, 0xECu, 0x80u,\r
+    0xB0u, 0x02u, 0xECu, 0x80u, 0x58u, 0x10u, 0x80u, 0x80u,\r
+    0x86u, 0x80u, 0x88u, 0x10u, 0xD4u, 0x80u, 0xE2u, 0x40u,\r
+    0xE6u, 0x80u, 0x53u, 0x81u, 0x57u, 0x0Au, 0x59u, 0x04u,\r
+    0x5Cu, 0x02u, 0x60u, 0x08u, 0x64u, 0x80u, 0x81u, 0x04u,\r
+    0x82u, 0x40u, 0x84u, 0x08u, 0x98u, 0x80u, 0x9Au, 0x80u,\r
+    0xD4u, 0xE0u, 0xD6u, 0xE0u, 0xD8u, 0xC0u, 0xE2u, 0x20u,\r
+    0xE6u, 0x90u, 0x8Cu, 0x02u, 0x92u, 0x40u, 0x9Au, 0x80u,\r
+    0x9Cu, 0x02u, 0xAFu, 0x80u, 0xB3u, 0x02u, 0xB7u, 0x09u,\r
+    0xEEu, 0x10u, 0x23u, 0x08u, 0x8Fu, 0x08u, 0x92u, 0x40u,\r
+    0x9Au, 0x80u, 0xC8u, 0x10u, 0x0Cu, 0x01u, 0x51u, 0x02u,\r
+    0x54u, 0x20u, 0x80u, 0x20u, 0x8Cu, 0x40u, 0xC2u, 0x04u,\r
+    0xD4u, 0x03u, 0xE6u, 0x08u, 0x02u, 0x04u, 0x03u, 0x10u,\r
+    0x04u, 0x80u, 0x07u, 0x40u, 0x09u, 0x02u, 0x0Bu, 0x01u,\r
+    0x0Cu, 0x18u, 0x80u, 0x08u, 0x85u, 0x02u, 0x94u, 0x80u,\r
+    0x9Cu, 0x10u, 0x9Fu, 0x10u, 0xADu, 0x02u, 0xB0u, 0x11u,\r
+    0xB7u, 0x10u, 0xC0u, 0x0Fu, 0xC2u, 0x0Fu, 0xEAu, 0x04u,\r
+    0xEEu, 0x06u, 0x83u, 0x40u, 0x8Eu, 0x04u, 0x93u, 0x01u,\r
+    0x9Au, 0x04u, 0x9Bu, 0x40u, 0xE6u, 0x08u, 0xABu, 0x01u,\r
+    0x23u, 0x10u, 0x27u, 0x08u, 0x88u, 0x01u, 0x92u, 0x40u,\r
+    0x97u, 0x10u, 0x9Au, 0x80u, 0xB3u, 0x10u, 0xC8u, 0x60u,\r
+    0x08u, 0x01u, 0x56u, 0x80u, 0x5Au, 0x40u, 0x92u, 0x40u,\r
+    0x9Au, 0x80u, 0x9Cu, 0x01u, 0xB3u, 0x08u, 0xC2u, 0x10u,\r
+    0xD4u, 0xC0u, 0x01u, 0x01u, 0x09u, 0x01u, 0x0Bu, 0x01u,\r
+    0x0Du, 0x01u, 0x11u, 0x01u, 0x1Bu, 0x01u, 0x00u, 0x00u,\r
+    0xC0u, 0x01u, 0x02u, 0x00u, 0x00u, 0x08u, 0xFFu, 0x21u,\r
+    0x80u, 0x40u, 0x00u, 0x00u, 0x90u, 0x40u, 0x40u, 0x00u,\r
+    0x00u, 0x10u, 0x60u, 0x80u, 0x7Fu, 0x22u, 0x80u, 0x08u,\r
+    0x1Fu, 0x01u, 0x20u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u,\r
+    0xC0u, 0x01u, 0x01u, 0x00u, 0xC0u, 0x07u, 0x04u, 0x18u,\r
+    0xC0u, 0x01u, 0x08u, 0x00u, 0x00u, 0x01u, 0x9Fu, 0x00u,\r
+    0x00u, 0x3Fu, 0xFFu, 0x80u, 0x00u, 0x00u, 0x00u, 0x40u,\r
+    0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u,\r
+    0x63u, 0x02u, 0x50u, 0x00u, 0x04u, 0x0Eu, 0xFCu, 0xBDu,\r
+    0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,\r
+    0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u,\r
+    0x04u, 0x0Bu, 0x0Bu, 0x04u, 0x90u, 0x99u, 0x00u, 0x01u,\r
     0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u,\r
     0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x00u, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+    0x00u, 0xFFu, 0xFFu, 0x00u, 0xFFu, 0x00u, 0x00u, 0x00u,\r
     0x08u, 0x00u, 0x30u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u,\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
     0x10u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, 0x00u,\r
     0x00u, 0x00u, 0x00u, 0x01u, 0x02u, 0x00u, 0xF1u, 0x0Eu,\r
     0x0Eu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0xF0u, 0x00u, 0x0Fu, 0xF0u, 0x00u, 0x00u, 0x00u, 0x00u,\r
-    0x00u, 0x01u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0x0Fu, 0x00u,\r
-    0x00u, 0x00u, 0x00u, 0x01u\r
+    0x00u, 0xFCu, 0xFCu, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u,\r
+    0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u,\r
+    0xF0u, 0x0Fu, 0x0Fu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x01u\r
 };\r
 \r
 #if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
@@ -175,6 +320,272 @@ const uint8 cy_meta_wonvl[] = {
     0xBCu, 0x90u, 0xACu, 0xAFu\r
 };\r
 \r
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
+__attribute__ ((__section__(".cyeeprom"), used))\r
+#elif defined(__ICCARM__)\r
+#pragma  location=".cyeeprom"\r
+#else\r
+#error "Unsupported toolchain"\r
+#endif\r
+const uint8 cy_eeprom[] = {\r
+    0x00u, 0x20u, 0x63u, 0x6Fu, 0x64u, 0x65u, 0x73u, 0x72u,\r
+    0x63u, 0x20u, 0x20u, 0x20u, 0x20u, 0x20u, 0x20u, 0x20u,\r
+    0x20u, 0x20u, 0x53u, 0x43u, 0x53u, 0x49u, 0x32u, 0x53u,\r
+    0x44u, 0x32u, 0x2Eu, 0x30u, 0x61u, 0x00u, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+    0x63u, 0x6Fu, 0x64u, 0x65u, 0x73u, 0x72u, 0x63u, 0x5Fu,\r
+    0x30u, 0x30u, 0x30u, 0x30u, 0x30u, 0x30u, 0x30u, 0x31u,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r