SCSI2SD Schematic Notes - Revision history

Michael: /* Change of PHY */

2013-06-01T02:27:20Z

Change of PHY

← Older revision		Revision as of 02:27, 1 June 2013
Line 12:		Line 12:
	The V1 schematic made use of a typical bus arrangement to interface to the SCSI wires. SCSI signals were split into read and write paths, with the microcontroller using a signal to switch the bus between read or write mode. This arrangement uses minimal microcontroller pins (18 SCSI pins + 1 R/W signal), but additional interface IC's.		The V1 schematic made use of a typical bus arrangement to interface to the SCSI wires. SCSI signals were split into read and write paths, with the microcontroller using a signal to switch the bus between read or write mode. This arrangement uses minimal microcontroller pins (18 SCSI pins + 1 R/W signal), but additional interface IC's.

	The V2 schematic will switch back to a much simpler arrangement whereby each SCSI signal is connected to the microcontroller twice - once for read, and another for write (via an inverting buffer). This arrangement is possible due to the additional I/Os available with the 100-pin QFP version of the microcontroller, and saves the cost/board space/soldering of 6 additional ICs.		The V2 schematic will switch back to a much simpler arrangement whereby each SCSI signal is connected to the microcontroller twice - once for read, and another for write (via an inverting buffer). This arrangement is possible due to the additional I/Os available with the 100-pin QFP version of the microcontroller, and saves the cost/board space/soldering of 6 additional ICs. The PSoC5 supports configurable CMOS or LVTTL (SCSI-compatible) signal levels on all GPIO pins.

	== Removal of the switching regulator ==		== Removal of the switching regulator ==

Michael: /* Changes between V1 and V2 */

2013-05-29T11:30:00Z

Changes between V1 and V2

← Older revision		Revision as of 11:30, 29 May 2013
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	The V2 schematic will switch back to a much simpler arrangement whereby each SCSI signal is connected to the microcontroller twice - once for read, and another for write (via an inverting buffer). This arrangement is possible due to the additional I/Os available with the 100-pin QFP version of the microcontroller, and saves the cost/board space/soldering of 6 additional ICs.		The V2 schematic will switch back to a much simpler arrangement whereby each SCSI signal is connected to the microcontroller twice - once for read, and another for write (via an inverting buffer). This arrangement is possible due to the additional I/Os available with the 100-pin QFP version of the microcontroller, and saves the cost/board space/soldering of 6 additional ICs.

			== Removal of the switching regulator ==
			Since the change of PHY has reduced the need for 3.3V power, it is now feasible to run the SD Card from a much simpler (cheaper) LDO linear regulator.

			The CY8C53 micro will use the 5V supply instead (internally regulated to 1.8V anyway). Running at 5V is necessary for the PHY design of directly connecting the input SCSI signals. This micro allows some I/O pins to run at a lower voltage for interfacing directly to the SD card at 3.3V.

	=== Use of a solder stencil ===		=== Use of a solder stencil ===
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	# Laser-cut 3mil mylar (plastic) stencils available from [http://www.pololu.com/catalog/product/446 pololu] for $25. Non-framed.		# Laser-cut 3mil mylar (plastic) stencils available from [http://www.pololu.com/catalog/product/446 pololu] for $25. Non-framed.
	# Laser-cut 3.5mil kapton (plastic) stencils available from [http://ohararp.com/Stencils.html ohararp] for $25. Non-framed.		# Laser-cut 3.5mil kapton (plastic) stencils available from [http://ohararp.com/Stencils.html ohararp] for $25. Non-framed.


	== Board specifications ==		== Board specifications ==

Michael: /* Power Supply */

2013-05-29T11:27:29Z

Power Supply

@@ Line 27: / Line 27: @@
 == Power Supply ==
 Everything except the SD Card and terminator will make use of the 5V supplied over the molex connector.
@@ Line 34: / Line 32: @@
 The SD Card (approv 200mA max) will be serviced by a fixed 3.3V version of the same LD1117 LDO regulator.
 == Switches ==

Michael: /* Power Requirements */

2013-05-29T11:26:58Z

Power Requirements

@@ Line 29: / Line 29: @@
 === Power Requirements ===
-{| border="1"
+Everything except the SD Card and terminator will make use of the 5V supplied over the molex connector.
-V supply from a hard drive molex connector should provide more than sufficient current.  The 3.3v supply will be regulated from the 5v supply to share input capacitance and therefore reduce complexity.
+The SCSI terminator will use a 2.85 fixed-voltage verson of the LD1117 (LT1117) LDO Regulator. The datasheet provides examples of use for SCSI termination.
 === Switching Regulator Requirements ===

Michael: /* Power Requirements */

2013-05-29T10:06:43Z

Power Requirements

← Older revision		Revision as of 10:06, 29 May 2013
Line 32:		Line 32:
	!		!
	!3.3V		!3.3V
	\|-
	~~\|CY8C53~~
	~~\|200mA~~
	~~rough estimate~~
	\|-		\|-
	\|SD Card		\|SD Card
Line 46:		Line 42:
	\|-		\|-
	\|'''Total'''		\|'''Total'''
	\|'''~~866mA~~'''		\|'''666mA'''
	\|}		\|}

Michael: Updates for V2

2013-05-28T10:30:24Z

Updates for V2

Show changes

Michael: /* Inrush Current Limiting */

2012-06-21T13:26:13Z

Inrush Current Limiting

← Older revision		Revision as of 13:26, 21 June 2012
Line 202:		Line 202:
	\|-		\|-
	\| 5V		\| 5V
	\| ~~2kΩ~~		\| 10kΩ
	\| 2.5mA		\| 0.5mA
	\|}		\|}

Michael: /* Inrush Current Limiting */

2012-06-21T12:59:58Z

Inrush Current Limiting

← Older revision		Revision as of 12:59, 21 June 2012
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	==== Inrush Current Limiting ====		==== Inrush Current Limiting ====
	The low-ESR ceramic input capacitors will act as a short to ground when the device is turned on. A 5Ω power resistor will be used to limit the initial inrush current to a maximum of 1A, dissipating 5W. 5W SMD resistors are very large, so we'll make do with a 2W resistor. Most power resistors are rated for 5x there rated power for a short duration (~ 5seconds). The resistor must be bypassed soon after the circuit turns on allow it to cool down, and to improve efficiency. The disconnection will be done with a P-Channel enhancement mode MOSFET, with the gate triggered via a ~~transistor~~ when the capacitor voltage ~~has risen~~ to 4V. Note that the regulator will switch on above the low-voltage lockout threshold of 2.35V.		The low-ESR ceramic input capacitors will act as a short to ground when the device is turned on. A 5Ω power resistor will be used to limit the initial inrush current to a maximum of 1A, dissipating 5W. 5W SMD resistors are very large, so we'll make do with a 2W resistor. Most power resistors are rated for 5x there rated power for a short duration (~ 5seconds). The resistor must be bypassed soon after the circuit turns on allow it to cool down, and to improve efficiency. The disconnection will be done with a P-Channel enhancement mode MOSFET, with the gate triggered via a voltage comparitor when the capacitor voltage rises to 4/5 of the input. Note that the regulator will switch on above the low-voltage lockout threshold of 2.35V.

	Resistor		Resistor
Line 195:		Line 195:
	\|}		\|}

	MOSFET Gate pullup resistor (to +5v). The current through this resistor, when grounded, will be ~~collector->emitter current of NPN transistor~~.		MOSFET Gate pullup resistor (to +5v). The current through this resistor, when grounded, will be sent to ground through the comparitor.
	{\| border="1"		{\| border="1"
	! Voltage		! Voltage
Line 221:		Line 221:
	<math>I = 0.2A</math>		<math>I = 0.2A</math>

			A standard [http://www.digikey.com/product-detail/en/LM311DR/296-1388-1-ND/379817 LM311] comparitor will be used. The comparitor provides an open-collector output to bring the MOSFET gate to ground when the +ve input is lower than the -ve input. The -ve input will be connected to the input caps, and the +ve input will be connected to a resistor voltage divider to bring the input down to 4v.

	~~Switching NPN Transistor (used to bring the MOSFET gate to ground to turn the MOSFET on).~~
	{\| border="1"		{\| border="1"
	! ~~Max Collector Current (Ic)~~		! R1 to +5v
	! ~~Collector Emitter breakdown voltage~~		! R2 to ground
	~~! collector-emitter saturation~~		! Comparitor +ve input
	! ~~base-emitter saturation~~
	~~! Part~~
	\|-
	~~\| 200mA~~
	~~\| 40V~~
	~~\| 300mV~~
	~~\| 0.95V~~
	~~\| [http://www.digikey.com/product-detail/en/MMBT3904-7-F/MMBT3904-FDICT-ND/815727 Diodes Inc. MMBT3904-7-F]~~
	\|}

	The base-emitter voltage will be 3.3V, which will certainly cause saturation (only need < 1V). The collector-emitter saturation voltage will bring the gate-to-source voltage of the MOSFET down to -4.7V (5V input ~~- 300mV in the transistor). This is sufficient to saturate the MOSFET (need -4.5V).~~

	~~Transistor Base current limiting resistor. We'll drive at 2.5mA so saturation isn't a problem (same as the intented collector current) .~~
	~~{\| border="1"~~
	~~! Voltage~~
	~~! DC Resistance~~
	~~! Current~~
	\|-		\|-
	\| ~~3.3V~~		\| 1000
	\| ~~1320Ω~~		\| 4000
	\| ~~2.5mA~~		\| 4V
	\|}		\|}

Michael: /* Inrush Current Limiting */

2012-06-21T12:35:02Z

Inrush Current Limiting

← Older revision		Revision as of 12:35, 21 June 2012
Line 159:		Line 159:

	==== Inrush Current Limiting ====		==== Inrush Current Limiting ====
	The low-ESR ceramic input capacitors will act as a short to ground when the device is turned on. A 5Ω power resistor will be used to limit the initial inrush current to a maximum of 1A, dissipating 5W. 5W SMD resistors are very large, so we'll make do with a 2W resistor. Most power resistors are rated for 5x there rated power for a short duration (~ 5seconds). The resistor must be bypassed soon after the circuit turns on allow it to cool down, and to improve efficiency. The disconnection will be done with a P-Channel enhancement mode MOSFET, with the gate ~~connected to the output of the 3.3W switching regulator~~ via a transistor. ~~ie. We'll make use of~~ the ~~built~~-~~in soft-start circuit~~ of ~~the regulator as a time delay for the MOSFET~~.		The low-ESR ceramic input capacitors will act as a short to ground when the device is turned on. A 5Ω power resistor will be used to limit the initial inrush current to a maximum of 1A, dissipating 5W. 5W SMD resistors are very large, so we'll make do with a 2W resistor. Most power resistors are rated for 5x there rated power for a short duration (~ 5seconds). The resistor must be bypassed soon after the circuit turns on allow it to cool down, and to improve efficiency. The disconnection will be done with a P-Channel enhancement mode MOSFET, with the gate triggered via a transistor when the capacitor voltage has risen to 4V. Note that the regulator will switch on above the low-voltage lockout threshold of 2.35V.

	Resistor		Resistor
Line 195:		Line 195:
	\|}		\|}

	The ~~MOSFET~~ will ~~turn on when the capacitor voltage has risen to the gate threshold value~~. Assume we have ~~2 x~~ 47uF ceramic ~~caps~~ as the bulk ~~capacitors~~ with zero charge (<math>V_0</math>). The ESR will be negligible (~ 0.1 Ohm) and will be ignored.		MOSFET Gate pullup resistor (to +5v). The current through this resistor, when grounded, will be collector->emitter current of NPN transistor.
			{\| border="1"
			! Voltage
			! DC Resistance
			! Current
			\|-
			\| 5V
			\| 2kΩ
			\| 2.5mA
			\|}

			Assume we have a single 47uF ceramic cap as the bulk capacitor with zero charge (<math>V_0</math>). The ESR will be negligible (~ 0.1 Ohm) and will be ignored. The time required to rise to 4V will be at least 378us:

	<math> V_c = V_s \left ( 1 - e{\frac{-t}{RC}} \right )</math>		<math> V_c = V_s \left ( 1 - e{\frac{-t}{RC}} \right )</math>
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	<math> \frac{-t}{RC} = ln \left ( 1 - \frac{V_c}{V_s} \right )</math>		<math> \frac{-t}{RC} = ln \left ( 1 - \frac{V_c}{V_s} \right )</math>
	<math> t = -RC * ln \left ( 1 - \frac{V_c}{V_s} \right )</math>		<math> t = -RC * ln \left ( 1 - \frac{V_c}{V_s} \right )</math>
	<math> t = -5 * 0.~~000094~~ * ln \left ( 1 - \frac{~~0.6~~}{5} \right )</math>		<math> t = -5 * 0.000047 * ln \left ( 1 - \frac{4}{5} \right )</math>
	<math> t = ~~60us~~</math>		<math> t = 378us</math>

	At this stage the current being used to charge the caps is low enough for the resistor to be removed.		At this stage the current being used to charge the caps is low enough for the resistor to be removed.
	<math>I = \frac{V_s}{R} e^{\frac{-t}{RC}} </math>		<math>I = \frac{V_s}{R} e^{\frac{-t}{RC}} </math>
	<math>I = \frac{5}{5} e^{\frac{-0.~~000060~~}{5 * 0.~~000094~~}} </math>		<math>I = \frac{5}{5} e^{\frac{-0.000378}{5 * 0.000047}} </math>
	<math>I = 0.~~88A~~</math>		<math>I = 0.2A</math>

	~~hmm, but if we disconnect the resistor, current will shoot up again !!!~~

	~~How about just wait until the output hits 4V ? ie. get a different MOSFET ?~~
	~~Or why don't we just put the resistor in series with the cap, and tap off before the resistor to the regulator. The regulator has it's own soft start anyway.~~

	~~MOSFET Gate pullup resistor (to +5v). The current through this resistor, when grounded, will be collector->emitter current of NPN transistor.~~
	~~{\| border="1"~~
	~~! Voltage~~
	~~! DC Resistance~~
	~~! Current~~

	\|-
	~~\| 5V~~
	~~\| 2kΩ~~
	~~\| 2.5mA~~
	\|}

	Switching NPN Transistor (used to bring the MOSFET gate to ground to turn the MOSFET on).		Switching NPN Transistor (used to bring the MOSFET gate to ground to turn the MOSFET on).

Michael: /* Inrush Current Limiting */

2012-06-16T12:45:38Z

Inrush Current Limiting

← Older revision		Revision as of 12:45, 16 June 2012
Line 213:		Line 213:

	How about just wait until the output hits 4V ? ie. get a different MOSFET ?		How about just wait until the output hits 4V ? ie. get a different MOSFET ?
			Or why don't we just put the resistor in series with the cap, and tap off before the resistor to the regulator. The regulator has it's own soft start anyway.

	MOSFET Gate pullup resistor (to +5v). The current through this resistor, when grounded, will be collector->emitter current of NPN transistor.		MOSFET Gate pullup resistor (to +5v). The current through this resistor, when grounded, will be collector->emitter current of NPN transistor.