SCSI2SD old - Revision history

Michael: Michael moved page SCSI2SD to SCSI2SD old: This page is now for historical reference only, and does not necessarily describe the device as-built.

2013-09-10T12:25:02Z

Michael moved page SCSI2SD to SCSI2SD old: This page is now for historical reference only, and does not necessarily describe the device as-built.

← Older revision		Revision as of 12:25, 10 September 2013
(No difference)

Michael: /* Implementation Detail */

2012-12-13T12:37:02Z

Implementation Detail

← Older revision		Revision as of 12:37, 13 December 2012
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	== Implementation Detail ==		== Implementation Detail ==
	* [[SCSI2SD Schematic Notes]]		* [[SCSI2SD Schematic Notes]]
			* [[First reflow soldering attempt]] (build attempt 1)

	== Links ==		== Links ==

Michael at 12:34, 13 December 2012

2012-12-13T12:34:06Z

@@ Line 47: / Line 47: @@
 === Microcontroller ===
-There are simply too many options here to list them all.  I'll simply go-with-the-flow, and choose an ARM, specifically the LPC1751.  The 5V-safe TTL level inputs eliminate the need for another IC between the SCSI bus and input pins.
+The [http://www.cypress.com/?id=2233 Cypress PSoc5] will be usedd for its flexibility in routing I/O pins, standard ARM core, and the possibility to use programmable logic to speed-up some interface interactions.
 === SCSI PHY ===
@@ Line 139: / Line 77: @@
 | 2V to 5.25V
 |}
-The microcontroller must provide TTL compatible, 5V safe GPIO inputs. ''Note: In practice, the SCSI terminators should keep each line at a safe 3.3V (passive) or 2.85V (active).''
+Multiple output buffer IC's will be used to overcome sinking current limitations.  Each IC has a limit on the overall current output by the ground pin; using multiple buffers instead of 16bit/octal buffers helps to overcome this limitation.
 == Implementation Detail ==

Michael: /* Parts Required */

2012-03-06T07:16:47Z

Parts Required

← Older revision		Revision as of 07:16, 6 March 2012
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	== Parts Required ==		== Parts Required ==
	* ~~NXP~~ [http://~~ics~~.~~nxp~~.com/~~products~~/~~lpc1000~~/~~datasheet~~/~~lpc1751.lpc1752.lpc1754.lpc1756.lpc1758.lpc1759.pdf LPC1751~~]		* Maxim [http://www.maxim-ic.com/datasheet/index.mvp/id/3649 MAX1951]
	* [http://www.ti.com/product/ucc5617?qgpn=ucc5617 UCC5617] Active SCSI Terminator.		* [http://www.ti.com/product/ucc5617?qgpn=ucc5617 UCC5617] Active SCSI Terminator.
	* 3 [http://www.fairchildsemi.com/pf/MM/MM74HCT05.html 74HCT05] Hex Inverter with open-drain outputs		* 3 [http://www.fairchildsemi.com/pf/MM/MM74HCT05.html 74HCT05] Hex Inverter with open-drain outputs

Michael: /* Requirements */

2012-02-29T04:16:21Z

Requirements

← Older revision		Revision as of 04:16, 29 February 2012
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	** Note that this drive is SCSI-2, single-ended, <strong>active</strong> termination.		** Note that this drive is SCSI-2, single-ended, <strong>active</strong> termination.
	* The device shall optionally provide active termination, enabled and disabled via a jumper.		* The device shall optionally provide active termination, enabled and disabled via a jumper.
	* The device shall ~~optionally~~ provide termination power~~, enabled and disabled via a jumper~~.		* The device shall provide termination power.
	** Some Macs don't provide termination power. See [http://docs.info.apple.com/article.html?artnum=6159]		** Some Macs don't provide termination power. See [http://docs.info.apple.com/article.html?artnum=6159]
	** This ~~requirement will not be met in V1.0~~.		** This enables "loopback" testing of the device without connecting to a SCSI bus.
	* The device shall optionally check parity, enabled and disabled via a jumper.		* The device shall optionally check parity, enabled and disabled via a jumper.
	** Some Amiga SCSI controllers don't provide parity.		** Some Amiga SCSI controllers don't provide parity.

Michael: /* Requirements */

2011-12-27T03:32:45Z

Requirements

← Older revision		Revision as of 03:32, 27 December 2011
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	* The device shall optionally provide termination power, enabled and disabled via a jumper.		* The device shall optionally provide termination power, enabled and disabled via a jumper.
	** Some Macs don't provide termination power. See [http://docs.info.apple.com/article.html?artnum=6159]		** Some Macs don't provide termination power. See [http://docs.info.apple.com/article.html?artnum=6159]
			** This requirement will not be met in V1.0.
	* The device shall optionally check parity, enabled and disabled via a jumper.		* The device shall optionally check parity, enabled and disabled via a jumper.
	** Some Amiga SCSI controllers don't provide parity.		** Some Amiga SCSI controllers don't provide parity.

Michael at 11:03, 7 October 2011

2011-10-07T11:03:22Z

← Older revision		Revision as of 11:03, 7 October 2011
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	A device that presents a ~~USB Mass Storage device~~ as a Direct Access device to a SCSI controller.		A device that presents a an SD Card as a Direct Access device to a SCSI controller.

Michael at 03:49, 7 October 2011

2011-10-07T03:49:29Z

← Older revision		Revision as of 03:49, 7 October 2011
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	* SD card socket		* SD card socket

			== Implementation Detail ==
			* [[SCSI2SD Schematic Notes]]

	== Links ==		== Links ==

Michael: /* Storage */

2011-10-03T09:57:41Z

Storage

← Older revision		Revision as of 09:57, 3 October 2011
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	# SATA/SAS is way too fast for a cheap microcontroller.		# SATA/SAS is way too fast for a cheap microcontroller.
	# Accessing remote storage over ethernet is an interesting idea, but I prefer a standalone solution for this project.		# Accessing remote storage over ethernet is an interesting idea, but I prefer a standalone solution for this project.
	~~- SD card.~~
	~~// SDcard SPI @ 25MHz = 25Mbit/sec. 4bit mode with same 25MHz clock is 100Mbit/sec. // From wikipedia, "Hi speed" mode is 50MHz "and supported by most cards". This is 6.25MB/sec. ok.~~

	=== Microcontroller ===		=== Microcontroller ===

Michael at 09:57, 3 October 2011

2011-10-03T09:57:22Z

← Older revision		Revision as of 09:57, 3 October 2011
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	== Design Choices ==		== Design Choices ==
	=== Storage ===		=== Storage ===
			An SD card will be used as the storage device.

			# A common class 4 or above SD card meets the throughput requirements.
			## "Hi speed" 50MHz SPI mode supports 6.25MB/sec.
			## 25MHz 4-bit mode supports 12.5MB/sec. Some microcontrollers have hardware support for this mode.
			# Trivial to interface with a micro over SPI.
			# Compact

			To achieve the required throughput, some hardware support within the microcontroller is required. For SPI, the micro should provide DMA support for SPI transfers. For the 4-bit mode, the micro must support the required compute-intensive CRC calculations and also provide DMA support.

			Alternative options:
			# Nand flash would need custom load leveling code, significantly increasing code complexity. SD cards handle load leveling internally.
			# An IDE interface would allow the use of compact flash. SD cards are cheaper and easier to communicate with.
			# SATA/SAS is way too fast for a cheap microcontroller.
			# Accessing remote storage over ethernet is an interesting idea, but I prefer a standalone solution for this project.
	- SD card.		- SD card.
	// SDcard SPI @ 25MHz = 25Mbit/sec. 4bit mode with same 25MHz clock is 100Mbit/sec. ~~http://www.freelabs.com/~whitis/sd_card/~~		// SDcard SPI @ 25MHz = 25Mbit/sec. 4bit mode with same 25MHz clock is 100Mbit/sec. // From wikipedia, "Hi speed" mode is 50MHz "and supported by most cards". This is 6.25MB/sec. ok.
	// From wikipedia, "Hi speed" mode is 50MHz "and supported by most cards". This is 6.25MB/sec. ok.
	~~// Other options:~~
	~~// nand flash. Writing the load levelling code increases complexity. SD cards do this internally.~~
	~~// IDE: allow compact-flash ? SD cards are cheaper.~~
	~~// SATA: Too fast - too difficult to interface to a microcontroller.~~
	~~// Ethernet: Interesting, but prefer a stand-alone solution~~.

	=== Microcontroller ===		=== Microcontroller ===
	There are simply too many options here to list them all. I'll simply go-with-the-flow, and choose an ARM. ~~I'm sure there would be equivalent microprocessors from~~ the ~~Coldfire~~ and ~~other families~~.		There are simply too many options here to list them all. I'll simply go-with-the-flow, and choose an ARM, specifically the LPC1751. The 5V-safe TTL level inputs eliminate the need for another IC between the SCSI bus and input pins.

	{\| border="1"		{\| border="1"
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	\|}		\|}

	The microcontroller must provide TTL compatible, 5V safe GPIO inputs.		The microcontroller must provide TTL compatible, 5V safe GPIO inputs. ''Note: In practice, the SCSI terminators should keep each line at a safe 3.3V (passive) or 2.85V (active).''

	Two GPIO pins are required per SCSI signal. One will be connected to an external open-collector output that can handle the required sinking current. The other will be an input pin, tied to the output of the open collector output. The microcontroller must provide at least 36 GPIO's, not including those required to drive the SD card.		Two GPIO pins are required per SCSI signal. One will be connected to an external open-collector output that can handle the required sinking current. The other will be an input pin, tied to the output of the open collector output. The microcontroller must provide at least 36 GPIO's, not including those required to drive the SD card.
			''Alternate solution requiring additional parts: A non-inverting buffer would be used instead, and the output of the buffer would be looped back into the same microcontroller pin via a current-limiting resistor (possibly in a voltage-divider arrangement if using non-5V safe micro). The line between the microcontroller pin and output buffer would be kept high (either by internal pullups, or external pullup) when the pin is in input mode.''

	Multiple output buffer IC's will be used to overcome sinking current limitations. Each IC has a limit on the overall current output by the ground pin; using multiple buffers instead of 16bit/octal buffers helps to overcome this limitation. Using an inverting buffer allows us to avoid the overhead negating every byte in the microcontroller before sending it over the SCSI interface. 3 [http://www.fairchildsemi.com/pf/MM/MM74HCT05.html 74HCT05 Hex Inverter with open-drain outputs] will be used. These allow for 50mA sinking current per pin, provide 3.3V compatible inputs, and are readily available.		Multiple output buffer IC's will be used to overcome sinking current limitations. Each IC has a limit on the overall current output by the ground pin; using multiple buffers instead of 16bit/octal buffers helps to overcome this limitation. Using an inverting buffer allows us to avoid the overhead negating every byte in the microcontroller before sending it over the SCSI interface. 3 [http://www.fairchildsemi.com/pf/MM/MM74HCT05.html 74HCT05 Hex Inverter with open-drain outputs] will be used. These allow for 50mA sinking current per pin, provide 3.3V compatible inputs, and are readily available.

	== Parts Required ==		== Parts Required ==
			* NXP [http://ics.nxp.com/products/lpc1000/datasheet/lpc1751.lpc1752.lpc1754.lpc1756.lpc1758.lpc1759.pdf LPC1751]
	* [http://www.ti.com/product/ucc5617?qgpn=ucc5617 UCC5617] Active SCSI Terminator.		* [http://www.ti.com/product/ucc5617?qgpn=ucc5617 UCC5617] Active SCSI Terminator.
	* 3 [http://www.fairchildsemi.com/pf/MM/MM74HCT05.html 74HCT05] Hex Inverter with open-drain outputs		* 3 [http://www.fairchildsemi.com/pf/MM/MM74HCT05.html 74HCT05] Hex Inverter with open-drain outputs
	* 50 pin IDC header		* 50 pin IDC header
	* 5V supply via Molex drive connector		* 5V supply via Molex drive connector
			* SD card socket