SCSI2SD Schematic Notes: Difference between revisions
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Details for the circuit design of [[SCSI2SD]]. | Details for the circuit design of [[SCSI2SD]]. | ||
== | == Changes between V1 and V2 == | ||
The [[First_reflow_soldering_attempt]] was a failure. As a result, the schematic is being improved to simplify construction. | |||
=== Change of microcontroller footprint === | |||
The V1 incorrectly made use of a 10x10mm QFN68 0.5mm pitch footprint for the [http://www.cypress.com/?id=2326 CY8C53] microcontroller, instead of the smaller 8x8mm QFN68. 8x8mm is seriously tiny, with a pitch of only 0.4mm. The TSSOP packages (0.635mm pitch) on the V1 boards had many solder bridges etc, and moving to an even finer pitch device would be well beyond my soldering ability. | |||
The solution is to make use of the 100-pin TQFP versions of the microcontroller instead. The devices use a 0.5mm pitch, 25% larger than the QFN68 devices, and the same as the (incorrect) footprint on the V1 board. | |||
== | === Change of PHY === | ||
The V1 schematic made use of a typical bus arrangement to interface to the SCSI wires. SCSI signals were split into read and write paths, with the microcontroller using a signal to switch the bus between read or write mode. This arrangement uses minimal microcontroller pins (18 SCSI pins + 1 R/W signal), but additional interface IC's. | |||
The V2 schematic will switch back to a much simpler arrangement whereby each SCSI signal is connected to the microcontroller twice - once for read, and another for write (via an inverting buffer). This arrangement is possible due to the additional I/Os available with the 100-pin QFP version of the microcontroller, and saves the cost/board space/soldering of 6 additional ICs. The PSoC5 supports configurable CMOS or LVTTL (SCSI-compatible) signal levels on all GPIO pins. | |||
== Removal of the switching regulator == | |||
Since the change of PHY has reduced the need for 3.3V power, it is now feasible to run the SD Card from a much simpler (cheaper) LDO linear regulator. | |||
The CY8C53 micro will use the 5V supply instead (internally regulated to 1.8V anyway). Running at 5V is necessary for the PHY design of directly connecting the input SCSI signals. This micro allows some I/O pins to run at a lower voltage for interfacing directly to the SD card at 3.3V. | |||
=== | === Use of a solder stencil === | ||
The 0.5mm pitch of the microcontroller will require the use of a stencil to limit the amount of solder paste applied. I applied way too much paste to the 0.635mm pitch devices on the V1 boards, and this caused many solder bridges. | |||
The 0.5mm pitch will require a laser-cut stencil. | |||
# Laser-cut 3mil mylar (plastic) stencils available from [http://www.pololu.com/catalog/product/446 pololu] for $25. Non-framed. | |||
# Laser-cut 3.5mil kapton (plastic) stencils available from [http://ohararp.com/Stencils.html ohararp] for $25. Non-framed. | |||
== | == Board specifications == | ||
# 0805 sized components will be used where applicable. These represent a good tradeoff between hand-solderability and PCB board space. | |||
# Pin pitch will be 0.5mm or (preferably) larger. | |||
==== | == Power Supply == | ||
Everything except the SD Card and terminator will make use of the 5V supplied over the molex connector. | |||
The SCSI terminator will use a 2.85 fixed-voltage verson of the LD1117 (LT1117) LDO Regulator. The datasheet provides examples of use for SCSI termination. | |||
The SD Card (approv 200mA max) will be serviced by a fixed 3.3V version of the same LD1117 LDO regulator. | |||
== Switches == | == Switches == | ||
* Parity and SCSI ID will be set via a set of DIP switches to ground. | |||
* The micro GPIO port pull-ups will be enabled (this is the default anyway). | |||
* Parity requires 1 bit, SCSI ID requires 3 bits, SCSI Terminator DISCNT requires 1 bit. (5-way DIP switch required) | |||
Latest revision as of 02:27, 1 June 2013
Details for the circuit design of SCSI2SD.
Changes between V1 and V2
The First_reflow_soldering_attempt was a failure. As a result, the schematic is being improved to simplify construction.
Change of microcontroller footprint
The V1 incorrectly made use of a 10x10mm QFN68 0.5mm pitch footprint for the CY8C53 microcontroller, instead of the smaller 8x8mm QFN68. 8x8mm is seriously tiny, with a pitch of only 0.4mm. The TSSOP packages (0.635mm pitch) on the V1 boards had many solder bridges etc, and moving to an even finer pitch device would be well beyond my soldering ability.
The solution is to make use of the 100-pin TQFP versions of the microcontroller instead. The devices use a 0.5mm pitch, 25% larger than the QFN68 devices, and the same as the (incorrect) footprint on the V1 board.
Change of PHY
The V1 schematic made use of a typical bus arrangement to interface to the SCSI wires. SCSI signals were split into read and write paths, with the microcontroller using a signal to switch the bus between read or write mode. This arrangement uses minimal microcontroller pins (18 SCSI pins + 1 R/W signal), but additional interface IC's.
The V2 schematic will switch back to a much simpler arrangement whereby each SCSI signal is connected to the microcontroller twice - once for read, and another for write (via an inverting buffer). This arrangement is possible due to the additional I/Os available with the 100-pin QFP version of the microcontroller, and saves the cost/board space/soldering of 6 additional ICs. The PSoC5 supports configurable CMOS or LVTTL (SCSI-compatible) signal levels on all GPIO pins.
Removal of the switching regulator
Since the change of PHY has reduced the need for 3.3V power, it is now feasible to run the SD Card from a much simpler (cheaper) LDO linear regulator.
The CY8C53 micro will use the 5V supply instead (internally regulated to 1.8V anyway). Running at 5V is necessary for the PHY design of directly connecting the input SCSI signals. This micro allows some I/O pins to run at a lower voltage for interfacing directly to the SD card at 3.3V.
Use of a solder stencil
The 0.5mm pitch of the microcontroller will require the use of a stencil to limit the amount of solder paste applied. I applied way too much paste to the 0.635mm pitch devices on the V1 boards, and this caused many solder bridges.
The 0.5mm pitch will require a laser-cut stencil.
- Laser-cut 3mil mylar (plastic) stencils available from pololu for $25. Non-framed.
- Laser-cut 3.5mil kapton (plastic) stencils available from ohararp for $25. Non-framed.
Board specifications
- 0805 sized components will be used where applicable. These represent a good tradeoff between hand-solderability and PCB board space.
- Pin pitch will be 0.5mm or (preferably) larger.
Power Supply
Everything except the SD Card and terminator will make use of the 5V supplied over the molex connector.
The SCSI terminator will use a 2.85 fixed-voltage verson of the LD1117 (LT1117) LDO Regulator. The datasheet provides examples of use for SCSI termination.
The SD Card (approv 200mA max) will be serviced by a fixed 3.3V version of the same LD1117 LDO regulator.
Switches
- Parity and SCSI ID will be set via a set of DIP switches to ground.
- The micro GPIO port pull-ups will be enabled (this is the default anyway).
- Parity requires 1 bit, SCSI ID requires 3 bits, SCSI Terminator DISCNT requires 1 bit. (5-way DIP switch required)
