SCSI2SD Schematic Notes: Difference between revisions

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Details for the circuit design of [[SCSI2SD]].
Details for the circuit design of [[SCSI2SD]].


== SMT Type ==
== Changes between V1 and V2 ==
# 0805 sized components will be used where applicable.  These represent a good tradeoff between hand-solderability and PCB board space.
The [[First_reflow_soldering_attempt]] was a failure.  As a result, the schematic is being improved to simplify construction.


== Crystal Oscillator ==
=== Change of microcontroller footprint ===
* LCP1751 requires a 25MHz crystal, which results in a 100MHz clock with x4 PLL
The V1 incorrectly made use of a 10x10mm QFN68 0.5mm pitch footprint for the [http://www.cypress.com/?id=2326 CY8C53] microcontroller, instead of the smaller 8x8mm QFN68. 8x8mm is seriously tiny, with a pitch of only 0.4mm. The TSSOP packages (0.635mm pitch) on the V1 boards had many solder bridges etc, and moving to an even finer pitch device would be well beyond my soldering ability.
* The crystal requires 2 caps for stability. The required value is:
2 * (CL - CS)


Where CL is the crystal's load capacitance, as specified by the crystal manufacturer, and CS is the PCB's stray capacitance (around 5pF for a reasonable PCB).
The solution is to make use of the 100-pin TQFP versions of the microcontroller instead.  The devices use a 0.5mm pitch, 25% larger than the QFN68 devices, and the same as the (incorrect) footprint on the V1 board.


[http://au.element14.com/txc/9c-25-000meej-t/quartz-crystal-25-mhz-18-pf-hc/dp/1842314 TXC - 9C-25.000MEEJ-T] Load capacitance 18pF. Therefore, use 2x 22pF standard ceramic capacitors.
=== Change of PHY ===
The V1 schematic made use of a typical bus arrangement to interface to the SCSI wires.   SCSI signals were split into read and write paths, with the microcontroller using a signal to switch the bus between read or write mode. This arrangement uses minimal microcontroller pins (18 SCSI pins + 1 R/W signal), but additional interface IC's.


== Power Supply ==
The V2 schematic will switch back to a much simpler arrangement whereby each SCSI signal is connected to the microcontroller twice - once for read, and another for write (via an inverting buffer).  This arrangement is possible due to the additional I/Os available with the 100-pin QFP version of the microcontroller, and saves the cost/board space/soldering of 6 additional ICs.  The PSoC5 supports configurable CMOS or LVTTL (SCSI-compatible) signal levels on all GPIO pins.


=== Power Requirements ===
== Removal of the switching regulator ==
{| border="1"
Since the change of PHY has reduced the need for 3.3V power, it is now feasible to run the SD Card from a much simpler (cheaper) LDO linear regulator.
!
!3.3V
!5V
|-
|LPC1751
|200mA
42mA excl. peripherals.<br />
See IDD(REG)(3V3), Table 6, LPC1751 datasheet.
|(160mA @ 80% efficiency)
|-
|SD Card
|200mA
Peak value from [http://www.embeddedrelated.com/groups/msp430/show/14851.php]
|(160mA @ 80% efficiency)
|-
|UCC5617
|N/A
|440mA
4V - 5.25V
|-
|74HCT05
| N/A
| 150mA (50mA * 3)
4.5V - 5.5V
|-
|'''Total'''
|'''400mA'''
|'''910mA'''
|}


5V supply from a hard drive molex connector should provide more than sufficient current.  The 3.3v supply will be regulated from the 5v supply to share input capacitance and therefore reduce complexity (since each set of input filter caps will need a resistor+disconnect circuit to decrease inrush current).
The CY8C53 micro will use the 5V supply instead (internally regulated to 1.8V anyway).  Running at 5V is necessary for the PHY design of directly connecting the input SCSI signals.  This micro allows some I/O pins to run at a lower voltage for interfacing directly to the SD card at 3.3V.


==== Preferred Option: Switching Regulator ====
=== Use of a solder stencil ===
* Require at least 83% duty cycle, to allow operation down to Vin = 4v.
The 0.5mm pitch of the microcontroller will require the use of a stencil to limit the amount of solder paste applied. I applied way too much paste to the 0.635mm pitch devices on the V1 boards, and this caused many solder bridges.
* Require >= 90% efficiency to reduce heat.
* > 500mA output.
* Fsw >= 1MHz for small output filtering capacitance.


The 0.5mm pitch will require a laser-cut stencil.
# Laser-cut 3mil mylar (plastic) stencils available from [http://www.pololu.com/catalog/product/446 pololu] for $25. Non-framed.
# Laser-cut 3.5mil kapton (plastic) stencils available from [http://ohararp.com/Stencils.html ohararp] for $25. Non-framed.


* [http://www.onsemi.com/PowerSolutions/product.do?id=NCP3170 NCP3170B]
== Board specifications ==
* Over 90% efficiency with 5V input.
# 0805 sized components will be used where applicable. These represent a good tradeoff between hand-solderability and PCB board space.
* [http://au.element14.com/on-semiconductor/ncp3170adr2g/buck-3a-8soic/dp/1924872?Ntt=NCP3170 CHEAP] $1.73
# Pin pitch will be 0.5mm or (preferably) larger.
* * Max load current without a heatsink is [http://www.codesrc.com/utilities/thermal-resistance.php?Tamb=70&Tj=150&r_jc=1&r_b=0&r_ha=87&efficiency=90&voltage=3.3&switching 2.75A]


The NCP3170 supports operation down to 4.5v. This is not quite low enough to enable stable operation from the 5v power supply rail, considering the intended use of the device with vintage systems with poor power supplies.  A low +5v rail, combined with transient voltage drops, will cause the NCP3170 to run out of spec.  The selected duty ratio must be in the range of 8-92%.
== Power Supply ==
 
Everything except the SD Card and terminator will make use of the 5V supplied over the molex connector.
Duty Ratio <math>D = \frac{3.3v}{12v}=27.5%</math>.
 
We will take 400mA as the expected load; in truth, it is likely to be much less. Derating to provide a safety margin will be done as a last step in chosing components - this derating should allow a higher load without any problems.
 
Ceramic capacitors will be used for output filtering.  Modern multilayer SMD ceramic caps are available in the required values (47uF and above), and provide superior [http://en.wikipedia.org/wiki/Equivalent_series_resistance ESR] to electrolytic and tantalum caps.  The low ESR allows a higher ripple current.
 
The NCP3170 advises a ripple current between 10%-40%. We'll use the upper range value to allow a smaller inductor..
 
  <math>ra = 20% = \frac{\vartriangle I}{I_{out}}</math>
  <math>{\vartriangle I} = 40% \times 400mA = 160mA</math> ripple current through the inductor
 
===== Inductor Selection =====
<math>L_{out} = \frac{V_{out}}{I_{out} \times ra \times F_{sw}} \times (1-D)</math>
<math>L_{out} = \frac{3.3}{0.4 \times 0.40 \times 1000000} \times (1-0.275) = 15uH</math>
 
The inductor is specified for the NCP3170'''B''' version, which switches at <math>F_{sw}=1MHz</math> (the 'A' version switches at 500kHz, and requires a much larger inductor).
 
Inductor RMS current = <math>I_{out} \sqrt{1+\frac{ra^2}{V_{in}}} = 0.4 \times \sqrt{1+\frac{0.4^2}{12}} = 403mA</math>
Inductor peak current = <math>I_{out} \left ( 1+\frac{ra}{2} \right ) = 0.4 \times \left ( 1 + \frac{0.4}{2} \right ) = 480mA</math>
 
TODO: Select inductor
TODO calculator power loss through inductor - Irms^2 * dc resistance.
* TODO link to excel worksheet
** and supply FILLED OUT spreadsheet -values- here.
** Link to specific chosen inductor.
* Link to the appnote on choosing caps.
* Input inductor filter - need more bulk capacitance then.
** Looks to be a good idea.
** May do some inrush current protecting as well
* Inrush current: XA. does it need limiting ? See spreadsheet. NOTE: HIGHER ESR INPUT caps = LOWER INRUSH CURRENT!
** Perhaps do soft-start as well
* Input filtering
** ripple RMS / frequency
** voltage
** esr requirements
** bulk capacitance needed ?
* Output filtering
** Same as input
 
==== Backup Option: Linear Regulator ====
 
A [http://www.national.com/mpf/LM/LMS1585A.html LMS1585A] linear LDO regulator can be used to convert the 5v supply to the required 3.3v.
* 5A max current is more than enough
* Easy TO-220 mounting
* 1.3V dropout @ 3A allows for 5V supply to drop to 4.6V
* Significantly cheaper than a switching regulator
* Simpler than a switching regulator.
* At an expected peak current of 800mA, the regulator will dissipate: (5-3.3)*0.8 = 1.36W
* Thermal Resistance Junction-to-Case: 2.3C/W
* Max load current without a heatsink is insufficient at [http://www.codesrc.com/utilities/thermal-resistance.php?Tamb=70&Tj=150&r_jc=2.3&r_b=0&r_ha=65&efficiency=66&voltage=3.3 0.7A]
 
== In-circuit programming ==
The LPC17xx micro will be programmed via JTAG using [http://openocd.sourceforge.net/doc/html/Flash-Commands.html Open OCD].
 
The standard ARM 0.1" 20-pin JTAG header will be used (see http://www.keil.com/support/man/docs/ulink2/ulink2_hw_connectors.htm for connector and necessary pull-up/pull-down details).


Serial programming of the LPC1751 is performed via the UART0 TX and RX pins. To enter programming mode, <span style="text-decoration: overline">P2.10</span> must be low on <span style="text-decoration: overline">RESET</span>.  The active-low <span style="text-decoration: overline">P2.10</span> and <span style="text-decoration: overline">RESET</span> lines will be pulled up to +3.3V via a 10kΩ resistor to ensure the micro isn't reset.
The SCSI terminator will use a 2.85 fixed-voltage verson of the LD1117 (LT1117) LDO Regulator. The datasheet provides examples of use for SCSI termination.


== Termination ==
The SD Card (approv 200mA max) will be serviced by a fixed 3.3V version of the same LD1117 LDO regulator.
* The [http://www.ti.com/product/ucc5617?qgpn=ucc5617 ucc5617] will be powered by +5v, not TERMPWR. This enables testing the device without connecting to a live SCSI bus.  The PHY essentially connects the outputs back to the inputs, but we still need the terminator powered to provide pullups.
* A DIP Switch will be used to connect the DISCNCT pin of the [http://www.ti.com/product/ucc5617?qgpn=ucc5617 ucc5617] to ground if the user wants to disable termination. The pin will be pulled-up to +5V via a 10k resistor.


== Switches ==
== Switches ==

Latest revision as of 02:27, 1 June 2013

Details for the circuit design of SCSI2SD.

Changes between V1 and V2

The First_reflow_soldering_attempt was a failure. As a result, the schematic is being improved to simplify construction.

Change of microcontroller footprint

The V1 incorrectly made use of a 10x10mm QFN68 0.5mm pitch footprint for the CY8C53 microcontroller, instead of the smaller 8x8mm QFN68. 8x8mm is seriously tiny, with a pitch of only 0.4mm. The TSSOP packages (0.635mm pitch) on the V1 boards had many solder bridges etc, and moving to an even finer pitch device would be well beyond my soldering ability.

The solution is to make use of the 100-pin TQFP versions of the microcontroller instead. The devices use a 0.5mm pitch, 25% larger than the QFN68 devices, and the same as the (incorrect) footprint on the V1 board.

Change of PHY

The V1 schematic made use of a typical bus arrangement to interface to the SCSI wires. SCSI signals were split into read and write paths, with the microcontroller using a signal to switch the bus between read or write mode. This arrangement uses minimal microcontroller pins (18 SCSI pins + 1 R/W signal), but additional interface IC's.

The V2 schematic will switch back to a much simpler arrangement whereby each SCSI signal is connected to the microcontroller twice - once for read, and another for write (via an inverting buffer). This arrangement is possible due to the additional I/Os available with the 100-pin QFP version of the microcontroller, and saves the cost/board space/soldering of 6 additional ICs. The PSoC5 supports configurable CMOS or LVTTL (SCSI-compatible) signal levels on all GPIO pins.

Removal of the switching regulator

Since the change of PHY has reduced the need for 3.3V power, it is now feasible to run the SD Card from a much simpler (cheaper) LDO linear regulator.

The CY8C53 micro will use the 5V supply instead (internally regulated to 1.8V anyway). Running at 5V is necessary for the PHY design of directly connecting the input SCSI signals. This micro allows some I/O pins to run at a lower voltage for interfacing directly to the SD card at 3.3V.

Use of a solder stencil

The 0.5mm pitch of the microcontroller will require the use of a stencil to limit the amount of solder paste applied. I applied way too much paste to the 0.635mm pitch devices on the V1 boards, and this caused many solder bridges.

The 0.5mm pitch will require a laser-cut stencil.

  1. Laser-cut 3mil mylar (plastic) stencils available from pololu for $25. Non-framed.
  2. Laser-cut 3.5mil kapton (plastic) stencils available from ohararp for $25. Non-framed.

Board specifications

  1. 0805 sized components will be used where applicable. These represent a good tradeoff between hand-solderability and PCB board space.
  2. Pin pitch will be 0.5mm or (preferably) larger.

Power Supply

Everything except the SD Card and terminator will make use of the 5V supplied over the molex connector.

The SCSI terminator will use a 2.85 fixed-voltage verson of the LD1117 (LT1117) LDO Regulator. The datasheet provides examples of use for SCSI termination.

The SD Card (approv 200mA max) will be serviced by a fixed 3.3V version of the same LD1117 LDO regulator.

Switches

  • Parity and SCSI ID will be set via a set of DIP switches to ground.
  • The micro GPIO port pull-ups will be enabled (this is the default anyway).
  • Parity requires 1 bit, SCSI ID requires 3 bits, SCSI Terminator DISCNT requires 1 bit. (5-way DIP switch required)
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