SCSI2SD Schematic Notes: Difference between revisions

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(Updates for V2)
Line 1: Line 1:
Details for the circuit design of [[SCSI2SD]].
Details for the circuit design of [[SCSI2SD]].


== SMT Type ==
== Changes between V1 and V2 ==
# 0805 sized components will be used where applicableThese represent a good tradeoff between hand-solderability and PCB board space.
The [[First_reflow_soldering_attempt]] was a failure.  As a result, the schematic is being improved to simplify construction.
 
=== Change of microcontroller footprint ===
The V1 incorrectly made use of a 10x10mm QFN68 0.5mm pitch footprint for the [http://www.cypress.com/?id=2326 CY8C53] microcontroller, instead of the smaller 8x8mm QFN68. 8x8mm is seriously tiny, with a pitch of only 0.4mm.  The TSSOP packages (0.635mm pitch) on the V1 boards had many solder bridges etc, and moving to an even finer pitch device would be well beyond my soldering ability.
 
The solution is to make use of the 100-pin TQFP versions of the microcontroller insteadThe devices use a 0.5mm pitch, 25% larger than the QFN68 devices, and the same as the (incorrect) footprint on the V1 board.
 
=== Change of PHY ===
The V1 schematic made use of a typical bus arrangement to interface to the SCSI wires.  SCSI signals were split into read and write paths, with the microcontroller using a signal to switch the bus between read or write mode.  This arrangement uses minimal microcontroller pins (18 SCSI pins + 1 R/W signal), but additional interface IC's.
 
The V2 schematic will switch back to a much simpler arrangement whereby each SCSI signal is connected to the microcontroller twice - once for read, and another for write (via an inverting buffer).  This arrangement is possible due to the additional I/Os available with the 100-pin QFP version of the microcontroller, and saves the cost/board space/soldering of 6 additional ICs.
 
=== Use of a solder stencil ===
The 0.5mm pitch of the microcontroller will require the use of a stencil to limit the amount of solder paste applied.  I applied way too much paste to the 0.635mm pitch devices on the V1 boards, and this caused many solder bridges.


== Crystal Oscillator ==
The 0.5mm pitch will require a laser-cut stencil.
* LCP1751 requires a 25MHz crystal, which results in a 100MHz clock with x4 PLL
# Laser-cut 3mil mylar (plastic) stencils available from [http://www.pololu.com/catalog/product/446 pololu] for $25. Non-framed.
* The crystal requires 2 caps for stability. The required value is:
# Laser-cut 3.5mil kapton (plastic) stencils available from [http://ohararp.com/Stencils.html ohararp] for $25. Non-framed.
2 * (CL - CS)


Where CL is the crystal's load capacitance, as specified by the crystal manufacturer, and CS is the PCB's stray capacitance (around 5pF for a reasonable PCB).


[http://au.element14.com/txc/9c-25-000meej-t/quartz-crystal-25-mhz-18-pf-hc/dp/1842314 TXC - 9C-25.000MEEJ-T] Load capacitance 18pF. Therefore, use 2x 22pF standard ceramic capacitors.
== Board specifications ==
# 0805 sized components will be used where applicable. These represent a good tradeoff between hand-solderability and PCB board space.
# Pin pitch will be 0.5mm or (preferably) larger.


== Power Supply ==
== Power Supply ==
Line 19: Line 32:
!
!
!3.3V
!3.3V
!5V
|-
|-
|LPC1751
|CY8C53
|200mA
|200mA
42mA excl. peripherals.<br />
rough estimate
See IDD(REG)(3V3), Table 6, LPC1751 datasheet.
|(160mA @ 80% efficiency)
|-
|-
|SD Card
|SD Card
|200mA
|200mA
Peak value from [http://www.embeddedrelated.com/groups/msp430/show/14851.php]
Peak value from [http://www.embeddedrelated.com/groups/msp430/show/14851.php]
|(160mA @ 80% efficiency)
|-
|-
|UCC5617
|Termination
|N/A
|466mA
|440mA
18 * (2.85V / 110ohms)
4V - 5.25V
|-
|74HCT05
| N/A
| 150mA (50mA * 3)
4.5V - 5.5V
|-
|-
|'''Total'''
|'''Total'''
|'''400mA'''
|'''866mA'''
|'''910mA'''
|}
|}


5V supply from a hard drive molex connector should provide more than sufficient current.  The 3.3v supply will be regulated from the 5v supply to share input capacitance and therefore reduce complexity (since each set of input filter caps will need a resistor+disconnect circuit to decrease inrush current).
5V supply from a hard drive molex connector should provide more than sufficient current.  The 3.3v supply will be regulated from the 5v supply to share input capacitance and therefore reduce complexity.


=== Switching Regulator Requirements ===
=== Switching Regulator Requirements ===
* Require at least 83% duty cycle, to allow operation down to Vin = 4v.
* Require at least 83% duty cycle, to allow operation down to Vin = 4v.
* Require >= 90% efficiency to reduce heat.
* Require >= 90% efficiency to reduce heat.
* > 500mA output.
* > 866mA output.
* Fsw >= 1MHz for small output filtering capacitance.
* Fsw >= 1MHz for small output filtering capacitance.
* Easy hand-soldering.
* Easy hand-soldering.
Line 158: Line 160:
|}
|}


==== Inrush Current Limiting ====
The low-ESR ceramic input capacitors will act as a short to ground when the device is turned on.  A 5Ω power resistor will be used to limit the initial inrush current to a maximum of 1A, dissipating 5W.  5W SMD resistors are very large, so we'll make do with a 2W resistor. Most power resistors are rated for 5x there rated power for a short duration (~ 5seconds).  The resistor must be bypassed soon after the circuit turns on allow it to cool down, and to improve efficiency. The disconnection will be done with a P-Channel enhancement mode MOSFET, with the gate triggered via a voltage comparitor when the capacitor voltage rises to 4/5 of the input. Note that the regulator will switch on above the low-voltage lockout threshold of 2.35V.
Resistor
{| border="1"
! DC Resistance
! Power Rating
! Peak Power
! Current Limit
! Part
|-
| 5.0Ω
| 2W
| 10W for 5 seconds
| 1A (5V)
| [http://search.digikey.com/au/en/products/PWR4318W5R00JE/PWR4318W5R00JECT-ND/2022991 PWR4318W5R00JE] Bourns PWR4318 series
|}
Bypass MOSFET
{| border="1"
! Threshold voltage (min)
! On Resistance (Vgs = -4.5V)
! On Resistance (Vgs = -2.5V)
! Continuous Drain Current
! Power Rating
! Power disapation @ 1A drain
! Part
|-
| -0.6V
| 40mΩ
| 70mΩ
| 4.6A
| 1.25W
| 40mW
| [http://search.digikey.com/au/en/products/DMP2066LDM-7/DMP2066LDMDICT-ND/1964762 Diodes Inc. DMP2066LDM-7]
|}
MOSFET Gate pullup resistor (to +5v). The current through this resistor, when grounded, will be sent to ground through the comparitor.
{| border="1"
! Voltage
! DC Resistance
! Current
|-
| 5V
| 10kΩ
| 0.5mA
|}
Assume we have a single 47uF ceramic cap as the bulk capacitor with zero charge (<math>V_0</math>).  The ESR will be negligible (~ 0.1 Ohm) and will be ignored.  The time required to rise to 4V will be at least 378us:
<math> V_c = V_s \left ( 1 - e{\frac{-t}{RC}} \right )</math>
<math> \frac{V_c}{V_s} = 1 - e{\frac{-t}{RC}} </math>
<math> e{\frac{-t}{RC}} = 1 - \frac{V_c}{V_s}</math>
<math> \frac{-t}{RC} = ln \left ( 1 - \frac{V_c}{V_s} \right )</math>
<math> t = -RC * ln \left ( 1 - \frac{V_c}{V_s} \right )</math>
<math> t = -5 * 0.000047 * ln \left ( 1 - \frac{4}{5} \right )</math>
<math> t = 378us</math>
At this stage the current being used to charge the caps is low enough for the resistor to be removed.
<math>I = \frac{V_s}{R} e^{\frac{-t}{RC}} </math>
<math>I = \frac{5}{5} e^{\frac{-0.000378}{5 * 0.000047}} </math>
<math>I = 0.2A</math>
A standard [http://www.digikey.com/product-detail/en/LM311DR/296-1388-1-ND/379817 LM311] comparitor will be used. The comparitor provides an open-collector output to bring the MOSFET gate to ground when the +ve input is lower than the -ve input.  The -ve input will be connected to the input caps, and the +ve input will be connected to a resistor voltage divider to bring the input down to 4v.
{| border="1"
! R1 to +5v
! R2 to ground
! Comparitor +ve input
|-
| 1000
| 4000
| 4V
|}
== In-circuit programming ==
The LPC17xx micro will be programmed via JTAG using [http://openocd.sourceforge.net/doc/html/Flash-Commands.html Open OCD].
The standard ARM 0.1" 20-pin JTAG header will be used (see http://www.keil.com/support/man/docs/ulink2/ulink2_hw_connectors.htm for connector and necessary pull-up/pull-down details).
Serial programming of the LPC1751 is performed via the UART0 TX and RX pins.  To enter programming mode, <span style="text-decoration: overline">P2.10</span> must be low on <span style="text-decoration: overline">RESET</span>.  The active-low <span style="text-decoration: overline">P2.10</span> and <span style="text-decoration: overline">RESET</span> lines will be pulled up to +3.3V via a 10kΩ resistor to ensure the micro isn't reset.
== Termination ==
* The [http://www.ti.com/product/ucc5617?qgpn=ucc5617 ucc5617] will be powered by +5v, not TERMPWR. This enables testing the device without connecting to a live SCSI bus.  The PHY essentially connects the outputs back to the inputs, but we still need the terminator powered to provide pullups.
* A DIP Switch will be used to connect the DISCNCT pin of the [http://www.ti.com/product/ucc5617?qgpn=ucc5617 ucc5617] to ground if the user wants to disable termination. The pin will be pulled-up to +5V via a 10k resistor.


== Switches ==
== Switches ==

Revision as of 10:30, 28 May 2013

Details for the circuit design of SCSI2SD.

Changes between V1 and V2

The First_reflow_soldering_attempt was a failure. As a result, the schematic is being improved to simplify construction.

Change of microcontroller footprint

The V1 incorrectly made use of a 10x10mm QFN68 0.5mm pitch footprint for the CY8C53 microcontroller, instead of the smaller 8x8mm QFN68. 8x8mm is seriously tiny, with a pitch of only 0.4mm. The TSSOP packages (0.635mm pitch) on the V1 boards had many solder bridges etc, and moving to an even finer pitch device would be well beyond my soldering ability.

The solution is to make use of the 100-pin TQFP versions of the microcontroller instead. The devices use a 0.5mm pitch, 25% larger than the QFN68 devices, and the same as the (incorrect) footprint on the V1 board.

Change of PHY

The V1 schematic made use of a typical bus arrangement to interface to the SCSI wires. SCSI signals were split into read and write paths, with the microcontroller using a signal to switch the bus between read or write mode. This arrangement uses minimal microcontroller pins (18 SCSI pins + 1 R/W signal), but additional interface IC's.

The V2 schematic will switch back to a much simpler arrangement whereby each SCSI signal is connected to the microcontroller twice - once for read, and another for write (via an inverting buffer). This arrangement is possible due to the additional I/Os available with the 100-pin QFP version of the microcontroller, and saves the cost/board space/soldering of 6 additional ICs.

Use of a solder stencil

The 0.5mm pitch of the microcontroller will require the use of a stencil to limit the amount of solder paste applied. I applied way too much paste to the 0.635mm pitch devices on the V1 boards, and this caused many solder bridges.

The 0.5mm pitch will require a laser-cut stencil.

  1. Laser-cut 3mil mylar (plastic) stencils available from pololu for $25. Non-framed.
  2. Laser-cut 3.5mil kapton (plastic) stencils available from ohararp for $25. Non-framed.


Board specifications

  1. 0805 sized components will be used where applicable. These represent a good tradeoff between hand-solderability and PCB board space.
  2. Pin pitch will be 0.5mm or (preferably) larger.

Power Supply

Power Requirements

3.3V
CY8C53 200mA

rough estimate

SD Card 200mA

Peak value from [1]

Termination 466mA

18 * (2.85V / 110ohms)

Total 866mA

5V supply from a hard drive molex connector should provide more than sufficient current. The 3.3v supply will be regulated from the 5v supply to share input capacitance and therefore reduce complexity.

Switching Regulator Requirements

  • Require at least 83% duty cycle, to allow operation down to Vin = 4v.
  • Require >= 90% efficiency to reduce heat.
  • > 866mA output.
  • Fsw >= 1MHz for small output filtering capacitance.
  • Easy hand-soldering.

MAX1951 Design

  • MAX1951
  • Supports Vout == Vin.
    • Regulator won't dropout if the 5V rail temporarily drops down to 3.3V.
  • Over 90% efficiency with 5V input.
  • 2A output
    • Max load current without a heatsink is 1.36A
  • 1MHz fixed switching
  • Digital soft-start
  • Reasonably priced for single units $4.41
  • Designed for use with small ceramic capacitors.
    • Only 10uF is required for both the input & output filters.
    • Additional bulk capacitance will be provided on input to deal with the 5V IC's.

We will take 400mA as the expected load; in truth, it is likely to be much less. Derating to provide a safety margin will be done as a last step in chosing components - this derating should allow a higher load without any problems.

Output Inductor

The MAX1951 recommends a 2μH inductor, making selection very simple.

  • 2A minimum current rating, 3A minimum saturation.
  • 20mΩ maximum DC resistance.

Given LIR = 30% (Inductor ripple %, recommended range 20%-40%):

Peak inductor current = <math>\left ( 1 + \frac{LIR}{2} \right ) \times I_{OUT} = \left ( 1 + \frac{0.3}{2} \right ) \times 0.4 = 460mA</math>

Given the above values, the chosen inductor is TDK SPM6530T-2R2M ($1.41 for single units).

Inductance Tolerance DC Resistance Current
2.2μH 20% 19mΩ 8.4A

Filter Capacitors

The MAX1951 recommends a 10μF input and output ceramic capacitor. There is no point calculating ripple current/voltages etc, because manufacturers don't bother supplying a ripple voltage spec on their datasheets; the low ESR and ESL of ceramic capacitors makes it somewhat irrelevant.

The value of ceramic capacitors decreases significantly (80% or greater) as they approach their rated voltage. For this reason, the filter caps will be over-rated to 25V, and the bypass caps to 10V.

The chosen capacitors are:

Use Value Voltage Type Package Device
Input and Output filtering 10μF 25V X5R or X7R 0805 Murata GRM21BR61E106KA73L
Input Bulk 47μF 25V X5R or X7R 1206 TDK C3216X5R1E476M
Bypass 100nF 25V X5R or X7R 0805 TDK C2012X7R1E104K
Compensation 220pF 50V

See Table 2 in datasheet.

C0G/NP0 0805 TDK C2012C0G1H221J

Ferrite Bead

A ferrite bead will be used on the incoming +5V line to reduce EMI being conducted back to the host.

  • Ideally, the bead should reject all frequencies from the switching frequency (1MHz) to the CPU Frequency (100MHz). Realistically, very few beads attenuate from 1MHz.
  • 2A current rating.

To be safe, we'll chose a ferrite bead with a very minimal DC resistance.

DC Resistance Peak current Case style Impedence Part
5mΩ 6A 1206 48Ω @ 100MHz Taiyo Yuden FBMJ3216HS480NT


Switches

  • Parity and SCSI ID will be set via a set of DIP switches to ground.
  • The micro GPIO port pull-ups will be enabled (this is the default anyway).
  • Parity requires 1 bit, SCSI ID requires 3 bits, SCSI Terminator DISCNT requires 1 bit. (5-way DIP switch required)