SCSI2SD old: Difference between revisions

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A device that presents a USB Mass Storage device as a Direct Access device to a SCSI controller.
A device that presents a an SD Card as a Direct Access device to a SCSI controller.


== Specifications ==
* Fast (10MHz) Narrow (8-bit parallel) Single-Ended SCSI-2


== Why ? ==
== Why ? ==
Line 12: Line 10:
* 50pin to 68pin or 80pin SCSI converters allow the use of newer drives.  Availability of new SCSI SCA (80 pin) drives is limited to prohibitively expensive 15K RPM "enterprise" drives.
* 50pin to 68pin or 80pin SCSI converters allow the use of newer drives.  Availability of new SCSI SCA (80 pin) drives is limited to prohibitively expensive 15K RPM "enterprise" drives.


== Why USB ? ==
== Requirements ==
Because USB Mass Storage devices already understand SCSI commands.
* The device shall act as the boot device for an Apple LCIII.  See [[Apple LCIII Restoration]].
** [http://support.apple.com/kb/TA29470?viewlocale=en_US NCR AM85C80 controller].
** SCSI-2
** Provides a 25-pin external connector, which implies single-ended support only.
** asynchronous support only to 1.5MB/sec. I think this is specified based on the longest possible external cable, and higher data-rates would be possible with short internal cables.
* The device shall support a sustained 4MB/s sequential transfer rate.
** Matches the speed of the [http://stason.org/TULARC/pc/hard-drives-hdd/quantum/PRODRIVE-LPS-270-S-270MB-3-5-SL-SCSI2-SE.html 512MB Quantum ProDrive LPS270-s] that was in the LCII. See [[Apple LCIII Restoration]].
** Note that this drive is SCSI-2, single-ended, <strong>active</strong> termination.
* The device shall optionally provide active termination, enabled and disabled via a jumper.
* The device shall provide termination power.
** Some Macs don't provide termination power. See [http://docs.info.apple.com/article.html?artnum=6159]
** This enables "loopback" testing of the device without connecting to a SCSI bus.
* The device shall optionally check parity, enabled and disabled via a jumper.
** Some Amiga SCSI controllers don't provide parity.
* The device shall provide jumpers to set the SCSI ID
* The entirety of the device shall physically fit within a 3 1/2" drive bay, including the storage device.


== Parts Required ==
== Design Choices ==
* SCSI Terminator.  [http://au.element14.com/texas-instruments/uc5601dwpg4/scsi-terminator-18-line-5v-soic28/dp/1234991 TI UC5601DWPG4]
=== Storage ===
* AT90USB1286
An SD card will be used as the storage device.
** USB Host functionality
** Sources/Sinks 40 mA per I/O pin (Specs require 48mA, but this includes a very large safety margin).
** TTL (5V) I/O output
** Up to 48 [http://en.wikipedia.org/wiki/Three-state_logic tri-state] GPIO pins (need minimum of 18 for SCSI data + control signals)
* 50 pin IDC header
* USB socket
* 5V supply via Molex drive connector
* [http://au.element14.com/texas-instruments/cd74ac280e/logic-parity-gen-chker-9bit-14dip/dp/1753467 TI CD74AC280E] Parity checker/generator.


== SCSI Electrical Interface ==
# A common class 4 or above SD card meets the throughput requirements.
SE and LVD devices may co-exist on a SCSI chain, but the chain will be reduced to SE functionality.
## "Hi speed" 50MHz SPI mode supports 6.25MB/sec.
## 25MHz 4-bit mode supports 12.5MB/sec. Some microcontrollers have hardware support for this mode.
# Trivial to interface with a micro over SPI.
# Compact


[http://en.wikipedia.org/wiki/Open_collector Open collector] signals are used. There are 8 (narrow SCSI) or 16 (wide SCSI) data signals, 1 parity signal, and 9 control signals.
To achieve the required throughput, some hardware support within the microcontroller is required. For SPI, the micro should provide DMA support for SPI transfers. For the 4-bit mode, the micro must support the required compute-intensive CRC calculations and also provide DMA support.


=== Single Ended (SE) ===
Alternative options:
* Still supported on new U320 drives.
# Nand flash would need custom load leveling code, significantly increasing code complexity. SD cards handle load leveling internally.
* TTL logic levels.
# An IDE interface would allow the use of compact flash. SD cards are cheaper and easier to communicate with.
* Up to 40MB/sec (Ultra Wide SCSI).
# SATA/SAS is way too fast for a cheap microcontroller.
* Terminated by 220ohms to TERMPWR, 330ohms to ground.
# Accessing remote storage over ethernet is an interesting idea, but I prefer a standalone solution for this project.
* Output signals:
** Signal asserted (true): 0V to 0.5V, up to 48mA sinking current.
** False: 2.5V to 5.25V
* Input signals:
** Signal asserted (true): 0V to 0.8V
** False: 2V to 5.25V


=== Low-voltage differential (LVD) ===
=== Microcontroller ===
* [http://en.wikipedia.org/wiki/RS-485 RS-485] compatible.  Either LVD SCSI transceivers or RS-485 transceivers may be used.
The [http://www.cypress.com/?id=2233 Cypress PSoc5] will be usedd for its flexibility in routing I/O pins, standard ARM core, and the possibility to use programmable logic to speed-up some interface interactions.
* Up to 320MB/sec (Ultra-320 SCSI).


== SCSI2USB Design ==
=== SCSI signal interface ===
* Single-ended (SE) mode will be used to allow direct connection of each SCSI data and control line to the I/O pins of the microcontroller.


=== Internal Termination ===
=== SCSI PHY ===
* Should be switchable, on and off.
Single-ended (SE) SCSI is an [http://en.wikipedia.org/wiki/Open_collector Open collector] design. We only ever want to drive an output low, never high. The terminators tie the lines high when the outputs are high impedance. Active terminators contain a 110ohm pullup resistor to a +2.85v voltage regulator powered by TERMPWR. Passive terminators contain a 220ohm pullup to TERMPWR (+5v), and 330ohm pulldown to ground.
* Use a purpose-built IC.


=== Parity Checker ===
The proposed design has does not consider low-voltage differential (LVD) mode ([http://en.wikipedia.org/wiki/RS-485 RS-485] compatible). Either LVD SCSI transceivers or RS-485 transceivers would be used. Note that LVD devices must be able to fallback to SE mode, so they can be mixed on the same SCSI chain.
* Programmatically calculating parity of each byte transferred will be too slow.
* The parity bit can be calculated in hardware using a common 74x280 parity checker/generator IC.
* Additional standard logic ICs will be used to switch between input and output data modes.
* Each IC should be chosen to reduce propagation delays. See [http://dsaprojects.110mb.com/electronics/data_book/ic_technology.html].
* <font color="red">Replace with 74x899. MOSFET's switching time is very slow.</font>
The SCSI parity bit is asserted (low) when D0-D7 parity is odd.


Input Mode:
http://www.codesrc.com/images/SCSI2SD/overview.png


Ground              ==========>  74x280 INPUT
# Direct connection of the SCSI wires to a microcontroller is not possible, as micros generally have [http://en.wikipedia.org/wiki/Three-state_logic 3-state] GPIO pins. It could be possible to simulate an open collector output by switching between output/low states and input states, however...
SCSI Cable Data x 8 ======+===>  74x280 <u>D0</u>-<u>D7</u>
# Direct connection of the SCSI wires to a microcontroller is not possible, as most micros cannot sink enough current when output is in the low state.
                          +======================================> AVR port A0-7<br />
  Consider the current required when the low output is pulled up with 1 passive and 1 active terminator- the micro would have to sink (5/220 + 2.85/110) = '''49mA'''.
SCSI Cable Parity  =============================================> AVR port C0
  The NXP LPC Arm controllers can only sink 4mA per pin.
                              |  74x280 Even  ===================> AVR port C1
                              |                    |
                              +--X  MOSFET  X------+
                              |____________________G|<============= AVR port C2
(pseudo code)
  byte parity = 0
set PORTC to INPUT
set PORTC2 to OUTPUT
  set PORTA to INPUT
PORTC &= 11111011 // Disable MOSFET
while (reading)
{
  buffer[n] = ~(Read port A)
  parity = parity ^ Read port C
  }
if ((parity & 0x1) != ((parity >> 1) & 0x2))
  Discard buffer, report error
else
  Process buffer


The SCSI signal levels are TTL compatible, as follows. ''Note that we never output a the high signals directly; the open-collector outputs become high-impedance, and the terminators bring the signal up to the required voltage.''


{| border="1"
!
!Asserted (true)
!Released (false)
|-
|<b>Output</b>
|0V to 0.5V<br />
|2.5V to 5.25V
|-
|<b>Input</b>
| 0V to 0.8V
| 2V to 5.25V
|}
'


Output Mode:
Multiple output buffer IC's will be used to overcome sinking current limitations. Each IC has a limit on the overall current output by the ground pin; using multiple buffers instead of 16bit/octal buffers helps to overcome this limitation.
 
  Ground        ==========>  74x280 INPUT
 
AVR port A0-7 ======+===>  74x280 <u>D0</u>-<u>D7</u>
== Implementation Detail ==
                    +======================================> SCSI Cable Data x 8<br />
* [[SCSI2SD Schematic Notes]]
                            74x280 EVEN ==>|S---------D|==================> SCSI Cable Parity
* [[First reflow soldering attempt]] (build attempt 1)
                                          | nMOSFET  |
AVR Port C2  ===========================>|G----------|<br />
(pseudo code)
set PORTC INPUT
set PORTC2 to OUTPUT
set PORTA to OUTPUT
PORTC |= 0x4
while (writing)
{
  Write port A = ~(buffer[n])
}


== Links ==
== Links ==

Latest revision as of 12:25, 10 September 2013

A device that presents a an SD Card as a Direct Access device to a SCSI controller.


Why ?

Because there are many vintage computers out there that require a 50-pin SCSI drive to boot from. Such disks are only available second-hand, and it's getting harder and harder to find a working disk.

Alternatives

  • The price of commercial SCSI converters can be much higher than the vintage computers they are used in. However, these devices are still readily available.
  • 50pin to 68pin or 80pin SCSI converters allow the use of newer drives. Availability of new SCSI SCA (80 pin) drives is limited to prohibitively expensive 15K RPM "enterprise" drives.

Requirements

  • The device shall act as the boot device for an Apple LCIII. See Apple LCIII Restoration.
    • NCR AM85C80 controller.
    • SCSI-2
    • Provides a 25-pin external connector, which implies single-ended support only.
    • asynchronous support only to 1.5MB/sec. I think this is specified based on the longest possible external cable, and higher data-rates would be possible with short internal cables.
  • The device shall support a sustained 4MB/s sequential transfer rate.
  • The device shall optionally provide active termination, enabled and disabled via a jumper.
  • The device shall provide termination power.
    • Some Macs don't provide termination power. See [1]
    • This enables "loopback" testing of the device without connecting to a SCSI bus.
  • The device shall optionally check parity, enabled and disabled via a jumper.
    • Some Amiga SCSI controllers don't provide parity.
  • The device shall provide jumpers to set the SCSI ID
  • The entirety of the device shall physically fit within a 3 1/2" drive bay, including the storage device.

Design Choices

Storage

An SD card will be used as the storage device.

  1. A common class 4 or above SD card meets the throughput requirements.
    1. "Hi speed" 50MHz SPI mode supports 6.25MB/sec.
    2. 25MHz 4-bit mode supports 12.5MB/sec. Some microcontrollers have hardware support for this mode.
  2. Trivial to interface with a micro over SPI.
  3. Compact

To achieve the required throughput, some hardware support within the microcontroller is required. For SPI, the micro should provide DMA support for SPI transfers. For the 4-bit mode, the micro must support the required compute-intensive CRC calculations and also provide DMA support.

Alternative options:

  1. Nand flash would need custom load leveling code, significantly increasing code complexity. SD cards handle load leveling internally.
  2. An IDE interface would allow the use of compact flash. SD cards are cheaper and easier to communicate with.
  3. SATA/SAS is way too fast for a cheap microcontroller.
  4. Accessing remote storage over ethernet is an interesting idea, but I prefer a standalone solution for this project.

Microcontroller

The Cypress PSoc5 will be usedd for its flexibility in routing I/O pins, standard ARM core, and the possibility to use programmable logic to speed-up some interface interactions.


SCSI PHY

Single-ended (SE) SCSI is an Open collector design. We only ever want to drive an output low, never high. The terminators tie the lines high when the outputs are high impedance. Active terminators contain a 110ohm pullup resistor to a +2.85v voltage regulator powered by TERMPWR. Passive terminators contain a 220ohm pullup to TERMPWR (+5v), and 330ohm pulldown to ground.

The proposed design has does not consider low-voltage differential (LVD) mode (RS-485 compatible). Either LVD SCSI transceivers or RS-485 transceivers would be used. Note that LVD devices must be able to fallback to SE mode, so they can be mixed on the same SCSI chain.

overview.png

  1. Direct connection of the SCSI wires to a microcontroller is not possible, as micros generally have 3-state GPIO pins. It could be possible to simulate an open collector output by switching between output/low states and input states, however...
  2. Direct connection of the SCSI wires to a microcontroller is not possible, as most micros cannot sink enough current when output is in the low state.
Consider the current required when the low output is pulled up with 1 passive and 1 active terminator- the micro would have to sink (5/220 + 2.85/110) = 49mA.
The NXP LPC Arm controllers can only sink 4mA per pin.

The SCSI signal levels are TTL compatible, as follows. Note that we never output a the high signals directly; the open-collector outputs become high-impedance, and the terminators bring the signal up to the required voltage.

Asserted (true) Released (false)
Output 0V to 0.5V
2.5V to 5.25V
Input 0V to 0.8V 2V to 5.25V

'

Multiple output buffer IC's will be used to overcome sinking current limitations. Each IC has a limit on the overall current output by the ground pin; using multiple buffers instead of 16bit/octal buffers helps to overcome this limitation.


Implementation Detail

Links

Projects

References