SCSI2SD old: Difference between revisions

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m (Michael moved page SCSI2SD to SCSI2SD old: This page is now for historical reference only, and does not necessarily describe the device as-built.)
 
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A device that presents a USB Mass Storage device as a Direct Access device to a SCSI controller.
A device that presents a an SD Card as a Direct Access device to a SCSI controller.




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** Note that this drive is SCSI-2, single-ended, <strong>active</strong> termination.
** Note that this drive is SCSI-2, single-ended, <strong>active</strong> termination.
* The device shall optionally provide active termination, enabled and disabled via a jumper.
* The device shall optionally provide active termination, enabled and disabled via a jumper.
* The device shall optionally provide termination power, enabled and disabled via a jumper.
* The device shall provide termination power.
** Some Macs don't provide termination power. See [http://docs.info.apple.com/article.html?artnum=6159]
** Some Macs don't provide termination power. See [http://docs.info.apple.com/article.html?artnum=6159]
** This enables "loopback" testing of the device without connecting to a SCSI bus.
* The device shall optionally check parity, enabled and disabled via a jumper.
* The device shall optionally check parity, enabled and disabled via a jumper.
** Some Amiga SCSI controllers don't provide parity.
** Some Amiga SCSI controllers don't provide parity.
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== Design Choices ==
== Design Choices ==
=== Storage ===
=== Storage ===
- SD card.
An SD card will be used as the storage device.
// SDcard SPI @ 25MHz = 25Mbit/sec. 4bit mode with same 25MHz clock is 100Mbit/sec. http://www.freelabs.com/~whitis/sd_card/
 
// From wikipedia, "Hi speed" mode is 50MHz "and supported by most cards". This is 6.25MB/sec. ok.
# A common class 4 or above SD card meets the throughput requirements.
// Other options:
## "Hi speed" 50MHz SPI mode supports 6.25MB/sec.
// nand flash. Writing the load levelling code increases complexity. SD cards do this internally.
## 25MHz 4-bit mode supports 12.5MB/sec. Some microcontrollers have hardware support for this mode.
//  IDE: allow compact-flash ? SD cards are cheaper.
# Trivial to interface with a micro over SPI.
//  SATA: Too fast - too difficult to interface to a microcontroller.
# Compact
//  Ethernet: Interesting, but prefer a stand-alone solution.
 
To achieve the required throughput, some hardware support within the microcontroller is required. For SPI, the micro should provide DMA support for SPI transfers. For the 4-bit mode, the micro must support the required compute-intensive CRC calculations and also provide DMA support.
 
Alternative options:
# Nand flash would need custom load leveling code, significantly increasing code complexity. SD cards handle load leveling internally.
# An IDE interface would allow the use of compact flashSD cards are cheaper and easier to communicate with.
# SATA/SAS is way too fast for a cheap microcontroller.
# Accessing remote storage over ethernet is an interesting idea, but I prefer a standalone solution for this project.


=== Microcontroller ===
=== Microcontroller ===
There are simply too many options here to list them all.  I'll simply go-with-the-flow, and choose an ARM. I'm sure there would be equivalent microprocessors from the AVR32, PIC32, Coldfire and other families.
The [http://www.cypress.com/?id=2233 Cypress PSoc5] will be usedd for its flexibility in routing I/O pins, standard ARM core, and the possibility to use programmable logic to speed-up some interface interactions.
 
{| border="1"
! Part
! Architecture
! Theoretical peak SD card data rate
! MHz
! DMIPS/MHz
! 5V safe I/O with TTL level inputs ?
! GPIO's, not including SD card pins
! Package
! Cost
(for a single item)
|-
| NXP [http://ics.nxp.com/products/lpc1000/datasheet/lpc1751.lpc1752.lpc1754.lpc1756.lpc1758.lpc1759.pdf LPC1751]
| [http://en.wikipedia.org/wiki/ARM_Cortex-M3 ARM Cortex-M3]
| 50Mbit/s
[http://en.wikipedia.org/wiki/Synchronous_Serial_Port SSP] running at half clock with DMA and multi-byte send/receive buffers.
| 100MHz
| 1.25
| Yes
See datasheet, Table 6 section 10.
| 48
| LQFP80
| [http://au.mouser.com/ProductDetail/NXP/LPC1751FBD80551/?qs=XO2CtKvNMEjZLpmE1jed7g%3d%3d $7.71]
|-
| [http://www.atmel.com/dyn/products/product_card.asp?part_id=5002 ATSAM3S1B]
| [http://en.wikipedia.org/wiki/ARM_Cortex-M3 ARM Cortex-M3]
| 100Mbit/s
HSMCI peripheral, SD 4-bit interface at 25MHz w/ DMA
| 64MHz
| 1.25
| No
Max 4V input, 0.7*VDD High level (2.31V) instead of TTL 2V.
| 41
| LQFP64
| [http://au.element14.com/atmel/atsam3s1ba-au/ic-mcu-32bit-64k-flash-64lqfp/dp/1841650?Ntt=SAM3S1B $7.19]
|}


AVR32: Need 144pin AT32UC3A3* for 4bit SD. SPI can run at master clock frequency.


=== SCSI PHY ===
=== SCSI PHY ===
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| 2V to 5.25V
| 2V to 5.25V
|}
|}
'


The microcontroller must provide TTL compatible, 5V safe GPIO inputs.
Multiple output buffer IC's will be used to overcome sinking current limitations.  Each IC has a limit on the overall current output by the ground pin; using multiple buffers instead of 16bit/octal buffers helps to overcome this limitation.
 
Two GPIO pins are required per SCSI signal. One will be connected to an external open-collector output that can handle the required sinking current.  The other will be an input pin, tied to the output of the open collector output.  The microcontroller must provide at least 36 GPIO's, not including those required to drive the SD card.
 
Multiple output buffer IC's will be used to overcome sinking current limitations.  Each IC has a limit on the overall current output by the ground pin; using multiple buffers instead of 16bit/octal buffers helps to overcome this limitation. Using an inverting buffer allows us to avoid the overhead negating every byte in the microcontroller before sending it over the SCSI interface. 3 [http://www.fairchildsemi.com/pf/MM/MM74HCT05.html 74HCT05 Hex Inverter with open-drain outputs] will be used. These allow for 50mA sinking current per pin, provide 3.3V compatible inputs, and are readily available.


== Parts Required ==
* [http://www.ti.com/product/ucc5617?qgpn=ucc5617 UCC5617] Active SCSI Terminator.
* 3 [http://www.fairchildsemi.com/pf/MM/MM74HCT05.html 74HCT05] Hex Inverter with open-drain outputs
* 50 pin IDC header
* 5V supply via Molex drive connector


== Implementation Detail ==
* [[SCSI2SD Schematic Notes]]
* [[First reflow soldering attempt]] (build attempt 1)


== Links ==
== Links ==

Latest revision as of 12:25, 10 September 2013

A device that presents a an SD Card as a Direct Access device to a SCSI controller.


Why ?

Because there are many vintage computers out there that require a 50-pin SCSI drive to boot from. Such disks are only available second-hand, and it's getting harder and harder to find a working disk.

Alternatives

  • The price of commercial SCSI converters can be much higher than the vintage computers they are used in. However, these devices are still readily available.
  • 50pin to 68pin or 80pin SCSI converters allow the use of newer drives. Availability of new SCSI SCA (80 pin) drives is limited to prohibitively expensive 15K RPM "enterprise" drives.

Requirements

  • The device shall act as the boot device for an Apple LCIII. See Apple LCIII Restoration.
    • NCR AM85C80 controller.
    • SCSI-2
    • Provides a 25-pin external connector, which implies single-ended support only.
    • asynchronous support only to 1.5MB/sec. I think this is specified based on the longest possible external cable, and higher data-rates would be possible with short internal cables.
  • The device shall support a sustained 4MB/s sequential transfer rate.
  • The device shall optionally provide active termination, enabled and disabled via a jumper.
  • The device shall provide termination power.
    • Some Macs don't provide termination power. See [1]
    • This enables "loopback" testing of the device without connecting to a SCSI bus.
  • The device shall optionally check parity, enabled and disabled via a jumper.
    • Some Amiga SCSI controllers don't provide parity.
  • The device shall provide jumpers to set the SCSI ID
  • The entirety of the device shall physically fit within a 3 1/2" drive bay, including the storage device.

Design Choices

Storage

An SD card will be used as the storage device.

  1. A common class 4 or above SD card meets the throughput requirements.
    1. "Hi speed" 50MHz SPI mode supports 6.25MB/sec.
    2. 25MHz 4-bit mode supports 12.5MB/sec. Some microcontrollers have hardware support for this mode.
  2. Trivial to interface with a micro over SPI.
  3. Compact

To achieve the required throughput, some hardware support within the microcontroller is required. For SPI, the micro should provide DMA support for SPI transfers. For the 4-bit mode, the micro must support the required compute-intensive CRC calculations and also provide DMA support.

Alternative options:

  1. Nand flash would need custom load leveling code, significantly increasing code complexity. SD cards handle load leveling internally.
  2. An IDE interface would allow the use of compact flash. SD cards are cheaper and easier to communicate with.
  3. SATA/SAS is way too fast for a cheap microcontroller.
  4. Accessing remote storage over ethernet is an interesting idea, but I prefer a standalone solution for this project.

Microcontroller

The Cypress PSoc5 will be usedd for its flexibility in routing I/O pins, standard ARM core, and the possibility to use programmable logic to speed-up some interface interactions.


SCSI PHY

Single-ended (SE) SCSI is an Open collector design. We only ever want to drive an output low, never high. The terminators tie the lines high when the outputs are high impedance. Active terminators contain a 110ohm pullup resistor to a +2.85v voltage regulator powered by TERMPWR. Passive terminators contain a 220ohm pullup to TERMPWR (+5v), and 330ohm pulldown to ground.

The proposed design has does not consider low-voltage differential (LVD) mode (RS-485 compatible). Either LVD SCSI transceivers or RS-485 transceivers would be used. Note that LVD devices must be able to fallback to SE mode, so they can be mixed on the same SCSI chain.

overview.png

  1. Direct connection of the SCSI wires to a microcontroller is not possible, as micros generally have 3-state GPIO pins. It could be possible to simulate an open collector output by switching between output/low states and input states, however...
  2. Direct connection of the SCSI wires to a microcontroller is not possible, as most micros cannot sink enough current when output is in the low state.
Consider the current required when the low output is pulled up with 1 passive and 1 active terminator- the micro would have to sink (5/220 + 2.85/110) = 49mA.
The NXP LPC Arm controllers can only sink 4mA per pin.

The SCSI signal levels are TTL compatible, as follows. Note that we never output a the high signals directly; the open-collector outputs become high-impedance, and the terminators bring the signal up to the required voltage.

Asserted (true) Released (false)
Output 0V to 0.5V
2.5V to 5.25V
Input 0V to 0.8V 2V to 5.25V

'

Multiple output buffer IC's will be used to overcome sinking current limitations. Each IC has a limit on the overall current output by the ground pin; using multiple buffers instead of 16bit/octal buffers helps to overcome this limitation.


Implementation Detail

Links

Projects

References