SCSI2SD old: Difference between revisions

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=== Microcontroller ===
=== Microcontroller ===
There are simply too many options here to list them all.  I'll simply go-with-the-flow, and choose an ARM. I'm sure there would be equivalent microprocessors from the PIC32, Coldfire and other families.
There are simply too many options here to list them all.  I'll simply go-with-the-flow, and choose an ARM. I'm sure there would be equivalent microprocessors from the Coldfire and other families.


{| border="1"
{| border="1"
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| TQFP64
| TQFP64
| [http://au.element14.com/atmel/at32uc3b064-a2ut/mcu-32bit-64k-flash-uc3b-64qfp/dp/1841641?Ntt=AT32UC3B064 $8.11]
| [http://au.element14.com/atmel/at32uc3b064-a2ut/mcu-32bit-64k-flash-uc3b-64qfp/dp/1841641?Ntt=AT32UC3B064 $8.11]
|-
| [http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en532433 PIC32MX320F064H]
| [http://en.wikipedia.org/wiki/MIPS_architecture MIPS M4K]
| ?
| 80MHz
| 1.56
| Yes
5V safe on some pins. Digital inputs described as TTL buffers.
| 49
| TQFP64
| [http://au.mouser.com/ProductDetail/Microchip-Technology/PIC32MX320F064H-80I-PT/?qs=sGAEpiMZZMvu0Nwh4cA1wbxtM2HhJVuE9wLLfMeXBwo%3d $7.83]
|}
|}



Revision as of 12:38, 2 October 2011

A device that presents a USB Mass Storage device as a Direct Access device to a SCSI controller.


Why ?

Because there are many vintage computers out there that require a 50-pin SCSI drive to boot from. Such disks are only available second-hand, and it's getting harder and harder to find a working disk.

Alternatives

  • The price of commercial SCSI converters can be much higher than the vintage computers they are used in. However, these devices are still readily available.
  • 50pin to 68pin or 80pin SCSI converters allow the use of newer drives. Availability of new SCSI SCA (80 pin) drives is limited to prohibitively expensive 15K RPM "enterprise" drives.

Requirements

  • The device shall act as the boot device for an Apple LCIII. See Apple LCIII Restoration.
    • NCR AM85C80 controller.
    • SCSI-2
    • Provides a 25-pin external connector, which implies single-ended support only.
    • asynchronous support only to 1.5MB/sec. I think this is specified based on the longest possible external cable, and higher data-rates would be possible with short internal cables.
  • The device shall support a sustained 4MB/s sequential transfer rate.
  • The device shall optionally provide active termination, enabled and disabled via a jumper.
  • The device shall optionally provide termination power, enabled and disabled via a jumper.
    • Some Macs don't provide termination power. See [1]
  • The device shall optionally check parity, enabled and disabled via a jumper.
    • Some Amiga SCSI controllers don't provide parity.
  • The device shall provide jumpers to set the SCSI ID
  • The entirety of the device shall physically fit within a 3 1/2" drive bay, including the storage device.

Design Choices

Storage

- SD card. // SDcard SPI @ 25MHz = 25Mbit/sec. 4bit mode with same 25MHz clock is 100Mbit/sec. http://www.freelabs.com/~whitis/sd_card/ // From wikipedia, "Hi speed" mode is 50MHz "and supported by most cards". This is 6.25MB/sec. ok. // Other options: // nand flash. Writing the load levelling code increases complexity. SD cards do this internally. // IDE: allow compact-flash ? SD cards are cheaper. // SATA: Too fast - too difficult to interface to a microcontroller. // Ethernet: Interesting, but prefer a stand-alone solution.

Microcontroller

There are simply too many options here to list them all. I'll simply go-with-the-flow, and choose an ARM. I'm sure there would be equivalent microprocessors from the Coldfire and other families.

Part Architecture Theoretical peak SD card data rate MHz DMIPS/MHz 5V safe I/O with TTL level inputs ? GPIO's, not including SD card pins Package Cost

(for a single item)

NXP LPC1751 ARM Cortex-M3 50Mbit/s

SSP running at half clock with DMA and multi-byte send/receive buffers.

100MHz 1.25 Yes

See datasheet, Table 6 section 10.

48 LQFP80 $7.71
ATSAM3S1B ARM Cortex-M3 100Mbit/s

HSMCI peripheral, SD 4-bit interface at 25MHz w/ DMA

64MHz

Run at 50MHz for SD compatibility.

1.25 No

Max 4V input, 0.7*VDD High level (2.31V) instead of TTL 2V.

41 LQFP64 $7.19

+ Extra cost for TTL level shifters

AT32UC3B064 AVR32 50Mbit/s

SPI running at master clock.

60MHz

Run at 50MHz for SD compatibility.

1.2 Yes

TTL, and 5V safe on 30 of the 44 GPIO pins.

44 TQFP64 $8.11
PIC32MX320F064H MIPS M4K ? 80MHz 1.56 Yes

5V safe on some pins. Digital inputs described as TTL buffers.

49 TQFP64 $7.83

SCSI PHY

Single-ended (SE) SCSI is an Open collector design. We only ever want to drive an output low, never high. The terminators tie the lines high when the outputs are high impedance. Active terminators contain a 110ohm pullup resistor to a +2.85v voltage regulator powered by TERMPWR. Passive terminators contain a 220ohm pullup to TERMPWR (+5v), and 330ohm pulldown to ground.

The proposed design has does not consider low-voltage differential (LVD) mode (RS-485 compatible). Either LVD SCSI transceivers or RS-485 transceivers would be used. Note that LVD devices must be able to fallback to SE mode, so they can be mixed on the same SCSI chain.

overview.png

  1. Direct connection of the SCSI wires to a microcontroller is not possible, as micros generally have 3-state GPIO pins. It could be possible to simulate an open collector output by switching between output/low states and input states, however...
  2. Direct connection of the SCSI wires to a microcontroller is not possible, as most micros cannot sink enough current when output is in the low state.
Consider the current required when the low output is pulled up with 1 passive and 1 active terminator- the micro would have to sink (5/220 + 2.85/110) = 49mA.
The NXP LPC Arm controllers can only sink 4mA per pin.

The SCSI signal levels are TTL compatible, as follows. Note that we never output a the high signals directly; the open-collector outputs become high-impedance, and the terminators bring the signal up to the required voltage.

Asserted (true) Released (false)
Output 0V to 0.5V
2.5V to 5.25V
Input 0V to 0.8V 2V to 5.25V

The microcontroller must provide TTL compatible, 5V safe GPIO inputs.

Two GPIO pins are required per SCSI signal. One will be connected to an external open-collector output that can handle the required sinking current. The other will be an input pin, tied to the output of the open collector output. The microcontroller must provide at least 36 GPIO's, not including those required to drive the SD card.

Multiple output buffer IC's will be used to overcome sinking current limitations. Each IC has a limit on the overall current output by the ground pin; using multiple buffers instead of 16bit/octal buffers helps to overcome this limitation. Using an inverting buffer allows us to avoid the overhead negating every byte in the microcontroller before sending it over the SCSI interface. 3 74HCT05 Hex Inverter with open-drain outputs will be used. These allow for 50mA sinking current per pin, provide 3.3V compatible inputs, and are readily available.

Parts Required

  • UCC5617 Active SCSI Terminator.
  • 3 74HCT05 Hex Inverter with open-drain outputs
  • 50 pin IDC header
  • 5V supply via Molex drive connector


Links

Projects

References