STM32CubeMX/2020c.diff

   1 diff --git a/STM32CubeMX/2020c/Src/sdio.c b/STM32CubeMX/2020c/Src/sdio.c
   2 index f2a0b7c..a00c6a8 100644
   3 --- a/STM32CubeMX/2020c/Src/sdio.c
   4 +++ b/STM32CubeMX/2020c/Src/sdio.c
   5 @@ -40,6 +40,8 @@ void MX_SDIO_SD_Init(void)
   6    hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
   7    hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
   8    hsd.Init.ClockDiv = 0;
   9 +
  10 +  /*
  11    if (HAL_SD_Init(&hsd) != HAL_OK)
  12    {
  13      Error_Handler();
  14 @@ -47,8 +49,7 @@ void MX_SDIO_SD_Init(void)
  15    if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
  16    {
  17      Error_Handler();
  18 -  }
  19 -
  20 +  }*/
  21  }
  22
  23  void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle)
  24 diff --git a/STM32CubeMX/2020c/Src/spi.c b/STM32CubeMX/2020c/Src/spi.c
  25 index 902bdb2..4935bf0 100644
  26 --- a/STM32CubeMX/2020c/Src/spi.c
  27 +++ b/STM32CubeMX/2020c/Src/spi.c
  28 @@ -37,6 +37,8 @@ void MX_SPI1_Init(void)
  29    hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
  30    hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
  31    hspi1.Init.NSS = SPI_NSS_SOFT;
  32 +
  33 +  // 13.5Mbaud FPGA device allows up to 25MHz write
  34    hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
  35    hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
  36    hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
  37 diff --git a/STM32CubeMX/2020c/Src/usbd_conf.c b/STM32CubeMX/2020c/Src/usbd_conf.c
  38 index eee1fd8..9567a95 100644
  39 --- a/STM32CubeMX/2020c/Src/usbd_conf.c
  40 +++ b/STM32CubeMX/2020c/Src/usbd_conf.c
  41 @@ -458,9 +458,12 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
  42    HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
  43    HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
  44  #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  45 +
  46 +  // Combined RX + TX fifo of 0x140 4-byte words (1280 bytes)
  47    HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
  48    HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
  49 -  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
  50 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x40);
  51 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 2, 0x40);
  52    }
  53    if (pdev->id == DEVICE_HS) {
  54    /* Link the driver to the stack. */
  55 @@ -497,9 +500,15 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
  56    HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOOUTIncompleteCallback);
  57    HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOINIncompleteCallback);
  58  #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  59 +  // Combined RX + TX fifo of 0x400 4-byte words (4096 bytes)
  60    HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_HS, 0x200);
  61 -  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x80);
  62 -  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x174);
  63 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x40);
  64 +
  65 +//  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x100);
  66 +// HOst requests 7 sectors, which is an odd number and doesn't fill the
  67 +// fifo, looks like it doesn't complete in this case !!!!
  68 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x80); // 512 bytes
  69 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 2, 0x40);
  70    }
  71    return USBD_OK;
  72  }
  73 diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sd.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sd.h
  74 index a4317e4..7165538 100644
  75 --- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sd.h
  76 +++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sd.h
  77 @@ -614,7 +614,8 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui
  78  HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
  79  /* Non-Blocking mode: DMA */
  80  HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
  81 -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
  82 +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
  83 +HAL_StatusTypeDef HAL_SD_WriteBlocks_Data(SD_HandleTypeDef *hsd, uint8_t *pData);
  84
  85  void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
  86
  87 diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h
  88 index 181b4b7..d71c37b 100644
  89 --- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h
  90 +++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h
  91 @@ -1064,6 +1064,7 @@ uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
  92  uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
  93  uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
  94  uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
  95 +uint32_t SDMMC_CmdSetBlockCount(SDIO_TypeDef *SDIOx, uint32_t appCmdArg, uint32_t blockCount);
  96  uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
  97  uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
  98  uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
  99 diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c
 100 index 569c8b1..b10dd0e 100644
 101 --- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c
 102 +++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c
 103 @@ -430,6 +430,10 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
 104    /* Enable SDIO Clock */
 105    __HAL_SD_ENABLE(hsd);
 106
 107 +  /* 1ms: required power up waiting time before starting the SD initialization
 108 +     sequence */
 109 +  HAL_Delay(1);
 110 +
 111    /* Identify card operating voltage */
 112    errorstate = SD_PowerON(hsd);
 113    if(errorstate != HAL_SD_ERROR_NONE)
 114 @@ -1227,22 +1231,21 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
 115      else
 116      {
 117        /* Enable SD DMA transfer */
 118 -      __HAL_SD_DMA_ENABLE(hsd);
 119 +      // MM disabled, as this fails on fast cards. __HAL_SD_DMA_ENABLE(hsd);
 120
 121        if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
 122        {
 123          add *= 512U;
 124 -      }
 125 -
 126 -      /* Set Block Size for Card */
 127 -      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
 128 -      if(errorstate != HAL_SD_ERROR_NONE)
 129 -      {
 130 -        /* Clear all the static flags */
 131 -        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
 132 -        hsd->ErrorCode |= errorstate;
 133 -        hsd->State = HAL_SD_STATE_READY;
 134 -        return HAL_ERROR;
 135 +        /* Set Block Size for Card */
 136 +        errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
 137 +        if(errorstate != HAL_SD_ERROR_NONE)
 138 +        {
 139 +          /* Clear all the static flags */
 140 +          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
 141 +          hsd->ErrorCode |= errorstate;
 142 +          hsd->State = HAL_SD_STATE_READY;
 143 +          return HAL_ERROR;
 144 +        }
 145        }
 146
 147        /* Configure the SD DPSM (Data Path State Machine) */
 148 @@ -1252,6 +1255,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
 149        config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
 150        config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
 151        config.DPSM          = SDIO_DPSM_ENABLE;
 152 +
 153 +      // We cannot enable DMA too early on UHS-I class 3 SD cards, or else the
 154 +      // data is just discarded before the dpsm is started.
 155 +      __HAL_SD_DMA_ENABLE();
 156 +
 157        (void)SDIO_ConfigData(hsd->Instance, &config);
 158
 159        /* Read Blocks in DMA mode */
 160 @@ -1301,18 +1309,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
 161    * @param  NumberOfBlocks: Number of blocks to write
 162    * @retval HAL status
 163    */
 164 -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
 165 +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
 166  {
 167 -  SDIO_DataInitTypeDef config;
 168    uint32_t errorstate;
 169    uint32_t add = BlockAdd;
 170
 171 -  if(NULL == pData)
 172 -  {
 173 -    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
 174 -    return HAL_ERROR;
 175 -  }
 176 -
 177    if(hsd->State == HAL_SD_STATE_READY)
 178    {
 179      hsd->ErrorCode = HAL_SD_ERROR_NONE;
 180 @@ -1323,15 +1324,29 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
 181        return HAL_ERROR;
 182      }
 183
 184 -    hsd->State = HAL_SD_STATE_BUSY;
 185 +    if(NumberOfBlocks > 1U && hsd->SdCard.CardType == CARD_SDHC_SDXC)
 186 +    {
 187 +      /* MM: Prepare for write */
 188 +      errorstate = SDMMC_CmdSetBlockCount(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd) << 16, NumberOfBlocks);
 189 +      if(errorstate != HAL_SD_ERROR_NONE)
 190 +      {
 191 +        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
 192 +        hsd->ErrorCode |= errorstate;
 193 +        hsd->State = HAL_SD_STATE_READY;
 194 +        return HAL_ERROR;
 195 +      }
 196 +    }
 197 +
 198 +    // hsd->State = HAL_SD_STATE_BUSY;
 199
 200      /* Initialize data control register */
 201      hsd->Instance->DCTRL = 0U;
 202
 203      /* Enable SD Error interrupts */
 204 -    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
 205 +    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND));
 206
 207      /* Set the DMA transfer complete callback */
 208 +    // This callback now doesn't do anything - enabling DATAEND interrupt is set above to avoid race conditions
 209      hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
 210
 211      /* Set the DMA error callback */
 212 @@ -1343,17 +1358,16 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
 213      if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
 214      {
 215        add *= 512U;
 216 -    }
 217 -
 218 -    /* Set Block Size for Card */
 219 -    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
 220 -    if(errorstate != HAL_SD_ERROR_NONE)
 221 -    {
 222 -      /* Clear all the static flags */
 223 -      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
 224 -      hsd->ErrorCode |= errorstate;
 225 -      hsd->State = HAL_SD_STATE_READY;
 226 -      return HAL_ERROR;
 227 +      /* Set Block Size for Card */
 228 +      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
 229 +      if(errorstate != HAL_SD_ERROR_NONE)
 230 +      {
 231 +        /* Clear all the static flags */
 232 +        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
 233 +        hsd->ErrorCode |= errorstate;
 234 +        hsd->State = HAL_SD_STATE_READY;
 235 +        return HAL_ERROR;
 236 +      }
 237      }
 238
 239      /* Write Blocks in Polling mode */
 240 @@ -1381,11 +1395,55 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
 241        return HAL_ERROR;
 242      }
 243
 244 -    /* Enable SDIO DMA transfer */
 245 -    __HAL_SD_DMA_ENABLE(hsd);
 246 +    return HAL_OK;
 247 +  }
 248 +  else
 249 +  {
 250 +    return HAL_BUSY;
 251 +  }
 252 +}
 253 +
 254 +/**
 255 +  * @brief  Writes block(s) to a specified address in a card. The Data transfer
 256 +  *         is managed by DMA mode.
 257 +  * @note   This API should be followed by a check on the card state through
 258 +  *         HAL_SD_GetCardState().
 259 +  * @note   You could also check the DMA transfer process through the SD Tx
 260 +  *         interrupt event.
 261 +  * @param  hsd: Pointer to SD handle
 262 +  * @param  pData: Pointer to the buffer that will contain the data to transmit
 263 +  * @param  BlockAdd: Block Address where data will be written
 264 +  * @param  NumberOfBlocks: Number of blocks to write
 265 +  * @retval HAL status
 266 +  */
 267 +HAL_StatusTypeDef HAL_SD_WriteBlocks_Data(SD_HandleTypeDef *hsd, uint8_t *pData)
 268 +{
 269 +  SDIO_DataInitTypeDef config;
 270 +
 271 +  if(hsd->State == HAL_SD_STATE_READY)
 272 +  {
 273 +    hsd->ErrorCode = HAL_SD_ERROR_NONE;
 274 +
 275 +    hsd->State = HAL_SD_STATE_BUSY;
 276 +
 277 +    /* Initialize data control register */
 278 +    hsd->Instance->DCTRL = 0U;
 279 +
 280 +    /* Enable SD Error interrupts */
 281 +    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND));
 282 +
 283 +    /* Set the DMA transfer complete callback */
 284 +    // This callback now doesn't do anything - enabling DATAEND interrupt is set above to avoid race conditions
 285 +    hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
 286 +
 287 +    /* Set the DMA error callback */
 288 +    hsd->hdmatx->XferErrorCallback = SD_DMAError;
 289 +
 290 +    /* Set the DMA Abort callback */
 291 +    hsd->hdmatx->XferAbortCallback = NULL;
 292
 293      /* Enable the DMA Channel */
 294 -    if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
 295 +    if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE)/4U) != HAL_OK)
 296      {
 297        __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
 298        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
 299 @@ -1398,11 +1456,16 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
 300      {
 301        /* Configure the SD DPSM (Data Path State Machine) */
 302        config.DataTimeOut   = SDMMC_DATATIMEOUT;
 303 -      config.DataLength    = BLOCKSIZE * NumberOfBlocks;
 304 +      config.DataLength    = BLOCKSIZE;
 305        config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
 306        config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
 307        config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
 308        config.DPSM          = SDIO_DPSM_ENABLE;
 309 +
 310 +      // We cannot enable DMA too early on UHS-I class 3 SD cards, or else the
 311 +      // data is just discarded before the dpsm is started.
 312 +      __HAL_SD_DMA_ENABLE();
 313 +
 314        (void)SDIO_ConfigData(hsd->Instance, &config);
 315
 316        return HAL_OK;
 317 @@ -1588,16 +1651,8 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
 318      {
 319        if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
 320        {
 321 -        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
 322 -        if(errorstate != HAL_SD_ERROR_NONE)
 323 -        {
 324 -          hsd->ErrorCode |= errorstate;
 325 -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
 326 -          hsd->ErrorCallback(hsd);
 327 -#else
 328 -          HAL_SD_ErrorCallback(hsd);
 329 -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
 330 -        }
 331 +        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
 332 +        __HAL_SD_DMA_DISABLE(hsd);
 333        }
 334        if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
 335        {
 336 @@ -2354,7 +2409,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
 337    hsd->Context = SD_CONTEXT_NONE;
 338
 339    CardState = HAL_SD_GetCardState(hsd);
 340 -  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
 341 +  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING) || (CardState == HAL_SD_CARD_PROGRAMMING))
 342    {
 343      hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
 344    }
 345 @@ -2460,10 +2515,13 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
 346    */
 347  static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 348  {
 349 -  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
 350 +  // SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
 351
 352    /* Enable DATAEND Interrupt */
 353 -  __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
 354 +  // __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
 355 +  //WHAT IF IT ALREADY TRIGGERED ? Maybe it can't due to interrupt priorities ?
 356 +  // Easier to just ignore it.
 357 +  //  __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
 358  }
 359
 360  /**
 361 diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_sdmmc.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_sdmmc.c
 362 index b060eae..de39f9d 100644
 363 --- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_sdmmc.c
 364 +++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_sdmmc.c
 365 @@ -606,6 +606,32 @@ uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
 366    return errorstate;
 367  }
 368
 369 +/**
 370 +  * @brief  Set the count of a multi-block write command
 371 +  * @param  SDIOx: Pointer to SDIO register base
 372 +  * @retval HAL status
 373 +  */
 374 +uint32_t SDMMC_CmdSetBlockCount(SDIO_TypeDef *SDIOx, uint32_t appCmdArg, uint32_t blockCount)
 375 +{
 376 +  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
 377 +  uint32_t errorstate;
 378 +
 379 +  errorstate = SDMMC_CmdAppCommand(SDIOx, appCmdArg);
 380 +  if(errorstate == HAL_SD_ERROR_NONE)
 381 +  {
 382 +    sdmmc_cmdinit.Argument         = blockCount;
 383 +    sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCK_COUNT;
 384 +    sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
 385 +    sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
 386 +    sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
 387 +    (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 388 +    errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCK_COUNT, SDIO_CMDTIMEOUT);
 389 +  }
 390 +
 391 +  return errorstate;
 392 +}
 393 +
 394 +
 395  /**
 396    * @brief  Send the Write Multi Block command and check the response
 397    * @param  SDIOx: Pointer to SDIO register base
 398 diff --git a/STM32CubeMX/2020c/Src/fsmc.c b/STM32CubeMX/2020c/Src/fsmc.c
 399 index 03a1b12..52f03f4 100644
 400 --- a/STM32CubeMX/2020c/Src/fsmc.c
 401 +++ b/STM32CubeMX/2020c/Src/fsmc.c
 402 @@ -50,12 +50,29 @@ void MX_FSMC_Init(void)
 403    hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
 404    hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
 405    /* Timing */
 406 -  Timing.AddressSetupTime = 2;
 407 +
 408 +  // 1 clock to read the address, + 2 for synchroniser skew
 409 +  Timing.AddressSetupTime = 3;
 410    Timing.AddressHoldTime = 1;
 411 +
 412 +  // Writes to device:
 413 +  //   2 for synchroniser skew (dbx also delayed)
 414 +  //   1 to skip hold time
 415 +  //   1 to write data.
 416 +
 417 +  // Reads from device:
 418 +  //   1 to skip hold time
 419 +  //   1 for synchroniser on OE
 420 +  //   1 to write back to fsmc bus.
 421    Timing.DataSetupTime = 4;
 422 +
 423 +  // Allow a clock for us to release signals
 424 +  // Need to avoid both devices acting as outputs
 425 +  // on the multiplexed lines at the same time.
 426    Timing.BusTurnAroundDuration = 1;
 427 -  Timing.CLKDivision = 16;
 428 -  Timing.DataLatency = 17;
 429 +
 430 +  Timing.CLKDivision = 16; // Ignored for async
 431 +  Timing.DataLatency = 17; // Ignored for async
 432    Timing.AccessMode = FSMC_ACCESS_MODE_A;
 433    /* ExtTiming */
 434
 435 @@ -105,6 +122,10 @@ static void HAL_FSMC_MspInit(void){
 436    PE0   ------> FSMC_NBL0
 437    PE1   ------> FSMC_NBL1
 438    */
 439 +
 440 +  // MM: GPIO_SPEED_FREQ_MEDIUM is rated up to 50MHz, which is fine as all the
 441 +  // fsmc timings are > 1 (ie. so clock speed / 2 is around 50MHz).
 442 +
 443    /* GPIO_InitStruct */
 444    GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
 445                            |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14