STM32CubeMX/2020c.diff

   1 diff --git a/STM32CubeMX/2020c/Src/fsmc.c b/STM32CubeMX/2020c/Src/fsmc.c
   2 index 03a1b12..1b01446 100644
   3 --- a/STM32CubeMX/2020c/Src/fsmc.c
   4 +++ b/STM32CubeMX/2020c/Src/fsmc.c
   5 @@ -50,12 +50,28 @@ void MX_FSMC_Init(void)
   6    hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
   7    hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
   8    /* Timing */
   9 +
  10 +  // 1 clock to read the address, + 1 for synchroniser skew
  11    Timing.AddressSetupTime = 2;
  12    Timing.AddressHoldTime = 1;
  13 +
  14 +  // Writes to device:
  15 +  //   1 for synchroniser skew (dbx also delayed)
  16 +  //   1 to skip hold time
  17 +  //   1 to write data.
  18 +
  19 +  // Reads from device:
  20 +  //   3 for syncroniser
  21 +  //   1 to write back to fsmc bus.
  22    Timing.DataSetupTime = 4;
  23 +
  24 +  // Allow a clock for us to release signals
  25 +  // Need to avoid both devices acting as outputs
  26 +  // on the multiplexed lines at the same time.
  27    Timing.BusTurnAroundDuration = 1;
  28 -  Timing.CLKDivision = 16;
  29 -  Timing.DataLatency = 17;
  30 +
  31 +  Timing.CLKDivision = 16; // Ignored for async
  32 +  Timing.DataLatency = 17; // Ignored for async
  33    Timing.AccessMode = FSMC_ACCESS_MODE_A;
  34    /* ExtTiming */
  35
  36 @@ -105,6 +121,10 @@ static void HAL_FSMC_MspInit(void){
  37    PE0   ------> FSMC_NBL0
  38    PE1   ------> FSMC_NBL1
  39    */
  40 +
  41 +  // MM: GPIO_SPEED_FREQ_MEDIUM is rated up to 50MHz, which is fine as all the
  42 +  // fsmc timings are > 1 (ie. so clock speed / 2 is around 50MHz).
  43 +
  44    /* GPIO_InitStruct */
  45    GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
  46                            |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
  47 diff --git a/STM32CubeMX/2020c/Src/sdio.c b/STM32CubeMX/2020c/Src/sdio.c
  48 index f2a0b7c..a00c6a8 100644
  49 --- a/STM32CubeMX/2020c/Src/sdio.c
  50 +++ b/STM32CubeMX/2020c/Src/sdio.c
  51 @@ -40,6 +40,8 @@ void MX_SDIO_SD_Init(void)
  52    hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
  53    hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
  54    hsd.Init.ClockDiv = 0;
  55 +
  56 +  /*
  57    if (HAL_SD_Init(&hsd) != HAL_OK)
  58    {
  59      Error_Handler();
  60 @@ -47,8 +49,7 @@ void MX_SDIO_SD_Init(void)
  61    if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
  62    {
  63      Error_Handler();
  64 -  }
  65 -
  66 +  }*/
  67  }
  68
  69  void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle)
  70 diff --git a/STM32CubeMX/2020c/Src/spi.c b/STM32CubeMX/2020c/Src/spi.c
  71 index 902bdb2..4935bf0 100644
  72 --- a/STM32CubeMX/2020c/Src/spi.c
  73 +++ b/STM32CubeMX/2020c/Src/spi.c
  74 @@ -37,6 +37,8 @@ void MX_SPI1_Init(void)
  75    hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
  76    hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
  77    hspi1.Init.NSS = SPI_NSS_SOFT;
  78 +
  79 +  // 13.5Mbaud FPGA device allows up to 25MHz write
  80    hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
  81    hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
  82    hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
  83 diff --git a/STM32CubeMX/2020c/Src/usbd_conf.c b/STM32CubeMX/2020c/Src/usbd_conf.c
  84 index eee1fd8..9567a95 100644
  85 --- a/STM32CubeMX/2020c/Src/usbd_conf.c
  86 +++ b/STM32CubeMX/2020c/Src/usbd_conf.c
  87 @@ -458,9 +458,12 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
  88    HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
  89    HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
  90  #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  91 +
  92 +  // Combined RX + TX fifo of 0x140 4-byte words (1280 bytes)
  93    HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
  94    HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
  95 -  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
  96 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x40);
  97 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 2, 0x40);
  98    }
  99    if (pdev->id == DEVICE_HS) {
 100    /* Link the driver to the stack. */
 101 @@ -497,9 +500,15 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
 102    HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOOUTIncompleteCallback);
 103    HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOINIncompleteCallback);
 104  #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 105 +  // Combined RX + TX fifo of 0x400 4-byte words (4096 bytes)
 106    HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_HS, 0x200);
 107 -  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x80);
 108 -  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x174);
 109 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x40);
 110 +
 111 +//  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x100);
 112 +// HOst requests 7 sectors, which is an odd number and doesn't fill the
 113 +// fifo, looks like it doesn't complete in this case !!!!
 114 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x80); // 512 bytes
 115 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 2, 0x40);
 116    }
 117    return USBD_OK;
 118  }
 119 diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h
 120 index c966c906..9d709100 100644
 121 --- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h
 122 +++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h
 123 @@ -1074,6 +1074,7 @@ uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
 124  uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
 125  uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
 126  uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
 127 +uint32_t SDMMC_CmdSetBlockCount(SDIO_TypeDef *SDIOx, uint32_t appCmdArg, uint32_t blockCount);
 128  uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
 129  uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
 130  uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
 131 diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_sdmmc.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_sdmmc.c
 132 index 4f23a455..614b6dce 100644
 133 --- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_sdmmc.c
 134 +++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_sdmmc.c
 135 @@ -606,6 +606,31 @@ uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
 136    return errorstate;
 137  }
 138
 139 +/**
 140 +  * @brief  Set the count of a multi-block write command
 141 +  * @param  SDIOx: Pointer to SDIO register base
 142 +  * @retval HAL status
 143 +  */
 144 +uint32_t SDMMC_CmdSetBlockCount(SDIO_TypeDef *SDIOx, uint32_t appCmdArg, uint32_t blockCount)
 145 +{
 146 +  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
 147 +  uint32_t errorstate;
 148 +
 149 +  errorstate = SDMMC_CmdAppCommand(SDIOx, appCmdArg);
 150 +  if(errorstate == HAL_SD_ERROR_NONE)
 151 +  {
 152 +    sdmmc_cmdinit.Argument         = blockCount;
 153 +    sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCK_COUNT;
 154 +    sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
 155 +    sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
 156 +    sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
 157 +    (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 158 +    errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCK_COUNT, SDIO_CMDTIMEOUT);
 159 +  }
 160 +
 161 +  return errorstate;
 162 +}
 163 +
 164  /**
 165    * @brief  Send the Write Multi Block command and check the response
 166    * @param  SDIOx: Pointer to SDIO register base
 167 diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c
 168 index d2a88d75..1a09028f 100644
 169 --- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c
 170 +++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c
 171 @@ -430,6 +430,10 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
 172    /* Enable SDIO Clock */
 173    __HAL_SD_ENABLE(hsd);
 174
 175 +  /* 1ms: required power up waiting time before starting the SD initialization
 176 +     sequence */
 177 +  HAL_Delay(1);
 178 +
 179    /* Identify card operating voltage */
 180    errorstate = SD_PowerON(hsd);
 181    if(errorstate != HAL_SD_ERROR_NONE)
 182 @@ -1247,22 +1251,22 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
 183      else
 184      {
 185        /* Enable SD DMA transfer */
 186 -      __HAL_SD_DMA_ENABLE(hsd);
 187 +      // MM disabled, as this fails on fast cards. __HAL_SD_DMA_ENABLE(hsd);
 188
 189        if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
 190        {
 191          add *= 512U;
 192 -      }
 193
 194 -      /* Set Block Size for Card */
 195 -      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
 196 -      if(errorstate != HAL_SD_ERROR_NONE)
 197 -      {
 198 -        /* Clear all the static flags */
 199 -        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
 200 -        hsd->ErrorCode |= errorstate;
 201 -        hsd->State = HAL_SD_STATE_READY;
 202 -        return HAL_ERROR;
 203 +        /* Set Block Size for Card */
 204 +        errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
 205 +        if(errorstate != HAL_SD_ERROR_NONE)
 206 +        {
 207 +          /* Clear all the static flags */
 208 +          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
 209 +          hsd->ErrorCode |= errorstate;
 210 +          hsd->State = HAL_SD_STATE_READY;
 211 +          return HAL_ERROR;
 212 +        }
 213        }
 214
 215        /* Configure the SD DPSM (Data Path State Machine) */
 216 @@ -1272,6 +1276,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
 217        config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
 218        config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
 219        config.DPSM          = SDIO_DPSM_ENABLE;
 220 +
 221 +      // We cannot enable DMA too early on UHS-I class 3 SD cards, or else the
 222 +      // data is just discarded before the dpsm is started.
 223 +      __HAL_SD_DMA_ENABLE();
 224 +
 225        (void)SDIO_ConfigData(hsd->Instance, &config);
 226
 227        /* Read Blocks in DMA mode */
 228 @@ -1343,6 +1352,19 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
 229        return HAL_ERROR;
 230      }
 231
 232 +    if(NumberOfBlocks > 1U && hsd->SdCard.CardType == CARD_SDHC_SDXC)
 233 +    {
 234 +      /* MM: Prepare for write */
 235 +      errorstate = SDMMC_CmdSetBlockCount(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd) << 16, NumberOfBlocks);
 236 +      if(errorstate != HAL_SD_ERROR_NONE)
 237 +      {
 238 +        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
 239 +        hsd->ErrorCode |= errorstate;
 240 +        hsd->State = HAL_SD_STATE_READY;
 241 +        return HAL_ERROR;
 242 +      }
 243 +    }
 244 +
 245      hsd->State = HAL_SD_STATE_BUSY;
 246
 247      /* Initialize data control register */
 248 @@ -1367,17 +1389,17 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
 249      if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
 250      {
 251        add *= 512U;
 252 -    }
 253
 254 -    /* Set Block Size for Card */
 255 -    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
 256 -    if(errorstate != HAL_SD_ERROR_NONE)
 257 -    {
 258 -      /* Clear all the static flags */
 259 -      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
 260 -      hsd->ErrorCode |= errorstate;
 261 -      hsd->State = HAL_SD_STATE_READY;
 262 -      return HAL_ERROR;
 263 +      /* Set Block Size for Card */
 264 +      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
 265 +      if(errorstate != HAL_SD_ERROR_NONE)
 266 +      {
 267 +        /* Clear all the static flags */
 268 +        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
 269 +        hsd->ErrorCode |= errorstate;
 270 +        hsd->State = HAL_SD_STATE_READY;
 271 +        return HAL_ERROR;
 272 +      }
 273      }
 274
 275      /* Write Blocks in Polling mode */
 276 @@ -1406,7 +1428,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
 277      }
 278
 279      /* Enable SDIO DMA transfer */
 280 -    __HAL_SD_DMA_ENABLE(hsd);
 281 +    // MM disabled, as this fails on fast cards. __HAL_SD_DMA_ENABLE(hsd);
 282
 283      /* Enable the DMA Channel */
 284      if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
 285 @@ -1431,6 +1453,11 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
 286        config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
 287        config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
 288        config.DPSM          = SDIO_DPSM_ENABLE;
 289 +
 290 +      // We cannot enable DMA too early on UHS-I class 3 SD cards, or else the
 291 +      // data is just discarded before the dpsm is started.
 292 +      __HAL_SD_DMA_ENABLE();
 293 +
 294        (void)SDIO_ConfigData(hsd->Instance, &config);
 295
 296        return HAL_OK;
 297 @@ -1632,6 +1659,10 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
 298            HAL_SD_ErrorCallback(hsd);
 299  #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
 300          }
 301 +        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
 302 +
 303 +        hsd->State = HAL_SD_STATE_READY;
 304 +        hsd->Context = SD_CONTEXT_NONE;
 305        }
 306        if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
 307        {