53f7cbf06ba6c94ad51f4dc050571b09c342d223
[SCSI2SD-V6.git] / STM32CubeMX / 2021.diff
1 diff --git a/STM32CubeMX/2021/Src/fmc.c b/STM32CubeMX/2021/Src/fmc.c
2 index dae179a..995fd15 100644
3 --- a/STM32CubeMX/2021/Src/fmc.c
4 +++ b/STM32CubeMX/2021/Src/fmc.c
5 @@ -52,12 +52,28 @@ void MX_FMC_Init(void)
6    hsram1.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE;
7    hsram1.Init.PageSize = FMC_PAGE_SIZE_NONE;
8    /* Timing */
9 +
10 +  // 1 clock to read the address, + 1 for synchroniser skew
11    Timing.AddressSetupTime = 2;
12    Timing.AddressHoldTime = 1;
13 +
14 +  // Writes to device:
15 +  //   1 for synchroniser skew (dbx also delayed)
16 +  //   1 to skip hold time
17 +  //   1 to write data.
18 +
19 +  // Reads from device:
20 +  //   3 for syncroniser
21 +  //   1 to write back to fsmc bus.
22    Timing.DataSetupTime = 4;
23 +
24 +  // Allow a clock for us to release signals
25 +  // Need to avoid both devices acting as outputs
26 +  // on the multiplexed lines at the same time.
27    Timing.BusTurnAroundDuration = 1;
28 -  Timing.CLKDivision = 16;
29 -  Timing.DataLatency = 17;
30 +
31 +  Timing.CLKDivision = 16; // Ignored for async
32 +  Timing.DataLatency = 17; // Ignored for async
33    Timing.AccessMode = FMC_ACCESS_MODE_A;
34    /* ExtTiming */
35  
36 @@ -107,6 +123,10 @@ static void HAL_FMC_MspInit(void){
37    PE0   ------> FMC_NBL0
38    PE1   ------> FMC_NBL1
39    */
40 +
41 +  // MM: GPIO_SPEED_FREQ_MEDIUM is rated up to 50MHz, which is fine as all the
42 +  // fsmc timings are > 1 (ie. so clock speed / 2 is around 50MHz).
43 +
44    /* GPIO_InitStruct */
45    GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 
46                            |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 
47 diff --git a/STM32CubeMX/2021/Src/sdio.c b/STM32CubeMX/2021/Src/sdio.c
48 index 01e3895..33fbae1 100644
49 --- a/STM32CubeMX/2021/Src/sdio.c
50 +++ b/STM32CubeMX/2021/Src/sdio.c
51 @@ -40,6 +40,8 @@ void MX_SDIO_SD_Init(void)
52    hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
53    hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_ENABLE;
54    hsd.Init.ClockDiv = 0;
55 +
56 +  /*
57    if (HAL_SD_Init(&hsd) != HAL_OK)
58    {
59      Error_Handler();
60 @@ -47,8 +49,7 @@ void MX_SDIO_SD_Init(void)
61    if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
62    {
63      Error_Handler();
64 -  }
65 -
66 +  }*/
67  }
68  
69  void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle)
70 diff --git a/STM32CubeMX/2021/Src/spi.c b/STM32CubeMX/2021/Src/spi.c
71 index 2f9fbfb..aa786dd 100644
72 --- a/STM32CubeMX/2021/Src/spi.c
73 +++ b/STM32CubeMX/2021/Src/spi.c
74 @@ -37,6 +37,8 @@ void MX_SPI1_Init(void)
75    hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
76    hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
77    hspi1.Init.NSS = SPI_NSS_SOFT;
78 +
79 +  // 22.5Mbaud. FPGA device allows up to 25MHz write
80    hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
81    hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
82    hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
83 diff --git a/STM32CubeMX/2021/Src/usbd_conf.c b/STM32CubeMX/2021/Src/usbd_conf.c
84 index 5b10126..a2c4047 100644
85 --- a/STM32CubeMX/2021/Src/usbd_conf.c
86 +++ b/STM32CubeMX/2021/Src/usbd_conf.c
87 @@ -466,9 +466,11 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
88    HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
89    HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
90  #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
91 +  // Combined RX + TX fifo of 0x140 4-byte words (1280 bytes)
92    HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
93    HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
94 -  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
95 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x40);
96 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 2, 0x40);
97    }
98    if (pdev->id == DEVICE_HS) {
99    /* Link the driver to the stack. */
100 @@ -506,9 +508,15 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
101    HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOOUTIncompleteCallback);
102    HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOINIncompleteCallback);
103  #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
104 +  // Combined RX + TX fifo of 0x400 4-byte words (4096 bytes)
105    HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_HS, 0x200);
106 -  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x80);
107 -  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x174);
108 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x40);
109 +
110 +//  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x100);
111 +// HOst requests 7 sectors, which is an odd number and doesn't fill the
112 +// fifo, looks like it doesn't complete in this case !!!!
113 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x80); // 512 bytes
114 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 2, 0x40);
115    }
116    return USBD_OK;
117  }
118 diff --git a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h
119 index 2e254f1..fe133b0 100644
120 --- a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h
121 +++ b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h
122 @@ -614,7 +614,8 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui
123  HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
124  /* Non-Blocking mode: DMA */
125  HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
126 -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
127 +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
128 +HAL_StatusTypeDef HAL_SD_WriteBlocks_Data(SD_HandleTypeDef *hsd, uint8_t *pData);
129  
130  void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
131  
132 diff --git a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h
133 index c966c90..9d70910 100644
134 --- a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h
135 +++ b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h
136 @@ -1074,6 +1074,7 @@ uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
137  uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
138  uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
139  uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
140 +uint32_t SDMMC_CmdSetBlockCount(SDIO_TypeDef *SDIOx, uint32_t appCmdArg, uint32_t blockCount);
141  uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
142  uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
143  uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
144 diff --git a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
145 index d2a88d7..d039e87 100644
146 --- a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
147 +++ b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
148 @@ -430,6 +430,10 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
149    /* Enable SDIO Clock */
150    __HAL_SD_ENABLE(hsd);
151  
152 +  /* 1ms: required power up waiting time before starting the SD initialization 
153 +     sequence */
154 +  HAL_Delay(1);
155 +
156    /* Identify card operating voltage */
157    errorstate = SD_PowerON(hsd);
158    if(errorstate != HAL_SD_ERROR_NONE)
159 @@ -1247,22 +1251,22 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
160      else
161      {
162        /* Enable SD DMA transfer */
163 -      __HAL_SD_DMA_ENABLE(hsd);
164 +      // MM disabled, as this fails on fast cards. __HAL_SD_DMA_ENABLE(hsd);
165  
166        if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
167        {
168          add *= 512U;
169 -      }
170  
171 -      /* Set Block Size for Card */
172 -      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
173 -      if(errorstate != HAL_SD_ERROR_NONE)
174 -      {
175 -        /* Clear all the static flags */
176 -        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
177 -        hsd->ErrorCode |= errorstate;
178 -        hsd->State = HAL_SD_STATE_READY;
179 -        return HAL_ERROR;
180 +        /* Set Block Size for Card */
181 +        errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
182 +        if(errorstate != HAL_SD_ERROR_NONE)
183 +        {
184 +          /* Clear all the static flags */
185 +          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
186 +          hsd->ErrorCode |= errorstate;
187 +          hsd->State = HAL_SD_STATE_READY;
188 +          return HAL_ERROR;
189 +        }
190        }
191  
192        /* Configure the SD DPSM (Data Path State Machine) */
193 @@ -1272,6 +1276,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
194        config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
195        config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
196        config.DPSM          = SDIO_DPSM_ENABLE;
197 +
198 +      // We cannot enable DMA too early on UHS-I class 3 SD cards, or else the
199 +      // data is just discarded before the dpsm is started.
200 +      __HAL_SD_DMA_ENABLE();
201 +
202        (void)SDIO_ConfigData(hsd->Instance, &config);
203  
204        /* Read Blocks in DMA mode */
205 @@ -1321,18 +1330,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
206    * @param  NumberOfBlocks: Number of blocks to write
207    * @retval HAL status
208    */
209 -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
210 +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
211  {
212 -  SDIO_DataInitTypeDef config;
213    uint32_t errorstate;
214    uint32_t add = BlockAdd;
215  
216 -  if(NULL == pData)
217 -  {
218 -    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
219 -    return HAL_ERROR;
220 -  }
221 -
222    if(hsd->State == HAL_SD_STATE_READY)
223    {
224      hsd->ErrorCode = HAL_SD_ERROR_NONE;
225 @@ -1343,19 +1345,33 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
226        return HAL_ERROR;
227      }
228  
229 -    hsd->State = HAL_SD_STATE_BUSY;
230 +    if(NumberOfBlocks > 1U && hsd->SdCard.CardType == CARD_SDHC_SDXC)
231 +    {
232 +      /* MM: Prepare for write */
233 +      errorstate = SDMMC_CmdSetBlockCount(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd) << 16, NumberOfBlocks);
234 +      if(errorstate != HAL_SD_ERROR_NONE)
235 +      {
236 +        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
237 +        hsd->ErrorCode |= errorstate;
238 +        hsd->State = HAL_SD_STATE_READY;
239 +        return HAL_ERROR;
240 +      }
241 +    }
242 +
243 +    // hsd->State = HAL_SD_STATE_BUSY;
244  
245      /* Initialize data control register */
246      hsd->Instance->DCTRL = 0U;
247  
248      /* Enable SD Error interrupts */
249  #if defined(SDIO_STA_STBITERR)
250 -    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
251 +    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
252  #else /* SDIO_STA_STBITERR not defined */
253 -    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));   
254 +    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND));
255  #endif /* SDIO_STA_STBITERR */
256  
257      /* Set the DMA transfer complete callback */
258 +    // This callback now doesn't do anything - enabling DATAEND interrupt is set above to avoid race conditions
259      hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
260  
261      /* Set the DMA error callback */
262 @@ -1367,17 +1383,17 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
263      if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
264      {
265        add *= 512U;
266 -    }
267  
268 -    /* Set Block Size for Card */
269 -    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
270 -    if(errorstate != HAL_SD_ERROR_NONE)
271 -    {
272 -      /* Clear all the static flags */
273 -      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
274 -      hsd->ErrorCode |= errorstate;
275 -      hsd->State = HAL_SD_STATE_READY;
276 -      return HAL_ERROR;
277 +      /* Set Block Size for Card */
278 +      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
279 +      if(errorstate != HAL_SD_ERROR_NONE)
280 +      {
281 +        /* Clear all the static flags */
282 +        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
283 +        hsd->ErrorCode |= errorstate;
284 +        hsd->State = HAL_SD_STATE_READY;
285 +        return HAL_ERROR;
286 +      }
287      }
288  
289      /* Write Blocks in Polling mode */
290 @@ -1405,11 +1421,59 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
291        return HAL_ERROR;
292      }
293  
294 -    /* Enable SDIO DMA transfer */
295 -    __HAL_SD_DMA_ENABLE(hsd);
296 +    return HAL_OK;
297 +  }
298 +  else
299 +  {
300 +    return HAL_BUSY;
301 +  }
302 +}
303 +
304 +/**
305 +  * @brief  Writes block(s) to a specified address in a card. The Data transfer
306 +  *         is managed by DMA mode.
307 +  * @note   This API should be followed by a check on the card state through
308 +  *         HAL_SD_GetCardState().
309 +  * @note   You could also check the DMA transfer process through the SD Tx
310 +  *         interrupt event.
311 +  * @param  hsd: Pointer to SD handle
312 +  * @param  pData: Pointer to the buffer that will contain the data to transmit
313 +  * @param  BlockAdd: Block Address where data will be written
314 +  * @param  NumberOfBlocks: Number of blocks to write
315 +  * @retval HAL status
316 +  */
317 +HAL_StatusTypeDef HAL_SD_WriteBlocks_Data(SD_HandleTypeDef *hsd, uint8_t *pData)
318 +{
319 +  SDIO_DataInitTypeDef config;
320 +
321 +  if(hsd->State == HAL_SD_STATE_READY)
322 +  {
323 +    hsd->ErrorCode = HAL_SD_ERROR_NONE;
324 +
325 +    hsd->State = HAL_SD_STATE_BUSY;
326 +
327 +    /* Initialize data control register */
328 +    hsd->Instance->DCTRL = 0U;
329 +
330 +    /* Enable SD Error interrupts */
331 +#if defined(SDIO_STA_STBITERR)
332 +    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
333 +#else /* SDIO_STA_STBITERR not defined */
334 +    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND));
335 +#endif /* SDIO_STA_STBITERR */
336 +
337 +    /* Set the DMA transfer complete callback */
338 +    // This callback now doesn't do anything - enabling DATAEND interrupt is set above to avoid race conditions
339 +    hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
340 +
341 +    /* Set the DMA error callback */
342 +    hsd->hdmatx->XferErrorCallback = SD_DMAError;
343 +
344 +    /* Set the DMA Abort callback */
345 +    hsd->hdmatx->XferAbortCallback = NULL;
346  
347      /* Enable the DMA Channel */
348 -    if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
349 +    if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE)/4U) != HAL_OK)
350      {
351  #if defined(SDIO_STA_STBITERR)
352        __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
353 @@ -1426,11 +1490,16 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
354      {
355        /* Configure the SD DPSM (Data Path State Machine) */
356        config.DataTimeOut   = SDMMC_DATATIMEOUT;
357 -      config.DataLength    = BLOCKSIZE * NumberOfBlocks;
358 +      config.DataLength    = BLOCKSIZE;
359        config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
360        config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
361        config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
362        config.DPSM          = SDIO_DPSM_ENABLE;
363 +
364 +      // We cannot enable DMA too early on UHS-I class 3 SD cards, or else the
365 +      // data is just discarded before the dpsm is started.
366 +      __HAL_SD_DMA_ENABLE();
367 +
368        (void)SDIO_ConfigData(hsd->Instance, &config);
369  
370        return HAL_OK;
371 @@ -1622,16 +1691,8 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
372      {
373        if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
374        {
375 -        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
376 -        if(errorstate != HAL_SD_ERROR_NONE)
377 -        {
378 -          hsd->ErrorCode |= errorstate;
379 -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
380 -          hsd->ErrorCallback(hsd);
381 -#else
382 -          HAL_SD_ErrorCallback(hsd);
383 -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
384 -        }
385 +        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
386 +        __HAL_SD_DMA_DISABLE(hsd);
387        }
388        if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
389        {
390 @@ -2407,7 +2468,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
391    hsd->Context = SD_CONTEXT_NONE;
392  
393    CardState = HAL_SD_GetCardState(hsd);
394 -  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
395 +  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING) || (CardState == HAL_SD_CARD_PROGRAMMING))
396    {
397      hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
398    }
399 @@ -2513,10 +2574,12 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
400    */
401  static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
402  {
403 -  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
404 +  // SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
405  
406    /* Enable DATAEND Interrupt */
407 -  __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
408 +  //WHAT IF IT ALREADY TRIGGERED ? Maybe it can't due to interrupt priorities ?
409 +  // Easier to just ignore it.
410 +  //  __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
411  }
412  
413  /**
414 diff --git a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c
415 index 4f23a45..614b6dc 100644
416 --- a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c
417 +++ b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c
418 @@ -606,6 +606,31 @@ uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
419    return errorstate;
420  }
421  
422 +/**
423 +  * @brief  Set the count of a multi-block write command
424 +  * @param  SDIOx: Pointer to SDIO register base 
425 +  * @retval HAL status
426 +  */
427 +uint32_t SDMMC_CmdSetBlockCount(SDIO_TypeDef *SDIOx, uint32_t appCmdArg, uint32_t blockCount)
428 +{
429 +  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
430 +  uint32_t errorstate;
431 +  
432 +  errorstate = SDMMC_CmdAppCommand(SDIOx, appCmdArg);
433 +  if(errorstate == HAL_SD_ERROR_NONE)
434 +  {
435 +    sdmmc_cmdinit.Argument         = blockCount;
436 +    sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCK_COUNT;
437 +    sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
438 +    sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
439 +    sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
440 +    (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
441 +    errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCK_COUNT, SDIO_CMDTIMEOUT);
442 +  }
443 +
444 +  return errorstate;
445 +}
446 +
447  /**
448    * @brief  Send the Write Multi Block command and check the response
449    * @param  SDIOx: Pointer to SDIO register base