Improve stability of fpga async mem interface
[SCSI2SD-V6.git] / STM32CubeMX / 2021.diff
1 diff --git a/STM32CubeMX/2021/Src/sdio.c b/STM32CubeMX/2021/Src/sdio.c
2 index 01e3895..33fbae1 100644
3 --- a/STM32CubeMX/2021/Src/sdio.c
4 +++ b/STM32CubeMX/2021/Src/sdio.c
5 @@ -40,6 +40,8 @@ void MX_SDIO_SD_Init(void)
6    hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
7    hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_ENABLE;
8    hsd.Init.ClockDiv = 0;
9 +
10 +  /*
11    if (HAL_SD_Init(&hsd) != HAL_OK)
12    {
13      Error_Handler();
14 @@ -47,8 +49,7 @@ void MX_SDIO_SD_Init(void)
15    if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
16    {
17      Error_Handler();
18 -  }
19 -
20 +  }*/
21  }
22  
23  void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle)
24 diff --git a/STM32CubeMX/2021/Src/spi.c b/STM32CubeMX/2021/Src/spi.c
25 index 2f9fbfb..aa786dd 100644
26 --- a/STM32CubeMX/2021/Src/spi.c
27 +++ b/STM32CubeMX/2021/Src/spi.c
28 @@ -37,6 +37,8 @@ void MX_SPI1_Init(void)
29    hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
30    hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
31    hspi1.Init.NSS = SPI_NSS_SOFT;
32 +
33 +  // 22.5Mbaud. FPGA device allows up to 25MHz write
34    hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
35    hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
36    hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
37 diff --git a/STM32CubeMX/2021/Src/usbd_conf.c b/STM32CubeMX/2021/Src/usbd_conf.c
38 index 5b10126..a2c4047 100644
39 --- a/STM32CubeMX/2021/Src/usbd_conf.c
40 +++ b/STM32CubeMX/2021/Src/usbd_conf.c
41 @@ -466,9 +466,11 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
42    HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
43    HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
44  #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
45 +  // Combined RX + TX fifo of 0x140 4-byte words (1280 bytes)
46    HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
47    HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
48 -  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
49 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x40);
50 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 2, 0x40);
51    }
52    if (pdev->id == DEVICE_HS) {
53    /* Link the driver to the stack. */
54 @@ -506,9 +508,15 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
55    HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOOUTIncompleteCallback);
56    HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOINIncompleteCallback);
57  #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
58 +  // Combined RX + TX fifo of 0x400 4-byte words (4096 bytes)
59    HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_HS, 0x200);
60 -  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x80);
61 -  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x174);
62 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x40);
63 +
64 +//  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x100);
65 +// HOst requests 7 sectors, which is an odd number and doesn't fill the
66 +// fifo, looks like it doesn't complete in this case !!!!
67 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x80); // 512 bytes
68 +  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 2, 0x40);
69    }
70    return USBD_OK;
71  }
72 diff --git a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h
73 index 2e254f1..fe133b0 100644
74 --- a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h
75 +++ b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h
76 @@ -614,7 +614,8 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui
77  HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
78  /* Non-Blocking mode: DMA */
79  HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
80 -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
81 +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
82 +HAL_StatusTypeDef HAL_SD_WriteBlocks_Data(SD_HandleTypeDef *hsd, uint8_t *pData);
83  
84  void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
85  
86 diff --git a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h
87 index c966c90..9d70910 100644
88 --- a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h
89 +++ b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h
90 @@ -1074,6 +1074,7 @@ uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
91  uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
92  uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
93  uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
94 +uint32_t SDMMC_CmdSetBlockCount(SDIO_TypeDef *SDIOx, uint32_t appCmdArg, uint32_t blockCount);
95  uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
96  uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
97  uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
98 diff --git a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
99 index d2a88d7..d039e87 100644
100 --- a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
101 +++ b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
102 @@ -430,6 +430,10 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
103    /* Enable SDIO Clock */
104    __HAL_SD_ENABLE(hsd);
105  
106 +  /* 1ms: required power up waiting time before starting the SD initialization 
107 +     sequence */
108 +  HAL_Delay(1);
109 +
110    /* Identify card operating voltage */
111    errorstate = SD_PowerON(hsd);
112    if(errorstate != HAL_SD_ERROR_NONE)
113 @@ -1247,22 +1251,22 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
114      else
115      {
116        /* Enable SD DMA transfer */
117 -      __HAL_SD_DMA_ENABLE(hsd);
118 +      // MM disabled, as this fails on fast cards. __HAL_SD_DMA_ENABLE(hsd);
119  
120        if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
121        {
122          add *= 512U;
123 -      }
124  
125 -      /* Set Block Size for Card */
126 -      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
127 -      if(errorstate != HAL_SD_ERROR_NONE)
128 -      {
129 -        /* Clear all the static flags */
130 -        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
131 -        hsd->ErrorCode |= errorstate;
132 -        hsd->State = HAL_SD_STATE_READY;
133 -        return HAL_ERROR;
134 +        /* Set Block Size for Card */
135 +        errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
136 +        if(errorstate != HAL_SD_ERROR_NONE)
137 +        {
138 +          /* Clear all the static flags */
139 +          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
140 +          hsd->ErrorCode |= errorstate;
141 +          hsd->State = HAL_SD_STATE_READY;
142 +          return HAL_ERROR;
143 +        }
144        }
145  
146        /* Configure the SD DPSM (Data Path State Machine) */
147 @@ -1272,6 +1276,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
148        config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
149        config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
150        config.DPSM          = SDIO_DPSM_ENABLE;
151 +
152 +      // We cannot enable DMA too early on UHS-I class 3 SD cards, or else the
153 +      // data is just discarded before the dpsm is started.
154 +      __HAL_SD_DMA_ENABLE();
155 +
156        (void)SDIO_ConfigData(hsd->Instance, &config);
157  
158        /* Read Blocks in DMA mode */
159 @@ -1321,18 +1330,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
160    * @param  NumberOfBlocks: Number of blocks to write
161    * @retval HAL status
162    */
163 -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
164 +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
165  {
166 -  SDIO_DataInitTypeDef config;
167    uint32_t errorstate;
168    uint32_t add = BlockAdd;
169  
170 -  if(NULL == pData)
171 -  {
172 -    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
173 -    return HAL_ERROR;
174 -  }
175 -
176    if(hsd->State == HAL_SD_STATE_READY)
177    {
178      hsd->ErrorCode = HAL_SD_ERROR_NONE;
179 @@ -1343,19 +1345,33 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
180        return HAL_ERROR;
181      }
182  
183 -    hsd->State = HAL_SD_STATE_BUSY;
184 +    if(NumberOfBlocks > 1U && hsd->SdCard.CardType == CARD_SDHC_SDXC)
185 +    {
186 +      /* MM: Prepare for write */
187 +      errorstate = SDMMC_CmdSetBlockCount(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd) << 16, NumberOfBlocks);
188 +      if(errorstate != HAL_SD_ERROR_NONE)
189 +      {
190 +        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
191 +        hsd->ErrorCode |= errorstate;
192 +        hsd->State = HAL_SD_STATE_READY;
193 +        return HAL_ERROR;
194 +      }
195 +    }
196 +
197 +    // hsd->State = HAL_SD_STATE_BUSY;
198  
199      /* Initialize data control register */
200      hsd->Instance->DCTRL = 0U;
201  
202      /* Enable SD Error interrupts */
203  #if defined(SDIO_STA_STBITERR)
204 -    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
205 +    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
206  #else /* SDIO_STA_STBITERR not defined */
207 -    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));   
208 +    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND));
209  #endif /* SDIO_STA_STBITERR */
210  
211      /* Set the DMA transfer complete callback */
212 +    // This callback now doesn't do anything - enabling DATAEND interrupt is set above to avoid race conditions
213      hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
214  
215      /* Set the DMA error callback */
216 @@ -1367,17 +1383,17 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
217      if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
218      {
219        add *= 512U;
220 -    }
221  
222 -    /* Set Block Size for Card */
223 -    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
224 -    if(errorstate != HAL_SD_ERROR_NONE)
225 -    {
226 -      /* Clear all the static flags */
227 -      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
228 -      hsd->ErrorCode |= errorstate;
229 -      hsd->State = HAL_SD_STATE_READY;
230 -      return HAL_ERROR;
231 +      /* Set Block Size for Card */
232 +      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
233 +      if(errorstate != HAL_SD_ERROR_NONE)
234 +      {
235 +        /* Clear all the static flags */
236 +        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
237 +        hsd->ErrorCode |= errorstate;
238 +        hsd->State = HAL_SD_STATE_READY;
239 +        return HAL_ERROR;
240 +      }
241      }
242  
243      /* Write Blocks in Polling mode */
244 @@ -1405,11 +1421,59 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
245        return HAL_ERROR;
246      }
247  
248 -    /* Enable SDIO DMA transfer */
249 -    __HAL_SD_DMA_ENABLE(hsd);
250 +    return HAL_OK;
251 +  }
252 +  else
253 +  {
254 +    return HAL_BUSY;
255 +  }
256 +}
257 +
258 +/**
259 +  * @brief  Writes block(s) to a specified address in a card. The Data transfer
260 +  *         is managed by DMA mode.
261 +  * @note   This API should be followed by a check on the card state through
262 +  *         HAL_SD_GetCardState().
263 +  * @note   You could also check the DMA transfer process through the SD Tx
264 +  *         interrupt event.
265 +  * @param  hsd: Pointer to SD handle
266 +  * @param  pData: Pointer to the buffer that will contain the data to transmit
267 +  * @param  BlockAdd: Block Address where data will be written
268 +  * @param  NumberOfBlocks: Number of blocks to write
269 +  * @retval HAL status
270 +  */
271 +HAL_StatusTypeDef HAL_SD_WriteBlocks_Data(SD_HandleTypeDef *hsd, uint8_t *pData)
272 +{
273 +  SDIO_DataInitTypeDef config;
274 +
275 +  if(hsd->State == HAL_SD_STATE_READY)
276 +  {
277 +    hsd->ErrorCode = HAL_SD_ERROR_NONE;
278 +
279 +    hsd->State = HAL_SD_STATE_BUSY;
280 +
281 +    /* Initialize data control register */
282 +    hsd->Instance->DCTRL = 0U;
283 +
284 +    /* Enable SD Error interrupts */
285 +#if defined(SDIO_STA_STBITERR)
286 +    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
287 +#else /* SDIO_STA_STBITERR not defined */
288 +    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND));
289 +#endif /* SDIO_STA_STBITERR */
290 +
291 +    /* Set the DMA transfer complete callback */
292 +    // This callback now doesn't do anything - enabling DATAEND interrupt is set above to avoid race conditions
293 +    hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
294 +
295 +    /* Set the DMA error callback */
296 +    hsd->hdmatx->XferErrorCallback = SD_DMAError;
297 +
298 +    /* Set the DMA Abort callback */
299 +    hsd->hdmatx->XferAbortCallback = NULL;
300  
301      /* Enable the DMA Channel */
302 -    if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
303 +    if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE)/4U) != HAL_OK)
304      {
305  #if defined(SDIO_STA_STBITERR)
306        __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
307 @@ -1426,11 +1490,16 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
308      {
309        /* Configure the SD DPSM (Data Path State Machine) */
310        config.DataTimeOut   = SDMMC_DATATIMEOUT;
311 -      config.DataLength    = BLOCKSIZE * NumberOfBlocks;
312 +      config.DataLength    = BLOCKSIZE;
313        config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
314        config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
315        config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
316        config.DPSM          = SDIO_DPSM_ENABLE;
317 +
318 +      // We cannot enable DMA too early on UHS-I class 3 SD cards, or else the
319 +      // data is just discarded before the dpsm is started.
320 +      __HAL_SD_DMA_ENABLE();
321 +
322        (void)SDIO_ConfigData(hsd->Instance, &config);
323  
324        return HAL_OK;
325 @@ -1622,16 +1691,8 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
326      {
327        if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
328        {
329 -        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
330 -        if(errorstate != HAL_SD_ERROR_NONE)
331 -        {
332 -          hsd->ErrorCode |= errorstate;
333 -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
334 -          hsd->ErrorCallback(hsd);
335 -#else
336 -          HAL_SD_ErrorCallback(hsd);
337 -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
338 -        }
339 +        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
340 +        __HAL_SD_DMA_DISABLE(hsd);
341        }
342        if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
343        {
344 @@ -2407,7 +2468,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
345    hsd->Context = SD_CONTEXT_NONE;
346  
347    CardState = HAL_SD_GetCardState(hsd);
348 -  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
349 +  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING) || (CardState == HAL_SD_CARD_PROGRAMMING))
350    {
351      hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
352    }
353 @@ -2513,10 +2574,12 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
354    */
355  static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
356  {
357 -  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
358 +  // SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
359  
360    /* Enable DATAEND Interrupt */
361 -  __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
362 +  //WHAT IF IT ALREADY TRIGGERED ? Maybe it can't due to interrupt priorities ?
363 +  // Easier to just ignore it.
364 +  //  __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
365  }
366  
367  /**
368 diff --git a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c
369 index 4f23a45..614b6dc 100644
370 --- a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c
371 +++ b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c
372 @@ -606,6 +606,31 @@ uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
373    return errorstate;
374  }
375  
376 +/**
377 +  * @brief  Set the count of a multi-block write command
378 +  * @param  SDIOx: Pointer to SDIO register base 
379 +  * @retval HAL status
380 +  */
381 +uint32_t SDMMC_CmdSetBlockCount(SDIO_TypeDef *SDIOx, uint32_t appCmdArg, uint32_t blockCount)
382 +{
383 +  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
384 +  uint32_t errorstate;
385 +  
386 +  errorstate = SDMMC_CmdAppCommand(SDIOx, appCmdArg);
387 +  if(errorstate == HAL_SD_ERROR_NONE)
388 +  {
389 +    sdmmc_cmdinit.Argument         = blockCount;
390 +    sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCK_COUNT;
391 +    sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
392 +    sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
393 +    sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
394 +    (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
395 +    errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCK_COUNT, SDIO_CMDTIMEOUT);
396 +  }
397 +
398 +  return errorstate;
399 +}
400 +
401  /**
402    * @brief  Send the Write Multi Block command and check the response
403    * @param  SDIOx: Pointer to SDIO register base 
404 diff --git a/STM32CubeMX/2021/Src/fmc.c b/STM32CubeMX/2021/Src/fmc.c
405 index dae179a..a527167 100644
406 --- a/STM32CubeMX/2021/Src/fmc.c
407 +++ b/STM32CubeMX/2021/Src/fmc.c
408 @@ -49,15 +49,33 @@ void MX_FMC_Init(void)
409    hsram1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
410    hsram1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
411    hsram1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
412 -  hsram1.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE;
413 +  hsram1.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE;
414 +
415    hsram1.Init.PageSize = FMC_PAGE_SIZE_NONE;
416    /* Timing */
417 -  Timing.AddressSetupTime = 2;
418 -  Timing.AddressHoldTime = 1;
419 -  Timing.DataSetupTime = 4;
420 -  Timing.BusTurnAroundDuration = 1;
421 -  Timing.CLKDivision = 16;
422 -  Timing.DataLatency = 17;
423 +
424 +  // 1 clock to read the address, + 2 for synchroniser skew
425 +  Timing.AddressSetupTime = 6;
426 +  Timing.AddressHoldTime = 2;
427 +
428 +  // Writes to device:
429 +  //   2 for synchroniser skew (dbx also delayed)
430 +  //   1 to skip hold time
431 +  //   1 to write data.
432 +
433 +  // Reads from device:
434 +  //   1 to skip hold time
435 +  //   2 for synchroniser skew on OE
436 +  //   1 to write back to fsmc bus.
437 +  Timing.DataSetupTime = 8;
438 +
439 +  // Allow a clock for us to release signals
440 +  // Need to avoid both devices acting as outputs
441 +  // on the multiplexed lines at the same time.
442 +  Timing.BusTurnAroundDuration = 2;
443 +
444 +  Timing.CLKDivision = 16; // Ignored for async
445 +  Timing.DataLatency = 17; // Ignored for async
446    Timing.AccessMode = FMC_ACCESS_MODE_A;
447    /* ExtTiming */
448  
449 @@ -107,6 +125,10 @@ static void HAL_FMC_MspInit(void){
450    PE0   ------> FMC_NBL0
451    PE1   ------> FMC_NBL1
452    */
453 +
454 +  // MM: GPIO_SPEED_FREQ_MEDIUM is rated up to 50MHz, which is fine as all the
455 +  // fsmc timings are > 1 (ie. so clock speed / 2 is around 50MHz).
456 +
457    /* GPIO_InitStruct */
458    GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 
459                            |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14