Add all phase bits to a control register for atomic phase changes.
[SCSI2SD-V6.git] / software / SCSI2SD / SCSI2SD.cydsn / Generated_Source / PSoC5 / cyfitter_cfg.c
1 /*******************************************************************************\r
2 * FILENAME: cyfitter_cfg.c\r
3 * PSoC Creator 3.0 Component Pack 7\r
4 *\r
5 * Description:\r
6 * This file is automatically generated by PSoC Creator with device \r
7 * initialization code.  Except for the user defined sections in\r
8 * CyClockStartupError(), this file should not be modified.\r
9 *\r
10 ********************************************************************************\r
11 * Copyright 2013, Cypress Semiconductor Corporation.  All rights reserved.\r
12 * You may use this file only in accordance with the license, terms, conditions, \r
13 * disclaimers, and limitations in the end user license agreement accompanying \r
14 * the software package with which this file was provided.\r
15 ********************************************************************************/\r
16 \r
17 #include <string.h>\r
18 #include <cytypes.h>\r
19 #include <cydevice_trm.h>\r
20 #include <cyfitter.h>\r
21 #include <CyLib.h>\r
22 #include <cyfitter_cfg.h>\r
23 \r
24 #define CY_NEED_CYCLOCKSTARTUPERROR 1\r
25 \r
26 \r
27 #if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
28     #define CYPACKED \r
29     #define CYPACKED_ATTR __attribute__ ((packed))\r
30     #define CYALIGNED __attribute__ ((aligned))\r
31     #define CY_CFG_UNUSED __attribute__ ((unused))\r
32     #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))\r
33     \r
34     #if defined(__ARMCC_VERSION)\r
35         #define CY_CFG_MEMORY_BARRIER() __memory_changed()\r
36     #else\r
37         #define CY_CFG_MEMORY_BARRIER() __sync_synchronize()\r
38     #endif\r
39     \r
40 #elif defined(__ICCARM__)\r
41     #include <intrinsics.h>\r
42 \r
43     #define CYPACKED __packed\r
44     #define CYPACKED_ATTR \r
45     #define CYALIGNED _Pragma("data_alignment=4")\r
46     #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")\r
47     #define CY_CFG_SECTION _Pragma("location=\".psocinit\"")\r
48     \r
49     #define CY_CFG_MEMORY_BARRIER() __DMB()\r
50     \r
51 #else\r
52     #error Unsupported toolchain\r
53 #endif\r
54 \r
55 \r
56 CY_CFG_UNUSED\r
57 static void CYMEMZERO(void *s, size_t n);\r
58 CY_CFG_UNUSED\r
59 static void CYMEMZERO(void *s, size_t n)\r
60 {\r
61         (void)memset(s, 0, n);\r
62 }\r
63 CY_CFG_UNUSED\r
64 static void CYCONFIGCPY(void *dest, const void *src, size_t n);\r
65 CY_CFG_UNUSED\r
66 static void CYCONFIGCPY(void *dest, const void *src, size_t n)\r
67 {\r
68         (void)memcpy(dest, src, n);\r
69 }\r
70 CY_CFG_UNUSED\r
71 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);\r
72 CY_CFG_UNUSED\r
73 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)\r
74 {\r
75         (void)memcpy(dest, src, n);\r
76 }\r
77 \r
78 \r
79 \r
80 /* Clock startup error codes                                                   */\r
81 #define CYCLOCKSTART_NO_ERROR    0u\r
82 #define CYCLOCKSTART_XTAL_ERROR  1u\r
83 #define CYCLOCKSTART_32KHZ_ERROR 2u\r
84 #define CYCLOCKSTART_PLL_ERROR   3u\r
85 \r
86 #ifdef CY_NEED_CYCLOCKSTARTUPERROR\r
87 /*******************************************************************************\r
88 * Function Name: CyClockStartupError\r
89 ********************************************************************************\r
90 * Summary:\r
91 *  If an error is encountered during clock configuration (crystal startup error,\r
92 *  PLL lock error, etc.), the system will end up here.  Unless reimplemented by\r
93 *  the customer, this function will stop in an infinite loop.\r
94 *\r
95 * Parameters:\r
96 *   void\r
97 *\r
98 * Return:\r
99 *   void\r
100 *\r
101 *******************************************************************************/\r
102 CY_CFG_UNUSED\r
103 static void CyClockStartupError(uint8 errorCode);\r
104 CY_CFG_UNUSED\r
105 static void CyClockStartupError(uint8 errorCode)\r
106 {\r
107     /* To remove the compiler warning if errorCode not used.                */\r
108     errorCode = errorCode;\r
109 \r
110     /* `#START CyClockStartupError` */\r
111 \r
112     /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */\r
113     /* we will end up here to allow the customer to implement something to  */\r
114     /* deal with the clock condition.                                       */\r
115 \r
116     /* `#END` */\r
117 \r
118     /* If nothing else, stop here since the clocks have not started         */\r
119     /* correctly.                                                           */\r
120     while(1) {}\r
121 }\r
122 #endif\r
123 \r
124 #define CY_CFG_BASE_ADDR_COUNT 33u\r
125 CYPACKED typedef struct\r
126 {\r
127         uint8 offset;\r
128         uint8 value;\r
129 } CYPACKED_ATTR cy_cfg_addrvalue_t;\r
130 \r
131 \r
132 \r
133 /*******************************************************************************\r
134 * Function Name: cfg_write_bytes32\r
135 ********************************************************************************\r
136 * Summary:\r
137 *  This function is used for setting up the chip configuration areas that\r
138 *  contain relatively sparse data.\r
139 *\r
140 * Parameters:\r
141 *   void\r
142 *\r
143 * Return:\r
144 *   void\r
145 *\r
146 *******************************************************************************/\r
147 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]);\r
148 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[])\r
149 {\r
150         /* For 32-bit little-endian architectures */\r
151         uint32 i, j = 0u;\r
152         for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++)\r
153         {\r
154                 uint32 baseAddr = addr_table[i];\r
155                 uint8 count = (uint8)baseAddr;\r
156                 baseAddr &= 0xFFFFFF00u;\r
157                 while (count != 0u)\r
158                 {\r
159                         CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value);\r
160                         j++;\r
161                         count--;\r
162                 }\r
163         }\r
164 }\r
165 \r
166 /*******************************************************************************\r
167 * Function Name: ClockSetup\r
168 ********************************************************************************\r
169 *\r
170 * Summary:\r
171 *  Performs the initialization of all of the clocks in the device based on the\r
172 *  settings in the Clock tab of the DWR.  This includes enabling the requested\r
173 *  clocks and setting the necessary dividers to produce the desired frequency. \r
174 *\r
175 * Parameters:\r
176 *  void\r
177 *\r
178 * Return:\r
179 *  void\r
180 *\r
181 *******************************************************************************/\r
182 static void ClockSetup(void);\r
183 static void ClockSetup(void)\r
184 {\r
185         uint32 timeout;\r
186         uint8 pllLock;\r
187 \r
188 \r
189         /* Configure Digital Clocks based on settings from Clock DWR */\r
190         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0001u);\r
191         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x10u);\r
192         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u);\r
193         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u);\r
194         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x001Du);\r
195         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);\r
196 \r
197         /* Configure ILO based on settings from Clock DWR */\r
198         CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);\r
199 \r
200         /* Configure IMO based on settings from Clock DWR */\r
201         CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u);\r
202         CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));\r
203 \r
204         /* Configure PLL based on settings from Clock DWR */\r
205         CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0919u);\r
206         CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);\r
207         /* Wait up to 250us for the PLL to lock */\r
208         pllLock = 0u;\r
209         for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--)\r
210         { \r
211                 pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));\r
212                 CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */\r
213         }\r
214         /* If we ran out of time the PLL didn't lock so go to the error function */\r
215         if (timeout == 0u)\r
216         {\r
217                 CyClockStartupError(CYCLOCKSTART_PLL_ERROR);\r
218         }\r
219 \r
220         /* Configure Bus/Master Clock based on settings from Clock DWR */\r
221         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);\r
222         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u);\r
223         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u);\r
224         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u);\r
225         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u);\r
226 \r
227         /* Configure USB Clock based on settings from Clock DWR */\r
228         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);\r
229         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);\r
230 \r
231         CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x06u)));\r
232 }\r
233 \r
234 \r
235 /* Analog API Functions */\r
236 \r
237 \r
238 /*******************************************************************************\r
239 * Function Name: AnalogSetDefault\r
240 ********************************************************************************\r
241 *\r
242 * Summary:\r
243 *  Sets up the analog portions of the chip to default values based on chip\r
244 *  configuration options from the project.\r
245 *\r
246 * Parameters:\r
247 *  void\r
248 *\r
249 * Return:\r
250 *  void\r
251 *\r
252 *******************************************************************************/\r
253 static void AnalogSetDefault(void);\r
254 static void AnalogSetDefault(void)\r
255 {\r
256         uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));\r
257         CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));\r
258         CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));\r
259         CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);\r
260 }\r
261 \r
262 \r
263 /*******************************************************************************\r
264 * Function Name: SetAnalogRoutingPumps\r
265 ********************************************************************************\r
266 *\r
267 * Summary:\r
268 * Enables or disables the analog pumps feeding analog routing switches.\r
269 * Intended to be called at startup, based on the Vdda system configuration;\r
270 * may be called during operation when the user informs us that the Vdda voltage\r
271 * crossed the pump threshold.\r
272 *\r
273 * Parameters:\r
274 *  enabled - 1 to enable the pumps, 0 to disable the pumps\r
275 *\r
276 * Return:\r
277 *  void\r
278 *\r
279 *******************************************************************************/\r
280 void SetAnalogRoutingPumps(uint8 enabled)\r
281 {\r
282         uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0);\r
283         if (enabled != 0u)\r
284         {\r
285                 regValue |= 0x00u;\r
286         }\r
287         else\r
288         {\r
289                 regValue &= (uint8)~0x00u;\r
290         }\r
291         CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);\r
292 }\r
293 \r
294 #define CY_AMUX_UNUSED CYREG_BOOST_SR\r
295 \r
296 \r
297 /*******************************************************************************\r
298 * Function Name: cyfitter_cfg\r
299 ********************************************************************************\r
300 * Summary:\r
301 *  This function is called by the start-up code for the selected device. It\r
302 *  performs all of the necessary device configuration based on the design\r
303 *  settings.  This includes settings from the Design Wide Resources (DWR) such\r
304 *  as Clocks and Pins as well as any component configuration that is necessary.\r
305 *\r
306 * Parameters:  \r
307 *   void\r
308 *\r
309 * Return:\r
310 *   void\r
311 *\r
312 *******************************************************************************/\r
313 \r
314 void cyfitter_cfg(void)\r
315 {\r
316         /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */\r
317         static const uint8 CYCODE BS_IOPINS0_0_VAL[] = {\r
318                 0x00u, 0xFFu, 0xFFu, 0x00u, 0x17u, 0x00u, 0x00u, 0x00u};\r
319 \r
320         /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */\r
321         static const uint8 CYCODE BS_IOPINS0_7_VAL[] = {\r
322                 0x08u, 0x00u, 0x30u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
323 \r
324         /* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */\r
325         static const uint8 CYCODE BS_IOPINS1_7_VAL[] = {\r
326                 0x00u, 0x00u, 0x00u, 0x00u, 0x10u};\r
327 \r
328         /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */\r
329         static const uint8 CYCODE BS_IOPINS0_8_VAL[] = {\r
330                 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u};\r
331 \r
332         /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */\r
333         static const uint8 CYCODE BS_IOPINS0_2_VAL[] = {\r
334                 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u};\r
335 \r
336         /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */\r
337         static const uint8 CYCODE BS_IOPINS0_3_VAL[] = {\r
338                 0x10u, 0x00u, 0x63u, 0x1Cu, 0x1Cu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u};\r
339 \r
340         /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */\r
341         static const uint8 CYCODE BS_IOPINS0_4_VAL[] = {\r
342                 0x00u, 0xFCu, 0xFCu, 0x00u, 0xF8u, 0x00u, 0x00u, 0x00u};\r
343 \r
344         /* IOPINS0_5 Address: CYREG_PRT5_DM0 Size (bytes): 8 */\r
345         static const uint8 CYCODE BS_IOPINS0_5_VAL[] = {\r
346                 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u};\r
347 \r
348         /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */\r
349         static const uint8 CYCODE BS_IOPINS0_6_VAL[] = {\r
350                 0xF0u, 0x0Fu, 0x0Fu, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x01u};\r
351 \r
352 #ifdef CYGlobalIntDisable\r
353         /* Disable interrupts by default. Let user enable if/when they want. */\r
354         CYGlobalIntDisable\r
355 #endif\r
356 \r
357 \r
358         /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */\r
359         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));\r
360         /* Setup clocks based on selections from Clock DWR */\r
361         ClockSetup();\r
362         /* Enable/Disable Debug functionality based on settings from System DWR */\r
363         CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u));\r
364 \r
365         {\r
366                 static const uint32 CYCODE cy_cfg_addr_table[] = {\r
367                         0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
368                         0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
369                         0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
370                         0x40010048u, /* Base address: 0x40010000 Count: 72 */\r
371                         0x4001012Cu, /* Base address: 0x40010100 Count: 44 */\r
372                         0x40010235u, /* Base address: 0x40010200 Count: 53 */\r
373                         0x4001034Fu, /* Base address: 0x40010300 Count: 79 */\r
374                         0x40010448u, /* Base address: 0x40010400 Count: 72 */\r
375                         0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
376                         0x40010606u, /* Base address: 0x40010600 Count: 6 */\r
377                         0x40010747u, /* Base address: 0x40010700 Count: 71 */\r
378                         0x40010901u, /* Base address: 0x40010900 Count: 1 */\r
379                         0x40010B0Cu, /* Base address: 0x40010B00 Count: 12 */\r
380                         0x40010C3Bu, /* Base address: 0x40010C00 Count: 59 */\r
381                         0x40010D39u, /* Base address: 0x40010D00 Count: 57 */\r
382                         0x40010F04u, /* Base address: 0x40010F00 Count: 4 */\r
383                         0x40011504u, /* Base address: 0x40011500 Count: 4 */\r
384                         0x4001164Du, /* Base address: 0x40011600 Count: 77 */\r
385                         0x4001173Fu, /* Base address: 0x40011700 Count: 63 */\r
386                         0x40011901u, /* Base address: 0x40011900 Count: 1 */\r
387                         0x4001400Cu, /* Base address: 0x40014000 Count: 12 */\r
388                         0x4001410Fu, /* Base address: 0x40014100 Count: 15 */\r
389                         0x4001420Bu, /* Base address: 0x40014200 Count: 11 */\r
390                         0x40014306u, /* Base address: 0x40014300 Count: 6 */\r
391                         0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
392                         0x40014513u, /* Base address: 0x40014500 Count: 19 */\r
393                         0x4001460Au, /* Base address: 0x40014600 Count: 10 */\r
394                         0x40014703u, /* Base address: 0x40014700 Count: 3 */\r
395                         0x4001480Du, /* Base address: 0x40014800 Count: 13 */\r
396                         0x40014908u, /* Base address: 0x40014900 Count: 8 */\r
397                         0x40014C02u, /* Base address: 0x40014C00 Count: 2 */\r
398                         0x4001500Au, /* Base address: 0x40015000 Count: 10 */\r
399                         0x40015101u, /* Base address: 0x40015100 Count: 1 */\r
400                 };\r
401 \r
402                 static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
403                         {0x36u, 0x02u},\r
404                         {0x7Eu, 0x02u},\r
405                         {0x00u, 0x12u},\r
406                         {0x01u, 0x01u},\r
407                         {0x18u, 0x04u},\r
408                         {0x19u, 0x08u},\r
409                         {0x1Cu, 0x61u},\r
410                         {0x20u, 0xA8u},\r
411                         {0x21u, 0xC8u},\r
412                         {0x30u, 0x03u},\r
413                         {0x31u, 0x06u},\r
414                         {0x7Cu, 0x40u},\r
415                         {0x33u, 0x01u},\r
416                         {0x87u, 0x0Fu},\r
417                         {0x03u, 0x08u},\r
418                         {0x04u, 0x21u},\r
419                         {0x06u, 0x42u},\r
420                         {0x07u, 0x40u},\r
421                         {0x08u, 0x42u},\r
422                         {0x0Au, 0x28u},\r
423                         {0x0Bu, 0x48u},\r
424                         {0x0Cu, 0x0Du},\r
425                         {0x0Fu, 0x06u},\r
426                         {0x10u, 0x02u},\r
427                         {0x11u, 0x01u},\r
428                         {0x12u, 0x0Du},\r
429                         {0x14u, 0x22u},\r
430                         {0x15u, 0x48u},\r
431                         {0x16u, 0x84u},\r
432                         {0x17u, 0x12u},\r
433                         {0x18u, 0xC0u},\r
434                         {0x1Bu, 0x30u},\r
435                         {0x1Cu, 0x0Du},\r
436                         {0x1Du, 0x01u},\r
437                         {0x20u, 0x0Du},\r
438                         {0x21u, 0x48u},\r
439                         {0x23u, 0x24u},\r
440                         {0x24u, 0x0Du},\r
441                         {0x25u, 0x01u},\r
442                         {0x28u, 0x0Du},\r
443                         {0x29u, 0x01u},\r
444                         {0x2Cu, 0x10u},\r
445                         {0x30u, 0x0Fu},\r
446                         {0x33u, 0x01u},\r
447                         {0x34u, 0xE0u},\r
448                         {0x35u, 0x70u},\r
449                         {0x36u, 0x10u},\r
450                         {0x37u, 0x0Eu},\r
451                         {0x38u, 0x20u},\r
452                         {0x39u, 0x08u},\r
453                         {0x3Au, 0x02u},\r
454                         {0x3Eu, 0x40u},\r
455                         {0x3Fu, 0x04u},\r
456                         {0x58u, 0x0Bu},\r
457                         {0x59u, 0x04u},\r
458                         {0x5Cu, 0x19u},\r
459                         {0x5Fu, 0x01u},\r
460                         {0x83u, 0x04u},\r
461                         {0x84u, 0x02u},\r
462                         {0x87u, 0x10u},\r
463                         {0x8Cu, 0x01u},\r
464                         {0x8Eu, 0x02u},\r
465                         {0x8Fu, 0x08u},\r
466                         {0x90u, 0x07u},\r
467                         {0x95u, 0x01u},\r
468                         {0x97u, 0x04u},\r
469                         {0x99u, 0x01u},\r
470                         {0x9Bu, 0x02u},\r
471                         {0xA0u, 0x02u},\r
472                         {0xA1u, 0x06u},\r
473                         {0xA3u, 0x01u},\r
474                         {0xA4u, 0x06u},\r
475                         {0xAAu, 0x05u},\r
476                         {0xABu, 0x07u},\r
477                         {0xADu, 0x08u},\r
478                         {0xAEu, 0x07u},\r
479                         {0xAFu, 0x10u},\r
480                         {0xB3u, 0x07u},\r
481                         {0xB6u, 0x07u},\r
482                         {0xB7u, 0x18u},\r
483                         {0xBFu, 0x40u},\r
484                         {0xD8u, 0x04u},\r
485                         {0xD9u, 0x04u},\r
486                         {0xDBu, 0x04u},\r
487                         {0xDCu, 0x11u},\r
488                         {0xDFu, 0x01u},\r
489                         {0x00u, 0x20u},\r
490                         {0x03u, 0x21u},\r
491                         {0x05u, 0x08u},\r
492                         {0x06u, 0x01u},\r
493                         {0x08u, 0x40u},\r
494                         {0x0Au, 0x64u},\r
495                         {0x0Fu, 0x80u},\r
496                         {0x10u, 0x88u},\r
497                         {0x11u, 0x04u},\r
498                         {0x12u, 0x02u},\r
499                         {0x16u, 0x42u},\r
500                         {0x17u, 0x24u},\r
501                         {0x19u, 0x80u},\r
502                         {0x1Au, 0x44u},\r
503                         {0x1Fu, 0x80u},\r
504                         {0x21u, 0x68u},\r
505                         {0x24u, 0x20u},\r
506                         {0x26u, 0x44u},\r
507                         {0x27u, 0x20u},\r
508                         {0x28u, 0x08u},\r
509                         {0x2Au, 0x04u},\r
510                         {0x2Bu, 0xC0u},\r
511                         {0x2Du, 0x40u},\r
512                         {0x2Fu, 0x84u},\r
513                         {0x30u, 0x02u},\r
514                         {0x31u, 0x20u},\r
515                         {0x33u, 0x44u},\r
516                         {0x37u, 0x24u},\r
517                         {0x38u, 0x20u},\r
518                         {0x39u, 0x89u},\r
519                         {0x3Du, 0x80u},\r
520                         {0x3Fu, 0x09u},\r
521                         {0x6Du, 0x40u},\r
522                         {0x78u, 0x01u},\r
523                         {0x81u, 0x2Cu},\r
524                         {0x8Eu, 0x05u},\r
525                         {0xC0u, 0xA7u},\r
526                         {0xC2u, 0x1Fu},\r
527                         {0xC4u, 0xFFu},\r
528                         {0xCAu, 0xB7u},\r
529                         {0xCCu, 0x6Fu},\r
530                         {0xCEu, 0xDFu},\r
531                         {0xDEu, 0x01u},\r
532                         {0xE0u, 0x04u},\r
533                         {0x05u, 0x01u},\r
534                         {0x37u, 0x01u},\r
535                         {0x3Fu, 0x40u},\r
536                         {0x59u, 0x04u},\r
537                         {0x5Bu, 0x04u},\r
538                         {0x5Fu, 0x01u},\r
539                         {0x80u, 0x01u},\r
540                         {0x83u, 0x04u},\r
541                         {0x85u, 0x80u},\r
542                         {0x88u, 0x04u},\r
543                         {0x8Bu, 0x24u},\r
544                         {0x8Fu, 0x20u},\r
545                         {0x93u, 0x18u},\r
546                         {0x95u, 0x24u},\r
547                         {0x97u, 0x09u},\r
548                         {0x9Fu, 0x03u},\r
549                         {0xA1u, 0x24u},\r
550                         {0xA3u, 0x12u},\r
551                         {0xA9u, 0x40u},\r
552                         {0xACu, 0x02u},\r
553                         {0xB0u, 0x01u},\r
554                         {0xB1u, 0x38u},\r
555                         {0xB3u, 0x40u},\r
556                         {0xB4u, 0x04u},\r
557                         {0xB5u, 0x80u},\r
558                         {0xB6u, 0x02u},\r
559                         {0xB7u, 0x07u},\r
560                         {0xBEu, 0x51u},\r
561                         {0xBFu, 0x14u},\r
562                         {0xC0u, 0x61u},\r
563                         {0xC1u, 0x03u},\r
564                         {0xC2u, 0x20u},\r
565                         {0xC5u, 0x2Cu},\r
566                         {0xC6u, 0x0Du},\r
567                         {0xC7u, 0xFEu},\r
568                         {0xC8u, 0x37u},\r
569                         {0xC9u, 0xFFu},\r
570                         {0xCAu, 0xFFu},\r
571                         {0xCBu, 0xFFu},\r
572                         {0xCFu, 0x2Cu},\r
573                         {0xD6u, 0x01u},\r
574                         {0xD8u, 0x04u},\r
575                         {0xD9u, 0x04u},\r
576                         {0xDAu, 0x04u},\r
577                         {0xDBu, 0x04u},\r
578                         {0xDCu, 0x10u},\r
579                         {0xDDu, 0x01u},\r
580                         {0xDFu, 0x01u},\r
581                         {0xE2u, 0xC0u},\r
582                         {0xE6u, 0x80u},\r
583                         {0xE8u, 0x40u},\r
584                         {0xE9u, 0x40u},\r
585                         {0xEEu, 0x08u},\r
586                         {0x01u, 0x02u},\r
587                         {0x03u, 0x08u},\r
588                         {0x12u, 0x02u},\r
589                         {0x19u, 0x51u},\r
590                         {0x21u, 0x09u},\r
591                         {0x22u, 0x81u},\r
592                         {0x23u, 0x08u},\r
593                         {0x27u, 0x02u},\r
594                         {0x2Au, 0x20u},\r
595                         {0x2Bu, 0x80u},\r
596                         {0x32u, 0x81u},\r
597                         {0x33u, 0x04u},\r
598                         {0x38u, 0x08u},\r
599                         {0x39u, 0x40u},\r
600                         {0x3Au, 0x02u},\r
601                         {0x3Bu, 0x10u},\r
602                         {0x3Eu, 0x08u},\r
603                         {0x43u, 0x94u},\r
604                         {0x49u, 0x08u},\r
605                         {0x4Au, 0x04u},\r
606                         {0x4Bu, 0x11u},\r
607                         {0x51u, 0x02u},\r
608                         {0x52u, 0x48u},\r
609                         {0x59u, 0x90u},\r
610                         {0x5Bu, 0x0Au},\r
611                         {0x60u, 0x04u},\r
612                         {0x61u, 0x49u},\r
613                         {0x69u, 0x59u},\r
614                         {0x6Cu, 0x20u},\r
615                         {0x6Eu, 0x20u},\r
616                         {0x6Fu, 0x02u},\r
617                         {0x72u, 0x92u},\r
618                         {0x73u, 0x04u},\r
619                         {0x81u, 0x0Au},\r
620                         {0x82u, 0x28u},\r
621                         {0x85u, 0x01u},\r
622                         {0x86u, 0x10u},\r
623                         {0x88u, 0x20u},\r
624                         {0x89u, 0x02u},\r
625                         {0x8Au, 0x40u},\r
626                         {0x8Eu, 0x08u},\r
627                         {0x8Fu, 0x40u},\r
628                         {0x91u, 0x80u},\r
629                         {0x92u, 0x04u},\r
630                         {0x93u, 0x08u},\r
631                         {0x95u, 0x0Du},\r
632                         {0x96u, 0x20u},\r
633                         {0x97u, 0x01u},\r
634                         {0x99u, 0x80u},\r
635                         {0x9Bu, 0x20u},\r
636                         {0x9Cu, 0x49u},\r
637                         {0x9Du, 0x0Cu},\r
638                         {0x9Eu, 0x40u},\r
639                         {0x9Fu, 0x45u},\r
640                         {0xA2u, 0x44u},\r
641                         {0xA3u, 0x80u},\r
642                         {0xA4u, 0x98u},\r
643                         {0xA5u, 0x41u},\r
644                         {0xA7u, 0x24u},\r
645                         {0xA8u, 0x02u},\r
646                         {0xA9u, 0x01u},\r
647                         {0xAEu, 0x02u},\r
648                         {0xAFu, 0x04u},\r
649                         {0xB2u, 0x02u},\r
650                         {0xC0u, 0x0Au},\r
651                         {0xC4u, 0x01u},\r
652                         {0xCAu, 0x05u},\r
653                         {0xCCu, 0x0Bu},\r
654                         {0xCEu, 0x4Fu},\r
655                         {0xD0u, 0x0Eu},\r
656                         {0xD2u, 0x04u},\r
657                         {0xD6u, 0x0Fu},\r
658                         {0xD8u, 0x0Fu},\r
659                         {0xE0u, 0x01u},\r
660                         {0xE2u, 0x04u},\r
661                         {0xE4u, 0x06u},\r
662                         {0xE6u, 0x21u},\r
663                         {0xEAu, 0x04u},\r
664                         {0xEEu, 0x08u},\r
665                         {0x01u, 0x01u},\r
666                         {0x04u, 0x21u},\r
667                         {0x05u, 0x01u},\r
668                         {0x06u, 0x02u},\r
669                         {0x0Au, 0x01u},\r
670                         {0x0Bu, 0x08u},\r
671                         {0x0Fu, 0x06u},\r
672                         {0x13u, 0x01u},\r
673                         {0x14u, 0x04u},\r
674                         {0x15u, 0x01u},\r
675                         {0x16u, 0x43u},\r
676                         {0x18u, 0xE0u},\r
677                         {0x19u, 0x08u},\r
678                         {0x1Bu, 0x02u},\r
679                         {0x1Du, 0x01u},\r
680                         {0x1Eu, 0xECu},\r
681                         {0x21u, 0x08u},\r
682                         {0x23u, 0x04u},\r
683                         {0x27u, 0x01u},\r
684                         {0x28u, 0x88u},\r
685                         {0x2Au, 0x03u},\r
686                         {0x2Bu, 0x08u},\r
687                         {0x2Eu, 0x12u},\r
688                         {0x30u, 0xE0u},\r
689                         {0x33u, 0x01u},\r
690                         {0x34u, 0x10u},\r
691                         {0x36u, 0x0Fu},\r
692                         {0x37u, 0x0Eu},\r
693                         {0x3Eu, 0x01u},\r
694                         {0x3Fu, 0x04u},\r
695                         {0x54u, 0x40u},\r
696                         {0x58u, 0x0Bu},\r
697                         {0x59u, 0x04u},\r
698                         {0x5Bu, 0x0Bu},\r
699                         {0x5Cu, 0x19u},\r
700                         {0x5Du, 0x90u},\r
701                         {0x5Fu, 0x01u},\r
702                         {0x80u, 0x18u},\r
703                         {0x82u, 0x60u},\r
704                         {0x83u, 0x30u},\r
705                         {0x84u, 0x28u},\r
706                         {0x86u, 0x53u},\r
707                         {0x87u, 0x40u},\r
708                         {0x8Cu, 0x30u},\r
709                         {0x8Eu, 0x48u},\r
710                         {0x95u, 0x43u},\r
711                         {0x96u, 0x04u},\r
712                         {0x97u, 0x1Cu},\r
713                         {0x9Bu, 0x4Au},\r
714                         {0xA0u, 0x04u},\r
715                         {0xA1u, 0x44u},\r
716                         {0xA2u, 0x02u},\r
717                         {0xA3u, 0x2Bu},\r
718                         {0xA4u, 0x04u},\r
719                         {0xA5u, 0x01u},\r
720                         {0xA6u, 0x01u},\r
721                         {0xAAu, 0x04u},\r
722                         {0xABu, 0x07u},\r
723                         {0xB1u, 0x70u},\r
724                         {0xB2u, 0x07u},\r
725                         {0xB3u, 0x08u},\r
726                         {0xB4u, 0x78u},\r
727                         {0xB5u, 0x07u},\r
728                         {0xBEu, 0x10u},\r
729                         {0xBFu, 0x04u},\r
730                         {0xD6u, 0x08u},\r
731                         {0xD8u, 0x04u},\r
732                         {0xD9u, 0x04u},\r
733                         {0xDBu, 0x04u},\r
734                         {0xDCu, 0x11u},\r
735                         {0xDDu, 0x90u},\r
736                         {0xDFu, 0x01u},\r
737                         {0x01u, 0x20u},\r
738                         {0x03u, 0x20u},\r
739                         {0x04u, 0x80u},\r
740                         {0x05u, 0x05u},\r
741                         {0x0Au, 0x26u},\r
742                         {0x0Eu, 0x10u},\r
743                         {0x12u, 0x01u},\r
744                         {0x13u, 0x10u},\r
745                         {0x15u, 0x01u},\r
746                         {0x17u, 0x24u},\r
747                         {0x19u, 0x20u},\r
748                         {0x1Au, 0x42u},\r
749                         {0x1Cu, 0x08u},\r
750                         {0x1Du, 0x04u},\r
751                         {0x21u, 0x40u},\r
752                         {0x22u, 0x08u},\r
753                         {0x24u, 0x80u},\r
754                         {0x25u, 0x01u},\r
755                         {0x26u, 0x20u},\r
756                         {0x27u, 0x14u},\r
757                         {0x29u, 0x10u},\r
758                         {0x2Au, 0x04u},\r
759                         {0x2Bu, 0x80u},\r
760                         {0x2Cu, 0x20u},\r
761                         {0x2Du, 0x01u},\r
762                         {0x2Fu, 0x84u},\r
763                         {0x30u, 0x48u},\r
764                         {0x32u, 0x20u},\r
765                         {0x33u, 0x41u},\r
766                         {0x34u, 0x10u},\r
767                         {0x35u, 0x10u},\r
768                         {0x37u, 0x24u},\r
769                         {0x39u, 0x94u},\r
770                         {0x3Au, 0x02u},\r
771                         {0x3Du, 0x02u},\r
772                         {0x3Fu, 0x04u},\r
773                         {0x5Eu, 0x80u},\r
774                         {0x61u, 0x20u},\r
775                         {0x62u, 0x08u},\r
776                         {0x63u, 0x01u},\r
777                         {0x64u, 0x01u},\r
778                         {0x67u, 0x02u},\r
779                         {0x78u, 0x01u},\r
780                         {0x81u, 0x40u},\r
781                         {0x82u, 0x40u},\r
782                         {0x85u, 0x40u},\r
783                         {0x8Du, 0x10u},\r
784                         {0x91u, 0x10u},\r
785                         {0x92u, 0x14u},\r
786                         {0x93u, 0x0Cu},\r
787                         {0x94u, 0x04u},\r
788                         {0x95u, 0x04u},\r
789                         {0x96u, 0x20u},\r
790                         {0x9Au, 0x80u},\r
791                         {0x9Bu, 0x20u},\r
792                         {0x9Cu, 0x41u},\r
793                         {0x9Du, 0x04u},\r
794                         {0x9Fu, 0x15u},\r
795                         {0xA0u, 0x20u},\r
796                         {0xA2u, 0x40u},\r
797                         {0xA3u, 0x80u},\r
798                         {0xA4u, 0x98u},\r
799                         {0xA5u, 0x41u},\r
800                         {0xA7u, 0x24u},\r
801                         {0xA9u, 0x40u},\r
802                         {0xAAu, 0x80u},\r
803                         {0xABu, 0x08u},\r
804                         {0xACu, 0x08u},\r
805                         {0xAEu, 0x02u},\r
806                         {0xAFu, 0x02u},\r
807                         {0xB4u, 0x04u},\r
808                         {0xC0u, 0xB6u},\r
809                         {0xC2u, 0x27u},\r
810                         {0xC4u, 0x73u},\r
811                         {0xCAu, 0xE7u},\r
812                         {0xCCu, 0x6Fu},\r
813                         {0xCEu, 0xCFu},\r
814                         {0xD6u, 0x10u},\r
815                         {0xD8u, 0x1Eu},\r
816                         {0xDEu, 0x01u},\r
817                         {0xE0u, 0x01u},\r
818                         {0xE8u, 0x01u},\r
819                         {0xEAu, 0x02u},\r
820                         {0xECu, 0x04u},\r
821                         {0xEEu, 0x09u},\r
822                         {0x17u, 0x01u},\r
823                         {0x1Bu, 0x01u},\r
824                         {0x35u, 0x01u},\r
825                         {0x3Fu, 0x10u},\r
826                         {0x59u, 0x04u},\r
827                         {0x5Fu, 0x01u},\r
828                         {0x01u, 0x02u},\r
829                         {0x03u, 0x29u},\r
830                         {0x09u, 0x08u},\r
831                         {0x0Au, 0x01u},\r
832                         {0x0Bu, 0x04u},\r
833                         {0x11u, 0x25u},\r
834                         {0x12u, 0x01u},\r
835                         {0x18u, 0x04u},\r
836                         {0x19u, 0x80u},\r
837                         {0x1Au, 0x80u},\r
838                         {0x20u, 0x28u},\r
839                         {0x21u, 0x09u},\r
840                         {0x22u, 0x11u},\r
841                         {0x23u, 0x14u},\r
842                         {0x26u, 0x20u},\r
843                         {0x2Au, 0x40u},\r
844                         {0x2Bu, 0x28u},\r
845                         {0x31u, 0x08u},\r
846                         {0x32u, 0x10u},\r
847                         {0x33u, 0x41u},\r
848                         {0x34u, 0x10u},\r
849                         {0x37u, 0x04u},\r
850                         {0x38u, 0x80u},\r
851                         {0x39u, 0x14u},\r
852                         {0x41u, 0x09u},\r
853                         {0x43u, 0x20u},\r
854                         {0x48u, 0x04u},\r
855                         {0x49u, 0x08u},\r
856                         {0x4Bu, 0x80u},\r
857                         {0x50u, 0x01u},\r
858                         {0x51u, 0x20u},\r
859                         {0x52u, 0x45u},\r
860                         {0x61u, 0x10u},\r
861                         {0x68u, 0x08u},\r
862                         {0x69u, 0x15u},\r
863                         {0x6Bu, 0x41u},\r
864                         {0x70u, 0xC0u},\r
865                         {0x72u, 0x03u},\r
866                         {0x78u, 0x01u},\r
867                         {0x8Eu, 0x20u},\r
868                         {0x93u, 0x02u},\r
869                         {0x94u, 0x04u},\r
870                         {0x95u, 0x04u},\r
871                         {0x96u, 0x20u},\r
872                         {0x97u, 0x10u},\r
873                         {0x98u, 0x11u},\r
874                         {0x9Au, 0x80u},\r
875                         {0x9Bu, 0x04u},\r
876                         {0x9Eu, 0x07u},\r
877                         {0x9Fu, 0x41u},\r
878                         {0xA1u, 0x10u},\r
879                         {0xA3u, 0x80u},\r
880                         {0xA4u, 0x98u},\r
881                         {0xA5u, 0x20u},\r
882                         {0xA7u, 0x24u},\r
883                         {0xAAu, 0x04u},\r
884                         {0xABu, 0x01u},\r
885                         {0xACu, 0x04u},\r
886                         {0xB5u, 0x01u},\r
887                         {0xC0u, 0x0Fu},\r
888                         {0xC2u, 0x07u},\r
889                         {0xC4u, 0x0Fu},\r
890                         {0xCAu, 0x0Eu},\r
891                         {0xCCu, 0x6Fu},\r
892                         {0xCEu, 0x0Eu},\r
893                         {0xD0u, 0x07u},\r
894                         {0xD2u, 0x0Cu},\r
895                         {0xD8u, 0x04u},\r
896                         {0xDEu, 0x01u},\r
897                         {0xE2u, 0x10u},\r
898                         {0xECu, 0x42u},\r
899                         {0xAFu, 0x08u},\r
900                         {0x80u, 0x40u},\r
901                         {0x94u, 0x80u},\r
902                         {0xA7u, 0x08u},\r
903                         {0xA8u, 0x28u},\r
904                         {0xA9u, 0x18u},\r
905                         {0xAAu, 0x02u},\r
906                         {0xAFu, 0x80u},\r
907                         {0xE0u, 0x01u},\r
908                         {0xE6u, 0x10u},\r
909                         {0xE8u, 0x01u},\r
910                         {0xEAu, 0x12u},\r
911                         {0xEEu, 0x01u},\r
912                         {0x00u, 0x0Fu},\r
913                         {0x02u, 0xF0u},\r
914                         {0x0Bu, 0xFFu},\r
915                         {0x0Cu, 0x33u},\r
916                         {0x0Eu, 0xCCu},\r
917                         {0x0Fu, 0xFFu},\r
918                         {0x11u, 0x33u},\r
919                         {0x13u, 0xCCu},\r
920                         {0x14u, 0xFFu},\r
921                         {0x18u, 0x96u},\r
922                         {0x19u, 0x55u},\r
923                         {0x1Au, 0x69u},\r
924                         {0x1Bu, 0xAAu},\r
925                         {0x1Cu, 0x55u},\r
926                         {0x1Eu, 0xAAu},\r
927                         {0x21u, 0xFFu},\r
928                         {0x26u, 0xFFu},\r
929                         {0x29u, 0x96u},\r
930                         {0x2Au, 0xFFu},\r
931                         {0x2Bu, 0x69u},\r
932                         {0x2Du, 0x0Fu},\r
933                         {0x2Fu, 0xF0u},\r
934                         {0x35u, 0xFFu},\r
935                         {0x36u, 0xFFu},\r
936                         {0x3Eu, 0x40u},\r
937                         {0x3Fu, 0x10u},\r
938                         {0x58u, 0x04u},\r
939                         {0x59u, 0x04u},\r
940                         {0x5Bu, 0x04u},\r
941                         {0x5Fu, 0x01u},\r
942                         {0x84u, 0xFFu},\r
943                         {0x88u, 0x69u},\r
944                         {0x8Au, 0x96u},\r
945                         {0x8Bu, 0xFFu},\r
946                         {0x8Cu, 0x33u},\r
947                         {0x8Du, 0x33u},\r
948                         {0x8Eu, 0xCCu},\r
949                         {0x8Fu, 0xCCu},\r
950                         {0x91u, 0x0Fu},\r
951                         {0x92u, 0xFFu},\r
952                         {0x93u, 0xF0u},\r
953                         {0x97u, 0xFFu},\r
954                         {0x98u, 0xFFu},\r
955                         {0x99u, 0x55u},\r
956                         {0x9Bu, 0xAAu},\r
957                         {0x9Cu, 0x0Fu},\r
958                         {0x9Eu, 0xF0u},\r
959                         {0xA3u, 0xFFu},\r
960                         {0xA4u, 0x55u},\r
961                         {0xA6u, 0xAAu},\r
962                         {0xA9u, 0x69u},\r
963                         {0xABu, 0x96u},\r
964                         {0xB0u, 0xFFu},\r
965                         {0xB7u, 0xFFu},\r
966                         {0xBEu, 0x01u},\r
967                         {0xBFu, 0x40u},\r
968                         {0xD8u, 0x04u},\r
969                         {0xD9u, 0x04u},\r
970                         {0xDFu, 0x01u},\r
971                         {0x01u, 0x08u},\r
972                         {0x03u, 0x09u},\r
973                         {0x04u, 0x80u},\r
974                         {0x05u, 0x01u},\r
975                         {0x07u, 0x01u},\r
976                         {0x09u, 0x12u},\r
977                         {0x0Bu, 0x02u},\r
978                         {0x0Cu, 0x08u},\r
979                         {0x0Du, 0x80u},\r
980                         {0x0Fu, 0x08u},\r
981                         {0x10u, 0x10u},\r
982                         {0x14u, 0x20u},\r
983                         {0x15u, 0x20u},\r
984                         {0x1Au, 0x80u},\r
985                         {0x1Fu, 0x80u},\r
986                         {0x20u, 0x01u},\r
987                         {0x25u, 0x20u},\r
988                         {0x2Au, 0x02u},\r
989                         {0x2Bu, 0x0Cu},\r
990                         {0x2Cu, 0x02u},\r
991                         {0x2Eu, 0x02u},\r
992                         {0x2Fu, 0x09u},\r
993                         {0x30u, 0x1Au},\r
994                         {0x31u, 0x01u},\r
995                         {0x34u, 0x10u},\r
996                         {0x37u, 0x01u},\r
997                         {0x38u, 0x80u},\r
998                         {0x39u, 0x20u},\r
999                         {0x3Cu, 0x80u},\r
1000                         {0x3Du, 0x20u},\r
1001                         {0x5Cu, 0x08u},\r
1002                         {0x5Du, 0x80u},\r
1003                         {0x5Eu, 0x11u},\r
1004                         {0x80u, 0x08u},\r
1005                         {0x82u, 0x10u},\r
1006                         {0x84u, 0x10u},\r
1007                         {0x85u, 0x80u},\r
1008                         {0x88u, 0x40u},\r
1009                         {0x89u, 0x12u},\r
1010                         {0x8Au, 0x01u},\r
1011                         {0x8Du, 0x80u},\r
1012                         {0x8Eu, 0x40u},\r
1013                         {0x94u, 0x01u},\r
1014                         {0xA0u, 0x02u},\r
1015                         {0xA5u, 0x20u},\r
1016                         {0xA9u, 0x20u},\r
1017                         {0xC0u, 0x97u},\r
1018                         {0xC2u, 0xEBu},\r
1019                         {0xC4u, 0x64u},\r
1020                         {0xCAu, 0xB5u},\r
1021                         {0xCCu, 0xA7u},\r
1022                         {0xCEu, 0x3Cu},\r
1023                         {0xD6u, 0xF0u},\r
1024                         {0xE2u, 0x94u},\r
1025                         {0xE4u, 0xE2u},\r
1026                         {0xE6u, 0x01u},\r
1027                         {0xEEu, 0x28u},\r
1028                         {0x80u, 0x02u},\r
1029                         {0x8Cu, 0x01u},\r
1030                         {0xE0u, 0x04u},\r
1031                         {0xE6u, 0x50u},\r
1032                         {0x8Cu, 0x40u},\r
1033                         {0x90u, 0x40u},\r
1034                         {0xABu, 0x21u},\r
1035                         {0xE2u, 0x40u},\r
1036                         {0x04u, 0x08u},\r
1037                         {0x06u, 0x33u},\r
1038                         {0x08u, 0x20u},\r
1039                         {0x0Au, 0x18u},\r
1040                         {0x0Eu, 0x01u},\r
1041                         {0x14u, 0x2Eu},\r
1042                         {0x15u, 0x04u},\r
1043                         {0x16u, 0x10u},\r
1044                         {0x17u, 0x01u},\r
1045                         {0x18u, 0x18u},\r
1046                         {0x1Au, 0x25u},\r
1047                         {0x1Bu, 0x03u},\r
1048                         {0x21u, 0x04u},\r
1049                         {0x23u, 0x02u},\r
1050                         {0x27u, 0x04u},\r
1051                         {0x2Fu, 0x04u},\r
1052                         {0x30u, 0x07u},\r
1053                         {0x33u, 0x07u},\r
1054                         {0x34u, 0x38u},\r
1055                         {0x3Au, 0x20u},\r
1056                         {0x58u, 0x08u},\r
1057                         {0x59u, 0x04u},\r
1058                         {0x5Cu, 0x19u},\r
1059                         {0x5Fu, 0x01u},\r
1060                         {0x80u, 0x2Cu},\r
1061                         {0x83u, 0x9Fu},\r
1062                         {0x84u, 0x24u},\r
1063                         {0x85u, 0xC0u},\r
1064                         {0x86u, 0x08u},\r
1065                         {0x87u, 0x04u},\r
1066                         {0x88u, 0x44u},\r
1067                         {0x89u, 0xC0u},\r
1068                         {0x8Au, 0x20u},\r
1069                         {0x8Bu, 0x08u},\r
1070                         {0x8Cu, 0x0Cu},\r
1071                         {0x8Du, 0xC0u},\r
1072                         {0x8Eu, 0x20u},\r
1073                         {0x8Fu, 0x01u},\r
1074                         {0x90u, 0x10u},\r
1075                         {0x91u, 0x90u},\r
1076                         {0x93u, 0x40u},\r
1077                         {0x94u, 0xE0u},\r
1078                         {0x95u, 0x7Fu},\r
1079                         {0x96u, 0x0Fu},\r
1080                         {0x97u, 0x80u},\r
1081                         {0x98u, 0xA1u},\r
1082                         {0x9Au, 0x42u},\r
1083                         {0x9Bu, 0xFFu},\r
1084                         {0x9Cu, 0x10u},\r
1085                         {0x9Du, 0xC0u},\r
1086                         {0x9Fu, 0x02u},\r
1087                         {0xA0u, 0x08u},\r
1088                         {0xA3u, 0x60u},\r
1089                         {0xA4u, 0xC1u},\r
1090                         {0xA5u, 0x1Fu},\r
1091                         {0xA6u, 0x2Eu},\r
1092                         {0xA7u, 0x20u},\r
1093                         {0xA8u, 0x20u},\r
1094                         {0xA9u, 0x80u},\r
1095                         {0xAAu, 0x0Cu},\r
1096                         {0xACu, 0x2Cu},\r
1097                         {0xB0u, 0x10u},\r
1098                         {0xB2u, 0x60u},\r
1099                         {0xB4u, 0x0Fu},\r
1100                         {0xB6u, 0x80u},\r
1101                         {0xB7u, 0xFFu},\r
1102                         {0xB8u, 0x02u},\r
1103                         {0xBAu, 0x08u},\r
1104                         {0xBEu, 0x40u},\r
1105                         {0xBFu, 0x40u},\r
1106                         {0xD4u, 0x09u},\r
1107                         {0xD8u, 0x0Bu},\r
1108                         {0xD9u, 0x04u},\r
1109                         {0xDBu, 0x0Bu},\r
1110                         {0xDCu, 0x09u},\r
1111                         {0xDDu, 0x90u},\r
1112                         {0xDFu, 0x01u},\r
1113                         {0x01u, 0x04u},\r
1114                         {0x03u, 0x49u},\r
1115                         {0x04u, 0x48u},\r
1116                         {0x05u, 0x10u},\r
1117                         {0x09u, 0x88u},\r
1118                         {0x0Au, 0x84u},\r
1119                         {0x0Du, 0x08u},\r
1120                         {0x0Fu, 0x04u},\r
1121                         {0x11u, 0x50u},\r
1122                         {0x12u, 0x40u},\r
1123                         {0x13u, 0x05u},\r
1124                         {0x18u, 0x08u},\r
1125                         {0x19u, 0x42u},\r
1126                         {0x1Au, 0x04u},\r
1127                         {0x1Bu, 0x28u},\r
1128                         {0x1Cu, 0x40u},\r
1129                         {0x1Du, 0x10u},\r
1130                         {0x21u, 0x80u},\r
1131                         {0x27u, 0x10u},\r
1132                         {0x29u, 0x02u},\r
1133                         {0x2Bu, 0x28u},\r
1134                         {0x2Cu, 0x10u},\r
1135                         {0x2Eu, 0x80u},\r
1136                         {0x2Fu, 0x80u},\r
1137                         {0x31u, 0x08u},\r
1138                         {0x32u, 0x10u},\r
1139                         {0x33u, 0x41u},\r
1140                         {0x37u, 0x14u},\r
1141                         {0x38u, 0x82u},\r
1142                         {0x39u, 0x54u},\r
1143                         {0x59u, 0x88u},\r
1144                         {0x5Au, 0x02u},\r
1145                         {0x5Bu, 0x20u},\r
1146                         {0x61u, 0x40u},\r
1147                         {0x78u, 0x01u},\r
1148                         {0x7Fu, 0x01u},\r
1149                         {0x83u, 0x10u},\r
1150                         {0x8Fu, 0x04u},\r
1151                         {0x90u, 0x82u},\r
1152                         {0x91u, 0x14u},\r
1153                         {0x92u, 0xA2u},\r
1154                         {0x93u, 0x06u},\r
1155                         {0x98u, 0x11u},\r
1156                         {0x99u, 0x88u},\r
1157                         {0x9Au, 0xC0u},\r
1158                         {0x9Bu, 0x45u},\r
1159                         {0x9Du, 0x12u},\r
1160                         {0xA1u, 0x08u},\r
1161                         {0xA3u, 0x80u},\r
1162                         {0xA7u, 0x2Cu},\r
1163                         {0xB3u, 0x40u},\r
1164                         {0xC0u, 0xEFu},\r
1165                         {0xC2u, 0x6Fu},\r
1166                         {0xC4u, 0x0Fu},\r
1167                         {0xCAu, 0xD7u},\r
1168                         {0xCCu, 0x6Fu},\r
1169                         {0xCEu, 0x0Fu},\r
1170                         {0xD6u, 0x0Fu},\r
1171                         {0xD8u, 0x08u},\r
1172                         {0xDEu, 0x11u},\r
1173                         {0xE0u, 0x40u},\r
1174                         {0xECu, 0x80u},\r
1175                         {0xEEu, 0x0Au},\r
1176                         {0xEEu, 0x0Au},\r
1177                         {0x33u, 0x80u},\r
1178                         {0x36u, 0x40u},\r
1179                         {0x5Bu, 0x08u},\r
1180                         {0x5Fu, 0x22u},\r
1181                         {0x60u, 0x10u},\r
1182                         {0x64u, 0x20u},\r
1183                         {0x83u, 0x22u},\r
1184                         {0xCCu, 0x30u},\r
1185                         {0xD6u, 0xE0u},\r
1186                         {0xD8u, 0xC0u},\r
1187                         {0xE2u, 0x80u},\r
1188                         {0xE6u, 0x80u},\r
1189                         {0x52u, 0x80u},\r
1190                         {0x57u, 0x10u},\r
1191                         {0x5Bu, 0x20u},\r
1192                         {0x5Eu, 0x01u},\r
1193                         {0x86u, 0x80u},\r
1194                         {0x8Bu, 0x20u},\r
1195                         {0x9Cu, 0x20u},\r
1196                         {0x9Fu, 0x08u},\r
1197                         {0xA6u, 0x40u},\r
1198                         {0xA7u, 0x80u},\r
1199                         {0xA8u, 0x10u},\r
1200                         {0xD4u, 0xE0u},\r
1201                         {0xD6u, 0x80u},\r
1202                         {0xE6u, 0x10u},\r
1203                         {0xEEu, 0x80u},\r
1204                         {0x80u, 0x02u},\r
1205                         {0x87u, 0x20u},\r
1206                         {0x9Fu, 0x08u},\r
1207                         {0xA6u, 0x40u},\r
1208                         {0xA7u, 0x90u},\r
1209                         {0xA8u, 0x20u},\r
1210                         {0xAEu, 0x01u},\r
1211                         {0xE0u, 0x40u},\r
1212                         {0xE2u, 0x20u},\r
1213                         {0xEAu, 0x10u},\r
1214                         {0xEEu, 0x20u},\r
1215                         {0x8Fu, 0x10u},\r
1216                         {0x9Fu, 0x28u},\r
1217                         {0xA0u, 0x02u},\r
1218                         {0xA6u, 0x40u},\r
1219                         {0xA7u, 0x90u},\r
1220                         {0xB7u, 0x08u},\r
1221                         {0x0Bu, 0x08u},\r
1222                         {0x0Cu, 0x02u},\r
1223                         {0x12u, 0x10u},\r
1224                         {0x53u, 0x10u},\r
1225                         {0x55u, 0x08u},\r
1226                         {0x5Au, 0x10u},\r
1227                         {0x5Eu, 0x40u},\r
1228                         {0x82u, 0x40u},\r
1229                         {0x8Cu, 0x02u},\r
1230                         {0xC2u, 0x06u},\r
1231                         {0xC4u, 0x08u},\r
1232                         {0xD4u, 0x07u},\r
1233                         {0xD6u, 0x04u},\r
1234                         {0xE6u, 0x02u},\r
1235                         {0x01u, 0x80u},\r
1236                         {0x04u, 0x80u},\r
1237                         {0x05u, 0x02u},\r
1238                         {0x08u, 0x81u},\r
1239                         {0x0Eu, 0x02u},\r
1240                         {0x0Fu, 0x20u},\r
1241                         {0x81u, 0x80u},\r
1242                         {0x83u, 0x10u},\r
1243                         {0x87u, 0x10u},\r
1244                         {0x89u, 0x02u},\r
1245                         {0x96u, 0x10u},\r
1246                         {0x97u, 0x20u},\r
1247                         {0xA5u, 0x08u},\r
1248                         {0xAFu, 0x04u},\r
1249                         {0xB2u, 0x10u},\r
1250                         {0xC0u, 0x07u},\r
1251                         {0xC2u, 0x0Fu},\r
1252                         {0xE2u, 0x01u},\r
1253                         {0xEEu, 0x04u},\r
1254                         {0x82u, 0x10u},\r
1255                         {0x8Cu, 0x40u},\r
1256                         {0x90u, 0x80u},\r
1257                         {0x96u, 0x10u},\r
1258                         {0xA9u, 0x08u},\r
1259                         {0xAAu, 0x01u},\r
1260                         {0xACu, 0x01u},\r
1261                         {0xB4u, 0x80u},\r
1262                         {0xE6u, 0x08u},\r
1263                         {0xEAu, 0x08u},\r
1264                         {0x08u, 0x08u},\r
1265                         {0x0Fu, 0x40u},\r
1266                         {0xC2u, 0x0Cu},\r
1267                         {0x26u, 0x80u},\r
1268                         {0x27u, 0x20u},\r
1269                         {0x83u, 0x08u},\r
1270                         {0x8Eu, 0x80u},\r
1271                         {0x9Eu, 0x40u},\r
1272                         {0x9Fu, 0x28u},\r
1273                         {0xA0u, 0x02u},\r
1274                         {0xAEu, 0x40u},\r
1275                         {0xAFu, 0x80u},\r
1276                         {0xB2u, 0x40u},\r
1277                         {0xC8u, 0xA0u},\r
1278                         {0xE2u, 0x20u},\r
1279                         {0xEEu, 0x50u},\r
1280                         {0x06u, 0x40u},\r
1281                         {0x50u, 0x02u},\r
1282                         {0x57u, 0x80u},\r
1283                         {0x8Fu, 0x80u},\r
1284                         {0x9Eu, 0x40u},\r
1285                         {0xA0u, 0x02u},\r
1286                         {0xC0u, 0x20u},\r
1287                         {0xD4u, 0xC0u},\r
1288                         {0xACu, 0x08u},\r
1289                         {0xAFu, 0x40u},\r
1290                         {0x00u, 0x02u},\r
1291                         {0x01u, 0x01u},\r
1292                         {0x08u, 0x02u},\r
1293                         {0x09u, 0x01u},\r
1294                         {0x0Au, 0x02u},\r
1295                         {0x0Bu, 0x01u},\r
1296                         {0x10u, 0x02u},\r
1297                         {0x11u, 0x01u},\r
1298                         {0x1Au, 0x02u},\r
1299                         {0x1Bu, 0x01u},\r
1300                         {0x00u, 0x0Au},\r
1301                 };\r
1302 \r
1303 \r
1304 \r
1305                 CYPACKED typedef struct {\r
1306                         void CYFAR *address;\r
1307                         uint16 size;\r
1308                 } CYPACKED_ATTR cfg_memset_t;\r
1309 \r
1310 \r
1311                 CYPACKED typedef struct {\r
1312                         void CYFAR *dest;\r
1313                         const void CYCODE *src;\r
1314                         uint16 size;\r
1315                 } CYPACKED_ATTR cfg_memcpy_t;\r
1316 \r
1317                 static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
1318                         /* address, size */\r
1319                         {(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
1320                         {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1664u},\r
1321                         {(void CYFAR *)(CYDEV_UCFG_B0_P3_ROUTE_BASE), 2304u},\r
1322                         {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
1323                         {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
1324                         {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
1325                         {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},\r
1326                 };\r
1327 \r
1328                 /* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */\r
1329                 static const uint8 CYCODE BS_UDB_1_2_0_CONFIG_VAL[] = {\r
1330                         0x04u, 0x00u, 0x00u, 0x00u, 0x07u, 0xC2u, 0x18u, 0x04u, 0x01u, 0x80u, 0x00u, 0x46u, 0x01u, 0xC6u, 0x00u, 0x00u, \r
1331                         0x00u, 0x46u, 0x00u, 0x80u, 0x22u, 0x01u, 0x08u, 0x5Eu, 0x08u, 0x39u, 0x21u, 0x06u, 0x01u, 0xC6u, 0x00u, 0x00u, \r
1332                         0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x77u, 0x00u, 0x08u, 0x40u, 0x42u, 0x00u, 0x00u, 0x10u, 0x04u, 0x00u, 0x20u, \r
1333                         0x3Fu, 0x80u, 0x00u, 0x70u, 0x40u, 0x0Fu, 0x08u, 0x00u, 0x02u, 0x20u, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x51u, 0x01u, \r
1334                         0x63u, 0x02u, 0x40u, 0x00u, 0x05u, 0x0Eu, 0xFCu, 0xBDu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
1335                         0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, \r
1336                         0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
1337                         0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
1338 \r
1339                 static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
1340                         /* dest, src, size */\r
1341                         {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), BS_UDB_1_2_0_CONFIG_VAL, 128u},\r
1342                 };\r
1343 \r
1344                 uint8 CYDATA i;\r
1345 \r
1346                 /* Zero out critical memory blocks before beginning configuration */\r
1347                 for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)\r
1348                 {\r
1349                         const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];\r
1350                         CYMEMZERO(ms->address, (uint32)(ms->size));\r
1351                 }\r
1352 \r
1353                 /* Copy device configuration data into registers */\r
1354                 for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)\r
1355                 {\r
1356                         const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];\r
1357                         void * CYDATA destPtr = mc->dest;\r
1358                         const void CYCODE * CYDATA srcPtr = mc->src;\r
1359                         uint16 CYDATA numBytes = mc->size;\r
1360                         CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);\r
1361                 }\r
1362 \r
1363                 cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);\r
1364 \r
1365                 /* Enable digital routing */\r
1366                 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);\r
1367                 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);\r
1368 \r
1369                 /* Enable UDB array */\r
1370                 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u);\r
1371                 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);\r
1372         }\r
1373 \r
1374         /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */\r
1375         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u);\r
1376         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u);\r
1377         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR + 0x0000000Bu), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u);\r
1378         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);\r
1379         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u);\r
1380         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u);\r
1381         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);\r
1382         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u);\r
1383         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);\r
1384 \r
1385         /* Switch Boost to the precision bandgap reference from its internal reference */\r
1386         CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));\r
1387 \r
1388         /* Perform basic analog initialization to defaults */\r
1389         AnalogSetDefault();\r
1390 \r
1391         /* Configure alternate active mode */\r
1392         CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u);\r
1393 }\r