1 // Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
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3 // This file is part of SCSI2SD.
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5 // SCSI2SD is free software: you can redistribute it and/or modify
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6 // it under the terms of the GNU General Public License as published by
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7 // the Free Software Foundation, either version 3 of the License, or
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8 // (at your option) any later version.
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10 // SCSI2SD is distributed in the hope that it will be useful,
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11 // but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 // GNU General Public License for more details.
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15 // You should have received a copy of the GNU General Public License
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16 // along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
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17 #pragma GCC push_options
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18 #pragma GCC optimize("-flto")
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29 #include "scsiPhy.h"
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36 enum SD_CMD_STATE { CMD_STATE_IDLE, CMD_STATE_READ, CMD_STATE_WRITE };
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37 static int sdCmdState = CMD_STATE_IDLE;
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38 static uint32_t sdCmdNextLBA; // Only valid in CMD_STATE_READ or CMD_STATE_WRITE
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39 static uint32_t sdCmdTime;
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40 static uint32_t sdLastCmdState = CMD_STATE_IDLE;
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42 enum SD_IO_STATE { SD_DMA, SD_ACCEPTED, SD_IDLE };
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43 static int sdIOState = SD_IDLE;
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45 // Private DMA variables.
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46 static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL;
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47 static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL;
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49 // Dummy location for DMA to send unchecked CRC bytes to
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50 static uint8 discardBuffer __attribute__((aligned(4)));
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52 // 2 bytes CRC, response, 8bits to close the clock..
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53 // "NCR" time is up to 8 bytes.
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54 static uint8_t writeResponseBuffer[8] __attribute__((aligned(4)));
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56 // Padded with a dummy byte just to allow the tx DMA channel to
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57 // use 2-byte bursts for performance.
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58 static uint8_t writeStartToken[2] __attribute__((aligned(4))) = {0xFF, 0xFC};
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60 // Source of dummy SPI bytes for DMA
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61 static uint8_t dummyBuffer[2] __attribute__((aligned(4))) = {0xFF, 0xFF};
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63 volatile uint8_t sdRxDMAComplete;
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64 volatile uint8_t sdTxDMAComplete;
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66 CY_ISR_PROTO(sdRxISR);
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69 sdRxDMAComplete = 1;
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71 CY_ISR_PROTO(sdTxISR);
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74 sdTxDMAComplete = 1;
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77 static uint8 sdCrc7(uint8* chr, uint8 cnt, uint8 crc)
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80 for(a = 0; a < cnt; a++)
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82 uint8 Data = chr[a];
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84 for(i = 0; i < 8; i++)
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87 if( (Data & 0x80) ^ (crc & 0x80) ) {crc ^= 0x09;}
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95 // Read and write 1 byte.
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96 static uint8_t sdSpiByte(uint8_t value)
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98 SDCard_WriteTxData(value);
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99 trace(trace_spinSpiByte);
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100 while (!(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)) {}
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101 trace(trace_sdSpiByte);
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102 return SDCard_ReadRxData();
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105 static void sdWaitWriteBusy()
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110 val = sdSpiByte(0xFF);
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111 } while (val != 0xFF);
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114 static void sdPreCmdState(uint32_t newState)
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116 if (sdCmdState == CMD_STATE_READ)
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120 else if (sdCmdState == CMD_STATE_WRITE)
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124 sdCmdState = CMD_STATE_IDLE;
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126 if (sdLastCmdState != newState && newState != CMD_STATE_IDLE)
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129 sdLastCmdState = newState;
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133 static uint16_t sdDoCommand(
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137 int use2byteResponse)
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139 int waitWhileBusy = (cmd != SD_GO_IDLE_STATE) && (cmd != SD_STOP_TRANSMISSION);
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141 // "busy" probe. We'll examine the results later.
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144 SDCard_WriteTxData(0xFF);
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147 // send is static as the address must remain consistent for the static
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148 // DMA descriptors to work.
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149 // Size must be divisible by 2 to suit 2-byte-burst TX DMA channel.
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150 static uint8_t send[6] __attribute__((aligned(4)));
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151 send[0] = cmd | 0x40;
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152 send[1] = param >> 24;
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153 send[2] = param >> 16;
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154 send[3] = param >> 8;
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156 if (unlikely(useCRC))
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158 send[5] = (sdCrc7(send, 5, 0) << 1) | 1;
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162 send[5] = 1; // stop bit
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165 static uint8_t dmaRxTd = CY_DMA_INVALID_TD;
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166 static uint8_t dmaTxTd = CY_DMA_INVALID_TD;
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167 if (unlikely(dmaRxTd == CY_DMA_INVALID_TD))
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169 dmaRxTd = CyDmaTdAllocate();
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170 dmaTxTd = CyDmaTdAllocate();
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171 CyDmaTdSetConfiguration(dmaTxTd, sizeof(send), CY_DMA_DISABLE_TD, TD_INC_SRC_ADR|SD_TX_DMA__TD_TERMOUT_EN);
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172 CyDmaTdSetAddress(dmaTxTd, LO16((uint32)&send), LO16((uint32)SDCard_TXDATA_PTR));
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173 CyDmaTdSetConfiguration(dmaRxTd, sizeof(send), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
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174 CyDmaTdSetAddress(dmaRxTd, LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
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177 sdTxDMAComplete = 0;
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178 sdRxDMAComplete = 0;
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180 CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd);
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181 CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd);
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183 // Some Samsung cards enter a busy-state after single-sector reads.
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184 // But we also need to wait for R1B to complete from the multi-sector
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188 trace(trace_spinSDRxFIFO);
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189 while (!(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)) {}
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190 int busy = SDCard_ReadRxData() != 0xFF;
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191 if (unlikely(busy))
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193 trace(trace_spinSDBusy);
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194 while (sdSpiByte(0xFF) != 0xFF) {}
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198 // The DMA controller is a bit trigger-happy. It will retain
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199 // a drq request that was triggered while the channel was
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201 CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ);
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202 CyDmaClearPendingDrq(sdDMARxChan);
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204 // There is no flow control, so we must ensure we can read the bytes
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205 // before we start transmitting
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206 CyDmaChEnable(sdDMARxChan, 1);
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207 CyDmaChEnable(sdDMATxChan, 1);
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209 trace(trace_spinSDDMA);
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210 int allComplete = 0;
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211 while (!allComplete)
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213 uint8_t intr = CyEnterCriticalSection();
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214 allComplete = sdTxDMAComplete && sdRxDMAComplete;
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219 CyExitCriticalSection(intr);
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222 uint16_t response = sdSpiByte(0xFF); // Result code or stuff byte
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223 if (unlikely(cmd == SD_STOP_TRANSMISSION))
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225 // Stuff byte is required for this command only.
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226 // Part 1 Simplified standard 3.01
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227 // "The stop command has an execution delay due to the serial command
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229 response = sdSpiByte(0xFF);
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232 uint32_t start = getTime_ms();
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234 trace(trace_spinSDBusy);
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235 while ((response & 0x80) && likely(elapsedTime_ms(start) <= 200))
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237 response = sdSpiByte(0xFF);
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239 if (unlikely(use2byteResponse))
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241 response = (response << 8) | sdSpiByte(0xFF);
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247 static inline uint16_t sdCommandAndResponse(uint8_t cmd, uint32_t param)
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249 return sdDoCommand(cmd, param, 0, 0);
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252 static inline uint16_t sdCRCCommandAndResponse(uint8_t cmd, uint32_t param)
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254 return sdDoCommand(cmd, param, 1, 0);
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257 // Clear the sticky status bits on error.
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258 static void sdClearStatus()
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261 uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 1, 1);
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266 sdReadMultiSectorPrep(uint32_t sdLBA, uint32_t sdSectors)
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268 uint32_t tmpNextLBA = sdLBA + sdSectors;
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272 sdLBA = sdLBA * SD_SECTOR_SIZE;
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273 tmpNextLBA = tmpNextLBA * SD_SECTOR_SIZE;
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276 if (sdCmdState == CMD_STATE_READ && sdCmdNextLBA == sdLBA)
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278 // Well, that was lucky. We're already reading this data
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279 sdCmdNextLBA = tmpNextLBA;
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280 sdCmdTime = getTime_ms();
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284 sdPreCmdState(CMD_STATE_READ);
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286 uint8_t v = sdCommandAndResponse(SD_READ_MULTIPLE_BLOCK, sdLBA);
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292 scsiDev.status = CHECK_CONDITION;
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293 scsiDev.target->sense.code = HARDWARE_ERROR;
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294 scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
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295 scsiDev.phase = STATUS;
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299 sdCmdNextLBA = tmpNextLBA;
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300 sdCmdState = CMD_STATE_READ;
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301 sdCmdTime = getTime_ms();
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307 dmaReadSector(uint8_t* outputBuffer)
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309 // Wait for a start-block token.
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310 // Don't wait more than 200ms. The standard recommends 100ms.
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311 uint32_t start = getTime_ms();
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312 uint8_t token = sdSpiByte(0xFF);
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313 trace(trace_spinSDBusy);
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314 while (token != 0xFE && likely(elapsedTime_ms(start) <= 200))
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316 if (unlikely(token && ((token & 0xE0) == 0)))
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321 token = sdSpiByte(0xFF);
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323 if (unlikely(token != 0xFE))
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325 if (transfer.multiBlock)
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329 if (scsiDev.status != CHECK_CONDITION)
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331 scsiDev.status = CHECK_CONDITION;
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332 scsiDev.target->sense.code = HARDWARE_ERROR;
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333 scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;
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334 scsiDev.phase = STATUS;
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340 static uint8_t dmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD};
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341 static uint8_t dmaTxTd = CY_DMA_INVALID_TD;
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342 if (unlikely(dmaRxTd[0] == CY_DMA_INVALID_TD))
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344 dmaRxTd[0] = CyDmaTdAllocate();
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345 dmaRxTd[1] = CyDmaTdAllocate();
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346 dmaTxTd = CyDmaTdAllocate();
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348 // Receive 512 bytes of data and then 2 bytes CRC.
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349 CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE, dmaRxTd[1], TD_INC_DST_ADR);
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350 CyDmaTdSetConfiguration(dmaRxTd[1], 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
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351 CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
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353 CyDmaTdSetConfiguration(dmaTxTd, SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
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354 CyDmaTdSetAddress(dmaTxTd, LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
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357 CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)outputBuffer));
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359 sdIOState = SD_DMA;
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360 sdTxDMAComplete = 0;
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361 sdRxDMAComplete = 0;
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363 // Re-loading the initial TD's here is very important, or else
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364 // we'll be re-using the last-used TD, which would be the last
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365 // in the chain (ie. CRC TD)
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366 CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd[0]);
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367 CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd);
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369 // The DMA controller is a bit trigger-happy. It will retain
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370 // a drq request that was triggered while the channel was
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372 CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ);
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373 CyDmaClearPendingDrq(sdDMARxChan);
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375 // There is no flow control, so we must ensure we can read the bytes
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376 // before we start transmitting
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377 CyDmaChEnable(sdDMARxChan, 1);
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378 CyDmaChEnable(sdDMATxChan, 1);
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382 sdReadSectorDMAPoll()
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384 if (sdRxDMAComplete && sdTxDMAComplete)
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386 // DMA transfer is complete
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387 sdIOState = SD_IDLE;
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396 void sdReadSingleSectorDMA(uint32_t lba, uint8_t* outputBuffer)
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398 sdPreCmdState(CMD_STATE_READ);
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403 lba = lba * SD_SECTOR_SIZE;
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405 v = sdCommandAndResponse(SD_READ_SINGLE_BLOCK, lba);
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411 scsiDev.status = CHECK_CONDITION;
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412 scsiDev.target->sense.code = HARDWARE_ERROR;
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413 scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
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414 scsiDev.phase = STATUS;
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418 dmaReadSector(outputBuffer);
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423 sdReadMultiSectorDMA(uint8_t* outputBuffer)
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425 // Pre: sdReadMultiSectorPrep called.
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426 dmaReadSector(outputBuffer);
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429 void sdCompleteRead()
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431 if (unlikely(sdIOState != SD_IDLE))
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433 // Not much choice but to wait until we've completed the transfer.
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434 // Cancelling the transfer can't be done as we have no way to reset
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436 trace(trace_spinSDCompleteRead);
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437 while (!sdReadSectorDMAPoll()) { /* spin */ }
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441 if (sdCmdState == CMD_STATE_READ)
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443 uint8 r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0);
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445 if (unlikely(r1b) && (scsiDev.PHASE == DATA_IN))
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447 scsiDev.status = CHECK_CONDITION;
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448 scsiDev.target->sense.code = HARDWARE_ERROR;
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449 scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;
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450 scsiDev.phase = STATUS;
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454 // R1b has an optional trailing "busy" signal, but we defer waiting on this.
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455 // The next call so sdCommandAndResponse will wait for the busy state to
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458 sdCmdState = CMD_STATE_IDLE;
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462 sdWriteMultiSectorDMA(uint8_t* outputBuffer)
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464 static uint8_t dmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD};
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465 static uint8_t dmaTxTd[3] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD, CY_DMA_INVALID_TD};
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466 if (unlikely(dmaRxTd[0] == CY_DMA_INVALID_TD))
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468 dmaRxTd[0] = CyDmaTdAllocate();
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469 dmaRxTd[1] = CyDmaTdAllocate();
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470 dmaTxTd[0] = CyDmaTdAllocate();
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471 dmaTxTd[1] = CyDmaTdAllocate();
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472 dmaTxTd[2] = CyDmaTdAllocate();
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474 // Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte
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475 // We need to do this without stopping the clock
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476 CyDmaTdSetConfiguration(dmaTxTd[0], 2, dmaTxTd[1], TD_INC_SRC_ADR);
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477 CyDmaTdSetAddress(dmaTxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR));
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479 CyDmaTdSetConfiguration(dmaTxTd[1], SD_SECTOR_SIZE, dmaTxTd[2], TD_INC_SRC_ADR);
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481 CyDmaTdSetConfiguration(dmaTxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
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482 CyDmaTdSetAddress(dmaTxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
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484 CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 4, dmaRxTd[1], 0);
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485 CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
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486 CyDmaTdSetConfiguration(dmaRxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR);
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487 CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer));
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489 CyDmaTdSetAddress(dmaTxTd[1], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));
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492 sdIOState = SD_DMA;
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493 // The DMA controller is a bit trigger-happy. It will retain
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494 // a drq request that was triggered while the channel was
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496 CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ);
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497 CyDmaClearPendingDrq(sdDMARxChan);
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499 sdTxDMAComplete = 0;
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500 sdRxDMAComplete = 0;
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502 // Re-loading the initial TD's here is very important, or else
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503 // we'll be re-using the last-used TD, which would be the last
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504 // in the chain (ie. CRC TD)
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505 CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd[0]);
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506 CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd[0]);
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508 // There is no flow control, so we must ensure we can read the bytes
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509 // before we start transmitting
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510 CyDmaChEnable(sdDMARxChan, 1);
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511 CyDmaChEnable(sdDMATxChan, 1);
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515 sdWriteSectorDMAPoll()
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517 if (sdRxDMAComplete && sdTxDMAComplete)
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519 if (sdIOState == SD_DMA)
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521 // Retry a few times. The data token format is:
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527 dataToken = writeResponseBuffer[i]; // Response
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529 } while (((dataToken & 0x0101) != 1) && (i < sizeof(writeResponseBuffer)));
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531 // At this point we should either have an accepted token, or we'll
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532 // timeout and proceed into the error case below.
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533 if (unlikely(((dataToken & 0x1F) >> 1) != 0x2)) // Accepted.
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535 sdIOState = SD_IDLE;
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538 sdSpiByte(0xFD); // STOP TOKEN
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541 sdCmdState = CMD_STATE_IDLE;
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545 scsiDev.status = CHECK_CONDITION;
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546 scsiDev.target->sense.code = HARDWARE_ERROR;
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547 scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
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548 scsiDev.phase = STATUS;
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552 sdIOState = SD_ACCEPTED;
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556 if (sdIOState == SD_ACCEPTED)
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558 // Wait while the SD card is busy
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559 if (sdSpiByte(0xFF) == 0xFF)
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561 sdIOState = SD_IDLE;
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565 return sdIOState == SD_IDLE;
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573 void sdCompleteWrite()
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575 if (unlikely(sdIOState != SD_IDLE))
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577 // Not much choice but to wait until we've completed the transfer.
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578 // Cancelling the transfer can't be done as we have no way to reset
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580 trace(trace_spinSDCompleteWrite);
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581 while (!sdWriteSectorDMAPoll()) { /* spin */ }
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584 if (sdCmdState == CMD_STATE_WRITE)
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588 sdSpiByte(0xFD); // STOP TOKEN
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594 if (likely(scsiDev.phase == DATA_OUT))
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596 uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 0, 1);
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600 scsiDev.status = CHECK_CONDITION;
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601 scsiDev.target->sense.code = HARDWARE_ERROR;
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602 scsiDev.target->sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED;
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603 scsiDev.phase = STATUS;
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606 sdCmdState = CMD_STATE_IDLE;
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609 void sdCompleteTransfer()
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611 sdPreCmdState(CMD_STATE_IDLE);
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615 // SD Version 2 (SDHC) support
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616 static int sendIfCond()
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622 // 11:8 Host voltage. 1 = 2.7-3.6V
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623 // 7:0 Echo bits. Ignore.
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624 uint8 status = sdCRCCommandAndResponse(SD_SEND_IF_COND, 0x000001AA);
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626 if (status == SD_R1_IDLE)
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630 // Read 32bit response. Should contain the same bytes that
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631 // we sent in the command parameter.
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638 else if (status & SD_R1_ILLEGAL)
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647 } while (--retries > 0);
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649 return retries > 0;
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652 static int sdOpCond()
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654 uint32_t start = getTime_ms();
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659 sdCRCCommandAndResponse(SD_APP_CMD, 0);
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660 // Host Capacity Support = 1 (SDHC/SDXC supported)
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661 status = sdCRCCommandAndResponse(SD_APP_SEND_OP_COND, 0x40000000);
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665 // Spec says to poll for 1 second.
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666 } while ((status != 0) && (elapsedTime_ms(start) < 1000));
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668 return status == 0;
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671 static int sdReadOCR()
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673 uint32_t start = getTime_ms();
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682 status = sdCRCCommandAndResponse(SD_READ_OCR, 0);
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683 if(status) { break; }
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685 for (i = 0; i < 4; ++i)
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687 buf[i] = sdSpiByte(0xFF);
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690 sdDev.ccs = (buf[0] & 0x40) ? 1 : 0;
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691 complete = (buf[0] & 0x80);
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693 } while (!status &&
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695 (elapsedTime_ms(start) < 1000));
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697 return (status == 0) && complete;
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700 static void sdReadCID()
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705 uint8 status = sdCRCCommandAndResponse(SD_SEND_CID, 0);
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706 if(status){return;}
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711 startToken = sdSpiByte(0xFF);
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712 } while(maxWait-- && (startToken != 0xFE));
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713 if (startToken != 0xFE) { return; }
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715 for (i = 0; i < 16; ++i)
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717 sdDev.cid[i] = sdSpiByte(0xFF);
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719 sdSpiByte(0xFF); // CRC
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720 sdSpiByte(0xFF); // CRC
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723 static int sdReadCSD()
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728 uint8 status = sdCRCCommandAndResponse(SD_SEND_CSD, 0);
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729 if(status){goto bad;}
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734 startToken = sdSpiByte(0xFF);
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735 } while(maxWait-- && (startToken != 0xFE));
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736 if (startToken != 0xFE) { goto bad; }
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738 for (i = 0; i < 16; ++i)
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740 sdDev.csd[i] = sdSpiByte(0xFF);
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742 sdSpiByte(0xFF); // CRC
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743 sdSpiByte(0xFF); // CRC
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745 if ((sdDev.csd[0] >> 6) == 0x00)
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748 // C_SIZE in bits [73:62]
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749 uint32 c_size = (((((uint32)sdDev.csd[6]) & 0x3) << 16) | (((uint32)sdDev.csd[7]) << 8) | sdDev.csd[8]) >> 6;
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750 uint32 c_mult = (((((uint32)sdDev.csd[9]) & 0x3) << 8) | ((uint32)sdDev.csd[0xa])) >> 7;
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751 uint32 sectorSize = sdDev.csd[5] & 0x0F;
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752 sdDev.capacity = ((c_size+1) * ((uint64)1 << (c_mult+2)) * ((uint64)1 << sectorSize)) / SD_SECTOR_SIZE;
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754 else if ((sdDev.csd[0] >> 6) == 0x01)
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757 // C_SIZE in bits [69:48]
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760 ((((uint32)sdDev.csd[7]) & 0x3F) << 16) |
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761 (((uint32)sdDev.csd[8]) << 8) |
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762 ((uint32)sdDev.csd[7]);
\r
763 sdDev.capacity = (c_size + 1) * 1024;
\r
775 static void sdInitDMA()
\r
777 // One-time init only.
\r
778 if (sdDMATxChan == CY_DMA_INVALID_CHANNEL)
\r
781 SD_TX_DMA_DmaInitialize(
\r
782 2, // Bytes per burst
\r
783 1, // request per burst
\r
784 HI16(CYDEV_SRAM_BASE),
\r
785 HI16(CYDEV_PERIPH_BASE)
\r
789 SD_RX_DMA_DmaInitialize(
\r
790 1, // Bytes per burst
\r
791 1, // request per burst
\r
792 HI16(CYDEV_PERIPH_BASE),
\r
793 HI16(CYDEV_SRAM_BASE)
\r
796 CyDmaChDisable(sdDMATxChan);
\r
797 CyDmaChDisable(sdDMARxChan);
\r
799 SD_RX_DMA_COMPLETE_StartEx(sdRxISR);
\r
800 SD_TX_DMA_COMPLETE_StartEx(sdTxISR);
\r
810 sdCmdState = CMD_STATE_IDLE;
\r
813 sdDev.capacity = 0;
\r
814 memset(sdDev.csd, 0, sizeof(sdDev.csd));
\r
815 memset(sdDev.cid, 0, sizeof(sdDev.cid));
\r
819 SD_CS_SetDriveMode(SD_CS_DM_STRONG);
\r
820 SD_CS_Write(1); // Set CS inactive (active low)
\r
822 // Set the SPI clock for 400kHz transfers
\r
823 // 25MHz / 400kHz approx factor of 63.
\r
824 // The register contains (divider - 1)
\r
825 uint16_t clkDiv25MHz = SD_Data_Clk_GetDividerRegister();
\r
826 SD_Data_Clk_SetDivider(((clkDiv25MHz + 1) * 63) - 1);
\r
827 // Wait for the clock to settle.
\r
830 SDCard_Start(); // Enable SPI hardware
\r
832 // Power on sequence. 74 clock cycles of a "1" while CS unasserted.
\r
833 for (i = 0; i < 10; ++i)
\r
838 SD_CS_Write(0); // Set CS active (active low)
\r
842 v = sdDoCommand(SD_GO_IDLE_STATE, 0, 1, 0);
\r
843 if(v != 1){goto bad;}
\r
846 if (!sendIfCond()) goto bad; // Sets V1 or V2 flag CMD8
\r
847 if (!sdOpCond()) goto bad; // ACMD41. Wait for init completes.
\r
848 if (!sdReadOCR()) goto bad; // CMD58. Get CCS flag. Only valid after init.
\r
850 // This command will be ignored if sdDev.ccs is set.
\r
851 // SDHC and SDXC are always 512bytes.
\r
852 v = sdCRCCommandAndResponse(SD_SET_BLOCKLEN, SD_SECTOR_SIZE); //Force sector size
\r
854 v = sdCRCCommandAndResponse(SD_CRC_ON_OFF, 0); //crc off
\r
857 // now set the sd card back to full speed.
\r
858 // The SD Card spec says we can run SPI @ 25MHz
\r
861 // We can't run at full-speed with the pullup resistors enabled.
\r
862 SD_MISO_SetDriveMode(SD_MISO_DM_DIG_HIZ);
\r
863 SD_MOSI_SetDriveMode(SD_MOSI_DM_STRONG);
\r
864 SD_SCK_SetDriveMode(SD_SCK_DM_STRONG);
\r
866 SD_Data_Clk_SetDivider(clkDiv25MHz);
\r
870 // Clear out rubbish data through clock change
\r
872 SDCard_ReadRxStatus();
\r
873 SDCard_ReadTxStatus();
\r
874 SDCard_ClearFIFO();
\r
876 if (!sdReadCSD()) goto bad;
\r
883 SD_Data_Clk_SetDivider(clkDiv25MHz); // Restore the clock for our next retry
\r
884 sdDev.capacity = 0;
\r
893 void sdWriteMultiSectorPrep(uint32_t sdLBA, uint32_t sdSectors)
\r
895 uint32_t tmpNextLBA = sdLBA + sdSectors;
\r
899 sdLBA = sdLBA * SD_SECTOR_SIZE;
\r
900 tmpNextLBA = tmpNextLBA * SD_SECTOR_SIZE;
\r
903 if (sdCmdState == CMD_STATE_WRITE && sdCmdNextLBA == sdLBA)
\r
905 // Well, that was lucky. We're already writing this data
\r
906 sdCmdNextLBA = tmpNextLBA;
\r
907 sdCmdTime = getTime_ms();
\r
911 sdPreCmdState(CMD_STATE_WRITE);
\r
913 // Set the number of blocks to pre-erase by the multiple block write
\r
914 // command. We don't care about the response - if the command is not
\r
915 // accepted, writes will just be a bit slower. Max 22bit parameter.
\r
916 uint32 blocks = sdSectors > 0x7FFFFF ? 0x7FFFFF : sdSectors;
\r
917 sdCommandAndResponse(SD_APP_CMD, 0);
\r
918 sdCommandAndResponse(SD_APP_SET_WR_BLK_ERASE_COUNT, blocks);
\r
920 uint8_t v = sdCommandAndResponse(SD_WRITE_MULTIPLE_BLOCK, sdLBA);
\r
925 scsiDev.status = CHECK_CONDITION;
\r
926 scsiDev.target->sense.code = HARDWARE_ERROR;
\r
927 scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
\r
928 scsiDev.phase = STATUS;
\r
932 sdCmdTime = getTime_ms();
\r
933 sdCmdNextLBA = tmpNextLBA;
\r
934 sdCmdState = CMD_STATE_WRITE;
\r
941 if ((scsiDev.phase == BUS_FREE) &&
\r
942 (sdCmdState != CMD_STATE_IDLE) &&
\r
943 (elapsedTime_ms(sdCmdTime) >= 50))
\r
945 sdPreCmdState(CMD_STATE_IDLE);
\r
949 void sdCheckPresent()
\r
951 // Check if there's an SD card present.
\r
952 if ((scsiDev.phase == BUS_FREE) &&
\r
953 (sdIOState == SD_IDLE) &&
\r
954 (sdCmdState == CMD_STATE_IDLE))
\r
956 // The CS line is pulled high by the SD card.
\r
957 // De-assert the line, and check if it's high.
\r
958 // This isn't foolproof as it'll be left floating without
\r
959 // an SD card. We can't use the built-in pull-down resistor as it will
\r
960 // overpower the SD pullup resistor.
\r
962 SD_CS_SetDriveMode(SD_CS_DM_DIG_HIZ);
\r
964 // Delay extended to work with 60cm cables running cards at 2.85V
\r
965 CyDelayCycles(128);
\r
966 uint8_t cs = SD_CS_Read();
\r
967 SD_CS_SetDriveMode(SD_CS_DM_STRONG) ;
\r
969 if (cs && !(blockDev.state & DISK_PRESENT))
\r
971 static int firstInit = 1;
\r
978 blockDev.state |= DISK_PRESENT | DISK_INITIALISED;
\r
980 // Always "start" the device. Many systems (eg. Apple System 7)
\r
981 // won't respond properly to
\r
982 // LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED sense
\r
983 // code, even if they stopped it first with
\r
984 // START STOP UNIT command.
\r
985 blockDev.state |= DISK_STARTED;
\r
990 for (i = 0; i < MAX_SCSI_TARGETS; ++i)
\r
992 scsiDev.targets[i].unitAttention = PARAMETERS_CHANGED;
\r
998 else if (!cs && (blockDev.state & DISK_PRESENT))
\r
1000 sdDev.capacity = 0;
\r
1001 blockDev.state &= ~DISK_PRESENT;
\r
1002 blockDev.state &= ~DISK_INITIALISED;
\r
1004 for (i = 0; i < MAX_SCSI_TARGETS; ++i)
\r
1006 scsiDev.targets[i].unitAttention = PARAMETERS_CHANGED;
\r
1012 #pragma GCC pop_options
\r