Glitch filter configuration options and update to PSoC Creator v3.2
[SCSI2SD-V6.git] / software / SCSI2SD / v4 / SCSI2SD.cydsn / Generated_Source / PSoC5 / cydevicegnu_trm.inc
1 /*******************************************************************************
2 * FILENAME: cydevicegnu_trm.inc
3
4 * PSoC Creator  3.2
5 *
6 * DESCRIPTION:
7 * This file provides all of the address values for the entire PSoC device.
8 * This file is automatically generated by PSoC Creator.
9 *
10 ********************************************************************************
11 * Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
12 * You may use this file only in accordance with the license, terms, conditions, 
13 * disclaimers, and limitations in the end user license agreement accompanying 
14 * the software package with which this file was provided.
15 ********************************************************************************/
16
17 .set CYDEV_FLASH_BASE, 0x00000000
18 .set CYDEV_FLASH_SIZE, 0x00020000
19 .set CYREG_FLASH_DATA_MBASE, 0x00000000
20 .set CYREG_FLASH_DATA_MSIZE, 0x00020000
21 .set CYDEV_SRAM_BASE, 0x1fffc000
22 .set CYDEV_SRAM_SIZE, 0x00008000
23 .set CYREG_SRAM_CODE64K_MBASE, 0x1fff8000
24 .set CYREG_SRAM_CODE64K_MSIZE, 0x00004000
25 .set CYREG_SRAM_CODE32K_MBASE, 0x1fffc000
26 .set CYREG_SRAM_CODE32K_MSIZE, 0x00002000
27 .set CYREG_SRAM_CODE16K_MBASE, 0x1fffe000
28 .set CYREG_SRAM_CODE16K_MSIZE, 0x00001000
29 .set CYREG_SRAM_CODE_MBASE, 0x1fffc000
30 .set CYREG_SRAM_CODE_MSIZE, 0x00004000
31 .set CYREG_SRAM_DATA_MBASE, 0x20000000
32 .set CYREG_SRAM_DATA_MSIZE, 0x00004000
33 .set CYREG_SRAM_DATA16K_MBASE, 0x20001000
34 .set CYREG_SRAM_DATA16K_MSIZE, 0x00001000
35 .set CYREG_SRAM_DATA32K_MBASE, 0x20002000
36 .set CYREG_SRAM_DATA32K_MSIZE, 0x00002000
37 .set CYREG_SRAM_DATA64K_MBASE, 0x20004000
38 .set CYREG_SRAM_DATA64K_MSIZE, 0x00004000
39 .set CYDEV_DMA_BASE, 0x20008000
40 .set CYDEV_DMA_SIZE, 0x00008000
41 .set CYREG_DMA_SRAM64K_MBASE, 0x20008000
42 .set CYREG_DMA_SRAM64K_MSIZE, 0x00004000
43 .set CYREG_DMA_SRAM32K_MBASE, 0x2000c000
44 .set CYREG_DMA_SRAM32K_MSIZE, 0x00002000
45 .set CYREG_DMA_SRAM16K_MBASE, 0x2000e000
46 .set CYREG_DMA_SRAM16K_MSIZE, 0x00001000
47 .set CYREG_DMA_SRAM_MBASE, 0x2000f000
48 .set CYREG_DMA_SRAM_MSIZE, 0x00001000
49 .set CYDEV_CLKDIST_BASE, 0x40004000
50 .set CYDEV_CLKDIST_SIZE, 0x00000110
51 .set CYREG_CLKDIST_CR, 0x40004000
52 .set CYREG_CLKDIST_LD, 0x40004001
53 .set CYREG_CLKDIST_WRK0, 0x40004002
54 .set CYREG_CLKDIST_WRK1, 0x40004003
55 .set CYREG_CLKDIST_MSTR0, 0x40004004
56 .set CYREG_CLKDIST_MSTR1, 0x40004005
57 .set CYREG_CLKDIST_BCFG0, 0x40004006
58 .set CYREG_CLKDIST_BCFG1, 0x40004007
59 .set CYREG_CLKDIST_BCFG2, 0x40004008
60 .set CYREG_CLKDIST_UCFG, 0x40004009
61 .set CYREG_CLKDIST_DLY0, 0x4000400a
62 .set CYREG_CLKDIST_DLY1, 0x4000400b
63 .set CYREG_CLKDIST_DMASK, 0x40004010
64 .set CYREG_CLKDIST_AMASK, 0x40004014
65 .set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080
66 .set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003
67 .set CYREG_CLKDIST_DCFG0_CFG0, 0x40004080
68 .set CYREG_CLKDIST_DCFG0_CFG1, 0x40004081
69 .set CYREG_CLKDIST_DCFG0_CFG2, 0x40004082
70 .set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084
71 .set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003
72 .set CYREG_CLKDIST_DCFG1_CFG0, 0x40004084
73 .set CYREG_CLKDIST_DCFG1_CFG1, 0x40004085
74 .set CYREG_CLKDIST_DCFG1_CFG2, 0x40004086
75 .set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088
76 .set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003
77 .set CYREG_CLKDIST_DCFG2_CFG0, 0x40004088
78 .set CYREG_CLKDIST_DCFG2_CFG1, 0x40004089
79 .set CYREG_CLKDIST_DCFG2_CFG2, 0x4000408a
80 .set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c
81 .set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003
82 .set CYREG_CLKDIST_DCFG3_CFG0, 0x4000408c
83 .set CYREG_CLKDIST_DCFG3_CFG1, 0x4000408d
84 .set CYREG_CLKDIST_DCFG3_CFG2, 0x4000408e
85 .set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090
86 .set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003
87 .set CYREG_CLKDIST_DCFG4_CFG0, 0x40004090
88 .set CYREG_CLKDIST_DCFG4_CFG1, 0x40004091
89 .set CYREG_CLKDIST_DCFG4_CFG2, 0x40004092
90 .set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094
91 .set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003
92 .set CYREG_CLKDIST_DCFG5_CFG0, 0x40004094
93 .set CYREG_CLKDIST_DCFG5_CFG1, 0x40004095
94 .set CYREG_CLKDIST_DCFG5_CFG2, 0x40004096
95 .set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098
96 .set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003
97 .set CYREG_CLKDIST_DCFG6_CFG0, 0x40004098
98 .set CYREG_CLKDIST_DCFG6_CFG1, 0x40004099
99 .set CYREG_CLKDIST_DCFG6_CFG2, 0x4000409a
100 .set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c
101 .set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003
102 .set CYREG_CLKDIST_DCFG7_CFG0, 0x4000409c
103 .set CYREG_CLKDIST_DCFG7_CFG1, 0x4000409d
104 .set CYREG_CLKDIST_DCFG7_CFG2, 0x4000409e
105 .set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100
106 .set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004
107 .set CYREG_CLKDIST_ACFG0_CFG0, 0x40004100
108 .set CYREG_CLKDIST_ACFG0_CFG1, 0x40004101
109 .set CYREG_CLKDIST_ACFG0_CFG2, 0x40004102
110 .set CYREG_CLKDIST_ACFG0_CFG3, 0x40004103
111 .set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104
112 .set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004
113 .set CYREG_CLKDIST_ACFG1_CFG0, 0x40004104
114 .set CYREG_CLKDIST_ACFG1_CFG1, 0x40004105
115 .set CYREG_CLKDIST_ACFG1_CFG2, 0x40004106
116 .set CYREG_CLKDIST_ACFG1_CFG3, 0x40004107
117 .set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108
118 .set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004
119 .set CYREG_CLKDIST_ACFG2_CFG0, 0x40004108
120 .set CYREG_CLKDIST_ACFG2_CFG1, 0x40004109
121 .set CYREG_CLKDIST_ACFG2_CFG2, 0x4000410a
122 .set CYREG_CLKDIST_ACFG2_CFG3, 0x4000410b
123 .set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c
124 .set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004
125 .set CYREG_CLKDIST_ACFG3_CFG0, 0x4000410c
126 .set CYREG_CLKDIST_ACFG3_CFG1, 0x4000410d
127 .set CYREG_CLKDIST_ACFG3_CFG2, 0x4000410e
128 .set CYREG_CLKDIST_ACFG3_CFG3, 0x4000410f
129 .set CYDEV_FASTCLK_BASE, 0x40004200
130 .set CYDEV_FASTCLK_SIZE, 0x00000026
131 .set CYDEV_FASTCLK_IMO_BASE, 0x40004200
132 .set CYDEV_FASTCLK_IMO_SIZE, 0x00000001
133 .set CYREG_FASTCLK_IMO_CR, 0x40004200
134 .set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210
135 .set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004
136 .set CYREG_FASTCLK_XMHZ_CSR, 0x40004210
137 .set CYREG_FASTCLK_XMHZ_CFG0, 0x40004212
138 .set CYREG_FASTCLK_XMHZ_CFG1, 0x40004213
139 .set CYDEV_FASTCLK_PLL_BASE, 0x40004220
140 .set CYDEV_FASTCLK_PLL_SIZE, 0x00000006
141 .set CYREG_FASTCLK_PLL_CFG0, 0x40004220
142 .set CYREG_FASTCLK_PLL_CFG1, 0x40004221
143 .set CYREG_FASTCLK_PLL_P, 0x40004222
144 .set CYREG_FASTCLK_PLL_Q, 0x40004223
145 .set CYREG_FASTCLK_PLL_SR, 0x40004225
146 .set CYDEV_SLOWCLK_BASE, 0x40004300
147 .set CYDEV_SLOWCLK_SIZE, 0x0000000b
148 .set CYDEV_SLOWCLK_ILO_BASE, 0x40004300
149 .set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002
150 .set CYREG_SLOWCLK_ILO_CR0, 0x40004300
151 .set CYREG_SLOWCLK_ILO_CR1, 0x40004301
152 .set CYDEV_SLOWCLK_X32_BASE, 0x40004308
153 .set CYDEV_SLOWCLK_X32_SIZE, 0x00000003
154 .set CYREG_SLOWCLK_X32_CR, 0x40004308
155 .set CYREG_SLOWCLK_X32_CFG, 0x40004309
156 .set CYREG_SLOWCLK_X32_TST, 0x4000430a
157 .set CYDEV_BOOST_BASE, 0x40004320
158 .set CYDEV_BOOST_SIZE, 0x00000007
159 .set CYREG_BOOST_CR0, 0x40004320
160 .set CYREG_BOOST_CR1, 0x40004321
161 .set CYREG_BOOST_CR2, 0x40004322
162 .set CYREG_BOOST_CR3, 0x40004323
163 .set CYREG_BOOST_SR, 0x40004324
164 .set CYREG_BOOST_CR4, 0x40004325
165 .set CYREG_BOOST_SR2, 0x40004326
166 .set CYDEV_PWRSYS_BASE, 0x40004330
167 .set CYDEV_PWRSYS_SIZE, 0x00000002
168 .set CYREG_PWRSYS_CR0, 0x40004330
169 .set CYREG_PWRSYS_CR1, 0x40004331
170 .set CYDEV_PM_BASE, 0x40004380
171 .set CYDEV_PM_SIZE, 0x00000057
172 .set CYREG_PM_TW_CFG0, 0x40004380
173 .set CYREG_PM_TW_CFG1, 0x40004381
174 .set CYREG_PM_TW_CFG2, 0x40004382
175 .set CYREG_PM_WDT_CFG, 0x40004383
176 .set CYREG_PM_WDT_CR, 0x40004384
177 .set CYREG_PM_INT_SR, 0x40004390
178 .set CYREG_PM_MODE_CFG0, 0x40004391
179 .set CYREG_PM_MODE_CFG1, 0x40004392
180 .set CYREG_PM_MODE_CSR, 0x40004393
181 .set CYREG_PM_USB_CR0, 0x40004394
182 .set CYREG_PM_WAKEUP_CFG0, 0x40004398
183 .set CYREG_PM_WAKEUP_CFG1, 0x40004399
184 .set CYREG_PM_WAKEUP_CFG2, 0x4000439a
185 .set CYDEV_PM_ACT_BASE, 0x400043a0
186 .set CYDEV_PM_ACT_SIZE, 0x0000000e
187 .set CYREG_PM_ACT_CFG0, 0x400043a0
188 .set CYREG_PM_ACT_CFG1, 0x400043a1
189 .set CYREG_PM_ACT_CFG2, 0x400043a2
190 .set CYREG_PM_ACT_CFG3, 0x400043a3
191 .set CYREG_PM_ACT_CFG4, 0x400043a4
192 .set CYREG_PM_ACT_CFG5, 0x400043a5
193 .set CYREG_PM_ACT_CFG6, 0x400043a6
194 .set CYREG_PM_ACT_CFG7, 0x400043a7
195 .set CYREG_PM_ACT_CFG8, 0x400043a8
196 .set CYREG_PM_ACT_CFG9, 0x400043a9
197 .set CYREG_PM_ACT_CFG10, 0x400043aa
198 .set CYREG_PM_ACT_CFG11, 0x400043ab
199 .set CYREG_PM_ACT_CFG12, 0x400043ac
200 .set CYREG_PM_ACT_CFG13, 0x400043ad
201 .set CYDEV_PM_STBY_BASE, 0x400043b0
202 .set CYDEV_PM_STBY_SIZE, 0x0000000e
203 .set CYREG_PM_STBY_CFG0, 0x400043b0
204 .set CYREG_PM_STBY_CFG1, 0x400043b1
205 .set CYREG_PM_STBY_CFG2, 0x400043b2
206 .set CYREG_PM_STBY_CFG3, 0x400043b3
207 .set CYREG_PM_STBY_CFG4, 0x400043b4
208 .set CYREG_PM_STBY_CFG5, 0x400043b5
209 .set CYREG_PM_STBY_CFG6, 0x400043b6
210 .set CYREG_PM_STBY_CFG7, 0x400043b7
211 .set CYREG_PM_STBY_CFG8, 0x400043b8
212 .set CYREG_PM_STBY_CFG9, 0x400043b9
213 .set CYREG_PM_STBY_CFG10, 0x400043ba
214 .set CYREG_PM_STBY_CFG11, 0x400043bb
215 .set CYREG_PM_STBY_CFG12, 0x400043bc
216 .set CYREG_PM_STBY_CFG13, 0x400043bd
217 .set CYDEV_PM_AVAIL_BASE, 0x400043c0
218 .set CYDEV_PM_AVAIL_SIZE, 0x00000017
219 .set CYREG_PM_AVAIL_CR0, 0x400043c0
220 .set CYREG_PM_AVAIL_CR1, 0x400043c1
221 .set CYREG_PM_AVAIL_CR2, 0x400043c2
222 .set CYREG_PM_AVAIL_CR3, 0x400043c3
223 .set CYREG_PM_AVAIL_CR4, 0x400043c4
224 .set CYREG_PM_AVAIL_CR5, 0x400043c5
225 .set CYREG_PM_AVAIL_CR6, 0x400043c6
226 .set CYREG_PM_AVAIL_SR0, 0x400043d0
227 .set CYREG_PM_AVAIL_SR1, 0x400043d1
228 .set CYREG_PM_AVAIL_SR2, 0x400043d2
229 .set CYREG_PM_AVAIL_SR3, 0x400043d3
230 .set CYREG_PM_AVAIL_SR4, 0x400043d4
231 .set CYREG_PM_AVAIL_SR5, 0x400043d5
232 .set CYREG_PM_AVAIL_SR6, 0x400043d6
233 .set CYDEV_PICU_BASE, 0x40004500
234 .set CYDEV_PICU_SIZE, 0x000000b0
235 .set CYDEV_PICU_INTTYPE_BASE, 0x40004500
236 .set CYDEV_PICU_INTTYPE_SIZE, 0x00000080
237 .set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500
238 .set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008
239 .set CYREG_PICU0_INTTYPE0, 0x40004500
240 .set CYREG_PICU0_INTTYPE1, 0x40004501
241 .set CYREG_PICU0_INTTYPE2, 0x40004502
242 .set CYREG_PICU0_INTTYPE3, 0x40004503
243 .set CYREG_PICU0_INTTYPE4, 0x40004504
244 .set CYREG_PICU0_INTTYPE5, 0x40004505
245 .set CYREG_PICU0_INTTYPE6, 0x40004506
246 .set CYREG_PICU0_INTTYPE7, 0x40004507
247 .set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508
248 .set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008
249 .set CYREG_PICU1_INTTYPE0, 0x40004508
250 .set CYREG_PICU1_INTTYPE1, 0x40004509
251 .set CYREG_PICU1_INTTYPE2, 0x4000450a
252 .set CYREG_PICU1_INTTYPE3, 0x4000450b
253 .set CYREG_PICU1_INTTYPE4, 0x4000450c
254 .set CYREG_PICU1_INTTYPE5, 0x4000450d
255 .set CYREG_PICU1_INTTYPE6, 0x4000450e
256 .set CYREG_PICU1_INTTYPE7, 0x4000450f
257 .set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510
258 .set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008
259 .set CYREG_PICU2_INTTYPE0, 0x40004510
260 .set CYREG_PICU2_INTTYPE1, 0x40004511
261 .set CYREG_PICU2_INTTYPE2, 0x40004512
262 .set CYREG_PICU2_INTTYPE3, 0x40004513
263 .set CYREG_PICU2_INTTYPE4, 0x40004514
264 .set CYREG_PICU2_INTTYPE5, 0x40004515
265 .set CYREG_PICU2_INTTYPE6, 0x40004516
266 .set CYREG_PICU2_INTTYPE7, 0x40004517
267 .set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518
268 .set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008
269 .set CYREG_PICU3_INTTYPE0, 0x40004518
270 .set CYREG_PICU3_INTTYPE1, 0x40004519
271 .set CYREG_PICU3_INTTYPE2, 0x4000451a
272 .set CYREG_PICU3_INTTYPE3, 0x4000451b
273 .set CYREG_PICU3_INTTYPE4, 0x4000451c
274 .set CYREG_PICU3_INTTYPE5, 0x4000451d
275 .set CYREG_PICU3_INTTYPE6, 0x4000451e
276 .set CYREG_PICU3_INTTYPE7, 0x4000451f
277 .set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520
278 .set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008
279 .set CYREG_PICU4_INTTYPE0, 0x40004520
280 .set CYREG_PICU4_INTTYPE1, 0x40004521
281 .set CYREG_PICU4_INTTYPE2, 0x40004522
282 .set CYREG_PICU4_INTTYPE3, 0x40004523
283 .set CYREG_PICU4_INTTYPE4, 0x40004524
284 .set CYREG_PICU4_INTTYPE5, 0x40004525
285 .set CYREG_PICU4_INTTYPE6, 0x40004526
286 .set CYREG_PICU4_INTTYPE7, 0x40004527
287 .set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528
288 .set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008
289 .set CYREG_PICU5_INTTYPE0, 0x40004528
290 .set CYREG_PICU5_INTTYPE1, 0x40004529
291 .set CYREG_PICU5_INTTYPE2, 0x4000452a
292 .set CYREG_PICU5_INTTYPE3, 0x4000452b
293 .set CYREG_PICU5_INTTYPE4, 0x4000452c
294 .set CYREG_PICU5_INTTYPE5, 0x4000452d
295 .set CYREG_PICU5_INTTYPE6, 0x4000452e
296 .set CYREG_PICU5_INTTYPE7, 0x4000452f
297 .set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530
298 .set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008
299 .set CYREG_PICU6_INTTYPE0, 0x40004530
300 .set CYREG_PICU6_INTTYPE1, 0x40004531
301 .set CYREG_PICU6_INTTYPE2, 0x40004532
302 .set CYREG_PICU6_INTTYPE3, 0x40004533
303 .set CYREG_PICU6_INTTYPE4, 0x40004534
304 .set CYREG_PICU6_INTTYPE5, 0x40004535
305 .set CYREG_PICU6_INTTYPE6, 0x40004536
306 .set CYREG_PICU6_INTTYPE7, 0x40004537
307 .set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560
308 .set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008
309 .set CYREG_PICU12_INTTYPE0, 0x40004560
310 .set CYREG_PICU12_INTTYPE1, 0x40004561
311 .set CYREG_PICU12_INTTYPE2, 0x40004562
312 .set CYREG_PICU12_INTTYPE3, 0x40004563
313 .set CYREG_PICU12_INTTYPE4, 0x40004564
314 .set CYREG_PICU12_INTTYPE5, 0x40004565
315 .set CYREG_PICU12_INTTYPE6, 0x40004566
316 .set CYREG_PICU12_INTTYPE7, 0x40004567
317 .set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578
318 .set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008
319 .set CYREG_PICU15_INTTYPE0, 0x40004578
320 .set CYREG_PICU15_INTTYPE1, 0x40004579
321 .set CYREG_PICU15_INTTYPE2, 0x4000457a
322 .set CYREG_PICU15_INTTYPE3, 0x4000457b
323 .set CYREG_PICU15_INTTYPE4, 0x4000457c
324 .set CYREG_PICU15_INTTYPE5, 0x4000457d
325 .set CYREG_PICU15_INTTYPE6, 0x4000457e
326 .set CYREG_PICU15_INTTYPE7, 0x4000457f
327 .set CYDEV_PICU_STAT_BASE, 0x40004580
328 .set CYDEV_PICU_STAT_SIZE, 0x00000010
329 .set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580
330 .set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001
331 .set CYREG_PICU0_INTSTAT, 0x40004580
332 .set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581
333 .set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001
334 .set CYREG_PICU1_INTSTAT, 0x40004581
335 .set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582
336 .set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001
337 .set CYREG_PICU2_INTSTAT, 0x40004582
338 .set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583
339 .set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001
340 .set CYREG_PICU3_INTSTAT, 0x40004583
341 .set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584
342 .set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001
343 .set CYREG_PICU4_INTSTAT, 0x40004584
344 .set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585
345 .set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001
346 .set CYREG_PICU5_INTSTAT, 0x40004585
347 .set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586
348 .set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001
349 .set CYREG_PICU6_INTSTAT, 0x40004586
350 .set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c
351 .set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001
352 .set CYREG_PICU12_INTSTAT, 0x4000458c
353 .set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f
354 .set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001
355 .set CYREG_PICU15_INTSTAT, 0x4000458f
356 .set CYDEV_PICU_SNAP_BASE, 0x40004590
357 .set CYDEV_PICU_SNAP_SIZE, 0x00000010
358 .set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590
359 .set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001
360 .set CYREG_PICU0_SNAP, 0x40004590
361 .set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591
362 .set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001
363 .set CYREG_PICU1_SNAP, 0x40004591
364 .set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592
365 .set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001
366 .set CYREG_PICU2_SNAP, 0x40004592
367 .set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593
368 .set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001
369 .set CYREG_PICU3_SNAP, 0x40004593
370 .set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594
371 .set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001
372 .set CYREG_PICU4_SNAP, 0x40004594
373 .set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595
374 .set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001
375 .set CYREG_PICU5_SNAP, 0x40004595
376 .set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596
377 .set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001
378 .set CYREG_PICU6_SNAP, 0x40004596
379 .set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c
380 .set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001
381 .set CYREG_PICU12_SNAP, 0x4000459c
382 .set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f
383 .set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001
384 .set CYREG_PICU_15_SNAP_15, 0x4000459f
385 .set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0
386 .set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010
387 .set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0
388 .set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001
389 .set CYREG_PICU0_DISABLE_COR, 0x400045a0
390 .set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1
391 .set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001
392 .set CYREG_PICU1_DISABLE_COR, 0x400045a1
393 .set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2
394 .set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001
395 .set CYREG_PICU2_DISABLE_COR, 0x400045a2
396 .set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3
397 .set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001
398 .set CYREG_PICU3_DISABLE_COR, 0x400045a3
399 .set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4
400 .set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001
401 .set CYREG_PICU4_DISABLE_COR, 0x400045a4
402 .set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5
403 .set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001
404 .set CYREG_PICU5_DISABLE_COR, 0x400045a5
405 .set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6
406 .set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001
407 .set CYREG_PICU6_DISABLE_COR, 0x400045a6
408 .set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac
409 .set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001
410 .set CYREG_PICU12_DISABLE_COR, 0x400045ac
411 .set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af
412 .set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001
413 .set CYREG_PICU15_DISABLE_COR, 0x400045af
414 .set CYDEV_MFGCFG_BASE, 0x40004600
415 .set CYDEV_MFGCFG_SIZE, 0x000000ed
416 .set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600
417 .set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038
418 .set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608
419 .set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001
420 .set CYREG_DAC0_TR, 0x40004608
421 .set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609
422 .set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001
423 .set CYREG_DAC1_TR, 0x40004609
424 .set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a
425 .set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001
426 .set CYREG_DAC2_TR, 0x4000460a
427 .set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b
428 .set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001
429 .set CYREG_DAC3_TR, 0x4000460b
430 .set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610
431 .set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001
432 .set CYREG_NPUMP_DSM_TR0, 0x40004610
433 .set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611
434 .set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001
435 .set CYREG_NPUMP_SC_TR0, 0x40004611
436 .set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612
437 .set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001
438 .set CYREG_NPUMP_OPAMP_TR0, 0x40004612
439 .set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614
440 .set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001
441 .set CYREG_SAR0_TR0, 0x40004614
442 .set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616
443 .set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001
444 .set CYREG_SAR1_TR0, 0x40004616
445 .set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620
446 .set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002
447 .set CYREG_OPAMP0_TR0, 0x40004620
448 .set CYREG_OPAMP0_TR1, 0x40004621
449 .set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622
450 .set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002
451 .set CYREG_OPAMP1_TR0, 0x40004622
452 .set CYREG_OPAMP1_TR1, 0x40004623
453 .set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624
454 .set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002
455 .set CYREG_OPAMP2_TR0, 0x40004624
456 .set CYREG_OPAMP2_TR1, 0x40004625
457 .set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626
458 .set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002
459 .set CYREG_OPAMP3_TR0, 0x40004626
460 .set CYREG_OPAMP3_TR1, 0x40004627
461 .set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630
462 .set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002
463 .set CYREG_CMP0_TR0, 0x40004630
464 .set CYREG_CMP0_TR1, 0x40004631
465 .set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632
466 .set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002
467 .set CYREG_CMP1_TR0, 0x40004632
468 .set CYREG_CMP1_TR1, 0x40004633
469 .set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634
470 .set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002
471 .set CYREG_CMP2_TR0, 0x40004634
472 .set CYREG_CMP2_TR1, 0x40004635
473 .set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636
474 .set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002
475 .set CYREG_CMP3_TR0, 0x40004636
476 .set CYREG_CMP3_TR1, 0x40004637
477 .set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680
478 .set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b
479 .set CYREG_PWRSYS_HIB_TR0, 0x40004680
480 .set CYREG_PWRSYS_HIB_TR1, 0x40004681
481 .set CYREG_PWRSYS_I2C_TR, 0x40004682
482 .set CYREG_PWRSYS_SLP_TR, 0x40004683
483 .set CYREG_PWRSYS_BUZZ_TR, 0x40004684
484 .set CYREG_PWRSYS_WAKE_TR0, 0x40004685
485 .set CYREG_PWRSYS_WAKE_TR1, 0x40004686
486 .set CYREG_PWRSYS_BREF_TR, 0x40004687
487 .set CYREG_PWRSYS_BG_TR, 0x40004688
488 .set CYREG_PWRSYS_WAKE_TR2, 0x40004689
489 .set CYREG_PWRSYS_WAKE_TR3, 0x4000468a
490 .set CYDEV_MFGCFG_ILO_BASE, 0x40004690
491 .set CYDEV_MFGCFG_ILO_SIZE, 0x00000002
492 .set CYREG_ILO_TR0, 0x40004690
493 .set CYREG_ILO_TR1, 0x40004691
494 .set CYDEV_MFGCFG_X32_BASE, 0x40004698
495 .set CYDEV_MFGCFG_X32_SIZE, 0x00000001
496 .set CYREG_X32_TR, 0x40004698
497 .set CYDEV_MFGCFG_IMO_BASE, 0x400046a0
498 .set CYDEV_MFGCFG_IMO_SIZE, 0x00000005
499 .set CYREG_IMO_TR0, 0x400046a0
500 .set CYREG_IMO_TR1, 0x400046a1
501 .set CYREG_IMO_GAIN, 0x400046a2
502 .set CYREG_IMO_C36M, 0x400046a3
503 .set CYREG_IMO_TR2, 0x400046a4
504 .set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8
505 .set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001
506 .set CYREG_XMHZ_TR, 0x400046a8
507 .set CYREG_MFGCFG_DLY, 0x400046c0
508 .set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0
509 .set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d
510 .set CYREG_MLOGIC_DMPSTR, 0x400046e2
511 .set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4
512 .set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002
513 .set CYREG_MLOGIC_SEG_CR, 0x400046e4
514 .set CYREG_MLOGIC_SEG_CFG0, 0x400046e5
515 .set CYREG_MLOGIC_DEBUG, 0x400046e8
516 .set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea
517 .set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001
518 .set CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea
519 .set CYREG_MLOGIC_REV_ID, 0x400046ec
520 .set CYDEV_RESET_BASE, 0x400046f0
521 .set CYDEV_RESET_SIZE, 0x0000000f
522 .set CYREG_RESET_IPOR_CR0, 0x400046f0
523 .set CYREG_RESET_IPOR_CR1, 0x400046f1
524 .set CYREG_RESET_IPOR_CR2, 0x400046f2
525 .set CYREG_RESET_IPOR_CR3, 0x400046f3
526 .set CYREG_RESET_CR0, 0x400046f4
527 .set CYREG_RESET_CR1, 0x400046f5
528 .set CYREG_RESET_CR2, 0x400046f6
529 .set CYREG_RESET_CR3, 0x400046f7
530 .set CYREG_RESET_CR4, 0x400046f8
531 .set CYREG_RESET_CR5, 0x400046f9
532 .set CYREG_RESET_SR0, 0x400046fa
533 .set CYREG_RESET_SR1, 0x400046fb
534 .set CYREG_RESET_SR2, 0x400046fc
535 .set CYREG_RESET_SR3, 0x400046fd
536 .set CYREG_RESET_TR, 0x400046fe
537 .set CYDEV_SPC_BASE, 0x40004700
538 .set CYDEV_SPC_SIZE, 0x00000100
539 .set CYREG_SPC_FM_EE_CR, 0x40004700
540 .set CYREG_SPC_FM_EE_WAKE_CNT, 0x40004701
541 .set CYREG_SPC_EE_SCR, 0x40004702
542 .set CYREG_SPC_EE_ERR, 0x40004703
543 .set CYREG_SPC_CPU_DATA, 0x40004720
544 .set CYREG_SPC_DMA_DATA, 0x40004721
545 .set CYREG_SPC_SR, 0x40004722
546 .set CYREG_SPC_CR, 0x40004723
547 .set CYDEV_SPC_DMM_MAP_BASE, 0x40004780
548 .set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080
549 .set CYREG_SPC_DMM_MAP_SRAM_MBASE, 0x40004780
550 .set CYREG_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080
551 .set CYDEV_CACHE_BASE, 0x40004800
552 .set CYDEV_CACHE_SIZE, 0x0000009c
553 .set CYREG_CACHE_CC_CTL, 0x40004800
554 .set CYREG_CACHE_ECC_CORR, 0x40004880
555 .set CYREG_CACHE_ECC_ERR, 0x40004888
556 .set CYREG_CACHE_FLASH_ERR, 0x40004890
557 .set CYREG_CACHE_HITMISS, 0x40004898
558 .set CYDEV_I2C_BASE, 0x40004900
559 .set CYDEV_I2C_SIZE, 0x000000e1
560 .set CYREG_I2C_XCFG, 0x400049c8
561 .set CYREG_I2C_ADR, 0x400049ca
562 .set CYREG_I2C_CFG, 0x400049d6
563 .set CYREG_I2C_CSR, 0x400049d7
564 .set CYREG_I2C_D, 0x400049d8
565 .set CYREG_I2C_MCSR, 0x400049d9
566 .set CYREG_I2C_CLK_DIV1, 0x400049db
567 .set CYREG_I2C_CLK_DIV2, 0x400049dc
568 .set CYREG_I2C_TMOUT_CSR, 0x400049dd
569 .set CYREG_I2C_TMOUT_SR, 0x400049de
570 .set CYREG_I2C_TMOUT_CFG0, 0x400049df
571 .set CYREG_I2C_TMOUT_CFG1, 0x400049e0
572 .set CYDEV_DEC_BASE, 0x40004e00
573 .set CYDEV_DEC_SIZE, 0x00000015
574 .set CYREG_DEC_CR, 0x40004e00
575 .set CYREG_DEC_SR, 0x40004e01
576 .set CYREG_DEC_SHIFT1, 0x40004e02
577 .set CYREG_DEC_SHIFT2, 0x40004e03
578 .set CYREG_DEC_DR2, 0x40004e04
579 .set CYREG_DEC_DR2H, 0x40004e05
580 .set CYREG_DEC_DR1, 0x40004e06
581 .set CYREG_DEC_OCOR, 0x40004e08
582 .set CYREG_DEC_OCORM, 0x40004e09
583 .set CYREG_DEC_OCORH, 0x40004e0a
584 .set CYREG_DEC_GCOR, 0x40004e0c
585 .set CYREG_DEC_GCORH, 0x40004e0d
586 .set CYREG_DEC_GVAL, 0x40004e0e
587 .set CYREG_DEC_OUTSAMP, 0x40004e10
588 .set CYREG_DEC_OUTSAMPM, 0x40004e11
589 .set CYREG_DEC_OUTSAMPH, 0x40004e12
590 .set CYREG_DEC_OUTSAMPS, 0x40004e13
591 .set CYREG_DEC_COHER, 0x40004e14
592 .set CYDEV_TMR0_BASE, 0x40004f00
593 .set CYDEV_TMR0_SIZE, 0x0000000c
594 .set CYREG_TMR0_CFG0, 0x40004f00
595 .set CYREG_TMR0_CFG1, 0x40004f01
596 .set CYREG_TMR0_CFG2, 0x40004f02
597 .set CYREG_TMR0_SR0, 0x40004f03
598 .set CYREG_TMR0_PER0, 0x40004f04
599 .set CYREG_TMR0_PER1, 0x40004f05
600 .set CYREG_TMR0_CNT_CMP0, 0x40004f06
601 .set CYREG_TMR0_CNT_CMP1, 0x40004f07
602 .set CYREG_TMR0_CAP0, 0x40004f08
603 .set CYREG_TMR0_CAP1, 0x40004f09
604 .set CYREG_TMR0_RT0, 0x40004f0a
605 .set CYREG_TMR0_RT1, 0x40004f0b
606 .set CYDEV_TMR1_BASE, 0x40004f0c
607 .set CYDEV_TMR1_SIZE, 0x0000000c
608 .set CYREG_TMR1_CFG0, 0x40004f0c
609 .set CYREG_TMR1_CFG1, 0x40004f0d
610 .set CYREG_TMR1_CFG2, 0x40004f0e
611 .set CYREG_TMR1_SR0, 0x40004f0f
612 .set CYREG_TMR1_PER0, 0x40004f10
613 .set CYREG_TMR1_PER1, 0x40004f11
614 .set CYREG_TMR1_CNT_CMP0, 0x40004f12
615 .set CYREG_TMR1_CNT_CMP1, 0x40004f13
616 .set CYREG_TMR1_CAP0, 0x40004f14
617 .set CYREG_TMR1_CAP1, 0x40004f15
618 .set CYREG_TMR1_RT0, 0x40004f16
619 .set CYREG_TMR1_RT1, 0x40004f17
620 .set CYDEV_TMR2_BASE, 0x40004f18
621 .set CYDEV_TMR2_SIZE, 0x0000000c
622 .set CYREG_TMR2_CFG0, 0x40004f18
623 .set CYREG_TMR2_CFG1, 0x40004f19
624 .set CYREG_TMR2_CFG2, 0x40004f1a
625 .set CYREG_TMR2_SR0, 0x40004f1b
626 .set CYREG_TMR2_PER0, 0x40004f1c
627 .set CYREG_TMR2_PER1, 0x40004f1d
628 .set CYREG_TMR2_CNT_CMP0, 0x40004f1e
629 .set CYREG_TMR2_CNT_CMP1, 0x40004f1f
630 .set CYREG_TMR2_CAP0, 0x40004f20
631 .set CYREG_TMR2_CAP1, 0x40004f21
632 .set CYREG_TMR2_RT0, 0x40004f22
633 .set CYREG_TMR2_RT1, 0x40004f23
634 .set CYDEV_TMR3_BASE, 0x40004f24
635 .set CYDEV_TMR3_SIZE, 0x0000000c
636 .set CYREG_TMR3_CFG0, 0x40004f24
637 .set CYREG_TMR3_CFG1, 0x40004f25
638 .set CYREG_TMR3_CFG2, 0x40004f26
639 .set CYREG_TMR3_SR0, 0x40004f27
640 .set CYREG_TMR3_PER0, 0x40004f28
641 .set CYREG_TMR3_PER1, 0x40004f29
642 .set CYREG_TMR3_CNT_CMP0, 0x40004f2a
643 .set CYREG_TMR3_CNT_CMP1, 0x40004f2b
644 .set CYREG_TMR3_CAP0, 0x40004f2c
645 .set CYREG_TMR3_CAP1, 0x40004f2d
646 .set CYREG_TMR3_RT0, 0x40004f2e
647 .set CYREG_TMR3_RT1, 0x40004f2f
648 .set CYDEV_IO_BASE, 0x40005000
649 .set CYDEV_IO_SIZE, 0x00000200
650 .set CYDEV_IO_PC_BASE, 0x40005000
651 .set CYDEV_IO_PC_SIZE, 0x00000080
652 .set CYDEV_IO_PC_PRT0_BASE, 0x40005000
653 .set CYDEV_IO_PC_PRT0_SIZE, 0x00000008
654 .set CYREG_PRT0_PC0, 0x40005000
655 .set CYREG_PRT0_PC1, 0x40005001
656 .set CYREG_PRT0_PC2, 0x40005002
657 .set CYREG_PRT0_PC3, 0x40005003
658 .set CYREG_PRT0_PC4, 0x40005004
659 .set CYREG_PRT0_PC5, 0x40005005
660 .set CYREG_PRT0_PC6, 0x40005006
661 .set CYREG_PRT0_PC7, 0x40005007
662 .set CYDEV_IO_PC_PRT1_BASE, 0x40005008
663 .set CYDEV_IO_PC_PRT1_SIZE, 0x00000008
664 .set CYREG_PRT1_PC0, 0x40005008
665 .set CYREG_PRT1_PC1, 0x40005009
666 .set CYREG_PRT1_PC2, 0x4000500a
667 .set CYREG_PRT1_PC3, 0x4000500b
668 .set CYREG_PRT1_PC4, 0x4000500c
669 .set CYREG_PRT1_PC5, 0x4000500d
670 .set CYREG_PRT1_PC6, 0x4000500e
671 .set CYREG_PRT1_PC7, 0x4000500f
672 .set CYDEV_IO_PC_PRT2_BASE, 0x40005010
673 .set CYDEV_IO_PC_PRT2_SIZE, 0x00000008
674 .set CYREG_PRT2_PC0, 0x40005010
675 .set CYREG_PRT2_PC1, 0x40005011
676 .set CYREG_PRT2_PC2, 0x40005012
677 .set CYREG_PRT2_PC3, 0x40005013
678 .set CYREG_PRT2_PC4, 0x40005014
679 .set CYREG_PRT2_PC5, 0x40005015
680 .set CYREG_PRT2_PC6, 0x40005016
681 .set CYREG_PRT2_PC7, 0x40005017
682 .set CYDEV_IO_PC_PRT3_BASE, 0x40005018
683 .set CYDEV_IO_PC_PRT3_SIZE, 0x00000008
684 .set CYREG_PRT3_PC0, 0x40005018
685 .set CYREG_PRT3_PC1, 0x40005019
686 .set CYREG_PRT3_PC2, 0x4000501a
687 .set CYREG_PRT3_PC3, 0x4000501b
688 .set CYREG_PRT3_PC4, 0x4000501c
689 .set CYREG_PRT3_PC5, 0x4000501d
690 .set CYREG_PRT3_PC6, 0x4000501e
691 .set CYREG_PRT3_PC7, 0x4000501f
692 .set CYDEV_IO_PC_PRT4_BASE, 0x40005020
693 .set CYDEV_IO_PC_PRT4_SIZE, 0x00000008
694 .set CYREG_PRT4_PC0, 0x40005020
695 .set CYREG_PRT4_PC1, 0x40005021
696 .set CYREG_PRT4_PC2, 0x40005022
697 .set CYREG_PRT4_PC3, 0x40005023
698 .set CYREG_PRT4_PC4, 0x40005024
699 .set CYREG_PRT4_PC5, 0x40005025
700 .set CYREG_PRT4_PC6, 0x40005026
701 .set CYREG_PRT4_PC7, 0x40005027
702 .set CYDEV_IO_PC_PRT5_BASE, 0x40005028
703 .set CYDEV_IO_PC_PRT5_SIZE, 0x00000008
704 .set CYREG_PRT5_PC0, 0x40005028
705 .set CYREG_PRT5_PC1, 0x40005029
706 .set CYREG_PRT5_PC2, 0x4000502a
707 .set CYREG_PRT5_PC3, 0x4000502b
708 .set CYREG_PRT5_PC4, 0x4000502c
709 .set CYREG_PRT5_PC5, 0x4000502d
710 .set CYREG_PRT5_PC6, 0x4000502e
711 .set CYREG_PRT5_PC7, 0x4000502f
712 .set CYDEV_IO_PC_PRT6_BASE, 0x40005030
713 .set CYDEV_IO_PC_PRT6_SIZE, 0x00000008
714 .set CYREG_PRT6_PC0, 0x40005030
715 .set CYREG_PRT6_PC1, 0x40005031
716 .set CYREG_PRT6_PC2, 0x40005032
717 .set CYREG_PRT6_PC3, 0x40005033
718 .set CYREG_PRT6_PC4, 0x40005034
719 .set CYREG_PRT6_PC5, 0x40005035
720 .set CYREG_PRT6_PC6, 0x40005036
721 .set CYREG_PRT6_PC7, 0x40005037
722 .set CYDEV_IO_PC_PRT12_BASE, 0x40005060
723 .set CYDEV_IO_PC_PRT12_SIZE, 0x00000008
724 .set CYREG_PRT12_PC0, 0x40005060
725 .set CYREG_PRT12_PC1, 0x40005061
726 .set CYREG_PRT12_PC2, 0x40005062
727 .set CYREG_PRT12_PC3, 0x40005063
728 .set CYREG_PRT12_PC4, 0x40005064
729 .set CYREG_PRT12_PC5, 0x40005065
730 .set CYREG_PRT12_PC6, 0x40005066
731 .set CYREG_PRT12_PC7, 0x40005067
732 .set CYDEV_IO_PC_PRT15_BASE, 0x40005078
733 .set CYDEV_IO_PC_PRT15_SIZE, 0x00000006
734 .set CYREG_IO_PC_PRT15_PC0, 0x40005078
735 .set CYREG_IO_PC_PRT15_PC1, 0x40005079
736 .set CYREG_IO_PC_PRT15_PC2, 0x4000507a
737 .set CYREG_IO_PC_PRT15_PC3, 0x4000507b
738 .set CYREG_IO_PC_PRT15_PC4, 0x4000507c
739 .set CYREG_IO_PC_PRT15_PC5, 0x4000507d
740 .set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e
741 .set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002
742 .set CYREG_IO_PC_PRT15_7_6_PC0, 0x4000507e
743 .set CYREG_IO_PC_PRT15_7_6_PC1, 0x4000507f
744 .set CYDEV_IO_DR_BASE, 0x40005080
745 .set CYDEV_IO_DR_SIZE, 0x00000010
746 .set CYDEV_IO_DR_PRT0_BASE, 0x40005080
747 .set CYDEV_IO_DR_PRT0_SIZE, 0x00000001
748 .set CYREG_PRT0_DR_ALIAS, 0x40005080
749 .set CYDEV_IO_DR_PRT1_BASE, 0x40005081
750 .set CYDEV_IO_DR_PRT1_SIZE, 0x00000001
751 .set CYREG_PRT1_DR_ALIAS, 0x40005081
752 .set CYDEV_IO_DR_PRT2_BASE, 0x40005082
753 .set CYDEV_IO_DR_PRT2_SIZE, 0x00000001
754 .set CYREG_PRT2_DR_ALIAS, 0x40005082
755 .set CYDEV_IO_DR_PRT3_BASE, 0x40005083
756 .set CYDEV_IO_DR_PRT3_SIZE, 0x00000001
757 .set CYREG_PRT3_DR_ALIAS, 0x40005083
758 .set CYDEV_IO_DR_PRT4_BASE, 0x40005084
759 .set CYDEV_IO_DR_PRT4_SIZE, 0x00000001
760 .set CYREG_PRT4_DR_ALIAS, 0x40005084
761 .set CYDEV_IO_DR_PRT5_BASE, 0x40005085
762 .set CYDEV_IO_DR_PRT5_SIZE, 0x00000001
763 .set CYREG_PRT5_DR_ALIAS, 0x40005085
764 .set CYDEV_IO_DR_PRT6_BASE, 0x40005086
765 .set CYDEV_IO_DR_PRT6_SIZE, 0x00000001
766 .set CYREG_PRT6_DR_ALIAS, 0x40005086
767 .set CYDEV_IO_DR_PRT12_BASE, 0x4000508c
768 .set CYDEV_IO_DR_PRT12_SIZE, 0x00000001
769 .set CYREG_PRT12_DR_ALIAS, 0x4000508c
770 .set CYDEV_IO_DR_PRT15_BASE, 0x4000508f
771 .set CYDEV_IO_DR_PRT15_SIZE, 0x00000001
772 .set CYREG_PRT15_DR_15_ALIAS, 0x4000508f
773 .set CYDEV_IO_PS_BASE, 0x40005090
774 .set CYDEV_IO_PS_SIZE, 0x00000010
775 .set CYDEV_IO_PS_PRT0_BASE, 0x40005090
776 .set CYDEV_IO_PS_PRT0_SIZE, 0x00000001
777 .set CYREG_PRT0_PS_ALIAS, 0x40005090
778 .set CYDEV_IO_PS_PRT1_BASE, 0x40005091
779 .set CYDEV_IO_PS_PRT1_SIZE, 0x00000001
780 .set CYREG_PRT1_PS_ALIAS, 0x40005091
781 .set CYDEV_IO_PS_PRT2_BASE, 0x40005092
782 .set CYDEV_IO_PS_PRT2_SIZE, 0x00000001
783 .set CYREG_PRT2_PS_ALIAS, 0x40005092
784 .set CYDEV_IO_PS_PRT3_BASE, 0x40005093
785 .set CYDEV_IO_PS_PRT3_SIZE, 0x00000001
786 .set CYREG_PRT3_PS_ALIAS, 0x40005093
787 .set CYDEV_IO_PS_PRT4_BASE, 0x40005094
788 .set CYDEV_IO_PS_PRT4_SIZE, 0x00000001
789 .set CYREG_PRT4_PS_ALIAS, 0x40005094
790 .set CYDEV_IO_PS_PRT5_BASE, 0x40005095
791 .set CYDEV_IO_PS_PRT5_SIZE, 0x00000001
792 .set CYREG_PRT5_PS_ALIAS, 0x40005095
793 .set CYDEV_IO_PS_PRT6_BASE, 0x40005096
794 .set CYDEV_IO_PS_PRT6_SIZE, 0x00000001
795 .set CYREG_PRT6_PS_ALIAS, 0x40005096
796 .set CYDEV_IO_PS_PRT12_BASE, 0x4000509c
797 .set CYDEV_IO_PS_PRT12_SIZE, 0x00000001
798 .set CYREG_PRT12_PS_ALIAS, 0x4000509c
799 .set CYDEV_IO_PS_PRT15_BASE, 0x4000509f
800 .set CYDEV_IO_PS_PRT15_SIZE, 0x00000001
801 .set CYREG_PRT15_PS15_ALIAS, 0x4000509f
802 .set CYDEV_IO_PRT_BASE, 0x40005100
803 .set CYDEV_IO_PRT_SIZE, 0x00000100
804 .set CYDEV_IO_PRT_PRT0_BASE, 0x40005100
805 .set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010
806 .set CYREG_PRT0_DR, 0x40005100
807 .set CYREG_PRT0_PS, 0x40005101
808 .set CYREG_PRT0_DM0, 0x40005102
809 .set CYREG_PRT0_DM1, 0x40005103
810 .set CYREG_PRT0_DM2, 0x40005104
811 .set CYREG_PRT0_SLW, 0x40005105
812 .set CYREG_PRT0_BYP, 0x40005106
813 .set CYREG_PRT0_BIE, 0x40005107
814 .set CYREG_PRT0_INP_DIS, 0x40005108
815 .set CYREG_PRT0_CTL, 0x40005109
816 .set CYREG_PRT0_PRT, 0x4000510a
817 .set CYREG_PRT0_BIT_MASK, 0x4000510b
818 .set CYREG_PRT0_AMUX, 0x4000510c
819 .set CYREG_PRT0_AG, 0x4000510d
820 .set CYREG_PRT0_LCD_COM_SEG, 0x4000510e
821 .set CYREG_PRT0_LCD_EN, 0x4000510f
822 .set CYDEV_IO_PRT_PRT1_BASE, 0x40005110
823 .set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010
824 .set CYREG_PRT1_DR, 0x40005110
825 .set CYREG_PRT1_PS, 0x40005111
826 .set CYREG_PRT1_DM0, 0x40005112
827 .set CYREG_PRT1_DM1, 0x40005113
828 .set CYREG_PRT1_DM2, 0x40005114
829 .set CYREG_PRT1_SLW, 0x40005115
830 .set CYREG_PRT1_BYP, 0x40005116
831 .set CYREG_PRT1_BIE, 0x40005117
832 .set CYREG_PRT1_INP_DIS, 0x40005118
833 .set CYREG_PRT1_CTL, 0x40005119
834 .set CYREG_PRT1_PRT, 0x4000511a
835 .set CYREG_PRT1_BIT_MASK, 0x4000511b
836 .set CYREG_PRT1_AMUX, 0x4000511c
837 .set CYREG_PRT1_AG, 0x4000511d
838 .set CYREG_PRT1_LCD_COM_SEG, 0x4000511e
839 .set CYREG_PRT1_LCD_EN, 0x4000511f
840 .set CYDEV_IO_PRT_PRT2_BASE, 0x40005120
841 .set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010
842 .set CYREG_PRT2_DR, 0x40005120
843 .set CYREG_PRT2_PS, 0x40005121
844 .set CYREG_PRT2_DM0, 0x40005122
845 .set CYREG_PRT2_DM1, 0x40005123
846 .set CYREG_PRT2_DM2, 0x40005124
847 .set CYREG_PRT2_SLW, 0x40005125
848 .set CYREG_PRT2_BYP, 0x40005126
849 .set CYREG_PRT2_BIE, 0x40005127
850 .set CYREG_PRT2_INP_DIS, 0x40005128
851 .set CYREG_PRT2_CTL, 0x40005129
852 .set CYREG_PRT2_PRT, 0x4000512a
853 .set CYREG_PRT2_BIT_MASK, 0x4000512b
854 .set CYREG_PRT2_AMUX, 0x4000512c
855 .set CYREG_PRT2_AG, 0x4000512d
856 .set CYREG_PRT2_LCD_COM_SEG, 0x4000512e
857 .set CYREG_PRT2_LCD_EN, 0x4000512f
858 .set CYDEV_IO_PRT_PRT3_BASE, 0x40005130
859 .set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010
860 .set CYREG_PRT3_DR, 0x40005130
861 .set CYREG_PRT3_PS, 0x40005131
862 .set CYREG_PRT3_DM0, 0x40005132
863 .set CYREG_PRT3_DM1, 0x40005133
864 .set CYREG_PRT3_DM2, 0x40005134
865 .set CYREG_PRT3_SLW, 0x40005135
866 .set CYREG_PRT3_BYP, 0x40005136
867 .set CYREG_PRT3_BIE, 0x40005137
868 .set CYREG_PRT3_INP_DIS, 0x40005138
869 .set CYREG_PRT3_CTL, 0x40005139
870 .set CYREG_PRT3_PRT, 0x4000513a
871 .set CYREG_PRT3_BIT_MASK, 0x4000513b
872 .set CYREG_PRT3_AMUX, 0x4000513c
873 .set CYREG_PRT3_AG, 0x4000513d
874 .set CYREG_PRT3_LCD_COM_SEG, 0x4000513e
875 .set CYREG_PRT3_LCD_EN, 0x4000513f
876 .set CYDEV_IO_PRT_PRT4_BASE, 0x40005140
877 .set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010
878 .set CYREG_PRT4_DR, 0x40005140
879 .set CYREG_PRT4_PS, 0x40005141
880 .set CYREG_PRT4_DM0, 0x40005142
881 .set CYREG_PRT4_DM1, 0x40005143
882 .set CYREG_PRT4_DM2, 0x40005144
883 .set CYREG_PRT4_SLW, 0x40005145
884 .set CYREG_PRT4_BYP, 0x40005146
885 .set CYREG_PRT4_BIE, 0x40005147
886 .set CYREG_PRT4_INP_DIS, 0x40005148
887 .set CYREG_PRT4_CTL, 0x40005149
888 .set CYREG_PRT4_PRT, 0x4000514a
889 .set CYREG_PRT4_BIT_MASK, 0x4000514b
890 .set CYREG_PRT4_AMUX, 0x4000514c
891 .set CYREG_PRT4_AG, 0x4000514d
892 .set CYREG_PRT4_LCD_COM_SEG, 0x4000514e
893 .set CYREG_PRT4_LCD_EN, 0x4000514f
894 .set CYDEV_IO_PRT_PRT5_BASE, 0x40005150
895 .set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010
896 .set CYREG_PRT5_DR, 0x40005150
897 .set CYREG_PRT5_PS, 0x40005151
898 .set CYREG_PRT5_DM0, 0x40005152
899 .set CYREG_PRT5_DM1, 0x40005153
900 .set CYREG_PRT5_DM2, 0x40005154
901 .set CYREG_PRT5_SLW, 0x40005155
902 .set CYREG_PRT5_BYP, 0x40005156
903 .set CYREG_PRT5_BIE, 0x40005157
904 .set CYREG_PRT5_INP_DIS, 0x40005158
905 .set CYREG_PRT5_CTL, 0x40005159
906 .set CYREG_PRT5_PRT, 0x4000515a
907 .set CYREG_PRT5_BIT_MASK, 0x4000515b
908 .set CYREG_PRT5_AMUX, 0x4000515c
909 .set CYREG_PRT5_AG, 0x4000515d
910 .set CYREG_PRT5_LCD_COM_SEG, 0x4000515e
911 .set CYREG_PRT5_LCD_EN, 0x4000515f
912 .set CYDEV_IO_PRT_PRT6_BASE, 0x40005160
913 .set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010
914 .set CYREG_PRT6_DR, 0x40005160
915 .set CYREG_PRT6_PS, 0x40005161
916 .set CYREG_PRT6_DM0, 0x40005162
917 .set CYREG_PRT6_DM1, 0x40005163
918 .set CYREG_PRT6_DM2, 0x40005164
919 .set CYREG_PRT6_SLW, 0x40005165
920 .set CYREG_PRT6_BYP, 0x40005166
921 .set CYREG_PRT6_BIE, 0x40005167
922 .set CYREG_PRT6_INP_DIS, 0x40005168
923 .set CYREG_PRT6_CTL, 0x40005169
924 .set CYREG_PRT6_PRT, 0x4000516a
925 .set CYREG_PRT6_BIT_MASK, 0x4000516b
926 .set CYREG_PRT6_AMUX, 0x4000516c
927 .set CYREG_PRT6_AG, 0x4000516d
928 .set CYREG_PRT6_LCD_COM_SEG, 0x4000516e
929 .set CYREG_PRT6_LCD_EN, 0x4000516f
930 .set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0
931 .set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010
932 .set CYREG_PRT12_DR, 0x400051c0
933 .set CYREG_PRT12_PS, 0x400051c1
934 .set CYREG_PRT12_DM0, 0x400051c2
935 .set CYREG_PRT12_DM1, 0x400051c3
936 .set CYREG_PRT12_DM2, 0x400051c4
937 .set CYREG_PRT12_SLW, 0x400051c5
938 .set CYREG_PRT12_BYP, 0x400051c6
939 .set CYREG_PRT12_BIE, 0x400051c7
940 .set CYREG_PRT12_INP_DIS, 0x400051c8
941 .set CYREG_PRT12_SIO_HYST_EN, 0x400051c9
942 .set CYREG_PRT12_PRT, 0x400051ca
943 .set CYREG_PRT12_BIT_MASK, 0x400051cb
944 .set CYREG_PRT12_SIO_REG_HIFREQ, 0x400051cc
945 .set CYREG_PRT12_AG, 0x400051cd
946 .set CYREG_PRT12_SIO_CFG, 0x400051ce
947 .set CYREG_PRT12_SIO_DIFF, 0x400051cf
948 .set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0
949 .set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010
950 .set CYREG_PRT15_DR, 0x400051f0
951 .set CYREG_PRT15_PS, 0x400051f1
952 .set CYREG_PRT15_DM0, 0x400051f2
953 .set CYREG_PRT15_DM1, 0x400051f3
954 .set CYREG_PRT15_DM2, 0x400051f4
955 .set CYREG_PRT15_SLW, 0x400051f5
956 .set CYREG_PRT15_BYP, 0x400051f6
957 .set CYREG_PRT15_BIE, 0x400051f7
958 .set CYREG_PRT15_INP_DIS, 0x400051f8
959 .set CYREG_PRT15_CTL, 0x400051f9
960 .set CYREG_PRT15_PRT, 0x400051fa
961 .set CYREG_PRT15_BIT_MASK, 0x400051fb
962 .set CYREG_PRT15_AMUX, 0x400051fc
963 .set CYREG_PRT15_AG, 0x400051fd
964 .set CYREG_PRT15_LCD_COM_SEG, 0x400051fe
965 .set CYREG_PRT15_LCD_EN, 0x400051ff
966 .set CYDEV_PRTDSI_BASE, 0x40005200
967 .set CYDEV_PRTDSI_SIZE, 0x0000007f
968 .set CYDEV_PRTDSI_PRT0_BASE, 0x40005200
969 .set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007
970 .set CYREG_PRT0_OUT_SEL0, 0x40005200
971 .set CYREG_PRT0_OUT_SEL1, 0x40005201
972 .set CYREG_PRT0_OE_SEL0, 0x40005202
973 .set CYREG_PRT0_OE_SEL1, 0x40005203
974 .set CYREG_PRT0_DBL_SYNC_IN, 0x40005204
975 .set CYREG_PRT0_SYNC_OUT, 0x40005205
976 .set CYREG_PRT0_CAPS_SEL, 0x40005206
977 .set CYDEV_PRTDSI_PRT1_BASE, 0x40005208
978 .set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007
979 .set CYREG_PRT1_OUT_SEL0, 0x40005208
980 .set CYREG_PRT1_OUT_SEL1, 0x40005209
981 .set CYREG_PRT1_OE_SEL0, 0x4000520a
982 .set CYREG_PRT1_OE_SEL1, 0x4000520b
983 .set CYREG_PRT1_DBL_SYNC_IN, 0x4000520c
984 .set CYREG_PRT1_SYNC_OUT, 0x4000520d
985 .set CYREG_PRT1_CAPS_SEL, 0x4000520e
986 .set CYDEV_PRTDSI_PRT2_BASE, 0x40005210
987 .set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007
988 .set CYREG_PRT2_OUT_SEL0, 0x40005210
989 .set CYREG_PRT2_OUT_SEL1, 0x40005211
990 .set CYREG_PRT2_OE_SEL0, 0x40005212
991 .set CYREG_PRT2_OE_SEL1, 0x40005213
992 .set CYREG_PRT2_DBL_SYNC_IN, 0x40005214
993 .set CYREG_PRT2_SYNC_OUT, 0x40005215
994 .set CYREG_PRT2_CAPS_SEL, 0x40005216
995 .set CYDEV_PRTDSI_PRT3_BASE, 0x40005218
996 .set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007
997 .set CYREG_PRT3_OUT_SEL0, 0x40005218
998 .set CYREG_PRT3_OUT_SEL1, 0x40005219
999 .set CYREG_PRT3_OE_SEL0, 0x4000521a
1000 .set CYREG_PRT3_OE_SEL1, 0x4000521b
1001 .set CYREG_PRT3_DBL_SYNC_IN, 0x4000521c
1002 .set CYREG_PRT3_SYNC_OUT, 0x4000521d
1003 .set CYREG_PRT3_CAPS_SEL, 0x4000521e
1004 .set CYDEV_PRTDSI_PRT4_BASE, 0x40005220
1005 .set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007
1006 .set CYREG_PRT4_OUT_SEL0, 0x40005220
1007 .set CYREG_PRT4_OUT_SEL1, 0x40005221
1008 .set CYREG_PRT4_OE_SEL0, 0x40005222
1009 .set CYREG_PRT4_OE_SEL1, 0x40005223
1010 .set CYREG_PRT4_DBL_SYNC_IN, 0x40005224
1011 .set CYREG_PRT4_SYNC_OUT, 0x40005225
1012 .set CYREG_PRT4_CAPS_SEL, 0x40005226
1013 .set CYDEV_PRTDSI_PRT5_BASE, 0x40005228
1014 .set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007
1015 .set CYREG_PRT5_OUT_SEL0, 0x40005228
1016 .set CYREG_PRT5_OUT_SEL1, 0x40005229
1017 .set CYREG_PRT5_OE_SEL0, 0x4000522a
1018 .set CYREG_PRT5_OE_SEL1, 0x4000522b
1019 .set CYREG_PRT5_DBL_SYNC_IN, 0x4000522c
1020 .set CYREG_PRT5_SYNC_OUT, 0x4000522d
1021 .set CYREG_PRT5_CAPS_SEL, 0x4000522e
1022 .set CYDEV_PRTDSI_PRT6_BASE, 0x40005230
1023 .set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007
1024 .set CYREG_PRT6_OUT_SEL0, 0x40005230
1025 .set CYREG_PRT6_OUT_SEL1, 0x40005231
1026 .set CYREG_PRT6_OE_SEL0, 0x40005232
1027 .set CYREG_PRT6_OE_SEL1, 0x40005233
1028 .set CYREG_PRT6_DBL_SYNC_IN, 0x40005234
1029 .set CYREG_PRT6_SYNC_OUT, 0x40005235
1030 .set CYREG_PRT6_CAPS_SEL, 0x40005236
1031 .set CYDEV_PRTDSI_PRT12_BASE, 0x40005260
1032 .set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006
1033 .set CYREG_PRT12_OUT_SEL0, 0x40005260
1034 .set CYREG_PRT12_OUT_SEL1, 0x40005261
1035 .set CYREG_PRT12_OE_SEL0, 0x40005262
1036 .set CYREG_PRT12_OE_SEL1, 0x40005263
1037 .set CYREG_PRT12_DBL_SYNC_IN, 0x40005264
1038 .set CYREG_PRT12_SYNC_OUT, 0x40005265
1039 .set CYDEV_PRTDSI_PRT15_BASE, 0x40005278
1040 .set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007
1041 .set CYREG_PRT15_OUT_SEL0, 0x40005278
1042 .set CYREG_PRT15_OUT_SEL1, 0x40005279
1043 .set CYREG_PRT15_OE_SEL0, 0x4000527a
1044 .set CYREG_PRT15_OE_SEL1, 0x4000527b
1045 .set CYREG_PRT15_DBL_SYNC_IN, 0x4000527c
1046 .set CYREG_PRT15_SYNC_OUT, 0x4000527d
1047 .set CYREG_PRT15_CAPS_SEL, 0x4000527e
1048 .set CYDEV_EMIF_BASE, 0x40005400
1049 .set CYDEV_EMIF_SIZE, 0x00000007
1050 .set CYREG_EMIF_NO_UDB, 0x40005400
1051 .set CYREG_EMIF_RP_WAIT_STATES, 0x40005401
1052 .set CYREG_EMIF_MEM_DWN, 0x40005402
1053 .set CYREG_EMIF_MEMCLK_DIV, 0x40005403
1054 .set CYREG_EMIF_CLOCK_EN, 0x40005404
1055 .set CYREG_EMIF_EM_TYPE, 0x40005405
1056 .set CYREG_EMIF_WP_WAIT_STATES, 0x40005406
1057 .set CYDEV_ANAIF_BASE, 0x40005800
1058 .set CYDEV_ANAIF_SIZE, 0x000003a9
1059 .set CYDEV_ANAIF_CFG_BASE, 0x40005800
1060 .set CYDEV_ANAIF_CFG_SIZE, 0x0000010f
1061 .set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800
1062 .set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003
1063 .set CYREG_SC0_CR0, 0x40005800
1064 .set CYREG_SC0_CR1, 0x40005801
1065 .set CYREG_SC0_CR2, 0x40005802
1066 .set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804
1067 .set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003
1068 .set CYREG_SC1_CR0, 0x40005804
1069 .set CYREG_SC1_CR1, 0x40005805
1070 .set CYREG_SC1_CR2, 0x40005806
1071 .set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808
1072 .set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003
1073 .set CYREG_SC2_CR0, 0x40005808
1074 .set CYREG_SC2_CR1, 0x40005809
1075 .set CYREG_SC2_CR2, 0x4000580a
1076 .set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c
1077 .set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003
1078 .set CYREG_SC3_CR0, 0x4000580c
1079 .set CYREG_SC3_CR1, 0x4000580d
1080 .set CYREG_SC3_CR2, 0x4000580e
1081 .set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820
1082 .set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003
1083 .set CYREG_DAC0_CR0, 0x40005820
1084 .set CYREG_DAC0_CR1, 0x40005821
1085 .set CYREG_DAC0_TST, 0x40005822
1086 .set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824
1087 .set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003
1088 .set CYREG_DAC1_CR0, 0x40005824
1089 .set CYREG_DAC1_CR1, 0x40005825
1090 .set CYREG_DAC1_TST, 0x40005826
1091 .set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828
1092 .set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003
1093 .set CYREG_DAC2_CR0, 0x40005828
1094 .set CYREG_DAC2_CR1, 0x40005829
1095 .set CYREG_DAC2_TST, 0x4000582a
1096 .set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c
1097 .set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003
1098 .set CYREG_DAC3_CR0, 0x4000582c
1099 .set CYREG_DAC3_CR1, 0x4000582d
1100 .set CYREG_DAC3_TST, 0x4000582e
1101 .set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840
1102 .set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001
1103 .set CYREG_CMP0_CR, 0x40005840
1104 .set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841
1105 .set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001
1106 .set CYREG_CMP1_CR, 0x40005841
1107 .set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842
1108 .set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001
1109 .set CYREG_CMP2_CR, 0x40005842
1110 .set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843
1111 .set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001
1112 .set CYREG_CMP3_CR, 0x40005843
1113 .set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848
1114 .set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002
1115 .set CYREG_LUT0_CR, 0x40005848
1116 .set CYREG_LUT0_MX, 0x40005849
1117 .set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a
1118 .set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002
1119 .set CYREG_LUT1_CR, 0x4000584a
1120 .set CYREG_LUT1_MX, 0x4000584b
1121 .set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c
1122 .set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002
1123 .set CYREG_LUT2_CR, 0x4000584c
1124 .set CYREG_LUT2_MX, 0x4000584d
1125 .set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e
1126 .set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002
1127 .set CYREG_LUT3_CR, 0x4000584e
1128 .set CYREG_LUT3_MX, 0x4000584f
1129 .set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858
1130 .set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002
1131 .set CYREG_OPAMP0_CR, 0x40005858
1132 .set CYREG_OPAMP0_RSVD, 0x40005859
1133 .set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a
1134 .set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002
1135 .set CYREG_OPAMP1_CR, 0x4000585a
1136 .set CYREG_OPAMP1_RSVD, 0x4000585b
1137 .set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c
1138 .set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002
1139 .set CYREG_OPAMP2_CR, 0x4000585c
1140 .set CYREG_OPAMP2_RSVD, 0x4000585d
1141 .set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e
1142 .set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002
1143 .set CYREG_OPAMP3_CR, 0x4000585e
1144 .set CYREG_OPAMP3_RSVD, 0x4000585f
1145 .set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868
1146 .set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002
1147 .set CYREG_LCDDAC_CR0, 0x40005868
1148 .set CYREG_LCDDAC_CR1, 0x40005869
1149 .set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a
1150 .set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001
1151 .set CYREG_LCDDRV_CR, 0x4000586a
1152 .set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b
1153 .set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001
1154 .set CYREG_LCDTMR_CFG, 0x4000586b
1155 .set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c
1156 .set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004
1157 .set CYREG_BG_CR0, 0x4000586c
1158 .set CYREG_BG_RSVD, 0x4000586d
1159 .set CYREG_BG_DFT0, 0x4000586e
1160 .set CYREG_BG_DFT1, 0x4000586f
1161 .set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870
1162 .set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002
1163 .set CYREG_CAPSL_CFG0, 0x40005870
1164 .set CYREG_CAPSL_CFG1, 0x40005871
1165 .set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872
1166 .set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002
1167 .set CYREG_CAPSR_CFG0, 0x40005872
1168 .set CYREG_CAPSR_CFG1, 0x40005873
1169 .set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876
1170 .set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002
1171 .set CYREG_PUMP_CR0, 0x40005876
1172 .set CYREG_PUMP_CR1, 0x40005877
1173 .set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878
1174 .set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002
1175 .set CYREG_LPF0_CR0, 0x40005878
1176 .set CYREG_LPF0_RSVD, 0x40005879
1177 .set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a
1178 .set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002
1179 .set CYREG_LPF1_CR0, 0x4000587a
1180 .set CYREG_LPF1_RSVD, 0x4000587b
1181 .set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c
1182 .set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001
1183 .set CYREG_ANAIF_CFG_MISC_CR0, 0x4000587c
1184 .set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880
1185 .set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020
1186 .set CYREG_DSM0_CR0, 0x40005880
1187 .set CYREG_DSM0_CR1, 0x40005881
1188 .set CYREG_DSM0_CR2, 0x40005882
1189 .set CYREG_DSM0_CR3, 0x40005883
1190 .set CYREG_DSM0_CR4, 0x40005884
1191 .set CYREG_DSM0_CR5, 0x40005885
1192 .set CYREG_DSM0_CR6, 0x40005886
1193 .set CYREG_DSM0_CR7, 0x40005887
1194 .set CYREG_DSM0_CR8, 0x40005888
1195 .set CYREG_DSM0_CR9, 0x40005889
1196 .set CYREG_DSM0_CR10, 0x4000588a
1197 .set CYREG_DSM0_CR11, 0x4000588b
1198 .set CYREG_DSM0_CR12, 0x4000588c
1199 .set CYREG_DSM0_CR13, 0x4000588d
1200 .set CYREG_DSM0_CR14, 0x4000588e
1201 .set CYREG_DSM0_CR15, 0x4000588f
1202 .set CYREG_DSM0_CR16, 0x40005890
1203 .set CYREG_DSM0_CR17, 0x40005891
1204 .set CYREG_DSM0_REF0, 0x40005892
1205 .set CYREG_DSM0_REF1, 0x40005893
1206 .set CYREG_DSM0_REF2, 0x40005894
1207 .set CYREG_DSM0_REF3, 0x40005895
1208 .set CYREG_DSM0_DEM0, 0x40005896
1209 .set CYREG_DSM0_DEM1, 0x40005897
1210 .set CYREG_DSM0_TST0, 0x40005898
1211 .set CYREG_DSM0_TST1, 0x40005899
1212 .set CYREG_DSM0_BUF0, 0x4000589a
1213 .set CYREG_DSM0_BUF1, 0x4000589b
1214 .set CYREG_DSM0_BUF2, 0x4000589c
1215 .set CYREG_DSM0_BUF3, 0x4000589d
1216 .set CYREG_DSM0_MISC, 0x4000589e
1217 .set CYREG_DSM0_RSVD1, 0x4000589f
1218 .set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900
1219 .set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007
1220 .set CYREG_SAR0_CSR0, 0x40005900
1221 .set CYREG_SAR0_CSR1, 0x40005901
1222 .set CYREG_SAR0_CSR2, 0x40005902
1223 .set CYREG_SAR0_CSR3, 0x40005903
1224 .set CYREG_SAR0_CSR4, 0x40005904
1225 .set CYREG_SAR0_CSR5, 0x40005905
1226 .set CYREG_SAR0_CSR6, 0x40005906
1227 .set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908
1228 .set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007
1229 .set CYREG_SAR1_CSR0, 0x40005908
1230 .set CYREG_SAR1_CSR1, 0x40005909
1231 .set CYREG_SAR1_CSR2, 0x4000590a
1232 .set CYREG_SAR1_CSR3, 0x4000590b
1233 .set CYREG_SAR1_CSR4, 0x4000590c
1234 .set CYREG_SAR1_CSR5, 0x4000590d
1235 .set CYREG_SAR1_CSR6, 0x4000590e
1236 .set CYDEV_ANAIF_RT_BASE, 0x40005a00
1237 .set CYDEV_ANAIF_RT_SIZE, 0x00000162
1238 .set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00
1239 .set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d
1240 .set CYREG_SC0_SW0, 0x40005a00
1241 .set CYREG_SC0_SW2, 0x40005a02
1242 .set CYREG_SC0_SW3, 0x40005a03
1243 .set CYREG_SC0_SW4, 0x40005a04
1244 .set CYREG_SC0_SW6, 0x40005a06
1245 .set CYREG_SC0_SW7, 0x40005a07
1246 .set CYREG_SC0_SW8, 0x40005a08
1247 .set CYREG_SC0_SW10, 0x40005a0a
1248 .set CYREG_SC0_CLK, 0x40005a0b
1249 .set CYREG_SC0_BST, 0x40005a0c
1250 .set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10
1251 .set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d
1252 .set CYREG_SC1_SW0, 0x40005a10
1253 .set CYREG_SC1_SW2, 0x40005a12
1254 .set CYREG_SC1_SW3, 0x40005a13
1255 .set CYREG_SC1_SW4, 0x40005a14
1256 .set CYREG_SC1_SW6, 0x40005a16
1257 .set CYREG_SC1_SW7, 0x40005a17
1258 .set CYREG_SC1_SW8, 0x40005a18
1259 .set CYREG_SC1_SW10, 0x40005a1a
1260 .set CYREG_SC1_CLK, 0x40005a1b
1261 .set CYREG_SC1_BST, 0x40005a1c
1262 .set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20
1263 .set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d
1264 .set CYREG_SC2_SW0, 0x40005a20
1265 .set CYREG_SC2_SW2, 0x40005a22
1266 .set CYREG_SC2_SW3, 0x40005a23
1267 .set CYREG_SC2_SW4, 0x40005a24
1268 .set CYREG_SC2_SW6, 0x40005a26
1269 .set CYREG_SC2_SW7, 0x40005a27
1270 .set CYREG_SC2_SW8, 0x40005a28
1271 .set CYREG_SC2_SW10, 0x40005a2a
1272 .set CYREG_SC2_CLK, 0x40005a2b
1273 .set CYREG_SC2_BST, 0x40005a2c
1274 .set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30
1275 .set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d
1276 .set CYREG_SC3_SW0, 0x40005a30
1277 .set CYREG_SC3_SW2, 0x40005a32
1278 .set CYREG_SC3_SW3, 0x40005a33
1279 .set CYREG_SC3_SW4, 0x40005a34
1280 .set CYREG_SC3_SW6, 0x40005a36
1281 .set CYREG_SC3_SW7, 0x40005a37
1282 .set CYREG_SC3_SW8, 0x40005a38
1283 .set CYREG_SC3_SW10, 0x40005a3a
1284 .set CYREG_SC3_CLK, 0x40005a3b
1285 .set CYREG_SC3_BST, 0x40005a3c
1286 .set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80
1287 .set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008
1288 .set CYREG_DAC0_SW0, 0x40005a80
1289 .set CYREG_DAC0_SW2, 0x40005a82
1290 .set CYREG_DAC0_SW3, 0x40005a83
1291 .set CYREG_DAC0_SW4, 0x40005a84
1292 .set CYREG_DAC0_STROBE, 0x40005a87
1293 .set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88
1294 .set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008
1295 .set CYREG_DAC1_SW0, 0x40005a88
1296 .set CYREG_DAC1_SW2, 0x40005a8a
1297 .set CYREG_DAC1_SW3, 0x40005a8b
1298 .set CYREG_DAC1_SW4, 0x40005a8c
1299 .set CYREG_DAC1_STROBE, 0x40005a8f
1300 .set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90
1301 .set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008
1302 .set CYREG_DAC2_SW0, 0x40005a90
1303 .set CYREG_DAC2_SW2, 0x40005a92
1304 .set CYREG_DAC2_SW3, 0x40005a93
1305 .set CYREG_DAC2_SW4, 0x40005a94
1306 .set CYREG_DAC2_STROBE, 0x40005a97
1307 .set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98
1308 .set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008
1309 .set CYREG_DAC3_SW0, 0x40005a98
1310 .set CYREG_DAC3_SW2, 0x40005a9a
1311 .set CYREG_DAC3_SW3, 0x40005a9b
1312 .set CYREG_DAC3_SW4, 0x40005a9c
1313 .set CYREG_DAC3_STROBE, 0x40005a9f
1314 .set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0
1315 .set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008
1316 .set CYREG_CMP0_SW0, 0x40005ac0
1317 .set CYREG_CMP0_SW2, 0x40005ac2
1318 .set CYREG_CMP0_SW3, 0x40005ac3
1319 .set CYREG_CMP0_SW4, 0x40005ac4
1320 .set CYREG_CMP0_SW6, 0x40005ac6
1321 .set CYREG_CMP0_CLK, 0x40005ac7
1322 .set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8
1323 .set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008
1324 .set CYREG_CMP1_SW0, 0x40005ac8
1325 .set CYREG_CMP1_SW2, 0x40005aca
1326 .set CYREG_CMP1_SW3, 0x40005acb
1327 .set CYREG_CMP1_SW4, 0x40005acc
1328 .set CYREG_CMP1_SW6, 0x40005ace
1329 .set CYREG_CMP1_CLK, 0x40005acf
1330 .set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0
1331 .set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008
1332 .set CYREG_CMP2_SW0, 0x40005ad0
1333 .set CYREG_CMP2_SW2, 0x40005ad2
1334 .set CYREG_CMP2_SW3, 0x40005ad3
1335 .set CYREG_CMP2_SW4, 0x40005ad4
1336 .set CYREG_CMP2_SW6, 0x40005ad6
1337 .set CYREG_CMP2_CLK, 0x40005ad7
1338 .set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8
1339 .set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008
1340 .set CYREG_CMP3_SW0, 0x40005ad8
1341 .set CYREG_CMP3_SW2, 0x40005ada
1342 .set CYREG_CMP3_SW3, 0x40005adb
1343 .set CYREG_CMP3_SW4, 0x40005adc
1344 .set CYREG_CMP3_SW6, 0x40005ade
1345 .set CYREG_CMP3_CLK, 0x40005adf
1346 .set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00
1347 .set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008
1348 .set CYREG_DSM0_SW0, 0x40005b00
1349 .set CYREG_DSM0_SW2, 0x40005b02
1350 .set CYREG_DSM0_SW3, 0x40005b03
1351 .set CYREG_DSM0_SW4, 0x40005b04
1352 .set CYREG_DSM0_SW6, 0x40005b06
1353 .set CYREG_DSM0_CLK, 0x40005b07
1354 .set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20
1355 .set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008
1356 .set CYREG_SAR0_SW0, 0x40005b20
1357 .set CYREG_SAR0_SW2, 0x40005b22
1358 .set CYREG_SAR0_SW3, 0x40005b23
1359 .set CYREG_SAR0_SW4, 0x40005b24
1360 .set CYREG_SAR0_SW6, 0x40005b26
1361 .set CYREG_SAR0_CLK, 0x40005b27
1362 .set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28
1363 .set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008
1364 .set CYREG_SAR1_SW0, 0x40005b28
1365 .set CYREG_SAR1_SW2, 0x40005b2a
1366 .set CYREG_SAR1_SW3, 0x40005b2b
1367 .set CYREG_SAR1_SW4, 0x40005b2c
1368 .set CYREG_SAR1_SW6, 0x40005b2e
1369 .set CYREG_SAR1_CLK, 0x40005b2f
1370 .set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40
1371 .set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002
1372 .set CYREG_OPAMP0_MX, 0x40005b40
1373 .set CYREG_OPAMP0_SW, 0x40005b41
1374 .set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42
1375 .set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002
1376 .set CYREG_OPAMP1_MX, 0x40005b42
1377 .set CYREG_OPAMP1_SW, 0x40005b43
1378 .set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44
1379 .set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002
1380 .set CYREG_OPAMP2_MX, 0x40005b44
1381 .set CYREG_OPAMP2_SW, 0x40005b45
1382 .set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46
1383 .set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002
1384 .set CYREG_OPAMP3_MX, 0x40005b46
1385 .set CYREG_OPAMP3_SW, 0x40005b47
1386 .set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50
1387 .set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005
1388 .set CYREG_LCDDAC_SW0, 0x40005b50
1389 .set CYREG_LCDDAC_SW1, 0x40005b51
1390 .set CYREG_LCDDAC_SW2, 0x40005b52
1391 .set CYREG_LCDDAC_SW3, 0x40005b53
1392 .set CYREG_LCDDAC_SW4, 0x40005b54
1393 .set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56
1394 .set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001
1395 .set CYREG_SC_MISC, 0x40005b56
1396 .set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58
1397 .set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004
1398 .set CYREG_BUS_SW0, 0x40005b58
1399 .set CYREG_BUS_SW2, 0x40005b5a
1400 .set CYREG_BUS_SW3, 0x40005b5b
1401 .set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c
1402 .set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006
1403 .set CYREG_DFT_CR0, 0x40005b5c
1404 .set CYREG_DFT_CR1, 0x40005b5d
1405 .set CYREG_DFT_CR2, 0x40005b5e
1406 .set CYREG_DFT_CR3, 0x40005b5f
1407 .set CYREG_DFT_CR4, 0x40005b60
1408 .set CYREG_DFT_CR5, 0x40005b61
1409 .set CYDEV_ANAIF_WRK_BASE, 0x40005b80
1410 .set CYDEV_ANAIF_WRK_SIZE, 0x00000029
1411 .set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80
1412 .set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001
1413 .set CYREG_DAC0_D, 0x40005b80
1414 .set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81
1415 .set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001
1416 .set CYREG_DAC1_D, 0x40005b81
1417 .set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82
1418 .set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001
1419 .set CYREG_DAC2_D, 0x40005b82
1420 .set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83
1421 .set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001
1422 .set CYREG_DAC3_D, 0x40005b83
1423 .set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88
1424 .set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002
1425 .set CYREG_DSM0_OUT0, 0x40005b88
1426 .set CYREG_DSM0_OUT1, 0x40005b89
1427 .set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90
1428 .set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005
1429 .set CYREG_LUT_SR, 0x40005b90
1430 .set CYREG_LUT_WRK1, 0x40005b91
1431 .set CYREG_LUT_MSK, 0x40005b92
1432 .set CYREG_LUT_CLK, 0x40005b93
1433 .set CYREG_LUT_CPTR, 0x40005b94
1434 .set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96
1435 .set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002
1436 .set CYREG_CMP_WRK, 0x40005b96
1437 .set CYREG_CMP_TST, 0x40005b97
1438 .set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98
1439 .set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005
1440 .set CYREG_SC_SR, 0x40005b98
1441 .set CYREG_SC_WRK1, 0x40005b99
1442 .set CYREG_SC_MSK, 0x40005b9a
1443 .set CYREG_SC_CMPINV, 0x40005b9b
1444 .set CYREG_SC_CPTR, 0x40005b9c
1445 .set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0
1446 .set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002
1447 .set CYREG_SAR0_WRK0, 0x40005ba0
1448 .set CYREG_SAR0_WRK1, 0x40005ba1
1449 .set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2
1450 .set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002
1451 .set CYREG_SAR1_WRK0, 0x40005ba2
1452 .set CYREG_SAR1_WRK1, 0x40005ba3
1453 .set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8
1454 .set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001
1455 .set CYREG_ANAIF_WRK_SARS_SOF, 0x40005ba8
1456 .set CYDEV_USB_BASE, 0x40006000
1457 .set CYDEV_USB_SIZE, 0x00000300
1458 .set CYREG_USB_EP0_DR0, 0x40006000
1459 .set CYREG_USB_EP0_DR1, 0x40006001
1460 .set CYREG_USB_EP0_DR2, 0x40006002
1461 .set CYREG_USB_EP0_DR3, 0x40006003
1462 .set CYREG_USB_EP0_DR4, 0x40006004
1463 .set CYREG_USB_EP0_DR5, 0x40006005
1464 .set CYREG_USB_EP0_DR6, 0x40006006
1465 .set CYREG_USB_EP0_DR7, 0x40006007
1466 .set CYREG_USB_CR0, 0x40006008
1467 .set CYREG_USB_CR1, 0x40006009
1468 .set CYREG_USB_SIE_EP_INT_EN, 0x4000600a
1469 .set CYREG_USB_SIE_EP_INT_SR, 0x4000600b
1470 .set CYDEV_USB_SIE_EP1_BASE, 0x4000600c
1471 .set CYDEV_USB_SIE_EP1_SIZE, 0x00000003
1472 .set CYREG_USB_SIE_EP1_CNT0, 0x4000600c
1473 .set CYREG_USB_SIE_EP1_CNT1, 0x4000600d
1474 .set CYREG_USB_SIE_EP1_CR0, 0x4000600e
1475 .set CYREG_USB_USBIO_CR0, 0x40006010
1476 .set CYREG_USB_USBIO_CR1, 0x40006012
1477 .set CYREG_USB_DYN_RECONFIG, 0x40006014
1478 .set CYREG_USB_SOF0, 0x40006018
1479 .set CYREG_USB_SOF1, 0x40006019
1480 .set CYDEV_USB_SIE_EP2_BASE, 0x4000601c
1481 .set CYDEV_USB_SIE_EP2_SIZE, 0x00000003
1482 .set CYREG_USB_SIE_EP2_CNT0, 0x4000601c
1483 .set CYREG_USB_SIE_EP2_CNT1, 0x4000601d
1484 .set CYREG_USB_SIE_EP2_CR0, 0x4000601e
1485 .set CYREG_USB_EP0_CR, 0x40006028
1486 .set CYREG_USB_EP0_CNT, 0x40006029
1487 .set CYDEV_USB_SIE_EP3_BASE, 0x4000602c
1488 .set CYDEV_USB_SIE_EP3_SIZE, 0x00000003
1489 .set CYREG_USB_SIE_EP3_CNT0, 0x4000602c
1490 .set CYREG_USB_SIE_EP3_CNT1, 0x4000602d
1491 .set CYREG_USB_SIE_EP3_CR0, 0x4000602e
1492 .set CYDEV_USB_SIE_EP4_BASE, 0x4000603c
1493 .set CYDEV_USB_SIE_EP4_SIZE, 0x00000003
1494 .set CYREG_USB_SIE_EP4_CNT0, 0x4000603c
1495 .set CYREG_USB_SIE_EP4_CNT1, 0x4000603d
1496 .set CYREG_USB_SIE_EP4_CR0, 0x4000603e
1497 .set CYDEV_USB_SIE_EP5_BASE, 0x4000604c
1498 .set CYDEV_USB_SIE_EP5_SIZE, 0x00000003
1499 .set CYREG_USB_SIE_EP5_CNT0, 0x4000604c
1500 .set CYREG_USB_SIE_EP5_CNT1, 0x4000604d
1501 .set CYREG_USB_SIE_EP5_CR0, 0x4000604e
1502 .set CYDEV_USB_SIE_EP6_BASE, 0x4000605c
1503 .set CYDEV_USB_SIE_EP6_SIZE, 0x00000003
1504 .set CYREG_USB_SIE_EP6_CNT0, 0x4000605c
1505 .set CYREG_USB_SIE_EP6_CNT1, 0x4000605d
1506 .set CYREG_USB_SIE_EP6_CR0, 0x4000605e
1507 .set CYDEV_USB_SIE_EP7_BASE, 0x4000606c
1508 .set CYDEV_USB_SIE_EP7_SIZE, 0x00000003
1509 .set CYREG_USB_SIE_EP7_CNT0, 0x4000606c
1510 .set CYREG_USB_SIE_EP7_CNT1, 0x4000606d
1511 .set CYREG_USB_SIE_EP7_CR0, 0x4000606e
1512 .set CYDEV_USB_SIE_EP8_BASE, 0x4000607c
1513 .set CYDEV_USB_SIE_EP8_SIZE, 0x00000003
1514 .set CYREG_USB_SIE_EP8_CNT0, 0x4000607c
1515 .set CYREG_USB_SIE_EP8_CNT1, 0x4000607d
1516 .set CYREG_USB_SIE_EP8_CR0, 0x4000607e
1517 .set CYDEV_USB_ARB_EP1_BASE, 0x40006080
1518 .set CYDEV_USB_ARB_EP1_SIZE, 0x00000003
1519 .set CYREG_USB_ARB_EP1_CFG, 0x40006080
1520 .set CYREG_USB_ARB_EP1_INT_EN, 0x40006081
1521 .set CYREG_USB_ARB_EP1_SR, 0x40006082
1522 .set CYDEV_USB_ARB_RW1_BASE, 0x40006084
1523 .set CYDEV_USB_ARB_RW1_SIZE, 0x00000005
1524 .set CYREG_USB_ARB_RW1_WA, 0x40006084
1525 .set CYREG_USB_ARB_RW1_WA_MSB, 0x40006085
1526 .set CYREG_USB_ARB_RW1_RA, 0x40006086
1527 .set CYREG_USB_ARB_RW1_RA_MSB, 0x40006087
1528 .set CYREG_USB_ARB_RW1_DR, 0x40006088
1529 .set CYREG_USB_BUF_SIZE, 0x4000608c
1530 .set CYREG_USB_EP_ACTIVE, 0x4000608e
1531 .set CYREG_USB_EP_TYPE, 0x4000608f
1532 .set CYDEV_USB_ARB_EP2_BASE, 0x40006090
1533 .set CYDEV_USB_ARB_EP2_SIZE, 0x00000003
1534 .set CYREG_USB_ARB_EP2_CFG, 0x40006090
1535 .set CYREG_USB_ARB_EP2_INT_EN, 0x40006091
1536 .set CYREG_USB_ARB_EP2_SR, 0x40006092
1537 .set CYDEV_USB_ARB_RW2_BASE, 0x40006094
1538 .set CYDEV_USB_ARB_RW2_SIZE, 0x00000005
1539 .set CYREG_USB_ARB_RW2_WA, 0x40006094
1540 .set CYREG_USB_ARB_RW2_WA_MSB, 0x40006095
1541 .set CYREG_USB_ARB_RW2_RA, 0x40006096
1542 .set CYREG_USB_ARB_RW2_RA_MSB, 0x40006097
1543 .set CYREG_USB_ARB_RW2_DR, 0x40006098
1544 .set CYREG_USB_ARB_CFG, 0x4000609c
1545 .set CYREG_USB_USB_CLK_EN, 0x4000609d
1546 .set CYREG_USB_ARB_INT_EN, 0x4000609e
1547 .set CYREG_USB_ARB_INT_SR, 0x4000609f
1548 .set CYDEV_USB_ARB_EP3_BASE, 0x400060a0
1549 .set CYDEV_USB_ARB_EP3_SIZE, 0x00000003
1550 .set CYREG_USB_ARB_EP3_CFG, 0x400060a0
1551 .set CYREG_USB_ARB_EP3_INT_EN, 0x400060a1
1552 .set CYREG_USB_ARB_EP3_SR, 0x400060a2
1553 .set CYDEV_USB_ARB_RW3_BASE, 0x400060a4
1554 .set CYDEV_USB_ARB_RW3_SIZE, 0x00000005
1555 .set CYREG_USB_ARB_RW3_WA, 0x400060a4
1556 .set CYREG_USB_ARB_RW3_WA_MSB, 0x400060a5
1557 .set CYREG_USB_ARB_RW3_RA, 0x400060a6
1558 .set CYREG_USB_ARB_RW3_RA_MSB, 0x400060a7
1559 .set CYREG_USB_ARB_RW3_DR, 0x400060a8
1560 .set CYREG_USB_CWA, 0x400060ac
1561 .set CYREG_USB_CWA_MSB, 0x400060ad
1562 .set CYDEV_USB_ARB_EP4_BASE, 0x400060b0
1563 .set CYDEV_USB_ARB_EP4_SIZE, 0x00000003
1564 .set CYREG_USB_ARB_EP4_CFG, 0x400060b0
1565 .set CYREG_USB_ARB_EP4_INT_EN, 0x400060b1
1566 .set CYREG_USB_ARB_EP4_SR, 0x400060b2
1567 .set CYDEV_USB_ARB_RW4_BASE, 0x400060b4
1568 .set CYDEV_USB_ARB_RW4_SIZE, 0x00000005
1569 .set CYREG_USB_ARB_RW4_WA, 0x400060b4
1570 .set CYREG_USB_ARB_RW4_WA_MSB, 0x400060b5
1571 .set CYREG_USB_ARB_RW4_RA, 0x400060b6
1572 .set CYREG_USB_ARB_RW4_RA_MSB, 0x400060b7
1573 .set CYREG_USB_ARB_RW4_DR, 0x400060b8
1574 .set CYREG_USB_DMA_THRES, 0x400060bc
1575 .set CYREG_USB_DMA_THRES_MSB, 0x400060bd
1576 .set CYDEV_USB_ARB_EP5_BASE, 0x400060c0
1577 .set CYDEV_USB_ARB_EP5_SIZE, 0x00000003
1578 .set CYREG_USB_ARB_EP5_CFG, 0x400060c0
1579 .set CYREG_USB_ARB_EP5_INT_EN, 0x400060c1
1580 .set CYREG_USB_ARB_EP5_SR, 0x400060c2
1581 .set CYDEV_USB_ARB_RW5_BASE, 0x400060c4
1582 .set CYDEV_USB_ARB_RW5_SIZE, 0x00000005
1583 .set CYREG_USB_ARB_RW5_WA, 0x400060c4
1584 .set CYREG_USB_ARB_RW5_WA_MSB, 0x400060c5
1585 .set CYREG_USB_ARB_RW5_RA, 0x400060c6
1586 .set CYREG_USB_ARB_RW5_RA_MSB, 0x400060c7
1587 .set CYREG_USB_ARB_RW5_DR, 0x400060c8
1588 .set CYREG_USB_BUS_RST_CNT, 0x400060cc
1589 .set CYDEV_USB_ARB_EP6_BASE, 0x400060d0
1590 .set CYDEV_USB_ARB_EP6_SIZE, 0x00000003
1591 .set CYREG_USB_ARB_EP6_CFG, 0x400060d0
1592 .set CYREG_USB_ARB_EP6_INT_EN, 0x400060d1
1593 .set CYREG_USB_ARB_EP6_SR, 0x400060d2
1594 .set CYDEV_USB_ARB_RW6_BASE, 0x400060d4
1595 .set CYDEV_USB_ARB_RW6_SIZE, 0x00000005
1596 .set CYREG_USB_ARB_RW6_WA, 0x400060d4
1597 .set CYREG_USB_ARB_RW6_WA_MSB, 0x400060d5
1598 .set CYREG_USB_ARB_RW6_RA, 0x400060d6
1599 .set CYREG_USB_ARB_RW6_RA_MSB, 0x400060d7
1600 .set CYREG_USB_ARB_RW6_DR, 0x400060d8
1601 .set CYDEV_USB_ARB_EP7_BASE, 0x400060e0
1602 .set CYDEV_USB_ARB_EP7_SIZE, 0x00000003
1603 .set CYREG_USB_ARB_EP7_CFG, 0x400060e0
1604 .set CYREG_USB_ARB_EP7_INT_EN, 0x400060e1
1605 .set CYREG_USB_ARB_EP7_SR, 0x400060e2
1606 .set CYDEV_USB_ARB_RW7_BASE, 0x400060e4
1607 .set CYDEV_USB_ARB_RW7_SIZE, 0x00000005
1608 .set CYREG_USB_ARB_RW7_WA, 0x400060e4
1609 .set CYREG_USB_ARB_RW7_WA_MSB, 0x400060e5
1610 .set CYREG_USB_ARB_RW7_RA, 0x400060e6
1611 .set CYREG_USB_ARB_RW7_RA_MSB, 0x400060e7
1612 .set CYREG_USB_ARB_RW7_DR, 0x400060e8
1613 .set CYDEV_USB_ARB_EP8_BASE, 0x400060f0
1614 .set CYDEV_USB_ARB_EP8_SIZE, 0x00000003
1615 .set CYREG_USB_ARB_EP8_CFG, 0x400060f0
1616 .set CYREG_USB_ARB_EP8_INT_EN, 0x400060f1
1617 .set CYREG_USB_ARB_EP8_SR, 0x400060f2
1618 .set CYDEV_USB_ARB_RW8_BASE, 0x400060f4
1619 .set CYDEV_USB_ARB_RW8_SIZE, 0x00000005
1620 .set CYREG_USB_ARB_RW8_WA, 0x400060f4
1621 .set CYREG_USB_ARB_RW8_WA_MSB, 0x400060f5
1622 .set CYREG_USB_ARB_RW8_RA, 0x400060f6
1623 .set CYREG_USB_ARB_RW8_RA_MSB, 0x400060f7
1624 .set CYREG_USB_ARB_RW8_DR, 0x400060f8
1625 .set CYDEV_USB_MEM_BASE, 0x40006100
1626 .set CYDEV_USB_MEM_SIZE, 0x00000200
1627 .set CYREG_USB_MEM_DATA_MBASE, 0x40006100
1628 .set CYREG_USB_MEM_DATA_MSIZE, 0x00000200
1629 .set CYDEV_UWRK_BASE, 0x40006400
1630 .set CYDEV_UWRK_SIZE, 0x00000b60
1631 .set CYDEV_UWRK_UWRK8_BASE, 0x40006400
1632 .set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0
1633 .set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400
1634 .set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0
1635 .set CYREG_B0_UDB00_A0, 0x40006400
1636 .set CYREG_B0_UDB01_A0, 0x40006401
1637 .set CYREG_B0_UDB02_A0, 0x40006402
1638 .set CYREG_B0_UDB03_A0, 0x40006403
1639 .set CYREG_B0_UDB04_A0, 0x40006404
1640 .set CYREG_B0_UDB05_A0, 0x40006405
1641 .set CYREG_B0_UDB06_A0, 0x40006406
1642 .set CYREG_B0_UDB07_A0, 0x40006407
1643 .set CYREG_B0_UDB08_A0, 0x40006408
1644 .set CYREG_B0_UDB09_A0, 0x40006409
1645 .set CYREG_B0_UDB10_A0, 0x4000640a
1646 .set CYREG_B0_UDB11_A0, 0x4000640b
1647 .set CYREG_B0_UDB12_A0, 0x4000640c
1648 .set CYREG_B0_UDB13_A0, 0x4000640d
1649 .set CYREG_B0_UDB14_A0, 0x4000640e
1650 .set CYREG_B0_UDB15_A0, 0x4000640f
1651 .set CYREG_B0_UDB00_A1, 0x40006410
1652 .set CYREG_B0_UDB01_A1, 0x40006411
1653 .set CYREG_B0_UDB02_A1, 0x40006412
1654 .set CYREG_B0_UDB03_A1, 0x40006413
1655 .set CYREG_B0_UDB04_A1, 0x40006414
1656 .set CYREG_B0_UDB05_A1, 0x40006415
1657 .set CYREG_B0_UDB06_A1, 0x40006416
1658 .set CYREG_B0_UDB07_A1, 0x40006417
1659 .set CYREG_B0_UDB08_A1, 0x40006418
1660 .set CYREG_B0_UDB09_A1, 0x40006419
1661 .set CYREG_B0_UDB10_A1, 0x4000641a
1662 .set CYREG_B0_UDB11_A1, 0x4000641b
1663 .set CYREG_B0_UDB12_A1, 0x4000641c
1664 .set CYREG_B0_UDB13_A1, 0x4000641d
1665 .set CYREG_B0_UDB14_A1, 0x4000641e
1666 .set CYREG_B0_UDB15_A1, 0x4000641f
1667 .set CYREG_B0_UDB00_D0, 0x40006420
1668 .set CYREG_B0_UDB01_D0, 0x40006421
1669 .set CYREG_B0_UDB02_D0, 0x40006422
1670 .set CYREG_B0_UDB03_D0, 0x40006423
1671 .set CYREG_B0_UDB04_D0, 0x40006424
1672 .set CYREG_B0_UDB05_D0, 0x40006425
1673 .set CYREG_B0_UDB06_D0, 0x40006426
1674 .set CYREG_B0_UDB07_D0, 0x40006427
1675 .set CYREG_B0_UDB08_D0, 0x40006428
1676 .set CYREG_B0_UDB09_D0, 0x40006429
1677 .set CYREG_B0_UDB10_D0, 0x4000642a
1678 .set CYREG_B0_UDB11_D0, 0x4000642b
1679 .set CYREG_B0_UDB12_D0, 0x4000642c
1680 .set CYREG_B0_UDB13_D0, 0x4000642d
1681 .set CYREG_B0_UDB14_D0, 0x4000642e
1682 .set CYREG_B0_UDB15_D0, 0x4000642f
1683 .set CYREG_B0_UDB00_D1, 0x40006430
1684 .set CYREG_B0_UDB01_D1, 0x40006431
1685 .set CYREG_B0_UDB02_D1, 0x40006432
1686 .set CYREG_B0_UDB03_D1, 0x40006433
1687 .set CYREG_B0_UDB04_D1, 0x40006434
1688 .set CYREG_B0_UDB05_D1, 0x40006435
1689 .set CYREG_B0_UDB06_D1, 0x40006436
1690 .set CYREG_B0_UDB07_D1, 0x40006437
1691 .set CYREG_B0_UDB08_D1, 0x40006438
1692 .set CYREG_B0_UDB09_D1, 0x40006439
1693 .set CYREG_B0_UDB10_D1, 0x4000643a
1694 .set CYREG_B0_UDB11_D1, 0x4000643b
1695 .set CYREG_B0_UDB12_D1, 0x4000643c
1696 .set CYREG_B0_UDB13_D1, 0x4000643d
1697 .set CYREG_B0_UDB14_D1, 0x4000643e
1698 .set CYREG_B0_UDB15_D1, 0x4000643f
1699 .set CYREG_B0_UDB00_F0, 0x40006440
1700 .set CYREG_B0_UDB01_F0, 0x40006441
1701 .set CYREG_B0_UDB02_F0, 0x40006442
1702 .set CYREG_B0_UDB03_F0, 0x40006443
1703 .set CYREG_B0_UDB04_F0, 0x40006444
1704 .set CYREG_B0_UDB05_F0, 0x40006445
1705 .set CYREG_B0_UDB06_F0, 0x40006446
1706 .set CYREG_B0_UDB07_F0, 0x40006447
1707 .set CYREG_B0_UDB08_F0, 0x40006448
1708 .set CYREG_B0_UDB09_F0, 0x40006449
1709 .set CYREG_B0_UDB10_F0, 0x4000644a
1710 .set CYREG_B0_UDB11_F0, 0x4000644b
1711 .set CYREG_B0_UDB12_F0, 0x4000644c
1712 .set CYREG_B0_UDB13_F0, 0x4000644d
1713 .set CYREG_B0_UDB14_F0, 0x4000644e
1714 .set CYREG_B0_UDB15_F0, 0x4000644f
1715 .set CYREG_B0_UDB00_F1, 0x40006450
1716 .set CYREG_B0_UDB01_F1, 0x40006451
1717 .set CYREG_B0_UDB02_F1, 0x40006452
1718 .set CYREG_B0_UDB03_F1, 0x40006453
1719 .set CYREG_B0_UDB04_F1, 0x40006454
1720 .set CYREG_B0_UDB05_F1, 0x40006455
1721 .set CYREG_B0_UDB06_F1, 0x40006456
1722 .set CYREG_B0_UDB07_F1, 0x40006457
1723 .set CYREG_B0_UDB08_F1, 0x40006458
1724 .set CYREG_B0_UDB09_F1, 0x40006459
1725 .set CYREG_B0_UDB10_F1, 0x4000645a
1726 .set CYREG_B0_UDB11_F1, 0x4000645b
1727 .set CYREG_B0_UDB12_F1, 0x4000645c
1728 .set CYREG_B0_UDB13_F1, 0x4000645d
1729 .set CYREG_B0_UDB14_F1, 0x4000645e
1730 .set CYREG_B0_UDB15_F1, 0x4000645f
1731 .set CYREG_B0_UDB00_ST, 0x40006460
1732 .set CYREG_B0_UDB01_ST, 0x40006461
1733 .set CYREG_B0_UDB02_ST, 0x40006462
1734 .set CYREG_B0_UDB03_ST, 0x40006463
1735 .set CYREG_B0_UDB04_ST, 0x40006464
1736 .set CYREG_B0_UDB05_ST, 0x40006465
1737 .set CYREG_B0_UDB06_ST, 0x40006466
1738 .set CYREG_B0_UDB07_ST, 0x40006467
1739 .set CYREG_B0_UDB08_ST, 0x40006468
1740 .set CYREG_B0_UDB09_ST, 0x40006469
1741 .set CYREG_B0_UDB10_ST, 0x4000646a
1742 .set CYREG_B0_UDB11_ST, 0x4000646b
1743 .set CYREG_B0_UDB12_ST, 0x4000646c
1744 .set CYREG_B0_UDB13_ST, 0x4000646d
1745 .set CYREG_B0_UDB14_ST, 0x4000646e
1746 .set CYREG_B0_UDB15_ST, 0x4000646f
1747 .set CYREG_B0_UDB00_CTL, 0x40006470
1748 .set CYREG_B0_UDB01_CTL, 0x40006471
1749 .set CYREG_B0_UDB02_CTL, 0x40006472
1750 .set CYREG_B0_UDB03_CTL, 0x40006473
1751 .set CYREG_B0_UDB04_CTL, 0x40006474
1752 .set CYREG_B0_UDB05_CTL, 0x40006475
1753 .set CYREG_B0_UDB06_CTL, 0x40006476
1754 .set CYREG_B0_UDB07_CTL, 0x40006477
1755 .set CYREG_B0_UDB08_CTL, 0x40006478
1756 .set CYREG_B0_UDB09_CTL, 0x40006479
1757 .set CYREG_B0_UDB10_CTL, 0x4000647a
1758 .set CYREG_B0_UDB11_CTL, 0x4000647b
1759 .set CYREG_B0_UDB12_CTL, 0x4000647c
1760 .set CYREG_B0_UDB13_CTL, 0x4000647d
1761 .set CYREG_B0_UDB14_CTL, 0x4000647e
1762 .set CYREG_B0_UDB15_CTL, 0x4000647f
1763 .set CYREG_B0_UDB00_MSK, 0x40006480
1764 .set CYREG_B0_UDB01_MSK, 0x40006481
1765 .set CYREG_B0_UDB02_MSK, 0x40006482
1766 .set CYREG_B0_UDB03_MSK, 0x40006483
1767 .set CYREG_B0_UDB04_MSK, 0x40006484
1768 .set CYREG_B0_UDB05_MSK, 0x40006485
1769 .set CYREG_B0_UDB06_MSK, 0x40006486
1770 .set CYREG_B0_UDB07_MSK, 0x40006487
1771 .set CYREG_B0_UDB08_MSK, 0x40006488
1772 .set CYREG_B0_UDB09_MSK, 0x40006489
1773 .set CYREG_B0_UDB10_MSK, 0x4000648a
1774 .set CYREG_B0_UDB11_MSK, 0x4000648b
1775 .set CYREG_B0_UDB12_MSK, 0x4000648c
1776 .set CYREG_B0_UDB13_MSK, 0x4000648d
1777 .set CYREG_B0_UDB14_MSK, 0x4000648e
1778 .set CYREG_B0_UDB15_MSK, 0x4000648f
1779 .set CYREG_B0_UDB00_ACTL, 0x40006490
1780 .set CYREG_B0_UDB01_ACTL, 0x40006491
1781 .set CYREG_B0_UDB02_ACTL, 0x40006492
1782 .set CYREG_B0_UDB03_ACTL, 0x40006493
1783 .set CYREG_B0_UDB04_ACTL, 0x40006494
1784 .set CYREG_B0_UDB05_ACTL, 0x40006495
1785 .set CYREG_B0_UDB06_ACTL, 0x40006496
1786 .set CYREG_B0_UDB07_ACTL, 0x40006497
1787 .set CYREG_B0_UDB08_ACTL, 0x40006498
1788 .set CYREG_B0_UDB09_ACTL, 0x40006499
1789 .set CYREG_B0_UDB10_ACTL, 0x4000649a
1790 .set CYREG_B0_UDB11_ACTL, 0x4000649b
1791 .set CYREG_B0_UDB12_ACTL, 0x4000649c
1792 .set CYREG_B0_UDB13_ACTL, 0x4000649d
1793 .set CYREG_B0_UDB14_ACTL, 0x4000649e
1794 .set CYREG_B0_UDB15_ACTL, 0x4000649f
1795 .set CYREG_B0_UDB00_MC, 0x400064a0
1796 .set CYREG_B0_UDB01_MC, 0x400064a1
1797 .set CYREG_B0_UDB02_MC, 0x400064a2
1798 .set CYREG_B0_UDB03_MC, 0x400064a3
1799 .set CYREG_B0_UDB04_MC, 0x400064a4
1800 .set CYREG_B0_UDB05_MC, 0x400064a5
1801 .set CYREG_B0_UDB06_MC, 0x400064a6
1802 .set CYREG_B0_UDB07_MC, 0x400064a7
1803 .set CYREG_B0_UDB08_MC, 0x400064a8
1804 .set CYREG_B0_UDB09_MC, 0x400064a9
1805 .set CYREG_B0_UDB10_MC, 0x400064aa
1806 .set CYREG_B0_UDB11_MC, 0x400064ab
1807 .set CYREG_B0_UDB12_MC, 0x400064ac
1808 .set CYREG_B0_UDB13_MC, 0x400064ad
1809 .set CYREG_B0_UDB14_MC, 0x400064ae
1810 .set CYREG_B0_UDB15_MC, 0x400064af
1811 .set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500
1812 .set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0
1813 .set CYREG_B1_UDB04_A0, 0x40006504
1814 .set CYREG_B1_UDB05_A0, 0x40006505
1815 .set CYREG_B1_UDB06_A0, 0x40006506
1816 .set CYREG_B1_UDB07_A0, 0x40006507
1817 .set CYREG_B1_UDB08_A0, 0x40006508
1818 .set CYREG_B1_UDB09_A0, 0x40006509
1819 .set CYREG_B1_UDB10_A0, 0x4000650a
1820 .set CYREG_B1_UDB11_A0, 0x4000650b
1821 .set CYREG_B1_UDB04_A1, 0x40006514
1822 .set CYREG_B1_UDB05_A1, 0x40006515
1823 .set CYREG_B1_UDB06_A1, 0x40006516
1824 .set CYREG_B1_UDB07_A1, 0x40006517
1825 .set CYREG_B1_UDB08_A1, 0x40006518
1826 .set CYREG_B1_UDB09_A1, 0x40006519
1827 .set CYREG_B1_UDB10_A1, 0x4000651a
1828 .set CYREG_B1_UDB11_A1, 0x4000651b
1829 .set CYREG_B1_UDB04_D0, 0x40006524
1830 .set CYREG_B1_UDB05_D0, 0x40006525
1831 .set CYREG_B1_UDB06_D0, 0x40006526
1832 .set CYREG_B1_UDB07_D0, 0x40006527
1833 .set CYREG_B1_UDB08_D0, 0x40006528
1834 .set CYREG_B1_UDB09_D0, 0x40006529
1835 .set CYREG_B1_UDB10_D0, 0x4000652a
1836 .set CYREG_B1_UDB11_D0, 0x4000652b
1837 .set CYREG_B1_UDB04_D1, 0x40006534
1838 .set CYREG_B1_UDB05_D1, 0x40006535
1839 .set CYREG_B1_UDB06_D1, 0x40006536
1840 .set CYREG_B1_UDB07_D1, 0x40006537
1841 .set CYREG_B1_UDB08_D1, 0x40006538
1842 .set CYREG_B1_UDB09_D1, 0x40006539
1843 .set CYREG_B1_UDB10_D1, 0x4000653a
1844 .set CYREG_B1_UDB11_D1, 0x4000653b
1845 .set CYREG_B1_UDB04_F0, 0x40006544
1846 .set CYREG_B1_UDB05_F0, 0x40006545
1847 .set CYREG_B1_UDB06_F0, 0x40006546
1848 .set CYREG_B1_UDB07_F0, 0x40006547
1849 .set CYREG_B1_UDB08_F0, 0x40006548
1850 .set CYREG_B1_UDB09_F0, 0x40006549
1851 .set CYREG_B1_UDB10_F0, 0x4000654a
1852 .set CYREG_B1_UDB11_F0, 0x4000654b
1853 .set CYREG_B1_UDB04_F1, 0x40006554
1854 .set CYREG_B1_UDB05_F1, 0x40006555
1855 .set CYREG_B1_UDB06_F1, 0x40006556
1856 .set CYREG_B1_UDB07_F1, 0x40006557
1857 .set CYREG_B1_UDB08_F1, 0x40006558
1858 .set CYREG_B1_UDB09_F1, 0x40006559
1859 .set CYREG_B1_UDB10_F1, 0x4000655a
1860 .set CYREG_B1_UDB11_F1, 0x4000655b
1861 .set CYREG_B1_UDB04_ST, 0x40006564
1862 .set CYREG_B1_UDB05_ST, 0x40006565
1863 .set CYREG_B1_UDB06_ST, 0x40006566
1864 .set CYREG_B1_UDB07_ST, 0x40006567
1865 .set CYREG_B1_UDB08_ST, 0x40006568
1866 .set CYREG_B1_UDB09_ST, 0x40006569
1867 .set CYREG_B1_UDB10_ST, 0x4000656a
1868 .set CYREG_B1_UDB11_ST, 0x4000656b
1869 .set CYREG_B1_UDB04_CTL, 0x40006574
1870 .set CYREG_B1_UDB05_CTL, 0x40006575
1871 .set CYREG_B1_UDB06_CTL, 0x40006576
1872 .set CYREG_B1_UDB07_CTL, 0x40006577
1873 .set CYREG_B1_UDB08_CTL, 0x40006578
1874 .set CYREG_B1_UDB09_CTL, 0x40006579
1875 .set CYREG_B1_UDB10_CTL, 0x4000657a
1876 .set CYREG_B1_UDB11_CTL, 0x4000657b
1877 .set CYREG_B1_UDB04_MSK, 0x40006584
1878 .set CYREG_B1_UDB05_MSK, 0x40006585
1879 .set CYREG_B1_UDB06_MSK, 0x40006586
1880 .set CYREG_B1_UDB07_MSK, 0x40006587
1881 .set CYREG_B1_UDB08_MSK, 0x40006588
1882 .set CYREG_B1_UDB09_MSK, 0x40006589
1883 .set CYREG_B1_UDB10_MSK, 0x4000658a
1884 .set CYREG_B1_UDB11_MSK, 0x4000658b
1885 .set CYREG_B1_UDB04_ACTL, 0x40006594
1886 .set CYREG_B1_UDB05_ACTL, 0x40006595
1887 .set CYREG_B1_UDB06_ACTL, 0x40006596
1888 .set CYREG_B1_UDB07_ACTL, 0x40006597
1889 .set CYREG_B1_UDB08_ACTL, 0x40006598
1890 .set CYREG_B1_UDB09_ACTL, 0x40006599
1891 .set CYREG_B1_UDB10_ACTL, 0x4000659a
1892 .set CYREG_B1_UDB11_ACTL, 0x4000659b
1893 .set CYREG_B1_UDB04_MC, 0x400065a4
1894 .set CYREG_B1_UDB05_MC, 0x400065a5
1895 .set CYREG_B1_UDB06_MC, 0x400065a6
1896 .set CYREG_B1_UDB07_MC, 0x400065a7
1897 .set CYREG_B1_UDB08_MC, 0x400065a8
1898 .set CYREG_B1_UDB09_MC, 0x400065a9
1899 .set CYREG_B1_UDB10_MC, 0x400065aa
1900 .set CYREG_B1_UDB11_MC, 0x400065ab
1901 .set CYDEV_UWRK_UWRK16_BASE, 0x40006800
1902 .set CYDEV_UWRK_UWRK16_SIZE, 0x00000760
1903 .set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800
1904 .set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760
1905 .set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800
1906 .set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160
1907 .set CYREG_B0_UDB00_A0_A1, 0x40006800
1908 .set CYREG_B0_UDB01_A0_A1, 0x40006802
1909 .set CYREG_B0_UDB02_A0_A1, 0x40006804
1910 .set CYREG_B0_UDB03_A0_A1, 0x40006806
1911 .set CYREG_B0_UDB04_A0_A1, 0x40006808
1912 .set CYREG_B0_UDB05_A0_A1, 0x4000680a
1913 .set CYREG_B0_UDB06_A0_A1, 0x4000680c
1914 .set CYREG_B0_UDB07_A0_A1, 0x4000680e
1915 .set CYREG_B0_UDB08_A0_A1, 0x40006810
1916 .set CYREG_B0_UDB09_A0_A1, 0x40006812
1917 .set CYREG_B0_UDB10_A0_A1, 0x40006814
1918 .set CYREG_B0_UDB11_A0_A1, 0x40006816
1919 .set CYREG_B0_UDB12_A0_A1, 0x40006818
1920 .set CYREG_B0_UDB13_A0_A1, 0x4000681a
1921 .set CYREG_B0_UDB14_A0_A1, 0x4000681c
1922 .set CYREG_B0_UDB15_A0_A1, 0x4000681e
1923 .set CYREG_B0_UDB00_D0_D1, 0x40006840
1924 .set CYREG_B0_UDB01_D0_D1, 0x40006842
1925 .set CYREG_B0_UDB02_D0_D1, 0x40006844
1926 .set CYREG_B0_UDB03_D0_D1, 0x40006846
1927 .set CYREG_B0_UDB04_D0_D1, 0x40006848
1928 .set CYREG_B0_UDB05_D0_D1, 0x4000684a
1929 .set CYREG_B0_UDB06_D0_D1, 0x4000684c
1930 .set CYREG_B0_UDB07_D0_D1, 0x4000684e
1931 .set CYREG_B0_UDB08_D0_D1, 0x40006850
1932 .set CYREG_B0_UDB09_D0_D1, 0x40006852
1933 .set CYREG_B0_UDB10_D0_D1, 0x40006854
1934 .set CYREG_B0_UDB11_D0_D1, 0x40006856
1935 .set CYREG_B0_UDB12_D0_D1, 0x40006858
1936 .set CYREG_B0_UDB13_D0_D1, 0x4000685a
1937 .set CYREG_B0_UDB14_D0_D1, 0x4000685c
1938 .set CYREG_B0_UDB15_D0_D1, 0x4000685e
1939 .set CYREG_B0_UDB00_F0_F1, 0x40006880
1940 .set CYREG_B0_UDB01_F0_F1, 0x40006882
1941 .set CYREG_B0_UDB02_F0_F1, 0x40006884
1942 .set CYREG_B0_UDB03_F0_F1, 0x40006886
1943 .set CYREG_B0_UDB04_F0_F1, 0x40006888
1944 .set CYREG_B0_UDB05_F0_F1, 0x4000688a
1945 .set CYREG_B0_UDB06_F0_F1, 0x4000688c
1946 .set CYREG_B0_UDB07_F0_F1, 0x4000688e
1947 .set CYREG_B0_UDB08_F0_F1, 0x40006890
1948 .set CYREG_B0_UDB09_F0_F1, 0x40006892
1949 .set CYREG_B0_UDB10_F0_F1, 0x40006894
1950 .set CYREG_B0_UDB11_F0_F1, 0x40006896
1951 .set CYREG_B0_UDB12_F0_F1, 0x40006898
1952 .set CYREG_B0_UDB13_F0_F1, 0x4000689a
1953 .set CYREG_B0_UDB14_F0_F1, 0x4000689c
1954 .set CYREG_B0_UDB15_F0_F1, 0x4000689e
1955 .set CYREG_B0_UDB00_ST_CTL, 0x400068c0
1956 .set CYREG_B0_UDB01_ST_CTL, 0x400068c2
1957 .set CYREG_B0_UDB02_ST_CTL, 0x400068c4
1958 .set CYREG_B0_UDB03_ST_CTL, 0x400068c6
1959 .set CYREG_B0_UDB04_ST_CTL, 0x400068c8
1960 .set CYREG_B0_UDB05_ST_CTL, 0x400068ca
1961 .set CYREG_B0_UDB06_ST_CTL, 0x400068cc
1962 .set CYREG_B0_UDB07_ST_CTL, 0x400068ce
1963 .set CYREG_B0_UDB08_ST_CTL, 0x400068d0
1964 .set CYREG_B0_UDB09_ST_CTL, 0x400068d2
1965 .set CYREG_B0_UDB10_ST_CTL, 0x400068d4
1966 .set CYREG_B0_UDB11_ST_CTL, 0x400068d6
1967 .set CYREG_B0_UDB12_ST_CTL, 0x400068d8
1968 .set CYREG_B0_UDB13_ST_CTL, 0x400068da
1969 .set CYREG_B0_UDB14_ST_CTL, 0x400068dc
1970 .set CYREG_B0_UDB15_ST_CTL, 0x400068de
1971 .set CYREG_B0_UDB00_MSK_ACTL, 0x40006900
1972 .set CYREG_B0_UDB01_MSK_ACTL, 0x40006902
1973 .set CYREG_B0_UDB02_MSK_ACTL, 0x40006904
1974 .set CYREG_B0_UDB03_MSK_ACTL, 0x40006906
1975 .set CYREG_B0_UDB04_MSK_ACTL, 0x40006908
1976 .set CYREG_B0_UDB05_MSK_ACTL, 0x4000690a
1977 .set CYREG_B0_UDB06_MSK_ACTL, 0x4000690c
1978 .set CYREG_B0_UDB07_MSK_ACTL, 0x4000690e
1979 .set CYREG_B0_UDB08_MSK_ACTL, 0x40006910
1980 .set CYREG_B0_UDB09_MSK_ACTL, 0x40006912
1981 .set CYREG_B0_UDB10_MSK_ACTL, 0x40006914
1982 .set CYREG_B0_UDB11_MSK_ACTL, 0x40006916
1983 .set CYREG_B0_UDB12_MSK_ACTL, 0x40006918
1984 .set CYREG_B0_UDB13_MSK_ACTL, 0x4000691a
1985 .set CYREG_B0_UDB14_MSK_ACTL, 0x4000691c
1986 .set CYREG_B0_UDB15_MSK_ACTL, 0x4000691e
1987 .set CYREG_B0_UDB00_MC_00, 0x40006940
1988 .set CYREG_B0_UDB01_MC_00, 0x40006942
1989 .set CYREG_B0_UDB02_MC_00, 0x40006944
1990 .set CYREG_B0_UDB03_MC_00, 0x40006946
1991 .set CYREG_B0_UDB04_MC_00, 0x40006948
1992 .set CYREG_B0_UDB05_MC_00, 0x4000694a
1993 .set CYREG_B0_UDB06_MC_00, 0x4000694c
1994 .set CYREG_B0_UDB07_MC_00, 0x4000694e
1995 .set CYREG_B0_UDB08_MC_00, 0x40006950
1996 .set CYREG_B0_UDB09_MC_00, 0x40006952
1997 .set CYREG_B0_UDB10_MC_00, 0x40006954
1998 .set CYREG_B0_UDB11_MC_00, 0x40006956
1999 .set CYREG_B0_UDB12_MC_00, 0x40006958
2000 .set CYREG_B0_UDB13_MC_00, 0x4000695a
2001 .set CYREG_B0_UDB14_MC_00, 0x4000695c
2002 .set CYREG_B0_UDB15_MC_00, 0x4000695e
2003 .set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00
2004 .set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160
2005 .set CYREG_B1_UDB04_A0_A1, 0x40006a08
2006 .set CYREG_B1_UDB05_A0_A1, 0x40006a0a
2007 .set CYREG_B1_UDB06_A0_A1, 0x40006a0c
2008 .set CYREG_B1_UDB07_A0_A1, 0x40006a0e
2009 .set CYREG_B1_UDB08_A0_A1, 0x40006a10
2010 .set CYREG_B1_UDB09_A0_A1, 0x40006a12
2011 .set CYREG_B1_UDB10_A0_A1, 0x40006a14
2012 .set CYREG_B1_UDB11_A0_A1, 0x40006a16
2013 .set CYREG_B1_UDB04_D0_D1, 0x40006a48
2014 .set CYREG_B1_UDB05_D0_D1, 0x40006a4a
2015 .set CYREG_B1_UDB06_D0_D1, 0x40006a4c
2016 .set CYREG_B1_UDB07_D0_D1, 0x40006a4e
2017 .set CYREG_B1_UDB08_D0_D1, 0x40006a50
2018 .set CYREG_B1_UDB09_D0_D1, 0x40006a52
2019 .set CYREG_B1_UDB10_D0_D1, 0x40006a54
2020 .set CYREG_B1_UDB11_D0_D1, 0x40006a56
2021 .set CYREG_B1_UDB04_F0_F1, 0x40006a88
2022 .set CYREG_B1_UDB05_F0_F1, 0x40006a8a
2023 .set CYREG_B1_UDB06_F0_F1, 0x40006a8c
2024 .set CYREG_B1_UDB07_F0_F1, 0x40006a8e
2025 .set CYREG_B1_UDB08_F0_F1, 0x40006a90
2026 .set CYREG_B1_UDB09_F0_F1, 0x40006a92
2027 .set CYREG_B1_UDB10_F0_F1, 0x40006a94
2028 .set CYREG_B1_UDB11_F0_F1, 0x40006a96
2029 .set CYREG_B1_UDB04_ST_CTL, 0x40006ac8
2030 .set CYREG_B1_UDB05_ST_CTL, 0x40006aca
2031 .set CYREG_B1_UDB06_ST_CTL, 0x40006acc
2032 .set CYREG_B1_UDB07_ST_CTL, 0x40006ace
2033 .set CYREG_B1_UDB08_ST_CTL, 0x40006ad0
2034 .set CYREG_B1_UDB09_ST_CTL, 0x40006ad2
2035 .set CYREG_B1_UDB10_ST_CTL, 0x40006ad4
2036 .set CYREG_B1_UDB11_ST_CTL, 0x40006ad6
2037 .set CYREG_B1_UDB04_MSK_ACTL, 0x40006b08
2038 .set CYREG_B1_UDB05_MSK_ACTL, 0x40006b0a
2039 .set CYREG_B1_UDB06_MSK_ACTL, 0x40006b0c
2040 .set CYREG_B1_UDB07_MSK_ACTL, 0x40006b0e
2041 .set CYREG_B1_UDB08_MSK_ACTL, 0x40006b10
2042 .set CYREG_B1_UDB09_MSK_ACTL, 0x40006b12
2043 .set CYREG_B1_UDB10_MSK_ACTL, 0x40006b14
2044 .set CYREG_B1_UDB11_MSK_ACTL, 0x40006b16
2045 .set CYREG_B1_UDB04_MC_00, 0x40006b48
2046 .set CYREG_B1_UDB05_MC_00, 0x40006b4a
2047 .set CYREG_B1_UDB06_MC_00, 0x40006b4c
2048 .set CYREG_B1_UDB07_MC_00, 0x40006b4e
2049 .set CYREG_B1_UDB08_MC_00, 0x40006b50
2050 .set CYREG_B1_UDB09_MC_00, 0x40006b52
2051 .set CYREG_B1_UDB10_MC_00, 0x40006b54
2052 .set CYREG_B1_UDB11_MC_00, 0x40006b56
2053 .set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800
2054 .set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e
2055 .set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800
2056 .set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e
2057 .set CYREG_B0_UDB00_01_A0, 0x40006800
2058 .set CYREG_B0_UDB01_02_A0, 0x40006802
2059 .set CYREG_B0_UDB02_03_A0, 0x40006804
2060 .set CYREG_B0_UDB03_04_A0, 0x40006806
2061 .set CYREG_B0_UDB04_05_A0, 0x40006808
2062 .set CYREG_B0_UDB05_06_A0, 0x4000680a
2063 .set CYREG_B0_UDB06_07_A0, 0x4000680c
2064 .set CYREG_B0_UDB07_08_A0, 0x4000680e
2065 .set CYREG_B0_UDB08_09_A0, 0x40006810
2066 .set CYREG_B0_UDB09_10_A0, 0x40006812
2067 .set CYREG_B0_UDB10_11_A0, 0x40006814
2068 .set CYREG_B0_UDB11_12_A0, 0x40006816
2069 .set CYREG_B0_UDB12_13_A0, 0x40006818
2070 .set CYREG_B0_UDB13_14_A0, 0x4000681a
2071 .set CYREG_B0_UDB14_15_A0, 0x4000681c
2072 .set CYREG_B0_UDB00_01_A1, 0x40006820
2073 .set CYREG_B0_UDB01_02_A1, 0x40006822
2074 .set CYREG_B0_UDB02_03_A1, 0x40006824
2075 .set CYREG_B0_UDB03_04_A1, 0x40006826
2076 .set CYREG_B0_UDB04_05_A1, 0x40006828
2077 .set CYREG_B0_UDB05_06_A1, 0x4000682a
2078 .set CYREG_B0_UDB06_07_A1, 0x4000682c
2079 .set CYREG_B0_UDB07_08_A1, 0x4000682e
2080 .set CYREG_B0_UDB08_09_A1, 0x40006830
2081 .set CYREG_B0_UDB09_10_A1, 0x40006832
2082 .set CYREG_B0_UDB10_11_A1, 0x40006834
2083 .set CYREG_B0_UDB11_12_A1, 0x40006836
2084 .set CYREG_B0_UDB12_13_A1, 0x40006838
2085 .set CYREG_B0_UDB13_14_A1, 0x4000683a
2086 .set CYREG_B0_UDB14_15_A1, 0x4000683c
2087 .set CYREG_B0_UDB00_01_D0, 0x40006840
2088 .set CYREG_B0_UDB01_02_D0, 0x40006842
2089 .set CYREG_B0_UDB02_03_D0, 0x40006844
2090 .set CYREG_B0_UDB03_04_D0, 0x40006846
2091 .set CYREG_B0_UDB04_05_D0, 0x40006848
2092 .set CYREG_B0_UDB05_06_D0, 0x4000684a
2093 .set CYREG_B0_UDB06_07_D0, 0x4000684c
2094 .set CYREG_B0_UDB07_08_D0, 0x4000684e
2095 .set CYREG_B0_UDB08_09_D0, 0x40006850
2096 .set CYREG_B0_UDB09_10_D0, 0x40006852
2097 .set CYREG_B0_UDB10_11_D0, 0x40006854
2098 .set CYREG_B0_UDB11_12_D0, 0x40006856
2099 .set CYREG_B0_UDB12_13_D0, 0x40006858
2100 .set CYREG_B0_UDB13_14_D0, 0x4000685a
2101 .set CYREG_B0_UDB14_15_D0, 0x4000685c
2102 .set CYREG_B0_UDB00_01_D1, 0x40006860
2103 .set CYREG_B0_UDB01_02_D1, 0x40006862
2104 .set CYREG_B0_UDB02_03_D1, 0x40006864
2105 .set CYREG_B0_UDB03_04_D1, 0x40006866
2106 .set CYREG_B0_UDB04_05_D1, 0x40006868
2107 .set CYREG_B0_UDB05_06_D1, 0x4000686a
2108 .set CYREG_B0_UDB06_07_D1, 0x4000686c
2109 .set CYREG_B0_UDB07_08_D1, 0x4000686e
2110 .set CYREG_B0_UDB08_09_D1, 0x40006870
2111 .set CYREG_B0_UDB09_10_D1, 0x40006872
2112 .set CYREG_B0_UDB10_11_D1, 0x40006874
2113 .set CYREG_B0_UDB11_12_D1, 0x40006876
2114 .set CYREG_B0_UDB12_13_D1, 0x40006878
2115 .set CYREG_B0_UDB13_14_D1, 0x4000687a
2116 .set CYREG_B0_UDB14_15_D1, 0x4000687c
2117 .set CYREG_B0_UDB00_01_F0, 0x40006880
2118 .set CYREG_B0_UDB01_02_F0, 0x40006882
2119 .set CYREG_B0_UDB02_03_F0, 0x40006884
2120 .set CYREG_B0_UDB03_04_F0, 0x40006886
2121 .set CYREG_B0_UDB04_05_F0, 0x40006888
2122 .set CYREG_B0_UDB05_06_F0, 0x4000688a
2123 .set CYREG_B0_UDB06_07_F0, 0x4000688c
2124 .set CYREG_B0_UDB07_08_F0, 0x4000688e
2125 .set CYREG_B0_UDB08_09_F0, 0x40006890
2126 .set CYREG_B0_UDB09_10_F0, 0x40006892
2127 .set CYREG_B0_UDB10_11_F0, 0x40006894
2128 .set CYREG_B0_UDB11_12_F0, 0x40006896
2129 .set CYREG_B0_UDB12_13_F0, 0x40006898
2130 .set CYREG_B0_UDB13_14_F0, 0x4000689a
2131 .set CYREG_B0_UDB14_15_F0, 0x4000689c
2132 .set CYREG_B0_UDB00_01_F1, 0x400068a0
2133 .set CYREG_B0_UDB01_02_F1, 0x400068a2
2134 .set CYREG_B0_UDB02_03_F1, 0x400068a4
2135 .set CYREG_B0_UDB03_04_F1, 0x400068a6
2136 .set CYREG_B0_UDB04_05_F1, 0x400068a8
2137 .set CYREG_B0_UDB05_06_F1, 0x400068aa
2138 .set CYREG_B0_UDB06_07_F1, 0x400068ac
2139 .set CYREG_B0_UDB07_08_F1, 0x400068ae
2140 .set CYREG_B0_UDB08_09_F1, 0x400068b0
2141 .set CYREG_B0_UDB09_10_F1, 0x400068b2
2142 .set CYREG_B0_UDB10_11_F1, 0x400068b4
2143 .set CYREG_B0_UDB11_12_F1, 0x400068b6
2144 .set CYREG_B0_UDB12_13_F1, 0x400068b8
2145 .set CYREG_B0_UDB13_14_F1, 0x400068ba
2146 .set CYREG_B0_UDB14_15_F1, 0x400068bc
2147 .set CYREG_B0_UDB00_01_ST, 0x400068c0
2148 .set CYREG_B0_UDB01_02_ST, 0x400068c2
2149 .set CYREG_B0_UDB02_03_ST, 0x400068c4
2150 .set CYREG_B0_UDB03_04_ST, 0x400068c6
2151 .set CYREG_B0_UDB04_05_ST, 0x400068c8
2152 .set CYREG_B0_UDB05_06_ST, 0x400068ca
2153 .set CYREG_B0_UDB06_07_ST, 0x400068cc
2154 .set CYREG_B0_UDB07_08_ST, 0x400068ce
2155 .set CYREG_B0_UDB08_09_ST, 0x400068d0
2156 .set CYREG_B0_UDB09_10_ST, 0x400068d2
2157 .set CYREG_B0_UDB10_11_ST, 0x400068d4
2158 .set CYREG_B0_UDB11_12_ST, 0x400068d6
2159 .set CYREG_B0_UDB12_13_ST, 0x400068d8
2160 .set CYREG_B0_UDB13_14_ST, 0x400068da
2161 .set CYREG_B0_UDB14_15_ST, 0x400068dc
2162 .set CYREG_B0_UDB00_01_CTL, 0x400068e0
2163 .set CYREG_B0_UDB01_02_CTL, 0x400068e2
2164 .set CYREG_B0_UDB02_03_CTL, 0x400068e4
2165 .set CYREG_B0_UDB03_04_CTL, 0x400068e6
2166 .set CYREG_B0_UDB04_05_CTL, 0x400068e8
2167 .set CYREG_B0_UDB05_06_CTL, 0x400068ea
2168 .set CYREG_B0_UDB06_07_CTL, 0x400068ec
2169 .set CYREG_B0_UDB07_08_CTL, 0x400068ee
2170 .set CYREG_B0_UDB08_09_CTL, 0x400068f0
2171 .set CYREG_B0_UDB09_10_CTL, 0x400068f2
2172 .set CYREG_B0_UDB10_11_CTL, 0x400068f4
2173 .set CYREG_B0_UDB11_12_CTL, 0x400068f6
2174 .set CYREG_B0_UDB12_13_CTL, 0x400068f8
2175 .set CYREG_B0_UDB13_14_CTL, 0x400068fa
2176 .set CYREG_B0_UDB14_15_CTL, 0x400068fc
2177 .set CYREG_B0_UDB00_01_MSK, 0x40006900
2178 .set CYREG_B0_UDB01_02_MSK, 0x40006902
2179 .set CYREG_B0_UDB02_03_MSK, 0x40006904
2180 .set CYREG_B0_UDB03_04_MSK, 0x40006906
2181 .set CYREG_B0_UDB04_05_MSK, 0x40006908
2182 .set CYREG_B0_UDB05_06_MSK, 0x4000690a
2183 .set CYREG_B0_UDB06_07_MSK, 0x4000690c
2184 .set CYREG_B0_UDB07_08_MSK, 0x4000690e
2185 .set CYREG_B0_UDB08_09_MSK, 0x40006910
2186 .set CYREG_B0_UDB09_10_MSK, 0x40006912
2187 .set CYREG_B0_UDB10_11_MSK, 0x40006914
2188 .set CYREG_B0_UDB11_12_MSK, 0x40006916
2189 .set CYREG_B0_UDB12_13_MSK, 0x40006918
2190 .set CYREG_B0_UDB13_14_MSK, 0x4000691a
2191 .set CYREG_B0_UDB14_15_MSK, 0x4000691c
2192 .set CYREG_B0_UDB00_01_ACTL, 0x40006920
2193 .set CYREG_B0_UDB01_02_ACTL, 0x40006922
2194 .set CYREG_B0_UDB02_03_ACTL, 0x40006924
2195 .set CYREG_B0_UDB03_04_ACTL, 0x40006926
2196 .set CYREG_B0_UDB04_05_ACTL, 0x40006928
2197 .set CYREG_B0_UDB05_06_ACTL, 0x4000692a
2198 .set CYREG_B0_UDB06_07_ACTL, 0x4000692c
2199 .set CYREG_B0_UDB07_08_ACTL, 0x4000692e
2200 .set CYREG_B0_UDB08_09_ACTL, 0x40006930
2201 .set CYREG_B0_UDB09_10_ACTL, 0x40006932
2202 .set CYREG_B0_UDB10_11_ACTL, 0x40006934
2203 .set CYREG_B0_UDB11_12_ACTL, 0x40006936
2204 .set CYREG_B0_UDB12_13_ACTL, 0x40006938
2205 .set CYREG_B0_UDB13_14_ACTL, 0x4000693a
2206 .set CYREG_B0_UDB14_15_ACTL, 0x4000693c
2207 .set CYREG_B0_UDB00_01_MC, 0x40006940
2208 .set CYREG_B0_UDB01_02_MC, 0x40006942
2209 .set CYREG_B0_UDB02_03_MC, 0x40006944
2210 .set CYREG_B0_UDB03_04_MC, 0x40006946
2211 .set CYREG_B0_UDB04_05_MC, 0x40006948
2212 .set CYREG_B0_UDB05_06_MC, 0x4000694a
2213 .set CYREG_B0_UDB06_07_MC, 0x4000694c
2214 .set CYREG_B0_UDB07_08_MC, 0x4000694e
2215 .set CYREG_B0_UDB08_09_MC, 0x40006950
2216 .set CYREG_B0_UDB09_10_MC, 0x40006952
2217 .set CYREG_B0_UDB10_11_MC, 0x40006954
2218 .set CYREG_B0_UDB11_12_MC, 0x40006956
2219 .set CYREG_B0_UDB12_13_MC, 0x40006958
2220 .set CYREG_B0_UDB13_14_MC, 0x4000695a
2221 .set CYREG_B0_UDB14_15_MC, 0x4000695c
2222 .set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00
2223 .set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e
2224 .set CYREG_B1_UDB04_05_A0, 0x40006a08
2225 .set CYREG_B1_UDB05_06_A0, 0x40006a0a
2226 .set CYREG_B1_UDB06_07_A0, 0x40006a0c
2227 .set CYREG_B1_UDB07_08_A0, 0x40006a0e
2228 .set CYREG_B1_UDB08_09_A0, 0x40006a10
2229 .set CYREG_B1_UDB09_10_A0, 0x40006a12
2230 .set CYREG_B1_UDB10_11_A0, 0x40006a14
2231 .set CYREG_B1_UDB11_12_A0, 0x40006a16
2232 .set CYREG_B1_UDB04_05_A1, 0x40006a28
2233 .set CYREG_B1_UDB05_06_A1, 0x40006a2a
2234 .set CYREG_B1_UDB06_07_A1, 0x40006a2c
2235 .set CYREG_B1_UDB07_08_A1, 0x40006a2e
2236 .set CYREG_B1_UDB08_09_A1, 0x40006a30
2237 .set CYREG_B1_UDB09_10_A1, 0x40006a32
2238 .set CYREG_B1_UDB10_11_A1, 0x40006a34
2239 .set CYREG_B1_UDB11_12_A1, 0x40006a36
2240 .set CYREG_B1_UDB04_05_D0, 0x40006a48
2241 .set CYREG_B1_UDB05_06_D0, 0x40006a4a
2242 .set CYREG_B1_UDB06_07_D0, 0x40006a4c
2243 .set CYREG_B1_UDB07_08_D0, 0x40006a4e
2244 .set CYREG_B1_UDB08_09_D0, 0x40006a50
2245 .set CYREG_B1_UDB09_10_D0, 0x40006a52
2246 .set CYREG_B1_UDB10_11_D0, 0x40006a54
2247 .set CYREG_B1_UDB11_12_D0, 0x40006a56
2248 .set CYREG_B1_UDB04_05_D1, 0x40006a68
2249 .set CYREG_B1_UDB05_06_D1, 0x40006a6a
2250 .set CYREG_B1_UDB06_07_D1, 0x40006a6c
2251 .set CYREG_B1_UDB07_08_D1, 0x40006a6e
2252 .set CYREG_B1_UDB08_09_D1, 0x40006a70
2253 .set CYREG_B1_UDB09_10_D1, 0x40006a72
2254 .set CYREG_B1_UDB10_11_D1, 0x40006a74
2255 .set CYREG_B1_UDB11_12_D1, 0x40006a76
2256 .set CYREG_B1_UDB04_05_F0, 0x40006a88
2257 .set CYREG_B1_UDB05_06_F0, 0x40006a8a
2258 .set CYREG_B1_UDB06_07_F0, 0x40006a8c
2259 .set CYREG_B1_UDB07_08_F0, 0x40006a8e
2260 .set CYREG_B1_UDB08_09_F0, 0x40006a90
2261 .set CYREG_B1_UDB09_10_F0, 0x40006a92
2262 .set CYREG_B1_UDB10_11_F0, 0x40006a94
2263 .set CYREG_B1_UDB11_12_F0, 0x40006a96
2264 .set CYREG_B1_UDB04_05_F1, 0x40006aa8
2265 .set CYREG_B1_UDB05_06_F1, 0x40006aaa
2266 .set CYREG_B1_UDB06_07_F1, 0x40006aac
2267 .set CYREG_B1_UDB07_08_F1, 0x40006aae
2268 .set CYREG_B1_UDB08_09_F1, 0x40006ab0
2269 .set CYREG_B1_UDB09_10_F1, 0x40006ab2
2270 .set CYREG_B1_UDB10_11_F1, 0x40006ab4
2271 .set CYREG_B1_UDB11_12_F1, 0x40006ab6
2272 .set CYREG_B1_UDB04_05_ST, 0x40006ac8
2273 .set CYREG_B1_UDB05_06_ST, 0x40006aca
2274 .set CYREG_B1_UDB06_07_ST, 0x40006acc
2275 .set CYREG_B1_UDB07_08_ST, 0x40006ace
2276 .set CYREG_B1_UDB08_09_ST, 0x40006ad0
2277 .set CYREG_B1_UDB09_10_ST, 0x40006ad2
2278 .set CYREG_B1_UDB10_11_ST, 0x40006ad4
2279 .set CYREG_B1_UDB11_12_ST, 0x40006ad6
2280 .set CYREG_B1_UDB04_05_CTL, 0x40006ae8
2281 .set CYREG_B1_UDB05_06_CTL, 0x40006aea
2282 .set CYREG_B1_UDB06_07_CTL, 0x40006aec
2283 .set CYREG_B1_UDB07_08_CTL, 0x40006aee
2284 .set CYREG_B1_UDB08_09_CTL, 0x40006af0
2285 .set CYREG_B1_UDB09_10_CTL, 0x40006af2
2286 .set CYREG_B1_UDB10_11_CTL, 0x40006af4
2287 .set CYREG_B1_UDB11_12_CTL, 0x40006af6
2288 .set CYREG_B1_UDB04_05_MSK, 0x40006b08
2289 .set CYREG_B1_UDB05_06_MSK, 0x40006b0a
2290 .set CYREG_B1_UDB06_07_MSK, 0x40006b0c
2291 .set CYREG_B1_UDB07_08_MSK, 0x40006b0e
2292 .set CYREG_B1_UDB08_09_MSK, 0x40006b10
2293 .set CYREG_B1_UDB09_10_MSK, 0x40006b12
2294 .set CYREG_B1_UDB10_11_MSK, 0x40006b14
2295 .set CYREG_B1_UDB11_12_MSK, 0x40006b16
2296 .set CYREG_B1_UDB04_05_ACTL, 0x40006b28
2297 .set CYREG_B1_UDB05_06_ACTL, 0x40006b2a
2298 .set CYREG_B1_UDB06_07_ACTL, 0x40006b2c
2299 .set CYREG_B1_UDB07_08_ACTL, 0x40006b2e
2300 .set CYREG_B1_UDB08_09_ACTL, 0x40006b30
2301 .set CYREG_B1_UDB09_10_ACTL, 0x40006b32
2302 .set CYREG_B1_UDB10_11_ACTL, 0x40006b34
2303 .set CYREG_B1_UDB11_12_ACTL, 0x40006b36
2304 .set CYREG_B1_UDB04_05_MC, 0x40006b48
2305 .set CYREG_B1_UDB05_06_MC, 0x40006b4a
2306 .set CYREG_B1_UDB06_07_MC, 0x40006b4c
2307 .set CYREG_B1_UDB07_08_MC, 0x40006b4e
2308 .set CYREG_B1_UDB08_09_MC, 0x40006b50
2309 .set CYREG_B1_UDB09_10_MC, 0x40006b52
2310 .set CYREG_B1_UDB10_11_MC, 0x40006b54
2311 .set CYREG_B1_UDB11_12_MC, 0x40006b56
2312 .set CYDEV_PHUB_BASE, 0x40007000
2313 .set CYDEV_PHUB_SIZE, 0x00000c00
2314 .set CYREG_PHUB_CFG, 0x40007000
2315 .set CYREG_PHUB_ERR, 0x40007004
2316 .set CYREG_PHUB_ERR_ADR, 0x40007008
2317 .set CYDEV_PHUB_CH0_BASE, 0x40007010
2318 .set CYDEV_PHUB_CH0_SIZE, 0x0000000c
2319 .set CYREG_PHUB_CH0_BASIC_CFG, 0x40007010
2320 .set CYREG_PHUB_CH0_ACTION, 0x40007014
2321 .set CYREG_PHUB_CH0_BASIC_STATUS, 0x40007018
2322 .set CYDEV_PHUB_CH1_BASE, 0x40007020
2323 .set CYDEV_PHUB_CH1_SIZE, 0x0000000c
2324 .set CYREG_PHUB_CH1_BASIC_CFG, 0x40007020
2325 .set CYREG_PHUB_CH1_ACTION, 0x40007024
2326 .set CYREG_PHUB_CH1_BASIC_STATUS, 0x40007028
2327 .set CYDEV_PHUB_CH2_BASE, 0x40007030
2328 .set CYDEV_PHUB_CH2_SIZE, 0x0000000c
2329 .set CYREG_PHUB_CH2_BASIC_CFG, 0x40007030
2330 .set CYREG_PHUB_CH2_ACTION, 0x40007034
2331 .set CYREG_PHUB_CH2_BASIC_STATUS, 0x40007038
2332 .set CYDEV_PHUB_CH3_BASE, 0x40007040
2333 .set CYDEV_PHUB_CH3_SIZE, 0x0000000c
2334 .set CYREG_PHUB_CH3_BASIC_CFG, 0x40007040
2335 .set CYREG_PHUB_CH3_ACTION, 0x40007044
2336 .set CYREG_PHUB_CH3_BASIC_STATUS, 0x40007048
2337 .set CYDEV_PHUB_CH4_BASE, 0x40007050
2338 .set CYDEV_PHUB_CH4_SIZE, 0x0000000c
2339 .set CYREG_PHUB_CH4_BASIC_CFG, 0x40007050
2340 .set CYREG_PHUB_CH4_ACTION, 0x40007054
2341 .set CYREG_PHUB_CH4_BASIC_STATUS, 0x40007058
2342 .set CYDEV_PHUB_CH5_BASE, 0x40007060
2343 .set CYDEV_PHUB_CH5_SIZE, 0x0000000c
2344 .set CYREG_PHUB_CH5_BASIC_CFG, 0x40007060
2345 .set CYREG_PHUB_CH5_ACTION, 0x40007064
2346 .set CYREG_PHUB_CH5_BASIC_STATUS, 0x40007068
2347 .set CYDEV_PHUB_CH6_BASE, 0x40007070
2348 .set CYDEV_PHUB_CH6_SIZE, 0x0000000c
2349 .set CYREG_PHUB_CH6_BASIC_CFG, 0x40007070
2350 .set CYREG_PHUB_CH6_ACTION, 0x40007074
2351 .set CYREG_PHUB_CH6_BASIC_STATUS, 0x40007078
2352 .set CYDEV_PHUB_CH7_BASE, 0x40007080
2353 .set CYDEV_PHUB_CH7_SIZE, 0x0000000c
2354 .set CYREG_PHUB_CH7_BASIC_CFG, 0x40007080
2355 .set CYREG_PHUB_CH7_ACTION, 0x40007084
2356 .set CYREG_PHUB_CH7_BASIC_STATUS, 0x40007088
2357 .set CYDEV_PHUB_CH8_BASE, 0x40007090
2358 .set CYDEV_PHUB_CH8_SIZE, 0x0000000c
2359 .set CYREG_PHUB_CH8_BASIC_CFG, 0x40007090
2360 .set CYREG_PHUB_CH8_ACTION, 0x40007094
2361 .set CYREG_PHUB_CH8_BASIC_STATUS, 0x40007098
2362 .set CYDEV_PHUB_CH9_BASE, 0x400070a0
2363 .set CYDEV_PHUB_CH9_SIZE, 0x0000000c
2364 .set CYREG_PHUB_CH9_BASIC_CFG, 0x400070a0
2365 .set CYREG_PHUB_CH9_ACTION, 0x400070a4
2366 .set CYREG_PHUB_CH9_BASIC_STATUS, 0x400070a8
2367 .set CYDEV_PHUB_CH10_BASE, 0x400070b0
2368 .set CYDEV_PHUB_CH10_SIZE, 0x0000000c
2369 .set CYREG_PHUB_CH10_BASIC_CFG, 0x400070b0
2370 .set CYREG_PHUB_CH10_ACTION, 0x400070b4
2371 .set CYREG_PHUB_CH10_BASIC_STATUS, 0x400070b8
2372 .set CYDEV_PHUB_CH11_BASE, 0x400070c0
2373 .set CYDEV_PHUB_CH11_SIZE, 0x0000000c
2374 .set CYREG_PHUB_CH11_BASIC_CFG, 0x400070c0
2375 .set CYREG_PHUB_CH11_ACTION, 0x400070c4
2376 .set CYREG_PHUB_CH11_BASIC_STATUS, 0x400070c8
2377 .set CYDEV_PHUB_CH12_BASE, 0x400070d0
2378 .set CYDEV_PHUB_CH12_SIZE, 0x0000000c
2379 .set CYREG_PHUB_CH12_BASIC_CFG, 0x400070d0
2380 .set CYREG_PHUB_CH12_ACTION, 0x400070d4
2381 .set CYREG_PHUB_CH12_BASIC_STATUS, 0x400070d8
2382 .set CYDEV_PHUB_CH13_BASE, 0x400070e0
2383 .set CYDEV_PHUB_CH13_SIZE, 0x0000000c
2384 .set CYREG_PHUB_CH13_BASIC_CFG, 0x400070e0
2385 .set CYREG_PHUB_CH13_ACTION, 0x400070e4
2386 .set CYREG_PHUB_CH13_BASIC_STATUS, 0x400070e8
2387 .set CYDEV_PHUB_CH14_BASE, 0x400070f0
2388 .set CYDEV_PHUB_CH14_SIZE, 0x0000000c
2389 .set CYREG_PHUB_CH14_BASIC_CFG, 0x400070f0
2390 .set CYREG_PHUB_CH14_ACTION, 0x400070f4
2391 .set CYREG_PHUB_CH14_BASIC_STATUS, 0x400070f8
2392 .set CYDEV_PHUB_CH15_BASE, 0x40007100
2393 .set CYDEV_PHUB_CH15_SIZE, 0x0000000c
2394 .set CYREG_PHUB_CH15_BASIC_CFG, 0x40007100
2395 .set CYREG_PHUB_CH15_ACTION, 0x40007104
2396 .set CYREG_PHUB_CH15_BASIC_STATUS, 0x40007108
2397 .set CYDEV_PHUB_CH16_BASE, 0x40007110
2398 .set CYDEV_PHUB_CH16_SIZE, 0x0000000c
2399 .set CYREG_PHUB_CH16_BASIC_CFG, 0x40007110
2400 .set CYREG_PHUB_CH16_ACTION, 0x40007114
2401 .set CYREG_PHUB_CH16_BASIC_STATUS, 0x40007118
2402 .set CYDEV_PHUB_CH17_BASE, 0x40007120
2403 .set CYDEV_PHUB_CH17_SIZE, 0x0000000c
2404 .set CYREG_PHUB_CH17_BASIC_CFG, 0x40007120
2405 .set CYREG_PHUB_CH17_ACTION, 0x40007124
2406 .set CYREG_PHUB_CH17_BASIC_STATUS, 0x40007128
2407 .set CYDEV_PHUB_CH18_BASE, 0x40007130
2408 .set CYDEV_PHUB_CH18_SIZE, 0x0000000c
2409 .set CYREG_PHUB_CH18_BASIC_CFG, 0x40007130
2410 .set CYREG_PHUB_CH18_ACTION, 0x40007134
2411 .set CYREG_PHUB_CH18_BASIC_STATUS, 0x40007138
2412 .set CYDEV_PHUB_CH19_BASE, 0x40007140
2413 .set CYDEV_PHUB_CH19_SIZE, 0x0000000c
2414 .set CYREG_PHUB_CH19_BASIC_CFG, 0x40007140
2415 .set CYREG_PHUB_CH19_ACTION, 0x40007144
2416 .set CYREG_PHUB_CH19_BASIC_STATUS, 0x40007148
2417 .set CYDEV_PHUB_CH20_BASE, 0x40007150
2418 .set CYDEV_PHUB_CH20_SIZE, 0x0000000c
2419 .set CYREG_PHUB_CH20_BASIC_CFG, 0x40007150
2420 .set CYREG_PHUB_CH20_ACTION, 0x40007154
2421 .set CYREG_PHUB_CH20_BASIC_STATUS, 0x40007158
2422 .set CYDEV_PHUB_CH21_BASE, 0x40007160
2423 .set CYDEV_PHUB_CH21_SIZE, 0x0000000c
2424 .set CYREG_PHUB_CH21_BASIC_CFG, 0x40007160
2425 .set CYREG_PHUB_CH21_ACTION, 0x40007164
2426 .set CYREG_PHUB_CH21_BASIC_STATUS, 0x40007168
2427 .set CYDEV_PHUB_CH22_BASE, 0x40007170
2428 .set CYDEV_PHUB_CH22_SIZE, 0x0000000c
2429 .set CYREG_PHUB_CH22_BASIC_CFG, 0x40007170
2430 .set CYREG_PHUB_CH22_ACTION, 0x40007174
2431 .set CYREG_PHUB_CH22_BASIC_STATUS, 0x40007178
2432 .set CYDEV_PHUB_CH23_BASE, 0x40007180
2433 .set CYDEV_PHUB_CH23_SIZE, 0x0000000c
2434 .set CYREG_PHUB_CH23_BASIC_CFG, 0x40007180
2435 .set CYREG_PHUB_CH23_ACTION, 0x40007184
2436 .set CYREG_PHUB_CH23_BASIC_STATUS, 0x40007188
2437 .set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600
2438 .set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008
2439 .set CYREG_PHUB_CFGMEM0_CFG0, 0x40007600
2440 .set CYREG_PHUB_CFGMEM0_CFG1, 0x40007604
2441 .set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608
2442 .set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008
2443 .set CYREG_PHUB_CFGMEM1_CFG0, 0x40007608
2444 .set CYREG_PHUB_CFGMEM1_CFG1, 0x4000760c
2445 .set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610
2446 .set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008
2447 .set CYREG_PHUB_CFGMEM2_CFG0, 0x40007610
2448 .set CYREG_PHUB_CFGMEM2_CFG1, 0x40007614
2449 .set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618
2450 .set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008
2451 .set CYREG_PHUB_CFGMEM3_CFG0, 0x40007618
2452 .set CYREG_PHUB_CFGMEM3_CFG1, 0x4000761c
2453 .set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620
2454 .set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008
2455 .set CYREG_PHUB_CFGMEM4_CFG0, 0x40007620
2456 .set CYREG_PHUB_CFGMEM4_CFG1, 0x40007624
2457 .set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628
2458 .set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008
2459 .set CYREG_PHUB_CFGMEM5_CFG0, 0x40007628
2460 .set CYREG_PHUB_CFGMEM5_CFG1, 0x4000762c
2461 .set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630
2462 .set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008
2463 .set CYREG_PHUB_CFGMEM6_CFG0, 0x40007630
2464 .set CYREG_PHUB_CFGMEM6_CFG1, 0x40007634
2465 .set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638
2466 .set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008
2467 .set CYREG_PHUB_CFGMEM7_CFG0, 0x40007638
2468 .set CYREG_PHUB_CFGMEM7_CFG1, 0x4000763c
2469 .set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640
2470 .set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008
2471 .set CYREG_PHUB_CFGMEM8_CFG0, 0x40007640
2472 .set CYREG_PHUB_CFGMEM8_CFG1, 0x40007644
2473 .set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648
2474 .set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008
2475 .set CYREG_PHUB_CFGMEM9_CFG0, 0x40007648
2476 .set CYREG_PHUB_CFGMEM9_CFG1, 0x4000764c
2477 .set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650
2478 .set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008
2479 .set CYREG_PHUB_CFGMEM10_CFG0, 0x40007650
2480 .set CYREG_PHUB_CFGMEM10_CFG1, 0x40007654
2481 .set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658
2482 .set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008
2483 .set CYREG_PHUB_CFGMEM11_CFG0, 0x40007658
2484 .set CYREG_PHUB_CFGMEM11_CFG1, 0x4000765c
2485 .set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660
2486 .set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008
2487 .set CYREG_PHUB_CFGMEM12_CFG0, 0x40007660
2488 .set CYREG_PHUB_CFGMEM12_CFG1, 0x40007664
2489 .set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668
2490 .set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008
2491 .set CYREG_PHUB_CFGMEM13_CFG0, 0x40007668
2492 .set CYREG_PHUB_CFGMEM13_CFG1, 0x4000766c
2493 .set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670
2494 .set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008
2495 .set CYREG_PHUB_CFGMEM14_CFG0, 0x40007670
2496 .set CYREG_PHUB_CFGMEM14_CFG1, 0x40007674
2497 .set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678
2498 .set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008
2499 .set CYREG_PHUB_CFGMEM15_CFG0, 0x40007678
2500 .set CYREG_PHUB_CFGMEM15_CFG1, 0x4000767c
2501 .set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680
2502 .set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008
2503 .set CYREG_PHUB_CFGMEM16_CFG0, 0x40007680
2504 .set CYREG_PHUB_CFGMEM16_CFG1, 0x40007684
2505 .set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688
2506 .set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008
2507 .set CYREG_PHUB_CFGMEM17_CFG0, 0x40007688
2508 .set CYREG_PHUB_CFGMEM17_CFG1, 0x4000768c
2509 .set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690
2510 .set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008
2511 .set CYREG_PHUB_CFGMEM18_CFG0, 0x40007690
2512 .set CYREG_PHUB_CFGMEM18_CFG1, 0x40007694
2513 .set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698
2514 .set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008
2515 .set CYREG_PHUB_CFGMEM19_CFG0, 0x40007698
2516 .set CYREG_PHUB_CFGMEM19_CFG1, 0x4000769c
2517 .set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0
2518 .set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008
2519 .set CYREG_PHUB_CFGMEM20_CFG0, 0x400076a0
2520 .set CYREG_PHUB_CFGMEM20_CFG1, 0x400076a4
2521 .set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8
2522 .set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008
2523 .set CYREG_PHUB_CFGMEM21_CFG0, 0x400076a8
2524 .set CYREG_PHUB_CFGMEM21_CFG1, 0x400076ac
2525 .set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0
2526 .set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008
2527 .set CYREG_PHUB_CFGMEM22_CFG0, 0x400076b0
2528 .set CYREG_PHUB_CFGMEM22_CFG1, 0x400076b4
2529 .set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8
2530 .set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008
2531 .set CYREG_PHUB_CFGMEM23_CFG0, 0x400076b8
2532 .set CYREG_PHUB_CFGMEM23_CFG1, 0x400076bc
2533 .set CYDEV_PHUB_TDMEM0_BASE, 0x40007800
2534 .set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008
2535 .set CYREG_PHUB_TDMEM0_ORIG_TD0, 0x40007800
2536 .set CYREG_PHUB_TDMEM0_ORIG_TD1, 0x40007804
2537 .set CYDEV_PHUB_TDMEM1_BASE, 0x40007808
2538 .set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008
2539 .set CYREG_PHUB_TDMEM1_ORIG_TD0, 0x40007808
2540 .set CYREG_PHUB_TDMEM1_ORIG_TD1, 0x4000780c
2541 .set CYDEV_PHUB_TDMEM2_BASE, 0x40007810
2542 .set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008
2543 .set CYREG_PHUB_TDMEM2_ORIG_TD0, 0x40007810
2544 .set CYREG_PHUB_TDMEM2_ORIG_TD1, 0x40007814
2545 .set CYDEV_PHUB_TDMEM3_BASE, 0x40007818
2546 .set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008
2547 .set CYREG_PHUB_TDMEM3_ORIG_TD0, 0x40007818
2548 .set CYREG_PHUB_TDMEM3_ORIG_TD1, 0x4000781c
2549 .set CYDEV_PHUB_TDMEM4_BASE, 0x40007820
2550 .set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008
2551 .set CYREG_PHUB_TDMEM4_ORIG_TD0, 0x40007820
2552 .set CYREG_PHUB_TDMEM4_ORIG_TD1, 0x40007824
2553 .set CYDEV_PHUB_TDMEM5_BASE, 0x40007828
2554 .set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008
2555 .set CYREG_PHUB_TDMEM5_ORIG_TD0, 0x40007828
2556 .set CYREG_PHUB_TDMEM5_ORIG_TD1, 0x4000782c
2557 .set CYDEV_PHUB_TDMEM6_BASE, 0x40007830
2558 .set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008
2559 .set CYREG_PHUB_TDMEM6_ORIG_TD0, 0x40007830
2560 .set CYREG_PHUB_TDMEM6_ORIG_TD1, 0x40007834
2561 .set CYDEV_PHUB_TDMEM7_BASE, 0x40007838
2562 .set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008
2563 .set CYREG_PHUB_TDMEM7_ORIG_TD0, 0x40007838
2564 .set CYREG_PHUB_TDMEM7_ORIG_TD1, 0x4000783c
2565 .set CYDEV_PHUB_TDMEM8_BASE, 0x40007840
2566 .set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008
2567 .set CYREG_PHUB_TDMEM8_ORIG_TD0, 0x40007840
2568 .set CYREG_PHUB_TDMEM8_ORIG_TD1, 0x40007844
2569 .set CYDEV_PHUB_TDMEM9_BASE, 0x40007848
2570 .set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008
2571 .set CYREG_PHUB_TDMEM9_ORIG_TD0, 0x40007848
2572 .set CYREG_PHUB_TDMEM9_ORIG_TD1, 0x4000784c
2573 .set CYDEV_PHUB_TDMEM10_BASE, 0x40007850
2574 .set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008
2575 .set CYREG_PHUB_TDMEM10_ORIG_TD0, 0x40007850
2576 .set CYREG_PHUB_TDMEM10_ORIG_TD1, 0x40007854
2577 .set CYDEV_PHUB_TDMEM11_BASE, 0x40007858
2578 .set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008
2579 .set CYREG_PHUB_TDMEM11_ORIG_TD0, 0x40007858
2580 .set CYREG_PHUB_TDMEM11_ORIG_TD1, 0x4000785c
2581 .set CYDEV_PHUB_TDMEM12_BASE, 0x40007860
2582 .set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008
2583 .set CYREG_PHUB_TDMEM12_ORIG_TD0, 0x40007860
2584 .set CYREG_PHUB_TDMEM12_ORIG_TD1, 0x40007864
2585 .set CYDEV_PHUB_TDMEM13_BASE, 0x40007868
2586 .set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008
2587 .set CYREG_PHUB_TDMEM13_ORIG_TD0, 0x40007868
2588 .set CYREG_PHUB_TDMEM13_ORIG_TD1, 0x4000786c
2589 .set CYDEV_PHUB_TDMEM14_BASE, 0x40007870
2590 .set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008
2591 .set CYREG_PHUB_TDMEM14_ORIG_TD0, 0x40007870
2592 .set CYREG_PHUB_TDMEM14_ORIG_TD1, 0x40007874
2593 .set CYDEV_PHUB_TDMEM15_BASE, 0x40007878
2594 .set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008
2595 .set CYREG_PHUB_TDMEM15_ORIG_TD0, 0x40007878
2596 .set CYREG_PHUB_TDMEM15_ORIG_TD1, 0x4000787c
2597 .set CYDEV_PHUB_TDMEM16_BASE, 0x40007880
2598 .set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008
2599 .set CYREG_PHUB_TDMEM16_ORIG_TD0, 0x40007880
2600 .set CYREG_PHUB_TDMEM16_ORIG_TD1, 0x40007884
2601 .set CYDEV_PHUB_TDMEM17_BASE, 0x40007888
2602 .set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008
2603 .set CYREG_PHUB_TDMEM17_ORIG_TD0, 0x40007888
2604 .set CYREG_PHUB_TDMEM17_ORIG_TD1, 0x4000788c
2605 .set CYDEV_PHUB_TDMEM18_BASE, 0x40007890
2606 .set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008
2607 .set CYREG_PHUB_TDMEM18_ORIG_TD0, 0x40007890
2608 .set CYREG_PHUB_TDMEM18_ORIG_TD1, 0x40007894
2609 .set CYDEV_PHUB_TDMEM19_BASE, 0x40007898
2610 .set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008
2611 .set CYREG_PHUB_TDMEM19_ORIG_TD0, 0x40007898
2612 .set CYREG_PHUB_TDMEM19_ORIG_TD1, 0x4000789c
2613 .set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0
2614 .set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008
2615 .set CYREG_PHUB_TDMEM20_ORIG_TD0, 0x400078a0
2616 .set CYREG_PHUB_TDMEM20_ORIG_TD1, 0x400078a4
2617 .set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8
2618 .set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008
2619 .set CYREG_PHUB_TDMEM21_ORIG_TD0, 0x400078a8
2620 .set CYREG_PHUB_TDMEM21_ORIG_TD1, 0x400078ac
2621 .set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0
2622 .set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008
2623 .set CYREG_PHUB_TDMEM22_ORIG_TD0, 0x400078b0
2624 .set CYREG_PHUB_TDMEM22_ORIG_TD1, 0x400078b4
2625 .set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8
2626 .set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008
2627 .set CYREG_PHUB_TDMEM23_ORIG_TD0, 0x400078b8
2628 .set CYREG_PHUB_TDMEM23_ORIG_TD1, 0x400078bc
2629 .set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0
2630 .set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008
2631 .set CYREG_PHUB_TDMEM24_ORIG_TD0, 0x400078c0
2632 .set CYREG_PHUB_TDMEM24_ORIG_TD1, 0x400078c4
2633 .set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8
2634 .set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008
2635 .set CYREG_PHUB_TDMEM25_ORIG_TD0, 0x400078c8
2636 .set CYREG_PHUB_TDMEM25_ORIG_TD1, 0x400078cc
2637 .set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0
2638 .set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008
2639 .set CYREG_PHUB_TDMEM26_ORIG_TD0, 0x400078d0
2640 .set CYREG_PHUB_TDMEM26_ORIG_TD1, 0x400078d4
2641 .set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8
2642 .set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008
2643 .set CYREG_PHUB_TDMEM27_ORIG_TD0, 0x400078d8
2644 .set CYREG_PHUB_TDMEM27_ORIG_TD1, 0x400078dc
2645 .set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0
2646 .set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008
2647 .set CYREG_PHUB_TDMEM28_ORIG_TD0, 0x400078e0
2648 .set CYREG_PHUB_TDMEM28_ORIG_TD1, 0x400078e4
2649 .set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8
2650 .set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008
2651 .set CYREG_PHUB_TDMEM29_ORIG_TD0, 0x400078e8
2652 .set CYREG_PHUB_TDMEM29_ORIG_TD1, 0x400078ec
2653 .set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0
2654 .set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008
2655 .set CYREG_PHUB_TDMEM30_ORIG_TD0, 0x400078f0
2656 .set CYREG_PHUB_TDMEM30_ORIG_TD1, 0x400078f4
2657 .set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8
2658 .set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008
2659 .set CYREG_PHUB_TDMEM31_ORIG_TD0, 0x400078f8
2660 .set CYREG_PHUB_TDMEM31_ORIG_TD1, 0x400078fc
2661 .set CYDEV_PHUB_TDMEM32_BASE, 0x40007900
2662 .set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008
2663 .set CYREG_PHUB_TDMEM32_ORIG_TD0, 0x40007900
2664 .set CYREG_PHUB_TDMEM32_ORIG_TD1, 0x40007904
2665 .set CYDEV_PHUB_TDMEM33_BASE, 0x40007908
2666 .set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008
2667 .set CYREG_PHUB_TDMEM33_ORIG_TD0, 0x40007908
2668 .set CYREG_PHUB_TDMEM33_ORIG_TD1, 0x4000790c
2669 .set CYDEV_PHUB_TDMEM34_BASE, 0x40007910
2670 .set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008
2671 .set CYREG_PHUB_TDMEM34_ORIG_TD0, 0x40007910
2672 .set CYREG_PHUB_TDMEM34_ORIG_TD1, 0x40007914
2673 .set CYDEV_PHUB_TDMEM35_BASE, 0x40007918
2674 .set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008
2675 .set CYREG_PHUB_TDMEM35_ORIG_TD0, 0x40007918
2676 .set CYREG_PHUB_TDMEM35_ORIG_TD1, 0x4000791c
2677 .set CYDEV_PHUB_TDMEM36_BASE, 0x40007920
2678 .set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008
2679 .set CYREG_PHUB_TDMEM36_ORIG_TD0, 0x40007920
2680 .set CYREG_PHUB_TDMEM36_ORIG_TD1, 0x40007924
2681 .set CYDEV_PHUB_TDMEM37_BASE, 0x40007928
2682 .set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008
2683 .set CYREG_PHUB_TDMEM37_ORIG_TD0, 0x40007928
2684 .set CYREG_PHUB_TDMEM37_ORIG_TD1, 0x4000792c
2685 .set CYDEV_PHUB_TDMEM38_BASE, 0x40007930
2686 .set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008
2687 .set CYREG_PHUB_TDMEM38_ORIG_TD0, 0x40007930
2688 .set CYREG_PHUB_TDMEM38_ORIG_TD1, 0x40007934
2689 .set CYDEV_PHUB_TDMEM39_BASE, 0x40007938
2690 .set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008
2691 .set CYREG_PHUB_TDMEM39_ORIG_TD0, 0x40007938
2692 .set CYREG_PHUB_TDMEM39_ORIG_TD1, 0x4000793c
2693 .set CYDEV_PHUB_TDMEM40_BASE, 0x40007940
2694 .set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008
2695 .set CYREG_PHUB_TDMEM40_ORIG_TD0, 0x40007940
2696 .set CYREG_PHUB_TDMEM40_ORIG_TD1, 0x40007944
2697 .set CYDEV_PHUB_TDMEM41_BASE, 0x40007948
2698 .set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008
2699 .set CYREG_PHUB_TDMEM41_ORIG_TD0, 0x40007948
2700 .set CYREG_PHUB_TDMEM41_ORIG_TD1, 0x4000794c
2701 .set CYDEV_PHUB_TDMEM42_BASE, 0x40007950
2702 .set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008
2703 .set CYREG_PHUB_TDMEM42_ORIG_TD0, 0x40007950
2704 .set CYREG_PHUB_TDMEM42_ORIG_TD1, 0x40007954
2705 .set CYDEV_PHUB_TDMEM43_BASE, 0x40007958
2706 .set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008
2707 .set CYREG_PHUB_TDMEM43_ORIG_TD0, 0x40007958
2708 .set CYREG_PHUB_TDMEM43_ORIG_TD1, 0x4000795c
2709 .set CYDEV_PHUB_TDMEM44_BASE, 0x40007960
2710 .set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008
2711 .set CYREG_PHUB_TDMEM44_ORIG_TD0, 0x40007960
2712 .set CYREG_PHUB_TDMEM44_ORIG_TD1, 0x40007964
2713 .set CYDEV_PHUB_TDMEM45_BASE, 0x40007968
2714 .set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008
2715 .set CYREG_PHUB_TDMEM45_ORIG_TD0, 0x40007968
2716 .set CYREG_PHUB_TDMEM45_ORIG_TD1, 0x4000796c
2717 .set CYDEV_PHUB_TDMEM46_BASE, 0x40007970
2718 .set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008
2719 .set CYREG_PHUB_TDMEM46_ORIG_TD0, 0x40007970
2720 .set CYREG_PHUB_TDMEM46_ORIG_TD1, 0x40007974
2721 .set CYDEV_PHUB_TDMEM47_BASE, 0x40007978
2722 .set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008
2723 .set CYREG_PHUB_TDMEM47_ORIG_TD0, 0x40007978
2724 .set CYREG_PHUB_TDMEM47_ORIG_TD1, 0x4000797c
2725 .set CYDEV_PHUB_TDMEM48_BASE, 0x40007980
2726 .set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008
2727 .set CYREG_PHUB_TDMEM48_ORIG_TD0, 0x40007980
2728 .set CYREG_PHUB_TDMEM48_ORIG_TD1, 0x40007984
2729 .set CYDEV_PHUB_TDMEM49_BASE, 0x40007988
2730 .set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008
2731 .set CYREG_PHUB_TDMEM49_ORIG_TD0, 0x40007988
2732 .set CYREG_PHUB_TDMEM49_ORIG_TD1, 0x4000798c
2733 .set CYDEV_PHUB_TDMEM50_BASE, 0x40007990
2734 .set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008
2735 .set CYREG_PHUB_TDMEM50_ORIG_TD0, 0x40007990
2736 .set CYREG_PHUB_TDMEM50_ORIG_TD1, 0x40007994
2737 .set CYDEV_PHUB_TDMEM51_BASE, 0x40007998
2738 .set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008
2739 .set CYREG_PHUB_TDMEM51_ORIG_TD0, 0x40007998
2740 .set CYREG_PHUB_TDMEM51_ORIG_TD1, 0x4000799c
2741 .set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0
2742 .set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008
2743 .set CYREG_PHUB_TDMEM52_ORIG_TD0, 0x400079a0
2744 .set CYREG_PHUB_TDMEM52_ORIG_TD1, 0x400079a4
2745 .set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8
2746 .set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008
2747 .set CYREG_PHUB_TDMEM53_ORIG_TD0, 0x400079a8
2748 .set CYREG_PHUB_TDMEM53_ORIG_TD1, 0x400079ac
2749 .set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0
2750 .set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008
2751 .set CYREG_PHUB_TDMEM54_ORIG_TD0, 0x400079b0
2752 .set CYREG_PHUB_TDMEM54_ORIG_TD1, 0x400079b4
2753 .set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8
2754 .set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008
2755 .set CYREG_PHUB_TDMEM55_ORIG_TD0, 0x400079b8
2756 .set CYREG_PHUB_TDMEM55_ORIG_TD1, 0x400079bc
2757 .set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0
2758 .set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008
2759 .set CYREG_PHUB_TDMEM56_ORIG_TD0, 0x400079c0
2760 .set CYREG_PHUB_TDMEM56_ORIG_TD1, 0x400079c4
2761 .set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8
2762 .set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008
2763 .set CYREG_PHUB_TDMEM57_ORIG_TD0, 0x400079c8
2764 .set CYREG_PHUB_TDMEM57_ORIG_TD1, 0x400079cc
2765 .set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0
2766 .set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008
2767 .set CYREG_PHUB_TDMEM58_ORIG_TD0, 0x400079d0
2768 .set CYREG_PHUB_TDMEM58_ORIG_TD1, 0x400079d4
2769 .set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8
2770 .set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008
2771 .set CYREG_PHUB_TDMEM59_ORIG_TD0, 0x400079d8
2772 .set CYREG_PHUB_TDMEM59_ORIG_TD1, 0x400079dc
2773 .set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0
2774 .set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008
2775 .set CYREG_PHUB_TDMEM60_ORIG_TD0, 0x400079e0
2776 .set CYREG_PHUB_TDMEM60_ORIG_TD1, 0x400079e4
2777 .set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8
2778 .set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008
2779 .set CYREG_PHUB_TDMEM61_ORIG_TD0, 0x400079e8
2780 .set CYREG_PHUB_TDMEM61_ORIG_TD1, 0x400079ec
2781 .set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0
2782 .set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008
2783 .set CYREG_PHUB_TDMEM62_ORIG_TD0, 0x400079f0
2784 .set CYREG_PHUB_TDMEM62_ORIG_TD1, 0x400079f4
2785 .set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8
2786 .set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008
2787 .set CYREG_PHUB_TDMEM63_ORIG_TD0, 0x400079f8
2788 .set CYREG_PHUB_TDMEM63_ORIG_TD1, 0x400079fc
2789 .set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00
2790 .set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008
2791 .set CYREG_PHUB_TDMEM64_ORIG_TD0, 0x40007a00
2792 .set CYREG_PHUB_TDMEM64_ORIG_TD1, 0x40007a04
2793 .set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08
2794 .set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008
2795 .set CYREG_PHUB_TDMEM65_ORIG_TD0, 0x40007a08
2796 .set CYREG_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c
2797 .set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10
2798 .set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008
2799 .set CYREG_PHUB_TDMEM66_ORIG_TD0, 0x40007a10
2800 .set CYREG_PHUB_TDMEM66_ORIG_TD1, 0x40007a14
2801 .set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18
2802 .set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008
2803 .set CYREG_PHUB_TDMEM67_ORIG_TD0, 0x40007a18
2804 .set CYREG_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c
2805 .set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20
2806 .set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008
2807 .set CYREG_PHUB_TDMEM68_ORIG_TD0, 0x40007a20
2808 .set CYREG_PHUB_TDMEM68_ORIG_TD1, 0x40007a24
2809 .set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28
2810 .set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008
2811 .set CYREG_PHUB_TDMEM69_ORIG_TD0, 0x40007a28
2812 .set CYREG_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c
2813 .set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30
2814 .set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008
2815 .set CYREG_PHUB_TDMEM70_ORIG_TD0, 0x40007a30
2816 .set CYREG_PHUB_TDMEM70_ORIG_TD1, 0x40007a34
2817 .set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38
2818 .set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008
2819 .set CYREG_PHUB_TDMEM71_ORIG_TD0, 0x40007a38
2820 .set CYREG_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c
2821 .set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40
2822 .set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008
2823 .set CYREG_PHUB_TDMEM72_ORIG_TD0, 0x40007a40
2824 .set CYREG_PHUB_TDMEM72_ORIG_TD1, 0x40007a44
2825 .set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48
2826 .set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008
2827 .set CYREG_PHUB_TDMEM73_ORIG_TD0, 0x40007a48
2828 .set CYREG_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c
2829 .set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50
2830 .set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008
2831 .set CYREG_PHUB_TDMEM74_ORIG_TD0, 0x40007a50
2832 .set CYREG_PHUB_TDMEM74_ORIG_TD1, 0x40007a54
2833 .set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58
2834 .set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008
2835 .set CYREG_PHUB_TDMEM75_ORIG_TD0, 0x40007a58
2836 .set CYREG_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c
2837 .set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60
2838 .set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008
2839 .set CYREG_PHUB_TDMEM76_ORIG_TD0, 0x40007a60
2840 .set CYREG_PHUB_TDMEM76_ORIG_TD1, 0x40007a64
2841 .set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68
2842 .set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008
2843 .set CYREG_PHUB_TDMEM77_ORIG_TD0, 0x40007a68
2844 .set CYREG_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c
2845 .set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70
2846 .set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008
2847 .set CYREG_PHUB_TDMEM78_ORIG_TD0, 0x40007a70
2848 .set CYREG_PHUB_TDMEM78_ORIG_TD1, 0x40007a74
2849 .set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78
2850 .set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008
2851 .set CYREG_PHUB_TDMEM79_ORIG_TD0, 0x40007a78
2852 .set CYREG_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c
2853 .set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80
2854 .set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008
2855 .set CYREG_PHUB_TDMEM80_ORIG_TD0, 0x40007a80
2856 .set CYREG_PHUB_TDMEM80_ORIG_TD1, 0x40007a84
2857 .set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88
2858 .set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008
2859 .set CYREG_PHUB_TDMEM81_ORIG_TD0, 0x40007a88
2860 .set CYREG_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c
2861 .set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90
2862 .set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008
2863 .set CYREG_PHUB_TDMEM82_ORIG_TD0, 0x40007a90
2864 .set CYREG_PHUB_TDMEM82_ORIG_TD1, 0x40007a94
2865 .set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98
2866 .set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008
2867 .set CYREG_PHUB_TDMEM83_ORIG_TD0, 0x40007a98
2868 .set CYREG_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c
2869 .set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0
2870 .set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008
2871 .set CYREG_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0
2872 .set CYREG_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4
2873 .set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8
2874 .set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008
2875 .set CYREG_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8
2876 .set CYREG_PHUB_TDMEM85_ORIG_TD1, 0x40007aac
2877 .set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0
2878 .set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008
2879 .set CYREG_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0
2880 .set CYREG_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4
2881 .set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8
2882 .set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008
2883 .set CYREG_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8
2884 .set CYREG_PHUB_TDMEM87_ORIG_TD1, 0x40007abc
2885 .set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0
2886 .set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008
2887 .set CYREG_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0
2888 .set CYREG_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4
2889 .set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8
2890 .set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008
2891 .set CYREG_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8
2892 .set CYREG_PHUB_TDMEM89_ORIG_TD1, 0x40007acc
2893 .set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0
2894 .set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008
2895 .set CYREG_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0
2896 .set CYREG_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4
2897 .set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8
2898 .set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008
2899 .set CYREG_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8
2900 .set CYREG_PHUB_TDMEM91_ORIG_TD1, 0x40007adc
2901 .set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0
2902 .set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008
2903 .set CYREG_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0
2904 .set CYREG_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4
2905 .set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8
2906 .set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008
2907 .set CYREG_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8
2908 .set CYREG_PHUB_TDMEM93_ORIG_TD1, 0x40007aec
2909 .set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0
2910 .set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008
2911 .set CYREG_PHUB_TDMEM94_ORIG_TD0, 0x40007af0
2912 .set CYREG_PHUB_TDMEM94_ORIG_TD1, 0x40007af4
2913 .set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8
2914 .set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008
2915 .set CYREG_PHUB_TDMEM95_ORIG_TD0, 0x40007af8
2916 .set CYREG_PHUB_TDMEM95_ORIG_TD1, 0x40007afc
2917 .set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00
2918 .set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008
2919 .set CYREG_PHUB_TDMEM96_ORIG_TD0, 0x40007b00
2920 .set CYREG_PHUB_TDMEM96_ORIG_TD1, 0x40007b04
2921 .set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08
2922 .set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008
2923 .set CYREG_PHUB_TDMEM97_ORIG_TD0, 0x40007b08
2924 .set CYREG_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c
2925 .set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10
2926 .set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008
2927 .set CYREG_PHUB_TDMEM98_ORIG_TD0, 0x40007b10
2928 .set CYREG_PHUB_TDMEM98_ORIG_TD1, 0x40007b14
2929 .set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18
2930 .set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008
2931 .set CYREG_PHUB_TDMEM99_ORIG_TD0, 0x40007b18
2932 .set CYREG_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c
2933 .set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20
2934 .set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008
2935 .set CYREG_PHUB_TDMEM100_ORIG_TD0, 0x40007b20
2936 .set CYREG_PHUB_TDMEM100_ORIG_TD1, 0x40007b24
2937 .set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28
2938 .set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008
2939 .set CYREG_PHUB_TDMEM101_ORIG_TD0, 0x40007b28
2940 .set CYREG_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c
2941 .set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30
2942 .set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008
2943 .set CYREG_PHUB_TDMEM102_ORIG_TD0, 0x40007b30
2944 .set CYREG_PHUB_TDMEM102_ORIG_TD1, 0x40007b34
2945 .set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38
2946 .set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008
2947 .set CYREG_PHUB_TDMEM103_ORIG_TD0, 0x40007b38
2948 .set CYREG_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c
2949 .set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40
2950 .set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008
2951 .set CYREG_PHUB_TDMEM104_ORIG_TD0, 0x40007b40
2952 .set CYREG_PHUB_TDMEM104_ORIG_TD1, 0x40007b44
2953 .set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48
2954 .set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008
2955 .set CYREG_PHUB_TDMEM105_ORIG_TD0, 0x40007b48
2956 .set CYREG_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c
2957 .set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50
2958 .set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008
2959 .set CYREG_PHUB_TDMEM106_ORIG_TD0, 0x40007b50
2960 .set CYREG_PHUB_TDMEM106_ORIG_TD1, 0x40007b54
2961 .set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58
2962 .set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008
2963 .set CYREG_PHUB_TDMEM107_ORIG_TD0, 0x40007b58
2964 .set CYREG_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c
2965 .set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60
2966 .set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008
2967 .set CYREG_PHUB_TDMEM108_ORIG_TD0, 0x40007b60
2968 .set CYREG_PHUB_TDMEM108_ORIG_TD1, 0x40007b64
2969 .set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68
2970 .set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008
2971 .set CYREG_PHUB_TDMEM109_ORIG_TD0, 0x40007b68
2972 .set CYREG_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c
2973 .set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70
2974 .set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008
2975 .set CYREG_PHUB_TDMEM110_ORIG_TD0, 0x40007b70
2976 .set CYREG_PHUB_TDMEM110_ORIG_TD1, 0x40007b74
2977 .set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78
2978 .set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008
2979 .set CYREG_PHUB_TDMEM111_ORIG_TD0, 0x40007b78
2980 .set CYREG_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c
2981 .set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80
2982 .set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008
2983 .set CYREG_PHUB_TDMEM112_ORIG_TD0, 0x40007b80
2984 .set CYREG_PHUB_TDMEM112_ORIG_TD1, 0x40007b84
2985 .set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88
2986 .set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008
2987 .set CYREG_PHUB_TDMEM113_ORIG_TD0, 0x40007b88
2988 .set CYREG_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c
2989 .set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90
2990 .set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008
2991 .set CYREG_PHUB_TDMEM114_ORIG_TD0, 0x40007b90
2992 .set CYREG_PHUB_TDMEM114_ORIG_TD1, 0x40007b94
2993 .set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98
2994 .set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008
2995 .set CYREG_PHUB_TDMEM115_ORIG_TD0, 0x40007b98
2996 .set CYREG_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c
2997 .set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0
2998 .set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008
2999 .set CYREG_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0
3000 .set CYREG_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4
3001 .set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8
3002 .set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008
3003 .set CYREG_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8
3004 .set CYREG_PHUB_TDMEM117_ORIG_TD1, 0x40007bac
3005 .set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0
3006 .set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008
3007 .set CYREG_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0
3008 .set CYREG_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4
3009 .set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8
3010 .set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008
3011 .set CYREG_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8
3012 .set CYREG_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc
3013 .set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0
3014 .set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008
3015 .set CYREG_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0
3016 .set CYREG_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4
3017 .set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8
3018 .set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008
3019 .set CYREG_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8
3020 .set CYREG_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc
3021 .set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0
3022 .set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008
3023 .set CYREG_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0
3024 .set CYREG_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4
3025 .set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8
3026 .set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008
3027 .set CYREG_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8
3028 .set CYREG_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc
3029 .set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0
3030 .set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008
3031 .set CYREG_PHUB_TDMEM124_ORIG_TD0, 0x40007be0
3032 .set CYREG_PHUB_TDMEM124_ORIG_TD1, 0x40007be4
3033 .set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8
3034 .set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008
3035 .set CYREG_PHUB_TDMEM125_ORIG_TD0, 0x40007be8
3036 .set CYREG_PHUB_TDMEM125_ORIG_TD1, 0x40007bec
3037 .set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0
3038 .set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008
3039 .set CYREG_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0
3040 .set CYREG_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4
3041 .set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8
3042 .set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008
3043 .set CYREG_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8
3044 .set CYREG_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc
3045 .set CYDEV_EE_BASE, 0x40008000
3046 .set CYDEV_EE_SIZE, 0x00000800
3047 .set CYREG_EE_DATA_MBASE, 0x40008000
3048 .set CYREG_EE_DATA_MSIZE, 0x00000800
3049 .set CYDEV_CAN0_BASE, 0x4000a000
3050 .set CYDEV_CAN0_SIZE, 0x000002a0
3051 .set CYDEV_CAN0_CSR_BASE, 0x4000a000
3052 .set CYDEV_CAN0_CSR_SIZE, 0x00000018
3053 .set CYREG_CAN0_CSR_INT_SR, 0x4000a000
3054 .set CYREG_CAN0_CSR_INT_EN, 0x4000a004
3055 .set CYREG_CAN0_CSR_BUF_SR, 0x4000a008
3056 .set CYREG_CAN0_CSR_ERR_SR, 0x4000a00c
3057 .set CYREG_CAN0_CSR_CMD, 0x4000a010
3058 .set CYREG_CAN0_CSR_CFG, 0x4000a014
3059 .set CYDEV_CAN0_TX0_BASE, 0x4000a020
3060 .set CYDEV_CAN0_TX0_SIZE, 0x00000010
3061 .set CYREG_CAN0_TX0_CMD, 0x4000a020
3062 .set CYREG_CAN0_TX0_ID, 0x4000a024
3063 .set CYREG_CAN0_TX0_DH, 0x4000a028
3064 .set CYREG_CAN0_TX0_DL, 0x4000a02c
3065 .set CYDEV_CAN0_TX1_BASE, 0x4000a030
3066 .set CYDEV_CAN0_TX1_SIZE, 0x00000010
3067 .set CYREG_CAN0_TX1_CMD, 0x4000a030
3068 .set CYREG_CAN0_TX1_ID, 0x4000a034
3069 .set CYREG_CAN0_TX1_DH, 0x4000a038
3070 .set CYREG_CAN0_TX1_DL, 0x4000a03c
3071 .set CYDEV_CAN0_TX2_BASE, 0x4000a040
3072 .set CYDEV_CAN0_TX2_SIZE, 0x00000010
3073 .set CYREG_CAN0_TX2_CMD, 0x4000a040
3074 .set CYREG_CAN0_TX2_ID, 0x4000a044
3075 .set CYREG_CAN0_TX2_DH, 0x4000a048
3076 .set CYREG_CAN0_TX2_DL, 0x4000a04c
3077 .set CYDEV_CAN0_TX3_BASE, 0x4000a050
3078 .set CYDEV_CAN0_TX3_SIZE, 0x00000010
3079 .set CYREG_CAN0_TX3_CMD, 0x4000a050
3080 .set CYREG_CAN0_TX3_ID, 0x4000a054
3081 .set CYREG_CAN0_TX3_DH, 0x4000a058
3082 .set CYREG_CAN0_TX3_DL, 0x4000a05c
3083 .set CYDEV_CAN0_TX4_BASE, 0x4000a060
3084 .set CYDEV_CAN0_TX4_SIZE, 0x00000010
3085 .set CYREG_CAN0_TX4_CMD, 0x4000a060
3086 .set CYREG_CAN0_TX4_ID, 0x4000a064
3087 .set CYREG_CAN0_TX4_DH, 0x4000a068
3088 .set CYREG_CAN0_TX4_DL, 0x4000a06c
3089 .set CYDEV_CAN0_TX5_BASE, 0x4000a070
3090 .set CYDEV_CAN0_TX5_SIZE, 0x00000010
3091 .set CYREG_CAN0_TX5_CMD, 0x4000a070
3092 .set CYREG_CAN0_TX5_ID, 0x4000a074
3093 .set CYREG_CAN0_TX5_DH, 0x4000a078
3094 .set CYREG_CAN0_TX5_DL, 0x4000a07c
3095 .set CYDEV_CAN0_TX6_BASE, 0x4000a080
3096 .set CYDEV_CAN0_TX6_SIZE, 0x00000010
3097 .set CYREG_CAN0_TX6_CMD, 0x4000a080
3098 .set CYREG_CAN0_TX6_ID, 0x4000a084
3099 .set CYREG_CAN0_TX6_DH, 0x4000a088
3100 .set CYREG_CAN0_TX6_DL, 0x4000a08c
3101 .set CYDEV_CAN0_TX7_BASE, 0x4000a090
3102 .set CYDEV_CAN0_TX7_SIZE, 0x00000010
3103 .set CYREG_CAN0_TX7_CMD, 0x4000a090
3104 .set CYREG_CAN0_TX7_ID, 0x4000a094
3105 .set CYREG_CAN0_TX7_DH, 0x4000a098
3106 .set CYREG_CAN0_TX7_DL, 0x4000a09c
3107 .set CYDEV_CAN0_RX0_BASE, 0x4000a0a0
3108 .set CYDEV_CAN0_RX0_SIZE, 0x00000020
3109 .set CYREG_CAN0_RX0_CMD, 0x4000a0a0
3110 .set CYREG_CAN0_RX0_ID, 0x4000a0a4
3111 .set CYREG_CAN0_RX0_DH, 0x4000a0a8
3112 .set CYREG_CAN0_RX0_DL, 0x4000a0ac
3113 .set CYREG_CAN0_RX0_AMR, 0x4000a0b0
3114 .set CYREG_CAN0_RX0_ACR, 0x4000a0b4
3115 .set CYREG_CAN0_RX0_AMRD, 0x4000a0b8
3116 .set CYREG_CAN0_RX0_ACRD, 0x4000a0bc
3117 .set CYDEV_CAN0_RX1_BASE, 0x4000a0c0
3118 .set CYDEV_CAN0_RX1_SIZE, 0x00000020
3119 .set CYREG_CAN0_RX1_CMD, 0x4000a0c0
3120 .set CYREG_CAN0_RX1_ID, 0x4000a0c4
3121 .set CYREG_CAN0_RX1_DH, 0x4000a0c8
3122 .set CYREG_CAN0_RX1_DL, 0x4000a0cc
3123 .set CYREG_CAN0_RX1_AMR, 0x4000a0d0
3124 .set CYREG_CAN0_RX1_ACR, 0x4000a0d4
3125 .set CYREG_CAN0_RX1_AMRD, 0x4000a0d8
3126 .set CYREG_CAN0_RX1_ACRD, 0x4000a0dc
3127 .set CYDEV_CAN0_RX2_BASE, 0x4000a0e0
3128 .set CYDEV_CAN0_RX2_SIZE, 0x00000020
3129 .set CYREG_CAN0_RX2_CMD, 0x4000a0e0
3130 .set CYREG_CAN0_RX2_ID, 0x4000a0e4
3131 .set CYREG_CAN0_RX2_DH, 0x4000a0e8
3132 .set CYREG_CAN0_RX2_DL, 0x4000a0ec
3133 .set CYREG_CAN0_RX2_AMR, 0x4000a0f0
3134 .set CYREG_CAN0_RX2_ACR, 0x4000a0f4
3135 .set CYREG_CAN0_RX2_AMRD, 0x4000a0f8
3136 .set CYREG_CAN0_RX2_ACRD, 0x4000a0fc
3137 .set CYDEV_CAN0_RX3_BASE, 0x4000a100
3138 .set CYDEV_CAN0_RX3_SIZE, 0x00000020
3139 .set CYREG_CAN0_RX3_CMD, 0x4000a100
3140 .set CYREG_CAN0_RX3_ID, 0x4000a104
3141 .set CYREG_CAN0_RX3_DH, 0x4000a108
3142 .set CYREG_CAN0_RX3_DL, 0x4000a10c
3143 .set CYREG_CAN0_RX3_AMR, 0x4000a110
3144 .set CYREG_CAN0_RX3_ACR, 0x4000a114
3145 .set CYREG_CAN0_RX3_AMRD, 0x4000a118
3146 .set CYREG_CAN0_RX3_ACRD, 0x4000a11c
3147 .set CYDEV_CAN0_RX4_BASE, 0x4000a120
3148 .set CYDEV_CAN0_RX4_SIZE, 0x00000020
3149 .set CYREG_CAN0_RX4_CMD, 0x4000a120
3150 .set CYREG_CAN0_RX4_ID, 0x4000a124
3151 .set CYREG_CAN0_RX4_DH, 0x4000a128
3152 .set CYREG_CAN0_RX4_DL, 0x4000a12c
3153 .set CYREG_CAN0_RX4_AMR, 0x4000a130
3154 .set CYREG_CAN0_RX4_ACR, 0x4000a134
3155 .set CYREG_CAN0_RX4_AMRD, 0x4000a138
3156 .set CYREG_CAN0_RX4_ACRD, 0x4000a13c
3157 .set CYDEV_CAN0_RX5_BASE, 0x4000a140
3158 .set CYDEV_CAN0_RX5_SIZE, 0x00000020
3159 .set CYREG_CAN0_RX5_CMD, 0x4000a140
3160 .set CYREG_CAN0_RX5_ID, 0x4000a144