Static Timing Analysis

Project : USB_Bootloader
Build Time : 10/26/13 18:55:25
Device : CY8C5267AXI-LP051
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 64.000 MHz 64.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 64.000 MHz 64.000 MHz N/A
CyPLL_OUT CyPLL_OUT 64.000 MHz 64.000 MHz N/A