Use DMA for SCSI and SD card transfers for a massive performance boost.
[SCSI2SD-V6.git] / software / SCSI2SD / SCSI2SD.cydsn / Generated_Source / PSoC5 / cyfittergnu.inc
old mode 100755 (executable)
new mode 100644 (file)
index e2cddad..b4c3cb6
@@ -6,13 +6,33 @@
 /* Debug_Timer_Interrupt */\r
 .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set Debug_Timer_Interrupt__INTC_MASK, 0x01\r
-.set Debug_Timer_Interrupt__INTC_NUMBER, 0\r
+.set Debug_Timer_Interrupt__INTC_MASK, 0x02\r
+.set Debug_Timer_Interrupt__INTC_NUMBER, 1\r
 .set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7\r
-.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
 .set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
+/* SCSI_RX_DMA_COMPLETE */\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01\r
+.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA_COMPLETE */\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x04\r
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 2\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
 /* Debug_Timer_TimerHW */\r
 .set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0\r
 .set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1\r
 .set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1\r
 .set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0\r
 \r
+/* SD_RX_DMA_COMPLETE */\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x08\r
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 3\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SD_TX_DMA_COMPLETE */\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x10\r
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 4\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
 /* USBFS_bus_reset */\r
 .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
 /* SCSI_CTL_PHASE */\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
 \r
 /* SCSI_Out_Bits */\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
 .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
 \r
 /* USBFS_arb_int */\r
 .set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 /* SCSI_Out_Ctl */\r
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
 .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
 \r
 /* SCSI_Out_DBx */\r
 .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
 .set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
 .set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
 .set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
 .set SDCard_BSPIM_RxStsReg__4__POS, 4\r
 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
 .set SDCard_BSPIM_RxStsReg__6__POS, 6\r
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB06_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
 .set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
 .set SDCard_BSPIM_TxStsReg__1__POS, 1\r
 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
 .set SDCard_BSPIM_TxStsReg__4__POS, 4\r
 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB04_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB04_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1\r
 \r
 /* USBFS_dp_int */\r
 .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set SCSI_In_DBx__DB7__SHIFT, 1\r
 .set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW\r
 \r
+/* SCSI_RX_DMA */\r
+.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_RX_DMA__DRQ_NUMBER, 0\r
+.set SCSI_RX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_RX_DMA__PRIORITY, 2\r
+.set SCSI_RX_DMA__TERMIN_EN, 0\r
+.set SCSI_RX_DMA__TERMIN_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_RX_DMA__TERMOUT0_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_RX_DMA__TERMOUT1_SEL, 0\r
+\r
+/* SCSI_TX_DMA */\r
+.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_TX_DMA__DRQ_NUMBER, 1\r
+.set SCSI_TX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_TX_DMA__PRIORITY, 2\r
+.set SCSI_TX_DMA__TERMIN_EN, 0\r
+.set SCSI_TX_DMA__TERMIN_SEL, 0\r
+.set SCSI_TX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_TX_DMA__TERMOUT0_SEL, 1\r
+.set SCSI_TX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_TX_DMA__TERMOUT1_SEL, 0\r
+\r
 /* SD_Data_Clk */\r
 .set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0\r
 .set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1\r
 /* scsiTarget */\r
 .set scsiTarget_StatusReg__0__MASK, 0x01\r
 .set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
 .set scsiTarget_StatusReg__1__MASK, 0x02\r
 .set scsiTarget_StatusReg__1__POS, 1\r
 .set scsiTarget_StatusReg__2__MASK, 0x04\r
 .set scsiTarget_StatusReg__2__POS, 2\r
 .set scsiTarget_StatusReg__3__MASK, 0x08\r
 .set scsiTarget_StatusReg__3__POS, 3\r
-.set scsiTarget_StatusReg__MASK, 0x0F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB13_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB13_ST\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB12_MSK\r
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB12_ST\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB12_CTL\r
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB12_CTL\r
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB12_MSK\r
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB12_13_A0\r
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB12_13_A1\r
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB12_13_D0\r
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB12_13_D1\r
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB12_13_F0\r
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB12_13_F1\r
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB12_A0_A1\r
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB12_A0\r
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB12_A1\r
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB12_D0_D1\r
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB12_D0\r
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB12_D1\r
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB12_F0_F1\r
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB12_F0\r
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB12_F1\r
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_StatusReg__4__MASK, 0x10\r
+.set scsiTarget_StatusReg__4__POS, 4\r
+.set scsiTarget_StatusReg__MASK, 0x1F\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
 \r
 /* SD_Clk_Ctl */\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__REMOVED, 1\r
 \r
 /* USBFS_ep_0 */\r
 .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 /* USBFS_ep_1 */\r
 .set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_1__INTC_MASK, 0x02\r
-.set USBFS_ep_1__INTC_NUMBER, 1\r
+.set USBFS_ep_1__INTC_MASK, 0x20\r
+.set USBFS_ep_1__INTC_NUMBER, 5\r
 .set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
 .set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* USBFS_ep_2 */\r
 .set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_2__INTC_MASK, 0x04\r
-.set USBFS_ep_2__INTC_NUMBER, 2\r
+.set USBFS_ep_2__INTC_MASK, 0x40\r
+.set USBFS_ep_2__INTC_NUMBER, 6\r
 .set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* USBFS_ep_3 */\r
 .set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_3__INTC_MASK, 0x08\r
-.set USBFS_ep_3__INTC_NUMBER, 3\r
+.set USBFS_ep_3__INTC_MASK, 0x80\r
+.set USBFS_ep_3__INTC_NUMBER, 7\r
 .set USBFS_ep_3__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
 .set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
 /* USBFS_ep_4 */\r
 .set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
 .set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_4__INTC_MASK, 0x10\r
-.set USBFS_ep_4__INTC_NUMBER, 4\r
+.set USBFS_ep_4__INTC_MASK, 0x100\r
+.set USBFS_ep_4__INTC_NUMBER, 8\r
 .set USBFS_ep_4__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
 .set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
 .set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
 \r
+/* SD_RX_DMA */\r
+.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SD_RX_DMA__DRQ_NUMBER, 2\r
+.set SD_RX_DMA__NUMBEROF_TDS, 0\r
+.set SD_RX_DMA__PRIORITY, 1\r
+.set SD_RX_DMA__TERMIN_EN, 0\r
+.set SD_RX_DMA__TERMIN_SEL, 0\r
+.set SD_RX_DMA__TERMOUT0_EN, 1\r
+.set SD_RX_DMA__TERMOUT0_SEL, 2\r
+.set SD_RX_DMA__TERMOUT1_EN, 0\r
+.set SD_RX_DMA__TERMOUT1_SEL, 0\r
+\r
+/* SD_TX_DMA */\r
+.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SD_TX_DMA__DRQ_NUMBER, 3\r
+.set SD_TX_DMA__NUMBEROF_TDS, 0\r
+.set SD_TX_DMA__PRIORITY, 2\r
+.set SD_TX_DMA__TERMIN_EN, 0\r
+.set SD_TX_DMA__TERMIN_SEL, 0\r
+.set SD_TX_DMA__TERMOUT0_EN, 1\r
+.set SD_TX_DMA__TERMOUT0_SEL, 3\r
+.set SD_TX_DMA__TERMOUT1_EN, 0\r
+.set SD_TX_DMA__TERMOUT1_SEL, 0\r
+\r
 /* USBFS_USB */\r
 .set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG\r
 .set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG\r
 .set CYDEV_CHIP_FAMILY_PSOC5, 3\r
 .set CYDEV_CHIP_DIE_PSOC5LP, 4\r
 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP\r
-.set BCLK__BUS_CLK__HZ, 60000000\r
-.set BCLK__BUS_CLK__KHZ, 60000\r
-.set BCLK__BUS_CLK__MHZ, 60\r
+.set BCLK__BUS_CLK__HZ, 50000000\r
+.set BCLK__BUS_CLK__KHZ, 50000\r
+.set BCLK__BUS_CLK__MHZ, 50\r
 .set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT\r
 .set CYDEV_CHIP_DIE_LEOPARD, 1\r
 .set CYDEV_CHIP_DIE_PANTHER, 3\r
 .set CYDEV_ECC_ENABLE, 0\r
 .set CYDEV_HEAP_SIZE, 0x0400\r
 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
-.set CYDEV_INTR_RISING, 0x00000001\r
+.set CYDEV_INTR_RISING, 0x0000001E\r
 .set CYDEV_PROJ_TYPE, 2\r
 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1\r
 .set CYDEV_PROJ_TYPE_LOADABLE, 2\r
 .set CYDEV_VIO2, 5\r
 .set CYDEV_VIO2_MV, 5000\r
 .set CYDEV_VIO3_MV, 3300\r
-.set DMA_CHANNELS_USED__MASK0, 0x00000000\r
+.set DMA_CHANNELS_USED__MASK0, 0x0000000F\r
 .set CYDEV_BOOTLOADER_ENABLE, 0\r
 .endif\r