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[SCSI2SD-V6.git] / software / SCSI2SD / SCSI2SD.cydsn / SCSI2SD.cycdx
old mode 100755 (executable)
new mode 100644 (file)
index 265ed9e..4acdeea
@@ -1,8 +1,72 @@
 <?xml version="1.0" encoding="utf-8"?>\r
 <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
+  <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />\r
+  </block>\r
+  <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+    <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+    <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+    <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">\r
+      <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
+    </register>\r
+    <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">\r
+      <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
+      <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
+        <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
+        <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
+      </field>\r
+      <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
+      <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
+      <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
+      <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
+        <value name="Timer" value="0" desc="CMP and TC are output." />\r
+        <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
+      </field>\r
+      <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
+    </register>\r
+    <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">\r
+      <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
+      <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
+        <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
+        <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
+      </field>\r
+      <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
+      <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
+      <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
+      <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
+    </register>\r
+    <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">\r
+      <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
+        <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
+        <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
+        <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
+        <value name="Irq" value="11" desc="Timer runs until IRQ." />\r
+      </field>\r
+      <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
+      <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
+      <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
+        <value name="Equal" value="0" desc="Compare Equal " />\r
+        <value name="Less than" value="1" desc="Compare Less Than " />\r
+        <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
+        <value name="Greater" value="11" desc="Compare Greater Than ." />\r
+        <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
+      </field>\r
+      <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
+    </register>\r
+    <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
+    <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
+  </block>\r
+  <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006577" bitWidth="8" desc="" />\r
+  </block>\r
   <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
     <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
     <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
     <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
     <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   </block>\r
-  <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
     <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
     <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
     <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />\r
     <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
   </block>\r
+  <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
-    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-    <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">\r
-      <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
-    </register>\r
-    <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">\r
-      <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
-      <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
-        <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
-        <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
-      </field>\r
-      <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
-      <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
-      <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
-      <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
-        <value name="Timer" value="0" desc="CMP and TC are output." />\r
-        <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
-      </field>\r
-      <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
-    </register>\r
-    <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">\r
-      <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
-      <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
-        <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
-        <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
-      </field>\r
-      <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
-      <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
-      <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
-      <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
-    </register>\r
-    <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">\r
-      <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
-        <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
-        <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
-        <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
-        <value name="Irq" value="11" desc="Timer runs until IRQ." />\r
-      </field>\r
-      <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
-      <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
-      <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
-        <value name="Equal" value="0" desc="Compare Equal " />\r
-        <value name="Less than" value="1" desc="Compare Less Than " />\r
-        <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
-        <value name="Greater" value="11" desc="Compare Greater Than ." />\r
-        <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
-      </field>\r
-      <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
-    </register>\r
-    <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
-    <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
-  </block>\r
+  <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
-    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" />\r
-  </block>\r
-  <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
-    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006470" bitWidth="8" desc="" />\r
-  </block>\r
+  <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
+  </block>\r
+  <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
-    <register name="SD_Clk_Ctl_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
-  </block>\r
-  <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
-  <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
-    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" />\r
-  </block>\r
+  <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
   <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+  <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
 </blockRegMap>
\ No newline at end of file