Add all phase bits to a control register for atomic phase changes.
[SCSI2SD-V6.git] / software / SCSI2SD / src / scsiPhy.c
index 6a8052f..fc42b4f 100755 (executable)
@@ -123,35 +123,12 @@ static void busSettleDelay(void)
 \r
 void scsiEnterPhase(int phase)\r
 {\r
-       if (phase > 0)\r
+       int newPhase = phase > 0 ? phase : 0;\r
+       if (newPhase != SCSI_CTL_PHASE_Read())\r
        {\r
-               if (phase & __scsiphase_msg)\r
-               {\r
-                       SCSI_SetPin(SCSI_Out_MSG);\r
-               }\r
-               else\r
-               {\r
-                       SCSI_ClearPin(SCSI_Out_MSG);\r
-               }\r
-\r
-               if (phase & __scsiphase_cd)\r
-               {\r
-                       SCSI_SetPin(SCSI_Out_CD);\r
-               }\r
-               else\r
-               {\r
-                       SCSI_ClearPin(SCSI_Out_CD);\r
-               }\r
-\r
-               SCSI_CTL_IO_Write(phase & __scsiphase_io ? 1 : 0);\r
-       }\r
-       else\r
-       {\r
-               SCSI_ClearPin(SCSI_Out_MSG);\r
-               SCSI_ClearPin(SCSI_Out_CD);\r
-               SCSI_CTL_IO_Write(0);\r
+               SCSI_CTL_PHASE_Write(phase > 0 ? phase : 0);\r
+               busSettleDelay();\r
        }\r
-       busSettleDelay();\r
 }\r
 \r
 void scsiPhyReset()\r
@@ -165,15 +142,13 @@ void scsiPhyReset()
        // duration.\r
        SCSI_SetPin(SCSI_Out_RST);\r
 \r
-       SCSI_CTL_IO_Write(0);\r
+       SCSI_CTL_PHASE_Write(0);\r
        SCSI_ClearPin(SCSI_Out_ATN);\r
        SCSI_ClearPin(SCSI_Out_BSY);\r
        SCSI_ClearPin(SCSI_Out_ACK);\r
        SCSI_ClearPin(SCSI_Out_RST);\r
        SCSI_ClearPin(SCSI_Out_SEL);\r
        SCSI_ClearPin(SCSI_Out_REQ);\r
-       SCSI_ClearPin(SCSI_Out_MSG);\r
-       SCSI_ClearPin(SCSI_Out_CD);\r
 \r
        // Allow the FIFOs to fill up again.\r
        SCSI_ClearPin(SCSI_Out_RST);\r