Save a cycle in fpga memory interface
[SCSI2SD-V6.git] / src / firmware / scsiPhy.c
index 58d56f66a69b030a7deedfa1ccfd4a6e49add03c..d0e7002851756d3782d91c97bf64eecb11e50a6b 100755 (executable)
@@ -594,7 +594,7 @@ void scsiPhyReset()
        scsiSetDefaultTiming();\r
 \r
        // DMA Benchmark code\r
-       // Currently 11MB/s.\r
+       // Currently 14.9MB/s.\r
        #ifdef DMA_BENCHMARK\r
        while(1)\r
        {\r
@@ -770,8 +770,11 @@ int scsiSelfTest()
                return 32;\r
        }\r
        *SCSI_CTRL_BSY = 1;\r
+       s2s_delay_ms(1);\r
        if (! scsiStatusBSY())\r
        {\r
+               *SCSI_CTRL_BSY = 0;\r
+\r
                // Error, BSY doesn't work.\r
                return 32;\r
        }\r
@@ -851,7 +854,6 @@ int scsiSelfTest()
        }\r
        */\r
 \r
-\r
        // FPGA comms test code\r
        for(i = 0; i < 10000; ++i)\r
        {\r